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FEATURES
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54LVC74A . . . J OR W PACKAGE
SN74LVC74A . . . D, DB, NS, OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q V
2CLR
1Q
GND
NC
SN54LVC74A . . . FK PACKAGE
(TOP VIEW)
CC
NC - No internal connection
SN74LVC74A . . . RGY PACKAGE
(TOP VIEW)
1 14
7 8
2
3
4
5
6
13
12
11
10
9
2CLR
2D
2CLK
2PRE
2Q
1D
1CLK
1PRE
1Q
1Q
1CLR
2Q V
GND
CC
DESCRIPTION/ORDERING INFORMATION
SN54LVC74A, SN74LVC74ADUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH CLEAR AND PRESET
SCAS287S – JANUARY 1993 – REVISED MAY 2005
•Latch-Up Performance Exceeds 250 mA PerJESD 17•Operate From 1.65 V to 3.6 V
•ESD Protection Exceeds JESD 22•Inputs Accept Voltages to 5.5 V
– 2000-V Human-Body Model (A114-A)•Max t
pd
of 5.2 ns at 3.3 V
– 200-V Machine Model (A115-A)•Typical V
OLP
(Output Ground Bounce)<0.8 V at V
CC
= 3.3 V, T
A
= 25°C – 1000-V Charged-Device Model (C101)•Typical V
OHV
(Output V
OH
Undershoot)>2 V at V
CC
= 3.3 V, T
A
= 25°C
The SN54LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V
CC
operation, andthe SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V
CC
operation.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGY Reel of 1000 SN74LVC74ARGYR LC74ATube of 50 SN74LVC74ADSOIC – D Reel of 2500 SN74LVC74ADR LVC74AReel of 250 SN74LVC74ADT–40°C to 85°C SOP – NS Reel of 2000 SN74LVC74ANSR LCV74ASSOP – DB Reel of 2000 SN74LVC74ADBR LC74ATube of 90 SN74LVC74APWTSSOP – PW Reel of 2000 SN74LVC74APWR LC74AReel of 250 SN74LVC74APWTCDIP – J Tube of 25 SNJ54LVC74AJ SNJ54LVC74AJ–55°C to 125°C CFP – W Tube of 150 SNJ54LVC74AW SNJ54LVC74AWLCCC – FK Tube of 55 SNJ54LVC74AFK SNJ54LVC74AFK
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1993–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters areInstruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, productionnecessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
SN54LVC74A, SN74LVC74ADUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH CLEAR AND PRESET
SCAS287S – JANUARY 1993 – REVISED MAY 2005
A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of theother inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup timerequirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occursat a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,data at the D input can be changed without affecting the levels at the outputs.
The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of these devices fordown-translation in a mixed-voltage environment.
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H LH L X X L HL L X X H
(1)
H
(1)
H H ↑H H LH H ↑L L HH H L X Q
0
Q
0
(1) This configuration is nonstable; that is, it does not persist whenPRE or CLR returns to its inactive (high) level.
LOGIC DIAGRAM, EACH FLIP-FLOP(POSITIVE LOGIC)
2
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN54LVC74A, SN74LVC74ADUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH CLEAR AND PRESET
SCAS287S – JANUARY 1993 – REVISED MAY 2005
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 6.5 VV
O
Output voltage range
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through V
CC
or GND ±100 mAD package
(4)
86DB package
(4)
96θ
JA
Package thermal impedance NS package
(4)
76 °C/WPW package
(4)
113RGY package
(5)
47T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.(5) The package thermal impedance is calculated in accordance with JESD 51-5.
SN54LVC74A SN74LVC74A
UNITMIN MAX MIN MAX
Operating 2 3.6 1.65 3.6V
CC
Supply voltage VData retention only 1.5 1.5V
CC
= 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 VV
CC
= 2.7 V to 3.6 V 2 2V
CC
= 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 VV
CC
= 2.7 V to 3.6 V 0.8 0.8V
I
Input voltage 0 5.5 0 5.5 VV
O
Output voltage 0 V
CC
0 V
CC
VV
CC
= 1.65 V –4V
CC
= 2.3 V –8I
OH
High-level output current mAV
CC
= 2.7 V –12 –12V
CC
= 3 V –24 –24V
CC
= 1.65 V 4V
CC
= 2.3 V 8I
OL
Low-level output current mAV
CC
= 2.7 V 12 12V
CC
= 3 V 24 24∆t/ ∆v Input transition rise or fall rate 10 10 ns/VT
A
Operating free-air temperature –55 125 –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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Electrical Characteristics
Timing Requirements
SN54LVC74A, SN74LVC74ADUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH CLEAR AND PRESET
SCAS287S – JANUARY 1993 – REVISED MAY 2005
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC74A SN74LVC74APARAMETER TEST CONDITIONS V
CC
UNITMIN TYP
(1)
MAX MIN TYP
(1)
MAX
1.65 V to 3.6 V V
CC
– 0.2I
OH
= –100 µA
2.7 V to 3.6 V V
CC
– 0.2I
OH
= –4 mA 1.65 V 1.2V
OH
I
OH
= –8 mA 2.3 V 1.7 V2.7 V 2.2 2.2I
OH
= –12 mA
3 V 2.4 2.4I
OH
= –24 mA 3 V 2.2 2.21.65 V to 3.6 V 0.2I
OL
= 100 µA
2.7 V to 3.6 V 0.2I
OL
= 4 mA 1.65 V 0.45V
OL
VI
OL
= 8 mA 2.3 V 0.7I
OL
= 12 mA 2.7 V 0.4 0.4I
OL
= 24 mA 3 V 0.55 0.55I
I
V
I
= 5.5 V or GND 3.6 V ±5 ±5 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 3.6 V 10 10 µAOne input at V
CC
– 0.6 V,∆I
CC
2.7 V to 3.6 V 500 500 µAOther inputs at V
CC
or GNDC
i
V
I
= V
CC
or GND 3.3 V 5 5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
SN54LVC74A
V
CC
= 3.3 VV
CC
= 2.7 V UNIT± 0.3 V
MIN MAX MIN MAX
f
clock
Clock frequency 83 100 MHzPRE or CLR low 3.3 3.3t
w
Pulse duration nsCLK high or low 3.3 3.3Data 3.4 3t
su
Setup time before CLK ↑nsPRE or CLR inactive 2.2 2t
h
Hold time, data after CLK ↑1 1 ns
4
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Timing Requirements
Switching Characteristics
Switching Characteristics
Operating Characteristics
SN54LVC74A, SN74LVC74ADUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH CLEAR AND PRESET
SCAS287S – JANUARY 1993 – REVISED MAY 2005
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
SN74LVC74A
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 2.7 V UNIT± 0.15 V ± 0.2 V ± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency 83 83 83 150 MHzPRE or CLR low 4.1 3.3 3.3 3.3t
w
Pulse duration nsCLK high or low 4.1 3.3 3.3 3.3Data 3.6 2.3 3.4 3t
su
Setup time before CLK ↑nsPRE or CLR inactive 2.7 1.9 2.2 2t
h
Hold time, data after CLK ↑1 1 1 0 ns
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
SN54LVC74A
FROM TO V
CC
= 3.3 VPARAMETER V
CC
= 2.7 V UNIT(INPUT) (OUTPUT) ± 0.3 V
MIN MAX MIN MAX
f
max
83 100 MHzCLK 6 1 5.2t
pd
Q or Q nsPRE or CLR 6.4 1 5.4
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
SN74LVC74A
FROM TO V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER V
CC
= 2.7 V UNIT(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
f
max
83 83 83 150 MHzCLK 1 7.1 1 4.4 1 6 1 5.2t
pd
Q or Q nsPRE or CLR 1 6.9 1 4.6 1 6.4 1 5.4t
sk(o)
1 ns
T
A
= 25°C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VTESTPARAMETER UNITCONDITIONS
TYP TYP TYP
C
pd
Power dissipation capacitance per flip-flop f = 10 MHz 24 24 26 pF
5
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WA VEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH - V∆≈0 V
VI
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
SN54LVC74A, SN74LVC74ADUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH CLEAR AND PRESET
SCAS287S – JANUARY 1993 – REVISED MAY 2005
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9761601Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9761601QCA ACTIVE CDIP J 14 1 TBD Call TI Call TI
5962-9761601QDA ACTIVE CFP W 14 1 TBD Call TI Call TI
5962-9761601V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9761601VCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type
5962-9761601VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN74LVC74AD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74LVC74ADBR ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADTE4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ADTG4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ANSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LVC74APW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74LVC74APWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74APWRG3 PREVIEW TSSOP PW 14 2000 TBD Call TI Call TI
SN74LVC74APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74APWT ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC74ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVC74ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SNJ54LVC74AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LVC74AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SNJ54LVC74AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC74A, SN54LVC74A-SP, SN74LVC74A :
•Catalog: SN74LVC74A, SN54LVC74A
•Automotive: SN74LVC74A-Q1, SN74LVC74A-Q1
•Enhanced Product: SN74LVC74A-EP, SN74LVC74A-EP
•Military: SN54LVC74A
•Space: SN54LVC74A-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 4
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC74ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LVC74ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC74ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC74ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74LVC74APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC74ADBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LVC74ADR SOIC D 14 2500 367.0 367.0 38.0
SN74LVC74ADT SOIC D 14 250 367.0 367.0 38.0
SN74LVC74ANSR SO NS 14 2000 367.0 367.0 38.0
SN74LVC74APWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVC74APWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC74APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVC74APWT TSSOP PW 14 250 367.0 367.0 35.0
SN74LVC74ARGYR VQFN RGY 14 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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