10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
VS = ±5V
AV = 2V/V
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 4 VPP
10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
VS = ±5V
VOUT = 2 VPP
AV = 1, RF = 1.5 k:
AV = 2, RF = 575:
AV = 6, RF = 300:
AV = 10, RF = 180:
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6574
SNCS103E –NOVEMBER 2004–REVISED AUGUST 2018
LMH6574 4:1 High Speed Video Multiplexer
1
1 Features
1• 500 MHz, 500 mV −3 dB Bandwidth, AV= 2
• 400 MHz, 2 VPP −3 dB Bandwidth, AV= 2
• 8 ns Channel Switching Time
• 70 dB Channel to Channel Isolation at 10 MHz
• 0.02%, 0.05° Diff. Gain, Phase
• 0.1 dB Gain Flatness to 150 MHz
• 2200 V/μs Slew Rate
• Wide Supply Voltage Range: 6 V (±3 V) to 12 V
(±6 V)
•−68 dB HD2 at 5 MHz
•−84 dB HD3 at 5 MHz
2 Applications
• Video Router
• Multi Input Video Monitor
• Instrumentation / Test Equipment
• Receiver IF Diversity Switch
• Multi Channel A/D Driver
• Picture in Picture Video Switch
3 Description
The LMH6574 is a high-performance analog
multiplexer optimized for professional grade video
and other high fidelity high bandwidth analog
applications. The output amplifier selects any one of
four buffered input signals based on the state of the
two address bits. The LMH6574 provides a 400-MHz
bandwidth at 2 VPP output signal levels. Multimedia
and high definition television (HDTV) applications can
benefit from the LMH6574 0.1 dB bandwidth of 150
MHz and its 2200 V/μs slew rate.
The LMH6574 supports composite video applications
with its 0.02% and 0.05° differential gain and phase
errors for NTSC and PAL video signals while driving
a single, back terminated 75-Ωload. An 80-mA linear
output current is available for driving multiple video
load applications.
The LMH6574 gain is set by external feedback and
gain set resistors for maximum flexibility.
The LMH6574 is available in the 14-pin SOIC
package.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMH6574 SOIC (14) 8.65 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Frequency Response vs VOUT Frequency Response vs Gain
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics ±5 V ................................. 5
6.6 Electrical Characteristics ±3.3 V .............................. 7
6.7 Typical Characteristics.............................................. 8
7 Detailed Description............................................ 13
7.1 Functional Block Diagram....................................... 13
7.2 Feature Description................................................. 13
7.3 Device Functional Modes........................................ 16
8 Application and Implementation ........................ 17
8.1 Application Information............................................ 17
9 Power Supply Recommendations...................... 21
9.1 Power Dissipation ................................................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
11 Device and Documentation Support................. 22
11.1 Documentation Support ........................................ 22
11.2 Receiving Notification of Documentation Updates 22
11.3 Community Resources.......................................... 22
11.4 Trademarks........................................................... 22
11.5 Electrostatic Discharge Caution............................ 22
11.6 Glossary................................................................ 22
12 Mechanical, Packaging, and Orderable
Information........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2014) to Revision E Page
• Changed IBN parameter maximum specifications from ±5 µA to ±5.2 µA and from ±5.6 µA to ±5.8 µA.............................. 5
• Changed PSRR parameter minimum specifications from 47 dB to 43 dB and from 45 dB to 41 dB .................................... 5
• Changed Supply Current Disabled parameter maximum specifications from 5.8 mA to 6.2 mA and from 5.9 mA to
6.3 mA .................................................................................................................................................................................... 6
• Changed IiL parameter minimum specifications from –2.9 µA to –3.3 µA and from –8.5 µA to –9 µA................................. 6
• Added Feature Description and Device Functional Modes sections.................................................................................... 13
Changes from Revision C (November 2012) to Revision D Page
• Added, updated, or revised the following sections: Pin Configuration and Functions,Specifications,Application and
Implementation,Power Supply Recommendations ,Layout ,Device and Documentation Support , and Mechanical,
Packaging, and Orderable Information................................................................................................................................... 1
• Revised text in Application and Implementation section, formerly titled "Application Notes"............................................... 17
• Revised text in Multiplexer Expansion section. Added Figure 31,Figure 32, and Figure 33 .............................................. 17
V+
OUT
FB
SD
A1
A0IN3
V-
IN2
GND
IN1
GND
IN0 1
2
3
4
5
6
7 8
9
10
11
12
13
14
+
-
EN
3
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5 Pin Configuration and Functions
14-Pin SOIC
Package D
(Top View)
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 IN0 I Input Channel 0
2 GND –– Ground
3 IN1 I Input Channel 1
4 GND –– Ground
5 IN2 I Input Channel 2
6 V-I V-Supply
7 IN3 I Input Channel 3
8 A0 I Select Pin A0
9 A1 I Select Pin A1
10 EN I Enable
11 SD I Shutdown
12 FB I Feedback
13 OUT O Output
14 V+I V+Supply
Truth Table
A1 A0 EN SD OUT
1 1 0 0 CH 3
1 0 0 0 CH2
0 1 0 0 CH1
0 0 0 0 CH 0
X X 1 0 Disable
X X X 1 Shutdown
4
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(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics ±5 V tables
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum output current (IOUT) is determined by the device power dissipation limitations (The junction temperature cannot be
allowed to exceed 150°C). See the Power Dissipation for more details. A short circuit condition should be limited to 5 seconds or less.
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN MAX UNIT
Supply Voltage (V+−V−) 13.2 V
IOUT(3) 130 mA
Signal & Logic Input Pin Voltage ±(VS+0.6) V
Signal & Logic Input Pin Current ±20 mA
Maximum Junction Temperature +150 °C
Storage Temperature −65 +150 °C
(1) Human Body model, 1.5 kΩin series with 100 pF. Machine model, 0 ΩIn series with 200 pF.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 2000-V HBM is possible with the necessary precautions. Pins listed as ±200 V may actually have higher performance.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) ±2000 V
Machine model (MM) ±200
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics ±5 V tables
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
Operating Temperature −40 85 °C
Supply Voltage 6 12 V
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) DUNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 130 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 40 °C/W
5
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(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensure of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ> TA. See Application and Implementation for information on temperature de-rating of this
device. Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted.
(2) Parameters guaranteed by electrical testing at 25°C.
(3) Positive Value is current into device.
6.5 Electrical Characteristics ±5 V
VS= ±5 V, RL= 100 Ω, AV= 2 V/V, RF= 575 Ω, TJ= 25 °C, unless otherwise specified.
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW −3 dB Bandwidth VOUT = 0.5 VPP 500 MHz
LSBW –3 dB Bandwidth VOUT = 2 VPP 400 MHz
.1 dBBW 0. 1 dB Bandwidth VOUT = 0.25 VPP 150 MHz
DG Differential Gain RL= 150 Ω, f = 4.43 MHz 0.02%
DP Differential Phase RL= 150 Ω, f = 4.43 MHz 0.05 deg
XTLK Channel to Channel
Crosstalk All Hostile, 5 MHz −85 dB
TIME DOMAIN RESPONSE
TRS Channel to Channel
Switching Time Logic Transition to 90% Output 8 ns
Enable and Disable
Times Logic Transition to 90% or 10% Output 10 ns
TRL Rise and Fall Time 4-V Step 2.4 ns
TSS Settling Time to 0.05% 2-V Step 17 ns
OS Overshoot 2-V Step 5%
SR Slew Rate 4-V Step 2200 V/μs
DISTORTION
HD2 2nd Harmonic Distortion 2 VPP , 5 MHz −68 dBc
HD3 3rd Harmonic Distortion 2 VPP , 5 MHz −84 dBc
IMD 3rd Order
Intermodulation
Products 10 MHz, Two Tones 2 VPP at Output −80 dBc
EQUIVALENT INPUT NOISE
VN Voltage >1 MHz, Input Referred 5 nV√Hz
ICN Current >1 MHz, Input Referred 5 pA/√Hz
STATIC, DC PERFORMANCE
CHGM Channel to Channel
Gain Difference DC, Difference in Gain
Between Channels ±0.005% ±0.032%
-40°C ≤TJ≤85°C ±0.035%
VIO Input Offset Voltage(2) VIN = 0 V 1 ±20 mV
-40°C ≤TJ≤85°C ±25
DVIO Offset Voltage Drift 30 µV/°C
IBN Input Bias Current(2)(3) VIN = 0 V −3 ±5.2 µA
-40°C ≤TJ≤85°C ±5.8
DIBN Bias Current Drift 11 nA/°C
Inverting Input Bias
Current Pin 12, Feedback Point,
VIN = 0 V
−7 ±10
-40°C ≤TJ≤85°C ±13
PSRR Power Supply Rejection
Ratio(2) DC, Input Referred 43 54 dB
-40°C ≤TJ≤85°C 41
6
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Electrical Characteristics ±5 V (continued)
VS= ±5 V, RL= 100 Ω, AV= 2 V/V, RF= 575 Ω, TJ= 25 °C, unless otherwise specified.
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
(4) The maximum output current (IOUT) is determined by the device power dissipation limitations (The junction temperature cannot be
allowed to exceed 150°C). See the Power Dissipation for more details. A short circuit condition should be limited to 5 seconds or less.
ICC Supply Current(2) No Load 13 16 mA
-40°C ≤TJ≤85°C 18
Supply Current
Disabled(2) ENABLE > 2 V 4.7 6.2 mA
-40°C ≤TJ≤85°C 6.3
Supply Current
Shutdown SHUTDOWN > 2 V 1.8 2.5 mA
-40°C ≤TJ≤85°C 2.6
VIH Logic High Threshold(2) Select & Enable Pins (SD & EN) 2.0 V
VIL Logic Low Threshold(2) Select & Enable Pins (SD & EN) 0.8 V
IiL Logic Pin Input Current
Low(3) Logic Input = 0 V Select &
Enable Pins (SD & EN)
−3.3 −1µA
-40°C ≤TJ≤85°C –9
IiH Logic Pin Input Current
High(3) Logic Input = 2.0 V, Select
& Enable Pins (SD & EN) 47 68 µA
-40°C ≤TJ≤85°C 72.5
MISCELLANEOUS PERFORMANCE
RIN+ Input Resistance 5 kΩ
CIN Input Capacitance 0.8 pF
ROUT Output Resistance Output Active, (EN and SD < 0.8 V) 0.04 Ω
ROUT Output Resistance Output Disabled, (EN or SD > 2 V) 3000 Ω
COUT Output Capacitance Output Disabled, (EN or SD > 2 V) 3.1 pF
VO Output Voltage Range No Load ±3.54 ±3.7 V
-40°C ≤TJ≤85°C ±3.53
VOL RL= 100 Ω±3.18 ±3.5 V
-40°C ≤TJ≤85°C ±3.17
CMIR Input Voltage Range ±2.5 ±2.6 V
IO Linear Output
Current(2)(3) VIN = 0 V
+60
±80 mA
-70
-40°C ≤TJ≤85°C +50
-40°C ≤TJ≤85°C −60
ISC Short Circuit Current(4) VIN = ±2 V, Output Shorted to Ground ±230 mA
7
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(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensure of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ> TA. See Application and Implementation for information on temperature de-rating of this
device. Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted.
(2) Positive Value is current into device.
6.6 Electrical Characteristics ±3.3 V
VS= ±3.3 V, RL= 100 Ω, AV= 2 V/V, RF= 575 Ω; unless otherwise specified.
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW −3 dB Bandwidth VOUT = 0.5 VPP 475 MHz
LSBW −3 dB Bandwidth VOUT = 2.0 VPP 375 MHz
0.1 dBBW 0.1 dB Bandwidth VOUT = 0.5 VPP 100 MHz
GFP Peaking DC to 200 MHz 0.4 dB
XTLK Channel to Channel Crosstalk All Hostile, f = 5 MHz −85 dBc
TIME DOMAIN RESPONSE
TRL Rise and Fall Time 2-V Step 2 ns
TSS Settling Time to 0.05% 2-V Step 20 ns
OS Overshoot 2-V Step 5%
SR Slew Rate 2-V Step 1400 V/μs
DISTORTION
HD2 2nd Harmonic Distortion 2 VPP, 10 MHz −67 dBc
HD3 3rd Harmonic Distortion 2 VPP, 10 MHz −87 dBc
STATIC, DC PERFORMANCE
VIO Input Offset Voltage VIN = 0 V -5 mV
IBN Input Bias Current(2) VIN = 0 V -3 μA
PSRR Power Supply Rejection Ratio DC, Input Referred 49 dB
ICC Supply Current No Load 12 mA
VIH Logic High Threshold Select & Enable Pins (SD & EN) 1.3 V
VIL Logic Low Threshold Select & Enable Pins (SD & EN) 0.4 V
MISCELLANEOUS PERFORMANCE
RIN+ Input Resistance 5 kΩ
CIN Input Capacitance 0.8 pF
ROUT Output Resistance 0.06 Ω
VO Output Voltage Range No Load ±2 V
VOL RL= 100 Ω±1.8 V
CMIR Input Voltage Range ±1.2 V
IO Linear Output Current VIN = 0 V ±60 mA
ISC Short Circuit Current VIN = ±1 V, Output Shorted to Ground ±150 mA
0246810 12 14 16 18 20
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
OUTPUT (V)
TIME (ns)
VS = ±5V
12345678910
0
200
400
600
800
1000
1200
1400
1600
SUGGESTED VALUE OF RF (:)
GAIN (V/V)
110 100 1000
CAPACTIVE LOAD (pF)
0
10
20
30
40
50
60
70
80
90
SUGGESTED ROUT (:)
VS = ±5V
LOAD = 1 k:|| CL
10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
VS = ±5V
AV = 2V/V
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 4 VPP
10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
VS = ±5V
VOUT = 2 VPP
AV = 1, RF = 1.5 k:
AV = 2, RF = 575:
AV = 6, RF = 300:
AV = 10, RF = 180:
8
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6.7 Typical Characteristics
VS= ±5 V, RL= 100 Ω, AV= 2, RF= RG= 575 Ω, unless otherwise specified.
Figure 1. Frequency Response vs VOUT Figure 2. Frequency Response vs Gain
Figure 3. Frequency Response vs Capacitive Load Figure 4. Suggested ROUT vs Capacitive Load
Figure 5. Suggested Value of RFvs Gain Figure 6. Pulse Response 4VPP
0.1 1 10 100 1000
FREQUENCY (MHz)
0
10
20
30
40
50
60
PSRR (dB)
PSRR +
PSRR -
010 20 30 40 50 60 70 80
TIME (ns)
0
1
2
-0.5
-0.25
0
0.25
0.5
0.75
OUTPUT (V)
3
ADDRESS LINE 0 (V)
CHANNEL 1
CHANNEL 0
ADDRESS LINE 0
0.01 1 10 100 1000
FREQUENCY (MHz)
0.1
1
1000
10000
|Z| (:)
10
100
0.1
DISABLED
VS = ±5V
VIN = 0V
AV = 2V/V
ENABLED
0.01 1 10 100 1000
FREQUENCY (MHz)
0.1
1
1000
10000
|Z| (:)
10
100
0.1
DISABLED
VS = ±5V
VIN = 0V
AV = 1V/V
ENABLED
05 10 15 20 25 30
TIME (ns)
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
VS = ±5V
05 10 15 20 25 30
TIME (ns)
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
VS = ±3.3V
9
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Typical Characteristics (continued)
VS= ±5 V, RL= 100 Ω, AV= 2, RF= RG= 575 Ω, unless otherwise specified.
Figure 7. Pulse Response 2VPP Figure 8. Pulse Response 2VPP
Figure 9. Closed Loop Output Impedance Figure 10. Closed Loop Output Impedance
Figure 11. PSRR vs Frequency Figure 12. Channel Switching
FREQUENCY (MHz)
110 100
-100
-90
-80
-70
-60
-50
-40
DISTORTION (dBc)
CH3
CH2
CH1
CH0
VOUT = 2 VPP
FREQUENCY (MHz)
110 100
-100
-90
-80
-70
-60
-50
-40
DISTORTION (dBc)
HD3 ALL CHANNELS
VOUT = 2 VPP
020 40 60 80 100 120 140 160
TIME (ns)
-0.5
-0.25
0
0.25
0.5
OUTPUT (V)
0
2
4
6
VIN = 0V
AV = 2
VOUT
ENABLE
ENABLE (V)
010 20 30 40 50 60 70 80
TIME (ns)
0
1
2
3
-0.25
0
0.25
0.5
VOUT (V)
-0.5
VOUT
ENABLE
ENABLE (V)
020 40 60 80 100 120 140 160
TIME (ns)
-0.75
-0.5
-0.25
0
0.25
0.5
OUTPUT (V)
0
2
4
6
SHUTDOWN VOLTAGE (V)
VIN = 0V
AV = 2
VOUT
SHUTDOWN
010 20 30 40 50 60 70 80
TIME (ns)
0
1
2
3
-0.25
0
0.25
0.5
VOUT (V)
-0.5
SHUTDOWN
VOUT
SHUTDOWN (V)
10
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Typical Characteristics (continued)
VS= ±5 V, RL= 100 Ω, AV= 2, RF= RG= 575 Ω, unless otherwise specified.
Figure 13. SHUTDOWN Switching Figure 14. Shutdown Glitch
Figure 15. ENABLE Switching Figure 16. Disable Glitch
Figure 17. HD2 vs Frequency Figure 18. HD3 vs Frequency
0 20 40 60 80 100
-4
-3.8
-3.6
-3.4
-3.2
-3
-2.8
-2.6
-2.4
MINIMUM OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
-100 -80 -60 -40 -20 0
2.8
3
3.2
3.4
3.6
3.8
4
MAXIMUM OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
01 2 34 5 8
OUTPUT VOLTAGE (VPP)
-100
-90
-80
-70
-60
-50
-40
DISTORTION (dBc)
67
f = 5 MHz
CH0
CH1
CH2
CH3
01 2 34 5 8
OUTPUT VOLTAGE (VPP)
-100
-90
-80
-70
-60
-50
-40
-30
DISTORTION (dBc)
67
f = 5 MHz
56 7 89 10 12
SUPPLY VOLTAGE (V)
-100
-95
-90
-85
-80
-75
-70
-65
-60
DISTORTION (dBc)
11
f = 5 MHz
VOUT = 2 VPP
CH1
CH2
CH0
CH3
56 7 89 10 12
SUPPLY VOLTAGE (V)
-100
-95
-90
-85
-80
-75
-70
-65
-60
DISTORTION (dBc)
11
f = 5 MHz
VOUT = 2 VPP
CH1
CH2
CH0
CH3
11
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Typical Characteristics (continued)
VS= ±5 V, RL= 100 Ω, AV= 2, RF= RG= 575 Ω, unless otherwise specified.
Figure 19. HD2 vs VSFigure 20. HD3 vs VS
Figure 21. HD2 vs VOUT Figure 22. HD3 vs VOUT
Positive Value is current into device
Figure 23. Minimum VOUT vs IOUT
Positive Value is current into device
Figure 24. Maximum VOUT vs IOUT
0.01 0.1 1 10 100
FREQUENCY (MHz)
-110
-100
-90
-80
-70
-60
-50
-40
-30
ISOLATION (dB)
SELECTED INPUT TO OUTPUT
VIN = 2 VPP
DISABLE
SHUTDOWN
-30
0.01 11000
FREQUENCY (MHz)
-110
-80
CROSSTALK (dBc)
100
10
0.1
-50
-60
-90
-100
-70
-40 UNSELECTED INPUT TO
OUTPUT, VS = ±5V
12
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Typical Characteristics (continued)
VS= ±5 V, RL= 100 Ω, AV= 2, RF= RG= 575 Ω, unless otherwise specified.
Figure 25. Crosstalk vs Frequency Figure 26. Off Isolation
1 2 3 4 5 6 7 8 9 10
0
200
400
600
800
1000
1200
1400
1600
SUGGESTED VALUE OF RF (:)
GAIN (V/V)
V+
SD
7
RF
IN 3
+
-
1
RIN0
IN 0
5
IN 2
3
IN 1
RIN3
RIN2
RIN1
10
8
12
13
11
9
14
6
V-
RT
A0
RT
A1
VOUT
ROUT
RG
RT
EN
RT
2, 4
13
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7 Detailed Description
7.1 Functional Block Diagram
7.2 Feature Description
7.2.1 Video Performance
The LMH6574 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. Best performance will be obtained with back-
terminated loads. The back termination reduces reflections from the transmission line and effectively masks
transmission line and other parasitic capacitances from the amplifier output stage. The Functional Block Diagram
shows a typical configuration for driving a 75Ωcable. The output buffer is configured for a gain of 2, so using
back terminated loads will give a net gain of 1.
7.2.2 Feedback Resistor Selection
Figure 27. Suggested RFvs Gain
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Feature Description (continued)
The LMH6574 has a current feedback output buffer with gain determined by external feedback (RF) and gain set
(RG) resistors. With current feedback amplifiers, the closed loop frequency response is a function of RF. For a
gain of 2 V/V, the recommended value of RFis 575Ω. For other gains see Figure 27. Generally, lowering RFfrom
the recommended value will peak the frequency response and extend the bandwidth while increasing the value
of RFwill cause the frequency response to roll off faster. Reducing the value of RFtoo far below the
recommended value will cause overshoot, ringing and, eventually, oscillation.
Since all applications are slightly different it is worth some experimentation to find the optimal RFfor a given
circuit. For more information see Current Feedback Loop Gain Analysis and Performance Enhancement,
Application Note OA-13 (SNOA366), which describes the relationship between RFand closed-loop frequency
response for current feedback operational amplifiers. The impedance looking into pin 12 is approximately 20Ω.
This allows for good bandwidth at gains up to 10 V/V. When used with gains over 10 V/V, the LMH6574 will
exhibit a “gain bandwidth product” similar to a typical voltage feedback amplifier. For gains of over 10 V/V
consider selecting a high performance video amplifier like the LMH6720 (SNOSA39) to provide additional gain.
7.2.3 Other Applications
The LMH6574 could support a multi antenna receiver with up to four separate antennas. Monitoring the signal
strength of all 4 antennas and connecting the strongest signal to the final IF stage would provide effective spacial
diversity.
For direction finding, the LMH6574 could be used to provide high speed sampling of four separate antennas to a
single DSP which would use the information to calculate the direction of the received signal.
110 100 1000
CAPACTIVE LOAD (pF)
0
10
20
30
40
50
60
70
80
90
SUGGESTED ROUT (:)
VS = ±5V
LOAD = 1 k:|| CL
LMH6574
ROUT
45:
CL
10 pF RL
1 k:
VOUT
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Feature Description (continued)
7.2.4 Driving Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor ROUT.Figure 28 shows
the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive
loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
Figure 29 provides a recommended value for selecting a series output resistor for mitigating capacitive loads.
The values suggested in the charts are selected for 0.5 dB or less of peaking in the frequency response. This
gives a good compromise between settling time and bandwidth. For applications where maximum frequency
response is needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the
recommended values.
Figure 28. Decoupling Capacitive Loads
Figure 29. Suggested ROUT vs Capacitive Load Figure 30. Frequency Response vs Capacitive Load
7.2.5 ESD Protection
The LMH6574 is protected against electrostatic discharge (ESD) on all pins. The LMH6574 will survive 2000-V
Human Body model and 200-V Machine model events. Under normal operation the ESD diodes have no effect
on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6574 is
driven by a large signal while the device is powered down the ESD diodes will conduct . The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to
conserve power and still prevent unexpected operation.
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7.3 Device Functional Modes
7.3.1 SD vs EN
The LMH6574 has both shutdown and disable capability. The shutdown feature affects the entire chip, whereas
the disable function only affects the output buffer. When in shutdown mode, minimal power is consumed. The
shutdown function is very fast, but causes a very brief spike of about 400 mV to appear on the output. When in
shutdown mode the LMH6574 consumes only 1.8 mA of supply current. For maximum input to output isolation
use the shutdown function.
The EN pin only disables the output buffer which results in a substantially reduced output glitch of only 50 mV.
While disabled the chip consumes 4.7 mA, considerably more than when shutdown. This is because the input
buffers are still active. For minimal output glitch use the EN pin. Also, care should be taken to ensure that, while
in the disabled state, the voltage differential between the active input buffer (the one selected by pins A0 and A1)
and the output pin stays less than 2V. As the voltage differential increases, input to output isolation decreases.
Normally this is not an issue. See Multiplexer Expansion for further details.
To reduce the output glitch when using the SD pin, switch the EN pin at least 10 ns before switching the SD pin.
This can be accomplished by using an RC delay circuit between the two pins if only one control signal is
available.
Logic inputs "SD" and "EN" will revert to the "High", while "A0" and "A1" will revert to the "Low" state when left
floating.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH6574 is a high-speed 4:1 analog multiplexer, optimized for very high speed and low distortion. With
selectable gain and excellent AC performance, the LMH6574 is ideally suited for switching high resolution,
presentation grade video signals. The LMH6574 has no internal ground reference. Single or split supply
configurations are both possible. The LMH6574 features very high speed channel switching and disable times.
When disabled the LMH6574 output is high impedance making MUX expansion possible by combining multiple
devices. See Multiplexer Expansion.
8.1.1 Multiplexer Expansion
It is possible to use multiple LMH6574 devices to expand the number of inputs that can be selected for output.
Figure 31 shows an 8:1 MUX using two LMH6574 devices.
Figure 31. 8:1 MUX Using Two LMH6574 Devices
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Application Information (continued)
In such an application, the output settling may be longer than the LMH6574 switching specifications (~20ns),
while switching between two separate LMH6574 devices. The switching time limiting factor occurs when one
LMH6574 is turned off and another one is turned on, using the SD (shutdown) pin. The output settling time
consists of the time needed for the first LMH6574 to enter high impedance state plus the time required for the
second LMH6574 output to dissipate the left-over output charge of the first device (limited by the output current
capability of the second device) and the time needed to settle to the final voltage value.
While Figure 31 MUX expansion benefits from more isolation, originating from the parasitic loading of the un-
selected channels on the selected channel, afforded by individual ROUT on each multiplexer output, this
configuration does not produce the fastest transition between individual LMH6574 devices. For the fastest
transition, the configuration of Figure 32 can be used where the LMH6574 output pins are all shorted together.
Figure 32. Alternate 8:1 MUX Expansion Schematic (for Faster SD Switching)
R2D1
C1R1
TO SD
-1.5
-1
-0.5
0
0.5
1
1.5
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
-1E-07 -5E-08 0 5E-08 0.0000001 1.5E-07 0.0000002 2.5E-07
Vout (V)
SD Pin (V)
Time (50 ns/div)
SD_MUX1
SD_MUX2
OUT
145 ns
Settled final value
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Application Information (continued)
Figure 33 shows typical transition waveforms and shows that SD pin switching settles in less than 145 ns.
Figure 33. SD Pin Switching Waveform and Output Settling
If it is important in the end application to make sure that no two inputs are presented to the output at the same
time, an optional delay block can be added, to drive the SHUTDOWN pin of each device. Figure 34 shows one
possible approach to this delay circuit. The delay circuit shown will delay SHUTDOWN's H to L transitions (R1
and C1 decay) but will not delay its L to H transition. R2 should be kept small compared to R1 in order to not
reduce the SHUTDOWN voltage and to produce little or no delay to SHUTDOWN.
Figure 34. Delay Circuit Implementation
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Application Information (continued)
With the SHUTDOWN pin putting the output stage into a high impedance state, several LMH6574’s can be tied
together to form a larger input MUX. However, there is a loading effect on the active output caused by the
unselected devices. The circuit in Figure 35 shows how to compensate for this effect. For the 16:1 MUX function
shown in Figure 35, the gain error would be about −0.8 dB, or about 9%. In the circuit in Figure 35, resistor ratios
have been adjusted to compensate for this gain error. By adjusting the gain of each multiplexer circuit the error
can be reduced to the tolerance of the resistors used (1% in this example).
Figure 35. Multiplexer Gain Compensation
NOTE
Disabling of the LMH6574 using the EN pin is not recommended for use when doing
multiplexer expansion. While disabled, If the voltage between the selected input and the
chip output exceeds approximately 2V the device will begin to enter a soft breakdown
state. This will show up as reduced input to output isolation. The signal on the non-
inverting input of the output driver amplifier will leak through to the inverting input, and
then to the output through the feedback resistor. The worst case is a gain of 1
configuration where the non inverting input follows the active input buffer and (through the
feedback resistor) the inverting input follows the voltage driving the output stage. The
solution for this is to use shutdown mode for multiplexer expansion.
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9 Power Supply Recommendations
9.1 Power Dissipation
The LMH6574 is optimized for maximum speed and performance in the small form factor of the standard SOIC
package. To ensure maximum output drive and highest performance, thermal shutdown is not provided.
Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power
dissipation.
Follow these steps to determine the Maximum power dissipation for the LMH6574:
1. Calculate the quiescent (no-load) power.
PAMP = ICC* (VS)
where
• VS= V+- V−(1)
2. Calculate the RMS power dissipated in the output stage:
PD(rms) = rms ((VS- VOUT) * IOUT)
where
• VOUT is the voltage across the external load
• IOUT is the current through the external load
• VSis the total supply voltage (2)
3. Calculate the total RMS power: PT= PAMP + PD.
The maximum power that the LMH6574 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/RθJA
where
• TAMB = Ambient temperature (°C)
• RθJA = Thermal resistance, from junction to ambient, for a given package (°C/W) (3)
For the SOIC package RθJA is 130 °C/W.
10 Layout
10.1 Layout Guidelines
Whenever questions about layout arise, use the evaluation board LMH730276 as a guide. To reduce parasitic
capacitances, ground and power planes should be removed near the input and output pins. For long signal paths
controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass
capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are
applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller
ceramic capacitors should be placed as close to the device as possible. In the Functional Block Diagram, the
capacitor between V+and V−is optional, but is recommended for best second harmonic distortion. Another way
to enhance performance is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply bypass.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For additional information, see the following:
•Current Feedback Loop Gain Analysis and Performance Enhancement Application Note OA-13
•IC Package Thermal Metrics Application Report
•LMH730276 4:1 Multiplexer Evaluation Board
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6574MA NRND SOIC D 14 55 Non-RoHS
& Green Call TI Call TI -40 to 85 LMH65
74MA
LMH6574MA/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH65
74MA
LMH6574MAX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH65
74MA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6574MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6574MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2018
Pack Materials-Page 2
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