16-Bit, Quad Voltage Output, Serial Input
DIGITAL-TO-ANALOG CONVERTER
DAC7734
DESCRIPTION
The DAC7734 is a 16-bit, quad voltage output, digital-to-
analog converter (DAC) with ensured 16-bit monotonic
performance over the specified temperature range. It accepts
24-bit serial input data, has double-buffered DAC input logic
(allowing simultaneous update of all DACs), and provides a
serial data output for daisy-chaining multiple DACs.
Programmable asynchronous reset clears all registers to a
mid-scale code of 8000h or to a zero-scale of 0000h. The
DAC7734 can operate from a single +15V supply or from
+15V and –15V, and +5V supplies.
Low power and small size per DAC make the DAC7734
ideal for automatic test equipment, DAC-per-pin
programmers, data acquisition systems, and closed-loop
servo-control. The DAC7734 is available in a 48-lead
SSOP package and offers ensured specifications over the
–40°C to +85°C temperature range.
FEATURES
● LOW POWER: 200mW
● UNIPOLAR OR BIPOLAR OPERATION
● SINGLE SUPPLY OUTPUT RANGE: +10V
● DUAL SUPPLY OUTPUT RANGE: ±10V
● SETTLING TIME: 10µs to 0.003%
● 16-BIT MONOTONICITY: –40°C to +85°C
● PROGRAMMABLE RESET TO MID-SCALE
OR ZERO-SCALE
● DOUBLE-BUFFERED DATA INPUTS
● ±1 LSB DNL: –40°C to +85°C
APPLICATIONS
● PROCESS CONTROL
● ATE PIN ELECTRONICS
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
● DAC-PER-PIN PROGRAMMERS
DAC A
DAC
Register A
Input
Register A
Shift
Register
DAC B
DAC
Register B
Input
Register B
DAC C
DAC
Register C
Input
Register C
DAC D
DAC
Register D
Input
Register D
VREFL AB VREFH AB VREFH
AB Sense
VREFL
AB Sense
VOUT
D
VOUT
C
VOUT
B
VOUT
A
VOUT
B
Sense
VREFL CD VREFH CD
SDI
SDO
Control
Logic
CS
CLOCK
RST
RESTSEL
LDAC
LOAD
AGND DGND
VOUT
C
Sense
VOUT
D
Sense
VOUT
A
Sense
VCC
VSS
VDD
DAC7734
VREFL
CD Sense VREFH
CD Sense
DAC7734
SBAS138A – DECEMBER 1999 – REVISED OCTOBER 2008
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999-2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
www.ti.com
www.ti.com
DAC7734
2SBAS138A
www.ti.com
DAC7734E DAC7734EB DAC7734EC
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Linearity Error (INL) T = 25°C±3✻±2LSB
TMIN to TMAX ±4✻±3LSB
Linearity Match ±4✻±2LSB
Differential Linearity Error
(DNL)
T = 25°C±3±2±1LSB
TMIN to TMAX ±3±2±1LSB
Monotonicity, TMIN to TMAX 14 15 16 Bits
Bipolar Zero Error
T = 25°C±0.01 ±0.025 ✻✻% of FSR
Bipolar Zero Error, T
MIN
to T
MAX
±0.05 ✻✻% of FSR
Full-Scale Error T = 25°C±0.025 ✻✻% of FSR
Full-Scale Error, TMIN to TMAX ±0.05 ✻✻% of FSR
Bipolar Zero Matching Channel-to-Channel ±0.024 ✻✻% of FSR
Matching
Full-Scale Matching Channel-to-Channel ±0.024 ✻✻% of FSR
Matching
Power Supply Rejection Ratio (PSRR)
At Full Scale 25 ✻✻ppm/V
ANALOG OUTPUT
Voltage Output VREFLV
REFH✻✻✻✻V
Output Current ±5✻✻ mA
Maximum Load Capacitance 500 ✻✻pF
Short-Circuit Current ±20 ✻✻mA
Short-Circuit Duration To VSS, VCC or GND Indefinite ✻✻
REFERENCE INPUT
Ref High Input Voltage Range
VREFL + 1.25
+10 ✻✻✻✻V
Ref Low Input Voltage Range –10
VREFH – 1.25
✻✻✻✻V
Ref High Input Current –0.3 2.6 ✻✻mA
Ref Low Input Current –3.2 –0.3 ✻✻mA
DYNAMIC PERFORMANCE
Settling Time To ±0.003%, 20V 9 11 ✻✻ ✻✻ µs
Output Step
Channel-to-Channel Crosstalk See Figure 5 0.5 ✻✻LSB
Digital Feedthrough 2 ✻✻nV-s
Output Noise Voltage f = 10kHz 60 ✻✻nV/√Hz
DIGITAL INPUT
VIH 0.7 • VDD VDD ✻✻ V
VIL 0 0.3 • VDD ✻V
IIH ±10 ✻µA
IIL ±10 ✻µA
DIGITAL OUTPUT
VOH IOH = –0.8mA 3.6 4.5 ✻✻ ✻✻ V
VOL IOL = 1.6mA 0.3 0.4 ✻✻ ✻✻ V
POWER SUPPLY
VDD +4.75 +5.0 +5.25 ✻✻✻✻✻✻ V
VCC +14.25 +15.0 +15.75 ✻✻✻✻✻✻ V
VSS –14.25 –15.0 –15.75 ✻✻✻✻✻✻ V
IDD 50 ✻✻µA
ICC 6✻✻mA
ISS –5✻✻mA
Power 170 200 ✻✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻✻✻°C
✻ Specifications same as grade to the left.
SPECIFICATIONS (Dual Supply)
At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, and VREFL = –10V, unless otherwise noted.
DAC7734 3
SBAS138A www.ti.com
DAC7734E DAC7734EB DAC7734EC
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Linearity Error(1) (INL) T = 25°C±3✻±2LSB
TMIN to TMAX ±4✻±3LSB
Linearity Match ±4✻±2LSB
Differential Linearity Error
(DNL)
T = 25°C±3±2±1LSB
TMIN to TMAX ±3±2±1LSB
Monotonicity, TMIN to TMAX 14 15 16 Bits
Unipolar Zero T = 25°C±0.01 ±0.025 ✻✻% of FSR
Unipolar Zero Error,
TMIN to TMAX
±0.05 ✻✻% of FSR
Full-Scale Error T = 25°C±0.025 ✻✻% of FSR
Full-Scale Error,
TMIN to TMAX
±0.05 ✻✻% of FSR
Unipolar Zero Matching Channel-to-Channel ±0.024 ✻✻% of FSR
Matching
Full-Scale Matching Channel-to-Channel ±0.024 ✻✻% of FSR
Matching
Power Supply Rejection Ratio (PSRR)
At Full Scale 25 ✻✻ppm/V
ANALOG OUTPUT
Voltage Output VREFL = 0V, VSS = 0V 0 VREFH✻✻✻✻V
R = 10kΩ
Output Current ±5✻✻ mA
Maximum Load Capacitance 500 ✻✻pF
Short-Circuit Current ±20 ✻✻mA
Short-Circuit Duration To VCC or GND Indefinite ✻✻
REFERENCE INPUT
Ref High Input Voltage Range
VREFL + 1.25
+10 ✻✻✻✻V
Ref Low Input Voltage Range 0
VREFH – 1.25
✻✻✻✻V
Ref High Input Current –0.3 1.0 ✻✻mA
Ref Low Input Current –1.5 –0.3 ✻✻mA
DYNAMIC PERFORMANCE
Settling Time To ±0.003%, 10V 8 10 ✻✻ ✻✻ µs
Output Step
Channel-to-Channel Crosstalk See Figure 6 0.5 ✻✻LSB
Digital Feedthrough 2 ✻✻nV-s
Output Noise Voltage f = 10kHz 60 ✻✻nV/√Hz
DIGITAL INPUT
VIH 0.7 • VDD VDD ✻✻ V
VIL 0 0.3 • VDD ✻V
IIH ±10 ✻µA
IIL ±10 ✻µA
DIGITAL OUTPUT
VOH IOH = –0.8mA 3.6 4.5 ✻✻ ✻✻ V
VOL IOL = 1.6mA 0.3 0.4 ✻✻ ✻✻ V
POWER SUPPLY
VDD +4.75 +5.0 +5.25 ✻✻✻✻✻✻ V
VCC +14.25 +15.0 +15.75 ✻✻✻✻✻✻ V
VSS 0✻✻V
IDD 50 ✻✻µA
ICC 3.5 ✻✻mA
Power 50 70 ✻✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻✻✻°C
✻ Specifications same as grade to the left.
NOTE: (1) If VSS = 0V, the specification applies at code 0021H and above, due to possible negative zero scale error.
SPECIFICATIONS (Single Supply)
At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = GND, VREFH = +10V, and VREFL = +50mV, unless otherwise noted.
DAC7734
4SBAS138A
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
VCC to VSS ........................................................................... –0.3V to +32V
VCC to AGND ...................................................................... –0.3V to +16V
VSS to AGND ...................................................................... +0.3V to –16V
AGND to DGND................................................................. –0.3V to +0.3V
VREFH to AGND .....................................................................–9V to +11V
VREFL to AGND...................................................................... –11V to +9V
VDD to GND........................................................................... –0.3V to +6V
VREFH to VREFL ........................................................................ –1V to 22V
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND................................. –0.3V to VDD + 0.3V
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
NOTE: (1) Stresses above those listed under
Absolute Maximum Ratings
may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
LINEARITY DIFFERENTIAL SPECIFIED
ERROR NONLINEARITY PACKAGE TEMPERATURE ORDERING TRANSPORT
PRODUCT (LSB) (LSB) PACKAGE DESIGNATOR RANGE NUMBER MEDIA, QUANTITY
DAC7734E ±4±3 SSOP-48 333 –40°C to +85°C DAC7734E Rails, 30
""""" "DAC7734E/1K Tape and Reel, 1000
DAC7734EB ±4±2 SSOP-48 333 –40°C to +85°C DAC7734EB Rails, 30
""""" "DAC7734EB/1K Tape and Reel, 1000
DAC7734EC ±3±1 SSOP-48 333 –40°C to +85°C DAC7734EC Rails, 30
""""" "DAC7734EC/1K Tape and Reel, 1000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
ESD PROTECTION CIRCUITS
RefH V
OUT
Sense
V
CC
V
SS
V
DD
DGND
V
CC
AGND
V
SS
V
DD
DGND
V
OUT
RefH Sense
RefL Sense
RefL
1 of 2 1 of 4
Typ of Each
Logic Input Pin
SDO
DAC7734 5
SBAS138A www.ti.com
Top View SSOP
PIN CONFIGURATION
NC
NC
SDI
DGND
CLK
DGND
LDAC
DGND
LOAD
DGND
CS
DGND
SDO
DGND
RSTSEL
DGND
RST
DGND
NC
NC
DGND
DGND
V
DD
V
DD
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
V
OUT
C Sense
V
OUT
C
V
REF
H CD Sense
V
REF
H CD
V
REF
L CD
V
REF
L CD Sense
V
OUT
D Sense
V
OUT
D
V
SS
V
SS
AGND
AGND
V
CC
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7734
PIN NAME DESCRIPTION
1 NC No Connection
2 NC No Connection
3 SDI Serial Data Input
4 DGND Digital Ground
5 CLK Data Clock Input
6 DGND Digital Ground
7 LDAC DAC Register Load Control, Rising Edge
Triggered
8 DGND Digital Ground
9 LOAD DAC Input Register Load Control, Active Low
10 DGND Digital Ground
11 CS Chip Select, Active Low
12 DGND Digital Ground
13 SDO Serial Data Output
14 DGND Digital Ground
15 RSTSEL Reset Select. Determines the action of RST. If
HIGH, a RST common will set the DAC registers
to mid-scale (8000H). If LOW, a RST command
will set the DAC registers to zero (0000H).
16 DGND Digital Ground
17 RST Reset, Rising Edge Triggered. Depending on the
state of RSTSEL, the DAC registers are set to
either mid-scale or zero.
18 DGND Digital Ground
19 NC No Connection
20 NC No Connection
21 DGND Digital Ground
22 DGND Digital Ground
23 VDD Digital +5V Power Supply
24 VDD Digital +5V Power Supply
25 VCC Analog +15V Power Supply
26 VCC Analog +15V Power Supply
27 AGND Analog Ground
28 AGND Analog Ground
29 VSS Analog –15V Power Supply or 0V Single Supply
30 VSS Analog –15V Power Supply or 0V Single Supply
31 VOUTD DAC D Output Voltage
32 VOUTD Sense DAC D’s Output Amplifier Inverting Input. Used
to close feedback loop at load.
33 VREFL CD Sense DAC C and D Reference Low Sense Input
34 VREFL CD DAC C and D Reference Low Input
35 VREFH CD DAC C and D Reference High Input
36 VREFH CD Sense DAC C and D Reference High Sense Input
37 VOUTC DAC C Output Voltage
38 VOUTC Sense DAC C’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
39 VOUTB DAC B Output Voltage
40 VOUTB Sense DAC B’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
41 VREFH AB Sense DAC A and B Reference High Sense Input
42 VREFH AB DAC A and B Reference High Input
43 VOUTL AB DAC A and B Reference Low Input
44 VREFL AB Sense DAC A and B Reference Low Sense Input
45 VSS Analog –15V Power Supply or 0V Single Supply
46 AGND Analog Ground
47 VOUTA DAC A Output Voltage
48 VOUTA Sense DAC A’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
PIN DESCRIPTIONS
DAC7734
6SBAS138A
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
+25°C
+85°C
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
DAC7734 7
SBAS138A www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
+85°C (cont.)
–40°C
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
DAC7734
8SBAS138A
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
V
REF
(Current (mA)
REFERENCE CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC A and B)
V
REFH
V
REFL
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
V
REF
(Current (mA)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
V
REF
(Current (mA)
REFERENCE CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC C and D)
V
REFH
V
REFL
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
V
REF
(Current (mA)
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
Temperature (°C)
–40 –30 –10 0–20 10 20 40 5030 70 80 9060
ZERO-SCALE ERROR vs TEMPERATURE
Negative Full-Scale Error (mV)
Code (0040
H
)Code (0000
H
)
DAC D
DAC A
DAC C DAC B
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
Temperature (°C)
–40 –30 –10 0–20 10 20 40 5030 70 80 9060
POSITIVE FULL-SCALE ERROR
vs TEMPERATURE
Positive Full-Scale Error (mV)
DAC A
DAC D
DAC B
DAC C
Code (FFFF
H
)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
Temperature (°C)
–40 –30 –10 0–20 10 20 40 5030 70 80 9060
POWER SUPPLY CURRENT vs TEMPERATURE
Quiescent Current (mA)
I
CC
I
DD
Data = FFFF
H
(all DACs)
No Load
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
Digital Input Code
0 2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
I
CC
(mA)
No Load I
CC
I
DD
DAC7734 9
SBAS138A www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
+5V
LDAC
0
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +10V)
Output Voltage
+5V
LDAC
0
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to 0V)
Output Voltage
+5V
LDAC
0
Time (1µs/div)
OUTPUT VOLTAGE
MIDSCALE GLITCH PERFORMANCE
Output Voltage (200mV/div)
+5V
LDAC
0
Time (1µs/div)
Output Voltage (200mV/div)
OUTPUT VOLTAGE
MIDSCALE GLITCH PERFORMANCE
BROADBAND NOISE
Time (100µs/div)
Noise Voltage (20µV/div)
BW = 10kHz
Code = 8000H
120
100
80
60
40
20
0
Frequency (Hz)
100 1k 10k 100k 1M
OUTPUT NOISE VOLTAGE vs FREQUENCY
Noise (nV/√Hz)
Large-Signal Settling Time: 5V/div
Small-Signal Settling Time:
3LSB/div
Large-Signal Settling Time: 5V/div
Small-Signal Settling Time:
3LSB/div
7FFFH to 8000H8000H to 7FFFH
DAC7734
10 SBAS138A
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
16
14
12
10
8
6
4
2
0
R
LOAD
(kΩ)
0.01 0.1 1 10 100
OUTPUT VOLTAGE vs R
LOAD
V
OUT
(V)
Source
Sink
30
25
20
15
10
5
0
–5
–10
–15
–20
–25
–30
Input Code
0000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
SINGLE-SUPPLY CURRENT LIMIT vs INPUT CODE
IOUT (mA)
Short to Ground
Short to VCC
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
Frequency (Hz)
100 1k 10k 100k 1M
POWER SUPPLY REJECTION RATIO vs FREQUENCY
PSRR (dB)
+15V
+5V
+5V
CLK
0V
Time (50ns/div)
CLOCK FEEDTHROUGH
Output Voltage (5mV/div)
DAC7734 11
SBAS138A www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = –15V
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
+85°C
+25°C
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
DAC7734
12 SBAS138A
www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
+85°C (cont.)
–40°C
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
DAC7734 13
SBAS138A www.ti.com
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
2.5
2.0
1.5
1.0
0.5
0
–0.5
V
REF
(Current (mA)
REFERENCE CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC A and B)
VREFH
VREFL
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
V
REF
(Current (mA)
2.5
2.0
1.5
1.0
0.5
0
–0.5
V
REF
(Current (mA)
REFERENCE CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC C and D)
VREFH
VREFL
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
V
REF
(Current (mA)
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
Temperature (°C)
–40 –30 –20 –100 102030405060708090
BIPOLAR ZERO SCALE ERROR vs TEMPERATURE
(Code 8000
H
)
Bipolar Zero Scale Error (mV)
DAC A
DAC D DAC C
DAC B
2
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Temperature (°C)
–40 –10 0–30 –20 9010 20 30 40 50 60 70 80
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFF
H
)
Positive Full-Scale Error (mV)
DAC A
DAC B DAC D DAC C
2
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Temperature (°C)
–40 –10 0–30 –20 9010 20 30 40 50 60 70 80
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 0000
H
)
Negative Full-Scale Error (mV)
DAC A
DAC D DAC B DAC C
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
Temperature (°C)
–40 –10 0–30 –20 9010 20 30 40 50 60 70 80
POWER SUPPLY CURRENT vs TEMPERTURE
Quiescent Current (mA)
I
SS
I
CC
I
DD
Data = FFFF
H
(all DACs)
No Load
DAC7734
14 SBAS138A
www.ti.com
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(–10V to +10V)
Output Voltage
+5V
LDAC
0
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
15
10
5
0
–5
–10
–15
RLOAD (kΩ)
0.01 0.1 1 10 100
OUTPUT VOLTAGE vs RLOAD
VOUT (V)
Sink
Source
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
SUPPLY CURRENT vs CODE
(mA)
Digital Input Code
0000H2000H4000H6000H8000HA000HC000HE000HFFFFH
I
CC
I
DD
I
SS
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to –10V)
Output Voltage
+5V
LDAC
0
20
15
10
5
0
–5
–10
–15
–20
Digital Input Code
0000H2000H4000H6000H8000HA000HC000HE000HFFFFH
DUAL-SUPPLY CURRENT LIMIT vs INPUT CODE
(Short-to-Ground)
IOUT (mA)
Large-Signal Settling Time: 5V/div
Small-Signal Settling Time: 3LSB/div
Large-Signal Settling Time: 5V/div
Small-Signal Settling Time: 3LSB/div
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Frequency (Hz)
100 1k 10k 100k 1M
POWER SUPPLY REJECTION RATIO vs FREQUENCY
PSRR (dB)
–15V +15V
+5V
DAC7734 15
SBAS138A www.ti.com
Time (1µs/div)
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
Output Voltage (200mV/div)
+5V
LDAC
0
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
Time (1µs/div)
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
Output Voltage (200mV/div)
+5V
LDAC
0
7FFFH to 8000H8000H to 7FFFH
DAC7734
16 SBAS138A
www.ti.com
THEORY OF OPERATION
The DAC7734 is a quad voltage output, 16-bit Digital-to-
Analog Converter (DAC). The architecture is an R-2R
ladder configuration with the three MSBs segmented, fol-
lowed by an operational amplifier that serves as a buffer.
Each DAC has its own R-2R ladder network, segmented
MSBs, and output op amp, as shown in Figure 1. The
minimum voltage output (zero-scale) and maximum voltage
output (full-scale) are set by the external voltage references
VREFL and VREFH.
The digital input is a 24-bit serial word that contains a 2-bit
address code for selecting one of four DACs, a quick load
bit, five unused bits, and the 16-bit DAC code (MSB first).
The converters can be powered from either a single +15V
supply or a dual ±15V supply and a +5V logic supply. The
device offers a reset function that immediately sets all DAC
output voltages and DAC registers to mid-scale code 8000H
or to zero-scale, code 0000H. See Figures 2 and 3 for the
basic operation of the DAC7734.
FIGURE 1. DAC7734 Architecture.
FIGURE 2. Basic Single-Supply Operation of the DAC7734.
R
2R
2R2R 2R 2R 2R 2R 2R 2R
V
REF
H
V
OUT
V
OUT
Sense
V
REF
H Sense
V
REF
L
V
REF
L Sense
R
F
NC
NC
SDI
DGND
CLK
DGND
LDAC
DGND
LOAD
DGND
CS
DGND
SDO
DGND
RSTSEL
DGND
RST
DGND
NC
NC
DGND
DGND
VDD
VDD
VOUTA Sense
VOUTA
AGND
VSS
VREFL AB Sense
VREFL AB
VREFH AB
VREFH AB Sense
VOUTB Sense
VOUTB
VOUTC Sense
VOUTC
VREFH CD Sense
VREFH CD
VREFL CD
VREFL CD Sense
VOUTD Sense
VOUTD
VSS
VSS
AGND
AGND
VCC
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7734
Reset DAC Registers
Chips Select
Serial Data Out
Serial Data In
Clock
Load DAC Registers
Load
NC = No Connection
0V to +10V
0V to +10V
0V to +10V
0V to +10V
+10.000V
+10.000V
+15V
0.1µF1µF
+
0.1µF
1µF
+5V +
DAC7734 17
SBAS138A www.ti.com
FIGURE 3. Basic Dual-Supply Operation of the DAC7734.
ANALOG OUTPUTS
When VSS = –15V (dual-supply operation), the output am-
plifier can swing to within 4V of the supply rails, ensured
over the –40°C to +85°C temperature range. When
VSS = 0V (single-supply operation), and with RLOAD also
connected to ground, the output can swing to ground. Care
must also be taken when measuring the zero-scale error
when VSS = 0V. Since the output voltage cannot swing
below ground, the output voltage may not change for the
first few digital input codes (0000H, 0001H, 0002H, etc.) if
the output amplifier has a negative offset. At the negative
limit of –5mV, the first specified output starts at code 0021H.
Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance become
very important. A 16-bit converter with a 10V full-scale
range has a 1LSB value of 152µV. With a load current of
1mA, series wiring and connector resistance of only 150mΩ
(RW2) will cause a voltage drop of 150µV, as shown in
Figure 4. To understand what this means in terms of a
system layout, the resistivity of a typical 1-ounce copper-
clad printed circuit board is 1/2 mΩ per square. For a 1mA
load, a 20 milli-inch wide printed circuit conductor 6 inches
long will result in a voltage drop of 150µV.
The DAC7734 offers a force and sense output configuration
for the high open-loop gain output amplifier. This feature
allows the loop around the output amplifier to be closed at
the load (as shown in Figure 4), thus ensuring an accurate
output voltage.
FIGURE 4. Analog Output Closed-Loop Configuration
(1/2 DAC7734). RW represents wiring resis-
tances.
NC
NC
SDI
DGND
CLK
DGND
LDAC
DGND
LOAD
DGND
CS
DGND
SDO
DGND
RSTSEL
DGND
RST
DGND
NC
NC
DGND
DGND
VDD
VDD
VOUTA Sense
VOUTA
AGND
VSS
VREFL AB Sense
VREFL AB
VREFH AB
VREFH AB Sense
VOUTB Sense
VOUTB
VOUTC Sense
VOUTC
VREFH CD Sense
VREFH CD
VREFL CD
VREFL CD Sense
VOUTD Sense
VOUTD
VSS
VSS
AGND
AGND
VCC
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7734
Reset DAC Registers
Chips Select
Serial Data Out
Serial Data In
Clock
Load DAC Registers
Load
NC = No Connection
–10V to +10V
–10V to +10V
–10V to +10V
–10V to +10V
+10.000V
+10.000V
–10.000V
–10.000V
+5V
+15V
0.1µF1µF
1µF
+0.1µF
0.1µF 1µF
–15V
–15V
+5V
+
+
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7734
R
W1
R
W2
+10V
+V
V
OUT
R
W1
R
W2
V
OUT
DAC7734
18 SBAS138A
www.ti.com
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 4V and VCC – 4V, provided that VREFH is at
least 1.25V greater than VREFL. The minimum output of
each DAC is equal to VREFL plus a small offset voltage
(essentially, the offset of the output op amp). The maximum
output is equal to VREFH plus a similar offset voltage. Note
that VSS (the negative power supply) must either be
connected to ground or must be in the range of –14.25V to
–15.75V. The voltage on VSS sets several bias points within
the converter. If VSS is not in one of these two configura-
tions, the bias values may be in error and proper operation
of the device is not ensured.
The current into the VREFH input and out of VREFL depends
on the DAC output voltages, and can vary from a few
microamps to approximately 2.0mA. The reference input
appears as a varying load to the reference. The DAC7734
features a reference drive and sense connection such that the
internal errors caused by the changing reference current and
the circuit impedances can be minimized. Figures 5 through
9 show different reference configurations, and the effect on
the linearity and differential linearity.
The analog supplies must come up first. If VCC and VSS do not
come up together, then VSS should come up first. If the power
supplies for the reference come up first, then the VCC and VSS
supplies will be powered from the reference via the ESD
protection diode; see the ESD protection circuits on page 4.
FIGURE 5. Dual-Supply Configuration-Buffered References, used for Dual-Supply Performance (1/2 DAC7734).
FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV used for Single-Supply Performance Curves
(1/2 DAC7734).
+10V
+V
–10V
–V
V
OUT
–15V
V
OUT
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7734 2200pF
100Ω
1000pF
1000pF 2200pF
+V
OPA2234
–V
100Ω
V
OUT
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7734
+10V
+V
OPA350
OPA227
99.5kΩ
+0.050V
500Ω
50Ω
V
OUT
NOTE: V
REF
L has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp.
2200pF
100Ω
1000pF
1000pF 2200pF
+V
100Ω
DAC7734 19
SBAS138A www.ti.com
FIGURE 8. Dual-Supply Buffered Reference with VREFL = –5V and VREFH = +5V (1/2 DAC7734).
+5V
+V
–5V
–V
V
OUT
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7734
OPA2234
V
OUT
2200pF
100Ω
1000pF
1000pF 2200pF
+V
–V
100Ω
FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 8.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, 25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
DAC7734
20 SBAS138A
www.ti.com
FIGURE 9. Single-Supply Buffered Reference with a Reference Low of 50mV and Reference High of +5V.
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7734
V
OUT
V
OUT
99kΩ
0.05V
1kΩ
+5V
+V
1000pF
2200pF
+V
OPA350
OPA227
100Ω
1000pF 2200pF
100Ω
NOTE: V
REF
L has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp.
50Ω
FIGURE 10. Integral Linearity and Differential Linearity Error Curves for Figure 9.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, 25°C)
0000H2000H4000H6000H8000H
Digital Input Code
A000HC000HE000HFFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
DAC7734 21
SBAS138A www.ti.com
INPUT DAC
A1 A0 CS RST RSTSEL
LDAC
LOAD REGISTER REGISTER MODE DAC
L L L H X X L Write Hold Write Input A
L H L H X X L Write Hold Write Input B
H L L H X X L Write Hold Write Input C
H H L H X X L Write Hold Write Input D
XXHHX↑H Hold Write Update All
X X H H X H H Hold Hold Hold All
XXX↑L X X Reset to Zero Reset to Zero Reset to Zero All
XXX↑H X X Reset to Midscale Reset to Midscale Reset to Midscale All
TABLE I. DAC7734 Logic Truth Table.
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7734. The
interface consists of a Signal Data Clock (CLK) input, Serial
Data (SDI), DAC Input Register Load Control Signal
(LOAD), and DAC Register Load Control Signal (LDAC).
In addition, a Chip Select (CS) input is available to enable
serial communication when there are multiple serial devices.
An asynchronous Reset (RST) input, by the rising edge, is
provided to simplify start-up conditions, periodic resets, or
emergency resets to a known state, depending on the status
of the reset select (RSTSEL) signal.
The DAC code, quick load control, and address are provided
via a 24-bit serial interface (see Table I). The first two bits
shifted into the shift register, B23 and B22, are the DAC
register address. These bits select the input register that will
be updated when LOAD goes LOW. The third bit, B21, is a
“Quick Load” bit such that if HIGH, the code in the shift
register is loaded into ALL DAC input registers when the
LOAD signal goes LOW, independent of the state of the
address bits, B23 and B22. If the “Quick Load” bit is LOW,
the contents of the shift register is loaded only to the DAC
register that is addressed. Bits B20 through B16 are not used
and can assume any logical value. The last sixteen bits, B15
through B0, make up the DAC code to be loaded into the
selected input register.
The internal DAC register is edge-triggered and not level-
triggered. When the LDAC signal is transitioned from LOW
to HIGH, the digital word currently in the DAC input
register is latched. The first set of registers (the DAC input
registers) are level triggered via the LOAD signal. This
double-buffered architecture has been designed so that new
data can be entered for each DAC without disturbing the
analog outputs. When the new data has been entered into the
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
QUICK
LOAD
SERIAL DATA INPUT
device, all of the DAC outputs can be updated simulta-
neously by the rising edge of LDAC. Additionally, it allows
the DAC input registers to be written to at any point, then the
DAC output voltages can be synchronously changed via a
trigger signal (LDAC).
Note that CS and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. In addition, care must be
taken with the state of CLK when CS rises at the end of a
serial transfer. If CLK is LOW when CS rises, the OR gate
will provide a rising edge to the shift register, shifting the
internal data one additional bit. The result will be incorrect
data and possible selection of the wrong input register(s). If
both CS and CLK are used, CS should rise only when CLK
is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table II for more information.
CS(1) CLK(1)
LOAD
RST SERIAL SHIFT REGISTER
H(2) X(3) H H No Change
L(4) L H H No Change
L↑(5) H H Advanced One Bit
↑L H H Advanced One Bit
H(6) XL
(7) H No Change
H(6) XH↑(8) No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a “false clock” from advancing
the shift register and changing the shift register. (7) If data is clocked into the
serial register while LOAD is LOW, the selected DAC register will change as
the shift register bits “flow” through A1 and A0. This will corrupt the data in
each DAC register that has been erroneously selected. (8) Rising edge of RST
causes no change in the contents of the serial shift register.
TABLE II. Serial Shift Register Truth Table.
DAC7734
22 SBAS138A
www.ti.com
(1)
VVL
VHVLN
OUT REF REF REF
=+
()
–•
,65 536
FIGURE 11. Daisy-Chaining DAC7734.
SERIAL-DATA OUTPUT
The Serial-Data Output (SDO) is the internal shift register
output. For DAC7734, the SDO is a driven output and does
not require an external pull-up. Any number of DAC7734s
can be daisy-chained by connecting the SDO pin of one
device to the SDI pin of the following device in the chain,
as shown in Figure 11.
DIGITAL TIMING
Figure 12 and Table III provide detailed timing for the
digital interface of the DAC7734.
DIGITAL INPUT CODING
The DAC7734 input data is in Straight Binary format. The
output voltage is given by Equation 1. (2)
IVHVL
R
VLR
OUT REF REF
SENSE
REF SENSE
=
+
()
–•,
/
N
65 536
DIGITALLY-PROGRAMMABLE
CURRENT SOURCE
The DAC7734 offers a unique set of features that allows a
wide range of flexibility in designing applications circuits
such as programmable current sources. The DAC7734 offers
both a differential reference input, as well as an open-loop
configuration around the output amplifier. The open-loop
configuration around the output amplifier allows a transistor
to be placed within the loop to implement a digitally-
programmable, unidirectional current source. The availabil-
ity of a differential reference allows programmability for
both the full-scale and zero-scale currents. The output cur-
rent is calculated as:
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
DAC7734
CLK
SDI
CS
SCK
DIN
CS
LDAC
SDO
DAC7734
CLK
SDI
CS
SDO
LOAD
DAC7734
LOAD LOAD LOAD
CLK
SDI
CS
LDAC LDAC LDAC
SDO
To
Other
Serial
Devices
DAC7734 23
SBAS138A www.ti.com
SYMBOL DESCRIPTION MIN MAX UNITS
tDS Data Valid to CLK Rising 10 ns
tDH Data Held Valid after CLK Rises 20 ns
tCH CLK HIGH 25 ns
tCL CLK LOW 25 ns
tCSS CS LOW to CLK Rising 15 ns
tCSH CLK HIGH to CS Rising 0 ns
tLD1 LOAD HIGH to CLK Rising 10 ns
tLD2 CLK Rising to LOAD LOW 30 ns
tLDRW LOAD LOW Time 30 ns
tLDDL LDAC LOW Time 40 ns
tLDDH LDAC HIGH Time 40 ns
tSDO SDO Propagation Delay 10 45 ns
tRSSS RESETSEL Valid to RESET HIGH 0 ns
tRSSH RESET HIGH to RESETSEL Not Valid 100 ns
tRSTL RESET LOW Time 10 ns
tRSTH RESET HIGH Time 10 ns
tLDDD LOAD LOW to LDAC Rising Time 40 ns
tSSettling Time 11 (dual)/10(single) µs
TABLE III. Timing Specifications (TA = –40°C to +85°C).
FIGURE 12. Digital Input and Output Timing.
A1
(LSB)
SDI
CLK
CS
LOAD
A0 D3 D2 D1 D0
SDI
CLK
LDAC
RESET
V
OUT
tcss
t
LD1
t
CL
t
SDO
t
CH
t
DS
t
DH
t
LD2
t
LDRW
t
S
t
RSTH
t
RSTL
t
RSSS
t
RSSH
SDO
t
CSH
t
S
±0.003%
ERROR BAND ±0.003%
ERROR BAND
RESETSEL
D15 D14 D13XXXXX
QUICK
LOAD
(MSB)
t
LDDD
LDAC
t
LDDH
t
LDDL
DAC7734
24 SBAS138A
www.ti.com
(3)
FIGURE 13. 4-to-20mA Digitally Controlled Current Source (1/2 DAC7734).
I
OUT
V
PROGRAMMED
R
SENSE
250Ω
I
OUT
V
PROGRAMMED
R
SENSE
250Ω
V
OUT
A Sense
V
OUT
A
AGND
V
SS
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
DAC7734
5V
OPA2350
80kΩ
20kΩ
1.0V
2200pF
100Ω
1000pF
1000pF 2200pF
+V
+V
100Ω
IVV N V
OUT
=
+
51
250 65 536 1
250
–•,ΩΩ
Figure 13 shows a DAC7734 in a 4mA to 20mA current
output configuration. The output current can be determined
by Equation 3:
At full-scale, the output current is 16mA, plus the 4mA, for
the zero current. At zero scale, the output current is the offset
current of 4mA (1V/250Ω).
DAC7734 25
SBAS138A www.ti.com
DATE REVISION PAGE SECTION DESCRIPTION
1—Updated front page format to current standard; some page layout changed.
23 Table III Changed symbol from "tLDDWL" to "tLDDL" (typo).
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
10/08 A
PACKAGE OPTION ADDENDUM
www.ti.com 11-Sep-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC7734E ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DAC7734E/1K ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC7734E/1KG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC7734EB ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC7734EBG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC7734EC ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DAC7734EC/1K ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC7734EC/1KG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC7734ECG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Contact TI Distributor
or Sales Office
DAC7734EG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Contact TI Distributor
or Sales Office
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Sep-2010
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC7734E/1K SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
DAC7734EC/1K SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC7734E/1K SSOP DL 48 1000 367.0 367.0 55.0
DAC7734EC/1K SSOP DL 48 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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