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DRIVER
VDD
UVLO
HO
DRIVER
HB
UVLO
LEVEL
SHIFT
HB
HS
IN
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EDGE
DELAY
LEADING
EDGE
DELAY
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VSS
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LM5106
SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
LM5106 100-V Half-Bridge Gate Driver With Programmable Dead-Time
1 Features 3 Description
The LM5106 is a high-voltage gate driver designed to
1• Drives Both a High-Side and Low-Side N-Channel drive both the high-side and low-side N-channel
MOSFET MOSFETs in a synchronous buck or half-bridge
• 1.8-A Peak Output Sink Current configuration. The floating high-side driver can work
• 1.2-A Peak Output Source Current with rail voltages up to 100 V. The single control input
is compatible with TTL signal levels and a single
• Bootstrap Supply Voltage Range up to 118-V DC external resistor programs the switching transition
• Single TTL Compatible Input dead-time through tightly matched turnon delay
• Programmable Turnon Delays (Dead-Time) circuits. The robust level shift technology operates at
high speed while consuming low power and provides
• Enable Input Pin clean output transitions. Undervoltage lockout
• Fast Turnoff Propagation Delays (32 ns Typical) (UVLO) disables the gate driver when either the low
• Drives 1000 pF With 15-ns Rise and 10-ns Fall side or the bootstrapped high-side supply voltage is
Time below the operating threshold. The LM5106 is offered
in the 10-pin VSSOP or the thermally enhanced 10-
• Supply Rail Undervoltage Lockout pin WSON plastic package.
• Low Power Consumption
• 10-Pin WSON Package (4 mm × 4 mm) and 10- Device Information(1)
Pin VSSOP Package PART NUMBER PACKAGE BODY SIZE (NOM)
VSSOP (10) 3.00 mm × 3.00 mm
2 Applications LM5106 WSON (10) 4.00 mm × 4.00 mm
• Solid-State Motor Drives (1) For all available packages, see the orderable addendum at
• Half-Bridge and Full-Bridge Power Converters the end of the datasheet.
• Two Switch Forward Power Converters
Simplified Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5106
SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
www.ti.com
Table of Contents
7.3 Feature Description................................................. 11
1 Features.................................................................. 17.4 Device Functional Modes........................................ 11
2 Applications ........................................................... 18 Application and Implementation ........................ 12
3 Description............................................................. 18.1 Application Information............................................ 12
4 Revision History..................................................... 28.2 Typical Application ................................................. 12
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 14
6 Specifications......................................................... 49.1 Power Dissipation Considerations .......................... 14
6.1 Absolute Maximum Ratings ...................................... 410 Layout................................................................... 15
6.2 ESD Ratings.............................................................. 410.1 Layout Guidelines ................................................. 15
6.3 Recommended Operating Conditions....................... 410.2 Layout Example .................................................... 16
6.4 Thermal Information.................................................. 511 Device and Documentation Support................. 17
6.5 Electrical Characteristics........................................... 511.1 Trademarks........................................................... 17
6.6 Switching Characteristics.......................................... 611.2 Electrostatic Discharge Caution............................ 17
6.7 Typical Characteristics.............................................. 811.3 Glossary................................................................ 17
7 Detailed Description............................................ 11 12 Mechanical, Packaging, and Orderable
7.1 Overview................................................................. 11 Information........................................................... 17
7.2 Functional Block Diagram....................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2013) to Revision D Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 12
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VDD
HB
HO
HS
LO
VSS
IN
EN
110
29
38
47
NC RDT
56
LM5106
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SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
5 Pin Configuration and Functions
10-Pin
VSSOP (DGS), WSON (DPR)
Top View
Pin Functions
PIN DESCRIPTION APPLICATION INFORMATION
NO. NAME
1 VDD Positive gate drive supply Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close to
the IC as possible.
2 HB High-side gate driver Connect the positive terminal of bootstrap capacitor to the HB pin and
bootstrap rail connect negative terminal to HS. The Bootstrap capacitor should be placed
as close to IC as possible.
3 HO High-side gate driver output Connect to the gate of high-side N-MOS device through a short, low
inductance path.
4 HS High-side MOSFET source Connect to the negative terminal of the bootststrap capacitor and to the
connection source of the high-side N-MOS device.
5 NC Not connected
6 RDT Dead-time programming pin A resistor from RDT to VSS programs the turnon delay of both the high- and
low-side MOSFETs. The resistor should be placed close to the IC to
minimize noise coupling from adjacent PC board traces.
7 EN Logic input for driver TTL compatible threshold with hysteresis. LO and HO are held in the low
Disable/Enable state when EN is low.
8 IN Logic input for gate driver TTL compatible threshold with hysteresis. The high-side MOSFET is turned
on and the low-side MOSFET turned off when IN is high.
9 VSS Ground return All signals are referenced to this ground.
10 LO Low-side gate driver output Connect to the gate of the low-side N-MOS device with a short, low
inductance path.
— EP Exposed Pad The exposed pad has no electrical contact. Connect to system ground plane
for reduced thermal resistance.
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN MAX UNIT
VDD to VSS –0.3 18 V
HB to HS –0.3 18 V
IN and EN to VSS –0.3 VDD + 0.3 V
LO to VSS –0.3 VDD + 0.3 V
HO to VSS HS – 0.3 HB + 0.3 V
HS to VSS(3) 100 V
HB to VSS 118 V
RDT to VSS –0.3 5 V
Junction Temperature 150 °C
Storage temperature range, Tstg –55 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Recommended Operating Conditions are
conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured
performance limits and associated test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15 V. For example, if
VDD = 10 V, the negative transients at HS must not exceed –5 V.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions MIN MAX UNIT
VDD 8 14 V
HS(1) –1 100 V
HB HS + 8 HS + 14 V
HS Slew Rate < 50 V/ns
Junction Temperature –40 125 °C
(1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15 V. For example, if
VDD = 10 V, the negative transients at HS must not exceed –5 V.
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6.4 Thermal Information LM5102
THERMAL METRIC(1) DGS DPR(2) UNIT
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 165.3 37.9
RθJC(top) Junction-to-case (top) thermal resistance 58.9 38.1
RθJB Junction-to-board thermal resistance 54.4 14.9 °C/W
ψJT Junction-to-top characterization parameter 6.2 0.4
ψJB Junction-to-board characterization parameter 83.6 15.2
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 4.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
(2) Four-layer board with Cu finished thickness 1.5 oz, 1 oz, 1 oz, 1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top.
50-mm × 50-mm ground and power planes embedded in PCB. See Application Note AN-1187 Leadless Leadframe Package (LLP)
(SNOA401).
6.5 Electrical Characteristics
MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ= +25°C, VDD =
HB = 12 V, VSS = HS = 0 V, EN = 5 V. No load on LO or HO. RDT= 100kΩ(1).
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD Quiescent Current IN = EN = 0 V 0.34 0.6 mA
IDDO VDD Operating Current f = 500 kHz 2.1 3.5 mA
IHB Total HB Quiescent Current IN = EN = 0 V 0.06 0.2 mA
IHBO Total HB Operating Current f = 500 kHz 1.5 3 mA
IHBS HB to VSS Current, Quiescent HS = HB = 100 V 0.1 10 µA
IHBSO HB to VSS Current, Operating f = 500 kHz 0.5 mA
INPUT IN and EN
VIL Low Level Input Voltage Threshold 0.8 1.8 V
VIH High Level Input Voltage Threshold 1.8 2.2 V
Rpd Input Pulldown Resistance Pin IN and EN 100 200 500 kΩ
DEAD-TIME CONTROLS
VRDT Nominal Voltage at RDT 2.7 3 3.3 V
IRDT RDT Pin Current Limit RDT = 0 V 0.75 1.5 2.25 mA
UNDERVOLTAGE PROTECTION
VDDR VDD Rising Threshold 6.2 6.9 7.6 V
VDDH VDD Threshold Hysteresis 0.5 V
VHBR HB Rising Threshold 5.9 6.6 7.3 V
VHBH HB Threshold Hysteresis 0.4 V
LO GATE DRIVER
VOLL Low-Level Output Voltage ILO = 100 mA 0.21 0.4 V
VOHL ILO = –100 mA,
High-Level Output Voltage 0.5 0.85 V
VOHL = VDD – VLO
IOHL Peak Pullup Current LO = 0 V 1.2 A
IOLL Peak Pulldown Current LO = 12 V 1.8 A
HO GATE DRIVER
VOLH Low-Level Output Voltage IHO = 100 mA 0.21 0.4 V
VOHH IHO = –100 mA,
High-Level Output Voltage 0.5 0.85 V
VOHH = HB – HO
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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IN
EN
LO
HO
DT1 DT2 DT1 DT2
tLPHL tHPHL tHPLH tLPLH
tsd
tsd
ten
ten
LM5106
SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
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Electrical Characteristics (continued)
MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ= +25°C, VDD =
HB = 12 V, VSS = HS = 0 V, EN = 5 V. No load on LO or HO. RDT= 100kΩ(1).
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOHH Peak Pullup Current HO = 0 V 1.2 A
IOLH Peak Pulldown Current HO = 12 V 1.8 A
THERMAL RESISTANCE
θJA Junction to Ambient See(2)(3) 40 °C/W
(2) Four-layer board with Cu finished thickness 1.5/1.0/1.0/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50-mm
× 50-mm ground and power planes embedded in PCB. See AN-1187 Leadless Leadframe Package (LLP),SNOA401.
(3) The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
6.6 Switching Characteristics
MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ= +25°C, VDD =
HB = 12 V, VSS = HS = 0 V, No Load on LO or HO(1).
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLPHL Lower Turn-Off Propagation Delay 32 56 ns
tHPHL Upper Turn-Off Propagation Delay 32 56
tLPLH Lower Turn-On Propagation Delay RDT = 100k 400 520 640
tHPLH Upper Turn-On Propagation Delay RDT = 100k 450 570 690
tLPLH Lower Turn-On Propagation Delay RDT = 10k 85 115 160
tHPLH Upper Turn-On Propagation Delay RDT = 10k 85 115 160
ten, tsd Enable and Shutdown propagation delay 36
DT1, DT2 RDT = 100k 510
Dead-time LO OFF to HO ON & HO OFF to
LO ON RDT = 10k 86
MDT Dead-time matching RDT = 100k 50
tREither Output Rise Time CL= 1000pF 15
tFEither Output Fall Time CL= 1000pF 10
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Figure 1. LM5106 Input - Output Waveforms
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HO 10%
DT1 DT2
LO 10%
90%
90%
MDT = |DT1-DT2|
LM5106
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SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
Figure 2. LM5106 Switching Time Definitions: tLPLH, tLPHL, tHPLH, tHPHL
Figure 3. LM5106 Dead-time: DT
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0.1 1 10 100 1000
FREQUENCY (kHz)
10
100
1000
10000
100000
CURRENT (PA)
HB = 12V,
HS = 0V
CL = 470 pF
CL = 0 pF
CL = 4400 pF
CL = 2200 pF
CL = 1000 pF
2 4 6 8 10 12
HO, LO (V)
SOURCE CURRENT (A)
0
0.00
0.14
0.28
0.42
0.56
0.70
0.84
0.98
1.12
1.26
1.40
SINKING
SOURCING
VDD = HB = 12V, HS = 0V
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
SINK CURRENT (A)
8 9 10 11 12 13 14 15 16 17 18
VDD, VHB (V)
0.00
0.20
0.40
0.60
0.80
1.00
1.20
CURRENT (mA)
IHB @ RDT = 10k, 100k
VDD = HB
VSS = HS = 0V
IDD @ RDT = 100k
IDD @ RDT = 10k
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
0.00
0.20
0.40
0.60
0.80
1.00
1.20
CURRENT (mA)
VDD = HB = 12V
VSS = HS = 0V
IDD @ RDT = 10k
IHB @ RDT = 10k, 100k
IDD @ RDT = 100k
110 100 1000
FREQUENCY (kHz)
1
10
100
CURRENT (mA)
VDD = HB = 12V
CL = 0 pF
CL = 470 pF
CL = 1000 pF
CL = 2200 pF
VSS = HS = 0
-50 -30 -10 10 30 50 70 90 110 130 150
1.0
1.2
1.4
1.6
1.8
2.0
2.2
CURRENT (mA)
TEMPERATURE (oC)
VDD = HB = 12V
VSS = HS = 0V
RDT = 10K
f = 500 kHz
CL = 0 pF IDDO
IHBO
LM5106
SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
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6.7 Typical Characteristics
Figure 5. Operating Current vs Temperature
Figure 4. VDD Operating Current vs Frequency
Figure 7. Quiescent Current vs Temperature
Figure 6. Quiescent Current vs Supply Voltage
Figure 9. HO and LO Peak Output Current vs Output Voltage
Figure 8. HB Operating Current vs Frequency
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-50 -30 -10 10 30 50 70 90 110 130 150
1.76
1.78
1.80
1.82
1.84
1.86
1.88
1.90
1.92
1.94
1.96
VIL, VIH (V)
TEMPERATURE (oC)
-50 -30 -10 10 30 50 70 90 110 130 150
76
78
80
82
84
86
88
DEAD-TIME (ns)
TEMPERATURE (oC)
VDD = HB = 12V
VSS = HS = 0
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
0.100
0.300
0.500
0.700
0.900
1.100
1.300
VOH (V)
VDD = HB = 8V
VDD = HB = 12V
VDD = HB = 16V
Output Current = 100 mA
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
0.100
0.150
0.200
0.250
0.300
0.350
0.400
VOL (V)
VDD = HB = 8V
VDD = HB = 12V
VDD = HB = 16V
Output Current - 100 mA
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
6.30
6.40
6.50
6.60
6.70
6.80
6.90
7.00
7.10
7.20
7.30
THRESHOLD (V)
VHBR
VDDR
VDDR = VDD - VSS
VHBR = HB - HS
-25 0 25 50 75 100 125 150
TEMPERATURE (oC)
0.30
0.35
0.40
0.45
0.50
0.55
0.60
HYSTERESIS (V)
-50
VHBH
VDDH
LM5106
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SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
Typical Characteristics (continued)
Figure 11. Undervoltage Hysteresis vs Temperature
Figure 10. Undervoltage Rising Threshold vs Temperature
Figure 12. LO and HO - Low-Level Output Voltage vs Figure 13. LO and HO - High-Level Output Voltage vs
Temperature Temperature
Figure 15. Dead-Time vs Temperature (RT = 10k)
Figure 14. Input Threshold vs Temperature
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-50 -30 -10 10 30 50 70 90 110 130 150
540
550
560
570
580
590
600
DEAD-TIME (ns)
TEMPERATURE (oC)
VDD = HB = 12V
VSS = HS = 0V
LM5106
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Typical Characteristics (continued)
Figure 16. Dead-Time vs Temperature (RT = 100k)
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LO
DRIVER
VDD
UVLO
HO
DRIVER
HB
UVLO
LEVEL
SHIFT
HB
HS
IN
EN
LEADING
EDGE
DELAY
LEADING
EDGE
DELAY
RDT
VDD
VDD
VDD
VSS
LM5106
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SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
7 Detailed Description
7.1 Overview
The LM5106 is a single PWM input gate driver with Enable that offers a programmable dead-time. The dead-time
is set with a resistor at the RDT pin and can be adjusted from 100 ns to 600 ns. The wide dead-time
programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETs and
applications.
The RDT pin is biased at 3 V and current limited to 1 mA maximum programming current. The time delay
generator will accommodate resistor values from 5k to 100k with a dead-time time that is proportional to the RDT
resistance. Grounding the RDT pin programs the LM5106 to drive both outputs with minimum dead-time.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Start-up and UVLO
Both top and bottom drivers include undervoltage lockout (UVLO) protection circuitry which monitors the supply
voltage (VDD) and bootstrap capacitor voltage (HB – HS) independently. The UVLO circuit inhibits each driver
until sufficient supply voltage is available to turn on the external MOSFETs, and the UVLO hysteresis prevents
chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of the LM5106, the
top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.9 V. Any UVLO
condition on the bootstrap capacitor will disable only the high-side output (HO).
7.4 Device Functional Modes
EN IN Pin LO Pin HO Pin
L Any L L
H H L H
H L H L
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RGATE
CBOOT
HO
HS
LO
VSS
HB
LM5106 T1
IN
EN
VDD
VIN
VCC
CONTROLLER
GND
VDD
OUT1
ENABLE
0.1 PF
0.47 PFRDT RGATE
LM5106
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5106 is one of the latest generation of high-voltage gate drivers which are designed to drive both the
high-side and low-side N-channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck
circuit. The floating high-side driver can operate with supply voltages up to 110 V. This allows for N-channel
MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies.
The outputs of the LM5106 are controlled from a single input. The rising edge of each output can be delayed with
a programming resistor.
Table 1. Highlights
FEATURE BENEFIT
Programmable Turnon Delay Allows optimization of gate drive timings in bridge topologies
Reduces operating current when disabled to improved power system
Enable Pin standby power
Low Power Consumption Improves light load efficiency figures of the power stage.
8.2 Typical Application
Figure 17. LM5106 Driving MOSFETs Connected in Half-Bridge Configuration
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TOTAL
0.95
Q 43nC 10 A
100kHz
= + m ´
Max
TOTAL gmax HBO
SW
D
Q Q I F
= + ´
TOTAL
BOOT
HB
Q
C
V
=
D
LM5106
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SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
Typical Application (continued)
8.2.1 Design Requirements
PARAMETERS VALUES
Gate Drive IC LM5102
Mosfet CSD18531Q5A
VDD 10 V
Qgmax 43 nC
Fsw 100 kHz
DMax 95%
IHBO 10 µA
VDH 1.1 V
VHBR 7.3 V
VHBH 0.4 V
8.2.2 Detailed Design Procedure
8.2.2.1 Detailed Design Procedure
ΔVHB = VDD – VDH – VHBL
where
• VDD = Supply voltage of the gate drive IC
• VDH = Bootstrap diode forward voltage drop
• Vgsmin = Minimum gate source threshold voltage (1)
(2)
(3)
The quiescent current of the bootstrap circuit is 10 µA which is negligible compared to the Qgs of the MOSFET.
(4)
QTOTAL = 43.01 nC (5)
In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where
the power stage may skip pulse due to load transients. In this circumstance the boot capacitor must maintain the
HB pin voltage above the UVLO voltage for the HB circuit.
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.
VHBL = VHBR – VHBH (6)
VHBL = 6.9 V (7)
ΔVHB = 10 V – 1.1 V – 6.9 V (8)
ΔVHB = 2.0 V (9)
CBOOT = 43.01nc / 2 V (10)
CBOOT = 21.5 nF (11)
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be
twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across
them and to ensure long-term reliability of the devices.
The resistor values, RT, for setting turnon delay can be found in Figure 19.
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10 30 50 90 110 150
RDT (k:)
DEAD-TIME (ns)
0
100
200
300
400
500
600
700
800
900
70 130
EN
90%
LO or HO
VIH
tsd
LM5106
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8.2.3 Application Curves
Figure 18. LM5106 Enable: tsd
Figure 19. Dead-Time vs RT Resistor Value
9 Power Supply Recommendations
9.1 Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply
voltage (VDD) and can be roughly calculated as:
PDGATES = 2 • f • CL• VDD2(12)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. Figure 20 shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the Equation 12. This plot can be used to
approximate the power losses due to the gate drivers.
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0.1 1.0 10.0 100.0 1000.0
SWITCHING FREQUENCY (kHz)
POWER (W)
0.001
0.010
0.100
1.000
CL = 4400 pF
CL = 2200 pF
CL = 0 pF
CL = 470 pF
CL = 1000 pF
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SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
Power Dissipation Considerations (continued)
Figure 20. Gate Driver Power Dissipation (LO + HO)
VCC = 12 V
10 Layout
10.1 Layout Guidelines
The optimum performance of high- and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. The following points are emphasized:
1. Low ESR / ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB
and HS pins to support high peak currents being drawn from VDD and HB during the turnon of the external
MOSFETs.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).
3. To avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the source
of the top MOSFET and the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close
as possible to the MOSFETs.
– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
5. The resistor on the RDT pin must be placed very close to the IC and separated from the high current paths
to avoid noise coupling to the time delay generator which could disrupt timer operation.
10.1.1 HS Transient Voltages Below Ground
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS
node can swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling HO more than –0.3 V below HS can activate
parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed
Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5106
Q HS
Q LS
LM5106
C VDD
CBOOT
LM5106
SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
www.ti.com
Layout Guidelines (continued)
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must
be placed as close to the IC pins as possible in order to be effective.
2. HB to HS operating voltage should be 15 V or less. Hence, if the HS pin transient voltage is –5 V, VDD
should be ideally limited to 10V to keep HB to HS below 15 V.
3. Low ESR bypass capacitors from HB to HS and from VCC to VSS are essential for proper operation. The
capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO
and HO can be quite large. Any inductances in series with the bypass capacitor will cause voltage ringing at
the leads of the IC which must be avoided for reliable operation.
10.2 Layout Example
Figure 21. LM5106 Component Placement
16 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: LM5106
LM5106
www.ti.com
SNVS424D –JANUARY 2006–REVISED DECEMBER 2014
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM5106
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5106MM/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5106
LM5106MMX/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5106
LM5106SD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L5106SD
LM5106SDX/NOPB ACTIVE WSON DPR 10 4500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L5106SD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5106MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5106MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5106SD/NOPB WSON DPR 10 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1
LM5106SDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5106MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0
LM5106MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0
LM5106SD/NOPB WSON DPR 10 1000 200.0 183.0 25.0
LM5106SDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
10X 0.35
0.25
3 0.1
2.6 0.1
0.8
0.7
8X 0.8
10X 0.5
0.3
(0.1) TYP
2X
3.2
0.05
0.00
B4.1
3.9 A
4.1
3.9
(0.2)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
56
10
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SEE ALTERNATIVE
LEAD DETAIL
11
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
20.000
FULL R
ALTERNATIVE LEAD
DETAIL
BOTTOM VIEW SIDE VIEW
www.ti.com
EXAMPLE BOARD LAYOUT
(R0.05) TYP
8X (0.8)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(2.6)
(3.8)
10X (0.3)
10X (0.6)
(3)
( 0.2) VIA
TYP
(1.25)
(1.05)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
SYMM
1
56
10
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
11
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
EDGE
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
10X (0.3)
10X (0.6)
8X (0.8)
4X
(1.31)
4X (1.15)
(0.76)
(3.8)
(R0.05) TYP
(0.68)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
SYMM
1
56
10
SYMM
METAL
TYP
11
www.ti.com
PACKAGE OUTLINE
C
TYP
5.05
4.75
1.1 MAX
8X 0.5
10X 0.27
0.17
2X
2
0.15
0.05
TYP
0.23
0.13
0 - 8
0.25
GAGE PLANE
0.7
0.4
A
NOTE 3
3.1
2.9
B
NOTE 4
3.1
2.9
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
110
0.1 C A B
6
5
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.200
www.ti.com
EXAMPLE BOARD LAYOUT
(4.4)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
10X (1.45)
10X (0.3)
8X (0.5)
(R )
TYP
0.05
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
56
10
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(4.4)
8X (0.5)
10X (0.3)
10X (1.45)
(R ) TYP0.05
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
56
10
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
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