Features
•High Pe rformance, Low Power AVR® 8-Bit Microcontroller
•Advanced RISC Architecture
– 135 Po we rful Instructions – Most Single Clock Cy cle Execu tion
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Thro ug hp ut at 16 MHz
– On-Chip 2-c y cle Multiplier
•Non-volatile Program and Data Memories
– 32/64/128K Bytes of In-System Self-Programmable Flash
• Endurance: 100,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• USB Bootload er programmed by default in the Factory
• In-System Programming by On-chip Boot Program hardware activated after
reset
• True Read-While-Write Operation
• All supplied parts are preprogramed with a default USB bootloader
– 1K/2K/4K (32K/64K/128K Flash version) Bytes EEPR OM
• Endurance: 100,000 Write/Erase Cycles
– 2.5K/4K/8K (32K/64K/128K Flash version) Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
•JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
•USB 2.0 Full-speed/Low-speed Device and On-The-Go Module
– Complies fully with:
– Universal Serial Bus Specification REV 2.0
– On-The-Go Supplement to the USB 2.0 Specification Rev 1.0
– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s
•USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers : up to 64-bytes
– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
– Configurable Endpoints size up to 256 bytes in double bank mode
– Fully independant 832 bytes USB DPRAM for endpoint memory al location
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz PLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
•USB OTG Reduced Host :
– Supports Host Negotiat ion Protocol (HNP) and Session Request Protocol (SRP)
for OTG dual-role devices
– Provide Status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP
•Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
8-bit
Microcontroller
with
64/128K Bytes
of ISP Flash
and USB
Controller
ATmega32U6*
AT90USB646
AT90USB647
AT90USB1286
AT90USB1287
*Preliminary
7593J–AVR–03/09
27593J–AVR–03/09
ATmega32U6/AT90USB64/128
– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six PWM Channels with Pr ogrammable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channels, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
•Special Microco ntroller Features
– Power -on Reset and Programmable Br own-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
•I/O and Packages
– 48 Programmable I/O Lines
– 64-lead TQFP and 64-lead QFN
•Operating Voltages
– 2.7 - 5.5V
•Operating temperature
– Industria l (- 40°C to +85°C)
•Maximum Frequen cy
– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range
3
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
1. Pin Configurations
Figure 1-1. Pinout ATmega32U6/AT90USB64/128-TQFP
ATmega32U6
AT90USB90128/64
TQFP64
(INT.7/AIN.1/UVcon) PE7
UVcc
D-
D+
UGnd
UCap
VBus
(IUID) PE3
(SS/PCINT0) PB0
(INT.6/AIN.0) PE6
(PCINT1/SCLK) PB1
(PDI/PCINT2/MOSI) PB2
(PDO/PCINT3/MISO) PB3
(PCINT4/OC.2A) PB4
(PCINT5/OC.1A) PB5
(PCINT6/OC.1B) PB6
(PCINT7/OC.0A/OC.1C) PB7
(INT4/TOSC1) PE4
(INT.5/TOSC2) PE5
RESET
VCC
GND
XTAL2
XTAL1
(OC0B/SCL/INT0) PD0
(OC2B/SDA/INT1) PD1
(RXD1/INT2) PD2
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE2 (ALE/HWB)
PC7 (A15/IC.3/CLKO)
PC6 (A14/OC.3A)
PC5 (A13/OC.3B)
PC4 (A12/OC.3C)
PC3 (A11/T.3)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PE1 (RD)
PE0 (WR)
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
(T1) PD6
(T0) PD7
INDEX CORNER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
47593J–AVR–03/09
ATmega32U6/AT90USB64/128
Figure 1-2. Pinout ATmega32U6/AT90USB64/128-QFN
Note: The large center pad underneath the MLF packages is made of metal and internally connected to
GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center
pad is left unconnected, the package might loosen from the board.
1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of
other AVR micr ocontr ollers m anufa ct ured o n th e same proce ss tech nolo gy. Min a nd Ma x valu es
will be available after the device is characterized.
2. Overview The ATmega32U6/AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
2
3
1
4
5
6
7
8
9
10
11
12
13
14
16 33
15
47
46
48
45
44
43
42
41
40
39
38
37
36
35
34
17
18
20
19
21
22
23
24
25
26
27
29
28
32
31
30
52
51
50
49
64
63
62
53
61
60
59
58
57
56
55
54
ATmega32U6
AT90USB128/64
(64-lead QFN top view)
INDEX CORNER
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
(INT.7/AIN.1/UVcon) PE7
UVcc
D-
D+
UGnd
UCap
VBus
(IUID) PE3
(SS/PCINT0) PB0
(INT.6/AIN.0) PE6
(PCINT1/SCLK) PB1
(PDI/PCINT2/MOSI) PB2
(PDO/PCINT3/MISO) PB3
(PCINT4/OC.2A) PB4
(PCINT5/OC.1A) PB5
(PCINT6/OC.1B) PB6
(PCINT7/OC.0A/OC.1C) PB7
(INT4/TOSC1) PE4
(INT.5/TOSC2) PE5
VCC
GND
XTAL2
XTAL1
(OC0B/SCL/INT0) PD0
(OC2B/SDA/INT1) PD1
(RXD1/INT2) PD2
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
(T1) PD6
(T0) PD7
RESET
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE2 (ALE/HWB)
PC7 (A15/IC.3/CLKO)
PC6 (A14/OC.3A)
PC5 (A13/OC.3B)
PC4 (A12/OC.3C)
PC3 (A11/T.3)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PE1 (RD)
PE0 (WR)
5
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
ATmega32U6/AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optim ize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
PROGRAM
COUNTER
ST ACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTE
DATA DIR.
REG. PORT A
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTE
DATA REGISTER
PORT A
DAT A REGISTER
PORTD
INTERRUPT
UNIT
EEPROM
SPIUSART1
ST ATUS
REGISTER
Z
Y
X
ALU
POR TB DRIVERS
POR TE DRIVERS
POR TA DRIVERS
POR TF DRIVERS
POR TD DRIVERS
POR TC DRIVERS
PB7 - PB0PE7 - PE0
PA7 - P A0PF7 - PF0
RESET
VCC
AGND
GND
AREF
XT AL1
XT AL2
CONTROL
LINES
+
-
ANALOG
COMP ARATOR
PC7 - PC0
INTERNAL
OSCILLA TOR
WATCHDOG
TIMER
8-BIT DA TA BUS
AVCC
USB
TIMING AND
CONTROL
OSCILLA TOR
CALIB. OSC
DATA DIR.
REG. PORT C
DATA REGISTER
PORT C
ON-CHIP DEBUG
JTAG TAP
PROGRAMMING
LOGIC
BOUNDARY-
SCAN
DATA DIR.
REG. PORT F
DATA REGISTER
PORT F
ADC
POR - BOD
RESET
PD7 - PD0
TWO-WIRE SERIAL
INTERFACE
PLL
67593J–AVR–03/09
ATmega32U6/AT90USB64/128
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achiev ing throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega32U6/AT9 0USB64/128 provides the following features: 32/64/1 28K bytes of In-
System Programmable Flash with Read-While-W rite capabilities, 1K/2K/4K bytes EEPROM,
2.5K/4K/8K bytes SRAM, 48 general purpose I/O lines, 32 general purpose working registers,
Real Time Counter (RTC), four flexible Timer/Coun ters with compare modes and PWM, one
USART, a byte oriented 2-wire Serial Interface, a 8-channels, 10-bit ADC with optional differen-
tial input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the
On-chip Debug system and programming and six software selectable power saving modes. The
Idle mode stops the CPU while a llowin g the SRAM, Time r/ Co un te rs , SPI po rt , an d inte rr up t sy s-
tem to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-
save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all
I/O modules excep t Asynchronous Timer and ADC, to m inimize switching noise during ADC
conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory te chnology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programm er, or by an On-chip Boot program
running on the AVR core. The boot progra m can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Rea d-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-P rogrammable Flash on a monolithic chip,
the Atmel ATmega32U6/AT90USB64/128 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega32U6/AT90USB64/128 AVR is supported with a full suite of program and system
development tools including: C compilers, macro assemblers, program debugger/simulators, in-
circuit emulators, and evaluation kits.
7
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
2.2 Pin Descriptions
2.2.1 VCC Digital supply voltage.
2.2.2 GND Ground.
2.2.3 AVCC Analog supply voltage.
2.2.4 Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. Th e Port A pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the
ATmega32U6/AT90USB6 4/128 as listed on page 79.
2.2.5 Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. Th e Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the
ATmega32U6/AT90USB6 4/128 as listed on page 80.
2.2.6 Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both hig h sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega32U6/AT90USB64/128 as
listed on page 83.
2.2.7 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both hig h sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega32U6/AT90USB6 4/128 as listed on page 84.
87593J–AVR–03/09
ATmega32U6/AT90USB64/128
2.2.8 Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. Th e Port E pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega32U6/AT90USB6 4/128 as listed on page 87.
2.2.9 Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors ( selecte d for each bi t). The Por t F outpu t buffe rs have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tr i-stated when a reset co ndition becomes active, even if the cloc k is not runnin g. If th e
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated eve n if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.2.10 D- USB Full speed / Low Speed Negative Dat a Upstrea m Port. Should be connected t o the USB D-
connector pin with a serial 22 Ohms resistor.
2.2.11 D+ USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22 Ohms resistor.
2.2.12 UGND USB Pads Ground.
2.2.13 UVCC USB Pads Internal Regu lat or Inp ut supply volt ag e .
2.2.14 UCAP USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1µF).
2.2.15 VBUS USB VBUS monitor and OTG negociations.
2.2.16 RESET Reset input. A low level on this pin for longer than the minimum pu lse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page
58. Shorter pulses ar e not guaranteed to generate a reset.
2.2.17 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
9
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
2.2.18 XTAL2 Output from the inverting Oscillator amplifier.
2.2.19 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-
nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.2.20 AREF This is the analog reference pin for the A/ D Converter.
3. About Code Examples
This documentatio n contains simple co de examples that br iefly sh ow how to u se various parts of
the device. Be aware th at not all C compiler vendors include bit def initions in the header files
and interrupt ha ndlin g in C is com piler d epe nd ent. Please con firm wit h the C com piler d ocume n-
tation for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "I N", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
10 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
4. AVR CPU Core
4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
4.2 Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism , the AVR uses a Harvard architecture – with
separate memories and buses for progr am and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
11
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficien t address calculations. One of the these addre ss pointers
can also be used as an address pointer for loo k up tables in Flash prog ram memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single regi ster operation s can also be executed in th e ALU. After an ar ithmetic opera-
tion, the Stat us Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word for-
mat. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts an d subroutine calls, the retur n address Program Count er (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O fun ctions. The I/O Memory can be access ed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
ATmega32U6/AT90USB64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
4.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or betwee n a re gister an d an immedi ate ar e execut ed . The ALU ope ra tio ns are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
12 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
4.4 Status Register
The Status Regist er conta ins infor mation a bout the result of th e most recently e xecuted ari thme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the I nstru ction Se t Re ference. This will in many case s re move the n eed f or using t he
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an inte rr up t. T his mu st be ha nd le d by so ftw ar e.
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Globa l Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See t he “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or betwee n the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
Bit 76543210
I THSVNZCSREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
4.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruc tion set. In order t o achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit outpu t operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4-2, each register is also assigned a data me mory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memo ry organization provides great fle xibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file .
4.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect ad dressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 4- 3.
70Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
14 7593J–AVR–03/09
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Figure 4-3. The X-, Y-, and Z-registers
In the differ ent a ddr essing modes the se ad dr ess regist er s have fun cti ons a s fi xed d isp lacement ,
automatic increment, and automatic decrement (see the instruction set reference for details).
4.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of th e Stack. No te that the Sta ck is implement ed as growing from hig her memor y loca-
tions to lower memor y locat io ns. This im plies t hat a Stack PUSH co mmand decr ease s th e Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x0100. The initial value of the stack pointer is the last address of the internal
SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by three when the return address is pushed onto the
Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by three when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
15 XH XL 0
X-register 707 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 707 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7070
R31 (0x1F) R30 (0x1E)
Bit 1514131211109 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 1 0 0 0 0 0
11111111
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4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 4-4. Note that LPM is not affected by the RAMPZ setting.
Figure 4-4. The Z-pointer used by ELPM and SPM
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
4.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly genera te d fro m the select ed clock sour ce for t he
chip. No internal clock division is used.
Figure 4- 5 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 4-5. The Parallel Instruction Fetches and Instruction Executions
Figure 4-6 shows the int ernal timi ng con cept for th e Regi ster File . In a single clock cycl e an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Bit 7654321 0
RAMPZ
7RAMPZ
6RAMPZ
5RAMPZ
4RAMPZ
3RAMPZ
2RAMPZ1 RAMPZ0 RAMPZ
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit (
Individually) 707070
RAMPZ ZH ZL
Bit (Z-pointer) 23 16 15 8 7 0
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
16 7593J–AVR–03/09
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Figure 4-6. Single Cycle ALU Operation
4.8 Reset and Interrupt Handling
The AVR provides several different inte rrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be wr itten logic one to gether with th e Global Inter rupt
Enable bit in the Status Register in orde r to enable the interrupt. Depending on the Program
Counter value, interrupts ma y be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Program-
ming” on page 366 for details.
The lowest addresses in the progra m memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 68. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interru pt Vectors can be moved t o the star t of the Bo ot Flash sect ion by setti ng the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupt s” on page 68 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see “Memory Programming” on page 366.
When an interrupt occurs, th e Global Interrupt Enable I-bit is cleared and all interrup ts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is au tomatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writ ing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. The se
interrupts do not nece ssarily have I nterrupt Fla gs. If t he interr upt condit ion disappear s before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
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Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The f ollowing e xa mple sho ws how this can be used to a void interrupts during the
timed EEPROM write sequence..
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
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4.8.1 Interrupt Response Time
The interrupt execut ion respon se for all the en abled AVR interrupts is five clock cycles minimum.
After five clock cycles the progr am vector address for the act ual interrupt handlin g routine is exe-
cuted. During these five clock cycle period, the Program Counter is pushed onto the Stack. The
vector is normally a jump to the in terrupt routine, and this jump takes three clock cycles. If a n
interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before
the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt exe-
cution response time is increased by five clo ck cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes five clock cycles. During these five clock cycles,
the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incre-
mented by two, and the I-bit in SREG is set.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
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5. AVR ATmega32U6/AT90USB64/128 Memories
This section describes the different memor ies in the ATmega32U6/AT90USB64/128 . The AVR
architecture has two main memory spaces, the Data Memory and the Program Memory space.
In addition, the ATmega32U6/AT90USB64/128 features an EEPROM Memory for data storage.
All three memory spaces are linear and regular.
Notes: 1. Byte address.
2. Word (16-bit) address.
5.1 In-System Reprogrammable Flash Program Memory
The ATmega32U6/AT9 0USB64/128 contains 128K bytes On-chip In-System Re programmable
Flash memo ry for program st orage. Since all AVR inst ructions are 16 or 32 bits wide, th e Flash
is organized as 64K x 16. For sof tware security, the Flash Program me mory space is divided in to
two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 100,000 write/erase cycles. The
ATmega32U6/AT90USB64/128 Program Counter (PC) is 16 bits wide, thus addressing the
Table 5-1. Memory Mapping.
Memory Mnemonic ATmega32U6 AT90USB64 AT90USB128
Flash
Size Flash size 32 K bytes 64 K bytes 128K bytes
Star t Address - 0x00000 0x00000
End Address Flash end 0x07FFF(1)
0x3FFF(2) 0x0FFFF(1)
0x7FFF(2) 0x1FFFF(1)
0xFFFF(2)
32
Registers
Size - 32 bytes 32 bytes
Star t Address - 0x0000 0x0000
End Address - 0x001F 0x001F
I/O
Registers
Size - 64 bytes 64 bytes
Star t Address - 0x0020 0x0020
End Address - 0x005F 0x005F
Ext I/O
Registers
Size - 160 bytes 160 bytes
Star t Address - 0x0060 0x0060
End Address - 0x00FF 0x00FF
Internal
SRAM
Size ISRAM size 2.5 K bytes 4 K bytes 8 K bytes
Star t Address ISRAM start 0x0100 0x0100
End Address ISRAM end 0x0AFF 0x10FF 0x20FF
External
Memory
Size XMem size 0-64 K bytes 0-64 K bytes
Star t Address XMem start 0x1100 0x1100 0x2100
End Address XMem end 0xFFFF 0xFFFF
EEPROM
Size E2 s ize 1 K bytes 2 K bytes 4K bytes
Star t Address - 0x0000 0x0000
End Address E2 end 0x03FF 0x07FF 0x0FFF
20 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
128K program memory locations. The operation of Boot Program section and associated Boot
Lock bits for software protection are described in detail in “Memory Programming” on page 366.
“Memory Programming” on page 366 contains a detailed description on Flash data serial down-
loading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program M emory instruction description an d ELPM - Extended Load Progr am Memory
instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 15.
Figure 5-1. Program Memory Map
5.2 SRAM Data Memory
Figure 5-2 shows how the ATmega32U6/AT90USB64/128 SRAM Memory is organized.
The ATmega32U6/AT90USB6 4/128 is a complex microcontr oller with more peripher al units than
can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions.
For the Ext ended I /O space f rom $060 - $0FF in SRAM, only t he ST/S TS/STD an d LD/L DS/LDD
instructions can be used.
The first 4,352/8,448 Data Memo ry locations address both the Register File, the I/O Memo ry,
Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register
file, the next 64 location the standard I/O Me mory, then 160 locations of Extended I/O m emory
and the next 4, 096/8,192 locations address the internal data SRAM.
0x00000
Program Memory
Application Flash Section
Boot Flash Section
Flash End
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ATmega32U6/AT90USB64/128
An optional external data SRAM can be used with the ATmega32U6/AT90USB64/128. This
SRAM will occupy an area in the remaining address locations in the 64K address space. This
area starts at the address following the internal SRAM. The Register file, I/O, Extended I/O and
Internal SRAM occupies the lowest 4,352/8,448 bytes, so when using 64KB (65,536 bytes) of
External Memory, 61,184/57,08 8 Bytes of External Memory are available. See “External Mem-
ory Interface” on page 30 for details on how to take advantage of the external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data memory
locations, the external data SRAM is accessed using the same instructions as for the internal
data memory access. When the interna l data memories are accessed, the read and write strobe
pins (PE0 and PE1) are inactive during the whole access cycle. External SRAM operation is
enabled by setting the SRE bit in the XMCRA Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access of the
internal SRAM. This means that th e co mma nds LD, ST, LDS, STS, LDD, STD, PUSH, and POP
take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine
calls and returns take three clock cycles extra because the three-byte program counter is
pushed and popped, and external memory access does not take advantage of the internal pipe-
line memory access. When external SRAM interface is used with wait-state, one-byte external
access takes two, three, or four additional clock cycles for one, two, and three wait-states
respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles
more than specified in the instruction set manual for one, two, and three wait-states.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indir ect, Indire ct with Pre-decre ment, and Indirect with Po st-incre ment. In the Register file,
registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacemen t mode reaches 63 add ress locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decrement ed or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 8,192 bytes of internal data
SRAM in the ATmega32U 6/AT90USB64/128 are all accessible through all these ad dressing
modes. The Register File is described in “General Purpose Regist er File” on page 13.
22 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
Figure 5-2. Data Memory Map
5.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 5- 3.
32
R
eg
i
st
e
r
s
64
I/O
R
eg
i
st
e
r
s
I
n
t
e
r
na
l
S
R
A
M
(
8192
x
8
)
$0000
-
$001
F
$0020
-
$005
F
$
FFFF
$0060
-
$00
FF
D
a
t
a
M
e
m
o
r
y
E
xt
e
r
na
l
S
R
A
M
(
0
-
64
K
x
8
)
160
E
xt
I/O
R
eg
.
XMem start
ISRAM end
ISRAM start
23
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ATmega32U6/AT90USB64/128
Figure 5-3. On-chip Data SRAM Access Cycles
5.3 EEPROM Data Memory
The ATmega32U6/AT90USB64/128 contains 1K/2K/4K bytes of data EEPROM memory. It is
organized as a separate data space, in which single bytes can be read and written. The
EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the
EEPROM and the CPU is described in the follow ing, specifying the EEPROM Address Regis-
ters, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
page 380, pa ge 385, and page 369 respectively.
5.3.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in T able 5-3. A self-timing function, however,
lets the user software detect when the next byte can be writ ten. If the user code contain s instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some
period of time to r un at a voltage lo wer th an spe cified as minim um for the cloc k freq uen cy used .
See “Preventing EEPROM Corruption” on page 28. for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
clk
WR
RD
Data
Data
Address Address valid
T1 T2 T3
Compute Address
Read Write
CPU
Memory Access Instruction Next Instruction
24 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
5.3.2 The EEPROM Address Register – EEARH and EEARL
• Bits 15..12 – Res: Reserved Bits
These bits are reserved bits in the ATmega32U6/AT90USB64/128 and will always read as zero.
• Bits 11..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K
bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096.
The initial value of EEAR is undef in ed. A pr op er value must be wr itte n bef ore th e EEPRO M may
be accessed.
5.3.3 The EEPROM Data Register – EEDR
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write oper ation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
5.3.4 The EEPROM Control Register – EECR
• Bits 7..6 – Res: Reserved Bits
These bits are reserved bits in the ATmega32U6/AT90USB64/128 and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be trig-
gered when writing EEPE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Pr ogramming t imes for the d ifferen t modes ar e shown in Table 5-2. While EEPE
is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
Bit 1514131211 10 9 8
––––EEAR11EEAR10EEAR9EEAR8EEARH
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
76543 2 10
Read/WriteRRRRR/WR/WR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value0000XXXX
XXXXX X XX
Bit 76543210
MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 X X 0 0 X 0
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• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interr upt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEPE is cleared.
• Bit 2 – EEMPE: EEPROM Master Programming Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.
When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the
selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEPE bit for an EEPROM write procedure.
• Bit 1 – EEPE: EEPROM Programming Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEPE bit must be written to one to write the value into the
EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-
wise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEPE becomes zero.
2. Wait until SELFPRGEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If the Fl ash is never b eing up dated by t he CPU, step 2 can b e omitte d. See “Memor y Pro-
gramming” on page 366 for details about Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
Table 5-2. EEPROM Mode Bits
EEPM1 EEPM0 Programming
Time Operation
0 0 3.4 ms Erase and Write in one operation (Atomic Operation)
0 1 1.8 ms Erase Only
1 0 1.8 ms Write Only
1 1 – Reserved for future use
26 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft-
ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set,
the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is se t up in t he EEAR Regist er, the EERE bit must be writ ten to a log ic one to trigge r the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM access es. Table 5-3 lists the ty pical pro-
gramming time for EEPROM access from the CPU.
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob-
ally) so that no interrupts will occur during execution of these functions. The examples also
assume that no Flash Boot Loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.
Table 5-3. EEPROM Programming Time
Symbol Number of Calibrate d RC Oscillator Cycles Typ Programming Time
EEPROM write
(from CPU) 26,368 3.3 ms
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ATmega32U6/AT90USB64/128
Note: 1. See “About Code Examples” on page 9.
Assembly Code Example(1)
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
C Code Example(1)
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
28 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
The next code examples show assembly and C functions for reading the EEPROM. The exam-
ples assume that interrupts are controlled so that no interrupts will occur during execution of
these functio ns.
Note: 1. See “About Code Examples” on page 9.
5.3.5 Preventing EEPROM Corruption
During periods of low VCC, the EEPROM data can be co rrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues a re the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write seque nce to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly , if the su pp ly voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal
BOD does not match th e needed d etection le vel, an e xternal low VCC reset Protection circuit can
be used. If a reset occurs while a write operation is in progress , the write operation will be com-
pleted provided that the power supply voltage is sufficient.
Assembly Code Example (1)
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
C Code Example(1)
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
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5.4 I/O Memory The I/O space definition of the ATmega32U6/AT90USB64/128 is shown in “Register Summary”
on page 428.
All ATmega32U6/AT90USB64/ 128 I/Os and p eriphera ls are placed in t he I/O space. All I/O loca-
tions may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data
between the 32 general purpose working registers and the I/O space. I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS a nd SBIC instructions.
Refer to the instruction set sec tion for more details. When using the I/O specific comman ds IN
and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data
space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega32U6/AT90USB64/ 128 is a complex micro contro ller with more perip heral unit s than can
be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/ STD and LD/LDS/LDD instruc-
tions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
5.4.1 General Purpose I/O Registers
The ATmega32U6/AT90USB64/128 contains three General Purpose I/O Registers. These reg-
isters can be used for storing any information, and they are particularly useful for storing global
variables and Status Flags. General Purpose I/O Registers within the address range 0x00 -
0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
5.4.2 General Purpose I/O Register 2 – GPIOR2
5.4.3 General Purpose I/O Register 1 – GPIOR1
5.4.4 General Purpose I/O Register 0 – GPIOR0
Bit 76543210
MSB LSB GPIOR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
MSB LSB GPIOR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
MSB LSB GPIOR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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ATmega32U6/AT90USB64/128
5.5 External Memory Interface
With all the features the External Memory Interface provides, it is well suited to operate as an
interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-
display, A/D, and D/A. The main features are:
•Four different wait-state settings (including no wait-state).
•Independent wait-state setting for different external Memory sectors (configurable sector size).
•The number of bits dedicated to address high byte is selectable.
•Bus keepers on data lines to minimize current consumption (optional).
5.5.1 Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM
becomes available using the dedicated External Memory pins (see Figure 2-1 on page 5, Table
10-3 on page 79, and Table 10-9 on page 83). The memory configuration is shown in Figure 5-4.
Figure 5-4. External Memory with Sector Select
5.5.2 Using the External Memory Interface
The interface consists of:
• AD7:0: Multiplexed low-order address bus and data bus.
• A15:8: High-order address bus (configurable number of bits ).
• ALE: Address latch enable.
•RD
: Read strobe.
•WR
: Write strobe.
The control bits for the External Memory Interface are located in two registers, the External
Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.
M
e
m
o
r
y
C
on
f
igu
r
a
t
ion
A
0
x
0000
E
xt
e
r
na
l
M
e
m
o
r
y
(
0
-
60
K
x
8
)
0
x
FFFF
I
n
t
e
r
na
l
m
e
m
o
r
y
S
R
L
[
2
..
0
]
S
R
W
11
S
R
W
10
S
R
W
01
S
R
W
00
L
o
w
e
r
s
e
ct
o
r
U
ppe
r
s
e
ct
o
r
ISRAM end
XMem start
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When the XMEM interface is enabled, the XMEM interface will override the setting in the data
direction regi sters that corresponds to the ports dedicated to the XMEM in terface. For details
about the port override, see the al ternate f unctions in sect ion “I/O-Ports” on page 72. The XMEM
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to Fig-
ure 5-6 (this fi gure shows the wave forms wit hout wait- states). Wh en ALE goes fr om high-t o-low,
there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface
is enabled, also an internal access will cause activity on address, data and ALE ports, but the
RD and WR strobes will not toggle during internal ac cess. When the External Memory Interface
is disabled, the norma l pin an d data direct ion se tting s are use d. Note that when the XMEM inte r-
face is disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM. Figure 5-5 illustrates how to connect an external SRAM to the AVR using an
octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.
5.5.3 Address Latch Requirements
Due to the high-speed ope ra tion of the XRAM int er face, the add re ss lat ch must be select ed with
care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-
tions above thes e fr eq u en cie s, th e ty pic al old sty l e 74 HC ser ies latch becomes inad e qu at e. Th e
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with th e main tim ing par amete rs. The m ain paramet ers
for the addre ss latc h ar e:
• D to Q propagatio n de lay (tPD).
• Data setup time before G low (tSU).
• Data (address) hold time after G low (TH).
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of th = 5 ns. Refer to tLAXX_LD/tLLAXX_ST in “External Data Memory Timing” Tables 30-
7 through Tables 30-13 on pages 407 - 409. The D-to-Q propagation delay (tPD) must be taken
into consideration when calculating the access time requirement of the external component. The
data setup t ime be fore G low (tSU) must no t e xceed ad dress valid to AL E lo w ( tAVLLC) minus PCB
wiring delay (dependent on the capacitive load).
Figure 5-5. External SRAM Connected to the AVR
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
DQ
G
AD7:0
ALE
A15:8
RD
WR
AVR
32 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
5.5.4 Pull-up and Bus-keeper
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provide s a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in “External Memory Control Reg ister B – XMCRB”
on page 35. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while
these lines are tri-stated by the XMEM int erface.
5.5.5 Timing External Memory devices have different timing requirements. To meet these req uirements, the
XMEM interface provide s four diff erent w ait-stat es as sh own in Table 5-5. It is impo rtant t o con-
sider the timing specification of the External Memory device before selecting the wait-state. The
most important parameters are the access time for the external memory compared to the set-up
requirement. The access time for the External Mem ory is defined to be the time from receiving
the chip select/address until the data of this address actually is driven on the bus. The access
time cannot exceed the time from the ALE pulse must be asserted low until data is stable during
a read sequence (See tLLRL+ tRLRH - tDVRH in Tables 30-6 through Tables 30-13 on pages 407 -
409). The d ifferent wait-s tates are set up in software. As an additional feat ure, it is possible to
divide the external memory space in t wo sectors with individual wait-st ate settin gs. Thi s makes it
possible to connect two different memory devices with different timing requirements to the same
XMEM interface. For XMEM interface timing details, please refer to Tables 30-6 through Tables
30-13 and Figure 30-7 to Figure 30-10 in the “Ext ernal Data Memory Timing” on page 407.
Note that the XMEM int erface is asynchronous and that the waveform s in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and sup ply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
Figure 5-6. External Data Memor y Cycles without Wait-state (SRWn1=0 and SRWn0=0)
Note: 1. SRWn1 = SR W11 (upper sector) or SRW01 (lo wer sector), SRWn0 = SR W10 (upper sector) or
SRW00 (lower sector). The ALE pulse in period T4 is only present if th e next instruction
accesses the RAM (inter nal or external).
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8 AddressPrev. addr.
DA7:0 Address DataPrev. data XX
RD
DA7:0 (XMBK = 0) DataPrev. data Address
DataPrev. data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
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ATmega32U6/AT90USB64/128
Figure 5-7. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)
Note: 1. SRWn1 = SR W11 (upper sector) or SRW01 (lo wer sector), SRWn0 = SR W10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in per iod T5 is only present if the ne xt instruction accesses the RAM (internal
or external).
Figure 5-8. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)
Note: 1. SRWn1 = SR W11 (upper sector) or SRW01 (lo wer sector), SRWn0 = SR W10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in per iod T6 is only present if the ne xt instruction accesses the RAM (internal
or external).
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8 AddressPrev. addr.
DA7:0 Address DataPrev. data XX
RD
DA7:0 (XMBK = 0) DataPrev. data Address
DataPrev. data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
T4
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataPrev. data Address
DataPrev. data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
T4
34 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
Figure 5-9. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)
Note: 1. SRWn1 = SR W11 (upper sector) or SRW01 (lo wer sector), SRWn0 = SR W10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in per iod T7 is only present if the ne xt instruction accesses the RAM (internal
or external).
5.5.6 External Memory Control Register A – XMCRA
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. Th e SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memo r y Inte rf ac e an d the normal pin and data direction settings are used.
• Bit 6..4 – SRL2:0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses. The
external memory address sp ace ca n be divid ed in t wo se ctors th at h ave separa te wai t-sta te bi ts.
The SRL2, SRL1, and SRL0 bit s select the split of th e sector s, see T able 5- 4 an d Figure 5-4. By
default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address
space is treated as one sector. When the entire SRAM address space is configured as one sec-
tor, the wait-states are configured by the SRW11 and SRW10 bits.
ALE
T1 T2 T3
Write
Read
WR
T6
A15:8 AddressPrev. addr.
DA7:0 Address DataPrev. data XX
RD
DA7:0 (XMBK = 0) DataPrev. data Address
DataPrev. data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
T4 T5
Bit 76543210
SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 XMCRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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ATmega32U6/AT90USB64/128
• Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see Table 5-5.
• Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see Table 5-5.
Note: 1. n = 0 or 1 (lower/upper sector).
F or further details of the timing and wait-states of the External Memory Interface, see Figures
5-6 through Figures 5-9 for how the setting of the SRW bits affects the timing.
5.5.7 External Memory Control Register B – XMCRB
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is
enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-
stated the lines. Writing XMBK to zer o disables the bus keeper. XMBK is not qu alified with SRE,
Table 5-4. Sector limits with different settings of SRL2..0
SRL2 SRL1 SRL0 Sector Limits
00x
Lower sector = N/A
Upper sector = 0x2100 - 0xFFFF
010
Lower sector = 0x2100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
011
Lower sector = 0x2100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
100
Lower sector = 0x2100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
101
Lower sector = 0x2100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
110
Lower sector = 0x2100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
111
Lower sector = 0x2100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
Table 5-5. Wait States(1)
SRWn1 SRWn0 Wait States
0 0 No wait-states
0 1 Wait one cycle during read/write strobe
1 0 Wait two cycles during read/write strobe
11
Wait two cycles during read/write and wait one cycle before driving out
new address
Bit 7654 3 210
XMBK – – – – XMM2 XMM1 XMM0 XMCRB
Read/Write R/W R R R R R/W R/W R/W
Initial Value0000 0 000
36 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is
one.
• Bit 6..3 – Res: Reserved Bits
These bits are reserved and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is ena bled, all Port C pins are default used for the high address byte.
If the full 60KB address space is not required to access the External Memory, some, or all, Port
C pins can be relea sed for normal Port Pin function as described in Table 5-6. As described in
“Using all 64KB Locatio ns of External Memory ” on page 37, it is possible to use the XMMn bits to
access all 64KB locations of the External Memory.
5.5.8 Using all Locations of Externa l Memory Smaller than 64 KB
Since the external memory is mapped after the internal memory as shown in Figure 5-4, the
external memory is not addressed when addressing the first 8,448/4,352 bytes (128/64Kbytes
version) of dat a spa ce. It ma y app ear t hat t h e fi rst 8,44 8/ 4,35 2 b ytes o f th e ext er nal mem ory a re
inaccessible (external memory addresses 0x0000 to 0x10FF or 0x0000 to 0x20FF). However,
when connecting an external memory smaller than 64 KB, for example 32 KB, these locations
are easily accessed simp ly by addressing from ad dress 0x8000 to 0xA1FF. Since the External
Memory Address bit A15 is not connected to the ext ernal memory, add resses 0x8000 to 0xA1FF
will appear as addresses 0x0000 to 0x21FF for the external memory. Addressing above address
0xA1FF is not recommended, since this will address an external memory location that is already
accessed by another (lower) address. To the Application software, the external 32 KB me mory
will appear as one linear 32 KB address space from 0x2200 to 0xA1FF. This is illustrated in Fig-
ure 5-10.
Table 5-6. Port C Pins Released as Normal Port Pins when the External Memory is Enabled
XMM2 XMM1 XMM0 # Bits fo r External Memory Address Released Po rt Pins
0 0 0 8 (Full 56KB space) None
0017 PC7
0106 PC7 - PC6
0115 PC7 - PC5
1004 PC7 - PC4
1013 PC7 - PC3
1102 PC7 - PC2
1 1 1 No Address high bits Full Port C
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Figure 5-10. Address Map with 32 KB External Memory
5.5.9 Using all 64KB Locations of External Memory
Since the External Memory is mapped after the Internal Memory as shown in Figure 5-4, only
56KB of External Memory is available by default (address space 0x0000 to 0x20FF is reserved
for internal memory). However, it is possible to take advantage of the entire External Memo ry by
masking the higher address bits to zero. This can be done by using the XMMn bits and control
by software the most significant bits of the address. By settin g Port C to output 0x00, and releas-
ing the most significant bits for normal Port Pin operation, the Memory Interface will address
0x0000 - 0x2FFF. See the following code examples.
Care must be exercised using this option as most of the memory is masked away.
0
x
0000
0
x
20
FF
0
x
FFFF
0
x
2100
0
x
7
FFF
0
x
8000
0
x
0000
0
x
7
FFF
M
e
m
o
r
y
C
on
f
i
gu
r
a
t
i
on
A
I
n
t
e
r
na
l
M
e
m
o
r
y
(
U
nu
s
ed
)
AV
R
M
e
m
o
r
y
M
ap
E
xt
e
r
na
l
32
K S
R
A
M
E
xt
e
r
na
l
M
e
m
o
r
y
XMem start + 0x8000
ISRAM end + 0x8000
XMem start
ISRAM end
38 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
Note: 1. See “About Code Examples” on page 9.
Assembly Code Example(1)
; OFFSET is defined to 0x4000 to ensure
; external memory access
; Configure Port C (address high byte) to
; output 0x00 when the pins are released
; for normal Port Pin operation
ldi r16, 0xFF
out DDRC, r16
ldi r16, 0x00
out PORTC, r16
; release PC7:6
ldi r16, (1<<XMM1)
sts XMCRB, r16
; write 0xAA to address 0x0001 of external
; memory
ldi r16, 0xaa
sts 0x0001+OFFSET, r16
; re-enable PC7:6 for external memory
ldi r16, (0<<XMM1)
sts XMCRB, r16
; store 0x55 to address (OFFSET + 1) of
; external memory
ldi r16, 0x55
sts 0x0001+OFFSET, r16
C Code Example(1)
#define OFFSET 0x4000
void XRAM_example(void)
{
unsigned char *p = (unsigned char *) (OFFSET + 1);
DDRC = 0xFF;
PORTC = 0x00;
XMCRB = (1<<XMM1);
*p = 0xaa;
XMCRB = 0x00;
*p = 0x55;
}
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6. System Clock and Clock Options
6.1 Clock Systems and their Distribution
Figure 6-1 presents the principal clock systems in the AVR and th eir distributi on. All of the clocks
need not be active at a given time . In order to red uce power co nsumption, the clo cks to modu les
not being used can be halted by using different sleep modes, as described in “Power Manage-
ment and Sleep Modes” on page 51. The clock systems are detailed below.
Figure 6-1. Clock Distribution
6.1.1 CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
6.1.2 I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detecte d by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also, TWI address recognition is handled in all sleep modes.
6.1.3 Flash Clock – clkFLASH
The Flash clock controls o peration of t he Flash in terface. Th e Flash clock is usually active simul-
taneously with the CPU clock.
General I/O
Modules
Asynchronous
Timer/Counter CPU Core RAM
clk
I/O
clk
ASY
AVR Clock
Control Unit clk
CPU
Flash and
EEPROM
clk
FLASH
Source clock
Watchdog TimerReset Logic
Clock
Multiplexer
Watchdog clock
Calibrated RC
Oscillator
Timer/Counter
Oscillator Crystal
Oscillator External Clock
ADC
clkADC
System Clock
Prescaler
Watchdog
Oscillator
USB
clk
USB (48MHz)
PLL Clock
Prescaler
clk
Pllin (2MHz)
USB PLL
X24
40 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
6.1.4 Asynchronous Timer Clock – clkASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows
using this Timer/Counter as a real-time counter even when the device is in sleep mode.
6.1.5 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to re duce noise ge ner ated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion
results.
6.1.6 USB Clock – clkUSB
The USB is provided with a dedicat ed clock domain. This clock is gene rated with an on-chip PLL
running at 48MHz. The PLL always multiply its input frequency by 24. Thus the PLL clock regis-
ter should be programmed by software to generate a 2MHz clock on the PLL input.
6.2 Clock SourcesT he device has the following clock source options, selectable by Flash Fuse bits as shown
below. The cloc k fr om t he se lected so ur ce is i npu t t o th e AVR clo c k gene ra to r, an d rou te d t o the
appropriate modules.
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
6.2.1 Default Clock Source
The device is shipped with Low Power Crystal Oscillator (8.0 MHz-max) enabled and with the
fuse CKDIV8 programmed, resulting in 1.0MHz system clock (with a 8 MHz cristal). The default
fuse configuration is CKSEL = "1110", SUT = "01", CKDIV8 = "0". This default setting ensures
that all users can make their d esired clock source setting using any available programmin g
interface.
6.2.2 Clock Startup Sequence
Any clock source needs a sufficient VCC to start os cillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. “On-chip Debug Syste m” on page 56
describes the start condit ions for t he internal r eset. The delay ( tTOUT) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
Table 6-1. Device Clocking Options Select(1)
Device Clocking Option CKSEL3..0
Low Power Crystal Oscillator 1111 - 1000
Reserved 0111 - 0110
Low Frequency Crystal Oscil lator 0101 - 0100
Reserved 0011
Calibrated Internal RC Oscillator 0010
Exter nal Clock 0000
Reserved 0001
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selectable delays are shown in Table 6-2. The freque ncy of the Watchdog Oscillator is voltage
dependent as shown in “AT90USB64/128 Typical Characteristics” on page 412.
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The
delay will not monitor the actual voltage and it will be required to select a delay longer than the
Vcc rise time. If this is not possible, an internal or external Br own-Ou t Detect ion circuit sh ould be
used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay
can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is
not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-
ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal
reset active for a given number of clock cycles. The reset is then released and the device will
start to execute. The recommended oscillator start-up time is dependent on the clock type, and
varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when
the device starts up from reset . When st a rti ng up fr om Power -save or Po wer- do wn mode , Vcc is
assumed to be at a sufficient level and only the start-up time is included.
6.3 Low Power Crystal Oscillator
Pins XTAL1 and XTAL2 are inpu t and output, respectively, of an inverting amplifier which can be
configured for use as an On-chip Oscillator, as shown in Figure 6-2. Either a quartz c rystal or a
ceramic resonator may be used.
This Crystal Oscillator is a low power oscillator, with reduced volta ge swing on the XTAL2 out-
put. It gives the lowest power consumption, but is not capable of driving other clock inputs, and
may be more susceptible to noise in noisy environments. In these cases, refer to the “These
options are intended for use with ceramic resonators and will ensure frequency stability at start-
up. They can also be used with crystals when not operating close to the maximum frequency of
the device, and if frequency stability at start-up is not important for the application.” on page 43.
C1 and C2 should always be equal for both crystals and resonators. The optim al value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for
use with crystals are given in Table 6-3. For ceramic resonators, the capacitor values given by
the manufacturer should be used.
Table 6-2. Number of Watchdog Oscillator Cycles
Typ Time-o ut (V CC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
0 ms 0 ms 0
4.1 ms 4.3 ms 512
65 ms 69 ms 8K (8,192)
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Figure 6-2. Crystal Oscillator Connections
The Low Power Oscillator can operate in three different modes, each optimized for a specific fre-
quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-3.
Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.
2. This option should not be used with crystals, only with ceramic resonators.
3. If 8 MHz frequency e xceeds the specification of the device (depends on VCC), the CKDIV8
Fuse can be programmed in order to divide the inter nal frequency by 8. It must be ensured
that the resulting divided clock meets the frequency specification of the device.
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table
6-4.
Table 6-3. Low Power Crystal Oscillator Operating Modes(3)
Frequency Range(1) (MHz) CKSEL3..1 Recommended Range for Capacitors C1
and C2 (pF)
0.4 - 0.9 100(2) –
0.9 - 3.0 101 12 - 22
3.0 - 8.0 110 12 - 22
8.0 - 16.0 111 12 - 22
Table 6-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection
Oscillator Source /
Power Conditions
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) CKSEL0 SUT1..0
Ceramic resonator, fast
rising power 258 CK 14CK + 4.1 ms(1) 000
Ceramic resonator , slo wly
rising power 258 CK 14CK + 65 ms(1) 001
Ceramic resonator, BOD
enabled 1K CK 14CK(2) 010
Ceramic resonator, fast
rising power 1K CK 14CK + 4.1 ms(2) 011
Ceramic resonator , slo wly
rising power 1K CK 14CK + 65 ms(2) 100
XTAL2
XTAL1
GND
C2
C1
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Notes: 1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
Note: 1. The device is shipped with this option selected.
6.4 Low Frequency Crystal Oscillator
The device can utilize a 32.768 kHz watch crystal as clock source by a dedicated Low Fre-
quency Crystal Oscillator. The crystal should be connected as shown in Figure 6- 2. When this
Oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in
Table 6-6.
Crystal Oscillator, BOD
enabled 16K CK 14CK 1 01
Crystal Oscillator, fast
rising power 16K CK 14CK + 4.1 ms 1 10
Crystal Oscillator, slo wly
rising power 16K CK 14CK + 65 ms 1 11
Table 6-5. Start-up times for the internal calibrated RC Oscillator clock selection
Power Conditions Start-up Time from Power-
down and Po wer-save Additional Delay from
Reset (VCC = 5.0V) SUT1..0
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4.1 ms 01
Slowly rising power 6 CK 14CK + 65 ms(1) 10
Reserved 11
Table 6-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued)
Oscillator Source /
Power Conditions
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) CKSEL0 SUT1..0
Table 6-6. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
Power Conditions
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) CKSEL0 SUT1..0
BOD enabled 1K CK 14CK(1) 000
Fast rising power 1K CK 14CK + 4.1 ms(1) 001
Slowly rising power 1K CK 14CK + 65 ms(1) 010
Reserved 0 11
BOD enabled 32K CK 14CK 1 00
Fast rising power 32K CK 14CK + 4.1 ms 1 01
Slowly rising power 32K CK 14CK + 65 ms 1 10
Reserved 1 11
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Note: 1. These options should only be used if frequency stability at start-up is not important for the
application.
6.5 Calibrated Internal RC Oscillator
The calibrated internal RC Oscillator by default provides a 8.0 MHz clock. The frequency is nom-
inal value at 3V and 25⋅C. The device is shipped with the CKDIV8 Fuse programmed. See
“System Clock Prescaler” on page 47 for more details. This clock may be sele cted as the system
clock by programming the CKSEL Fuses as shown in Table 6-7. If selected, it will operate with
no external components. During reset, hardware loads the calibration byte into the OSCCAL
Register and thereby automatically calibrates the RC Oscillator. At 3V and 25⋅C, this calibration
gives a frequency of 8 MHz ±10%. The oscillator can be calibrated to any frequency in the range
7.3 - 8.1 MHz within ±10% accuracy, by changing the OSC CAL register. When this Osc illator is
used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for
the Reset Time -out. For more information on the pre-p rog r ammed ca libr at ion value , see the sec-
tion “Calibr ation Byte” on page 369
Notes: 1. The device is shipped with this option selected.
2. The frequency ranges are preliminary values. Actual values are TBD.
3. If 8 MHz frequency e xceeds the specification of the device (depends on VCC), the CKDIV8
Fuse can be programmed in order to divide the internal frequency by 8.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-5 on page 43.
Table 6-7. Internal Calibrated RC Oscillator Operating Modes(1)(3)
Frequency Range(2) (MHz) CKSEL3..0
7.3 - 8.1 0010
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Note: 1. The device is shipped with this option selected.
6.5.1 Oscillator Calibration Register – OSCCAL
• Bits 7..0 – CAL7..0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. The factory-calibrated value is automat-
ically written to this register during chip reset, giving an oscillator frequency of 8.0 MHz at 25°C.
The application software can write this register to change the oscillator frequency. The oscillator
can be calibrated to any fre que ncy in the ra ng e 7.3 - 8.1 MHz within ±1 0% accuracy. Calibr ation
outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write acc esses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowe st frequ ency in that range, a nd a setting of 0x7F g ives the highest fr equency in t he
range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the fre-
quency range 7.3 - 8.1 MHz.
6.6 External Cloc kThe device can utilize a external clock source as shown in Figure 6-3. To run the device on an
external clock, the CKSEL Fuses must be programmed as show n in Table 6-1.
Table 6-8. Start-up times for the internal calibrated RC Oscillator clock selection
Power Conditions Start-up Time from Power-
down and Po wer-save Additional Delay from
Reset (VCC = 5.0V) SUT1..0
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4.1 ms 01
Slowly rising power 6 CK 14CK + 65 ms(1) 10
Reserved 11
Bit 76543210
CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value Device Specific Calibration Value
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Figure 6-3. External Clock Drive Configuration
When this clock source is selected, start-up times are de termined by the SUT Fu ses as shown in
Table 6-9.
When applying an external clock, it is required t o avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is
required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implemen t run-time change s of the interna l
clock frequency while still ensuring stable operation. Refer to “Sys tem Clock Prescaler” on page
47 for details.
6.7 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programme d. This mode is suitable wh en the chip clock is u sed to d rive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
6.8 Timer/Counter Oscillator
The device can operate its Time r/Counter2 fr om an extern al 32.768 kHz watch crystal or a exte r-
nal clock source. See Figure 6-2 on page 42 for crystal connection.
Applying an external clock source to TOSC1 requires EXCLK in the ASSR Register written to
logic one. See “Asynchronous operation of the Timer/Counter” on page 165 for further descrip-
tion on selecting external clock as input instead of a 32 kHz crystal.
Table 6-9. Start-up Times for the External Clock Selection
Power Conditions Start-up Time from Power-
down and Po wer-save Additional Delay from
Reset (VCC = 5.0V) SUT1..0
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4.1 ms 01
Slowly rising power 6 CK 14CK + 65 ms 10
Reserved 11
NC
EXTERNAL
CLOCK
SIGNAL
XTAL2
XTAL1
GND
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6.9 System Clock Prescaler
The ATmega32U6/AT90USB64/128 has a system clock prescaler, and the system clock can be
divided by setting the “Clock Prescale Register – CLKPR” on page 47. This feature can be used
to decrease the system clock frequency and the power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH
are divided by a factor as shown in Table 6-10.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in t he clock syst em. It a lso en sures th at no in te rme diate f reque ncy is higher t han
neither the cl ock f reque ncy corr espondin g to the pr eviou s sett ing, nor t he clock fr equency co rr e-
sponding to the new settin g.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the
state of the prescaler - even if it were readable, and the exact time it takes to switch from one
clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-
ten, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this
interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the
period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing presca ler setting to make sure the write proce dure is
not interrupted.
6.9.1 Clock Prescale Register – CLKPR
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 3..0 – CLKPS3..0: Cloc k Prescaler Select Bit s 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As t he divider divide s the master clock input t o the MCU, the spe ed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 6-10.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
Bit 76543210
CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R/W R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Descri ption
48 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operat-
ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
Fuse setting. The Application softwar e must ensure that a sufficient division factor is chosen if
the selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with t he CKDIV8 Fuse programmed.
Table 6-10. Clock Presc aler Select
6.10 PLL The PLL is used to generate internal high frequency (48 MHz) clock for USB interface, the PLL
input is generated from an external low-frequency (the crystal oscillator or external clock input
pin from XTAL1). The internal RC Oscillator can not be used for USB operations.
6.10.1 Internal PLL for USB interface
The internal PLL in ATmega32 U6/AT90USB64 /128 gene rate s a clock freque ncy that is 24x mul-
tiplied from nominally 2 MHz input. The source of the 2 MHz PLL input clock is the output of the
internal PLL clock prescale r that generates the 2 MHz (See Section 6.10.2 for PLL interface).
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division F actor
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 128
1000 256
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
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Figure 6-4. PLL Clocking System
6.10.2 PLL Control and Status Register – PLLCSR
• Bit 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega32U6/AT90USB64/128 and always read as zero.
• Bit 4..2 – PLLP2:0 PLL Prescaler
These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the
PLL.
Note: 1. For AT90USB1 28x only. Do not use with AT90USB64x.
2. For AT90USB64x and ATmega32U6 only. Do not use with AT90USB128x.
8 MHz
RC OSCILLATOR
XTAL1
XTAL2 OSCILLATORS
PLL
24x
PLLE
Lock
Detector
PLOCK
clkUSB
System Clock
clk
2MHz
PLL clock
Prescaler (48MHz)
Bit 76543210
$29 ($29) PLLP2 PLLP1 PLLP0 PLLE PLOCK PLLCSR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0/1 0
Table 6-11. PLL input prescaler configurations
PLLP2 PLLP1 PLLP0 Clock Division
Factor External XTAL required for USB
operation (MHz)
000 Reserved -
001 Reserved -
010 Reserved -
011 4 8
100 Reserved -
101 8
(1) 16(1)
110 8
(2) 16(2)
111 Reserved -
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• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locke d to the reference clock. After the PLL is enabled, it
takes about 100 ms for the PLL to lock.
To clear PLOCK, clear PLLE and PLLPx bits.
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7. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides vario us sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See Table 7-1 for a summary. If an enabled interrupt occurs
while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in
addition to the start-up time, ex ecutes the interrupt routine, and resumes execu tion from the
instruction following SLEEP. The contents of the Register File and SRAM are unaltered when
the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and
executes from the Reset Vector.
Figure 6-1 on page 39 presents the different clock systems in the
ATmega32U6/AT90USB64/128, and their distribution. The figure is helpful in selecting an
appropriate slee p mode.
7.0.1 Sleep Mode Control Register – SMCR
The Sleep Mode Control Register contains control bits for power management.
• Bits 3, 2, 1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the six available sleep modes as shown in Table 7-1.
Note: 1. Standby modes are only recommended for use with external crys tals or resonators.
• Bit 1 – SE: Sleep Enable
The SE bit must be written to lo gic one to make the MCU enter the sle ep mode when the SLEEP
instruction is execut ed. To avoid t he MCU ent erin g the sleep mode un less it is the programmer’s
purpose, it is recomm ended to write the Sle ep Enable ( SE) bit to o ne just bef ore the e xecution of
the SLEEP instruction and to clear it immediately after waking up.
Bit 76543210
––––SM2SM1SM0SESMCR
Read/WriteRRRRR/WR/WR/WR/W
Initial Value00000000
Table 7-1. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
000Idle
0 0 1 ADC Noise Reduction
010Power-down
011Power-save
100Reserved
101Reserved
110Standby
(1)
1 1 1 Extended Standby(1)
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7.1 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire
Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This
sleep mode basically halts clkCPU an d clkFLASH, while allowing the other clocks to run.
Idle mode enables the M CU to wake up from external triggered interrupts as well a s internal
ones like the Timer O verflow and USART Transmit Complete interru pts. If wake-up from the
Analog Comparato r interrupt is not required , the Analog Comparator can b e powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
7.2 ADC Noise Reduction Mode
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowi ng the ADC, the external interrupts, 2-wire
Serial Interface address match, Timer/Counter2 and the Watchdog to continue operating (if
enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the
other clocks to run (includin g clkUSB).
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conve rsion star ts automa tically when this mode is enter ed. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog inter rupt, a Brown-out Reset, a 2-wire serial interfa ce interrupt, a Timer/Counter2
interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT7:4 or a pin
change interrupt can wakeup the MCU from ADC Noise Reduction mode.
7.3 Power-down Mode
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-
wire Serial Interf ace, an d th e Watch dog co nt inu e oper at ing (i f e nabled ). Only an Exter nal Reset,
a Watchdog Reset, a Brown-out Reset, 2-wire Serial Interface address match, an external level
interrupt on INT7:4, an external interrupt on INT3:0, a pin change interrupt or an asynchronous
USB interrupt sources (VBUSTI, WAKEUPI, IDTI and HWUPI), can wake up the MCU. This
sleep mode basically ha lts all generated clocks, allowing operation of asynchronou s modules
only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 94
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in “Clock Sources” on page 40.
7.4 Power-save Mode
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. This mode is identical to Power-down, with one exception:
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If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from
either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding
Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in
SREG is set.
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save
mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save
mode. If the Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is
stopped during sleep. If the Timer/Counter2 is not using the synchronous clock, the clock source
is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this
clock is only available for the Timer/Counter2.
7.5 Standby ModeWhen the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles. N ote that in Stanby mode the P LL is disabled and the USB interface will not
function.
7.6 Extended Standb y Mode
When the SM2..0 bits are 111 and an external crystal/resonator clock o ption is selected, the
SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to
Power-save mode with the exception that the Oscillator is kept running. From Extended Standby
mode, the device wakes up in six clock cycles.
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT7:4, only level interrupt.
4. Asynchronous USB interrupts are VBUSTI, WAKEUPI, IDTI and HWUPI.
Table 7-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains Oscillators Wake-up Sources
Sleep Mode
clkCPU
clkFLASH
clkIO
clkADC
clkASY
Main Clock
Source
Enabled
Timer Osc
Enabled
INT7:0 and
Pin Change
TWI Address
Match
Timer2
SPM/
EEPROM Ready
ADC
WDT Interrupt
Other I/O
USB Synchronous
Interrupts
USB Asynchonous
Interrupts(4)
Idle XXXXX
(2) XXXXXXXXX
ADCNRM X X X X(2) X(3) XX
(2) XXX XX
Power-down X(3) XXX
Power-save X X(2) X(3) XXXX
Standby(1) XX
(3) XXX
Extended
Standby X(2) XX
(2) X(3) XXXX
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7.7 Power Reduction Register
The Power Reduction Register, PRR, pr ovides a me thod to stop th e clock t o individ ua l per iphe r-
als to reduce power consumption. The current state of the peripheral is frozen and the I/O
registers can not be read or written. Resources used by the peripheral when stopping the clock
will remain occupied, hence the peripheral should in most cases be disabled before stopping the
clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the
same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
7.7.1 Power Reduction Register 0 - PRR0
• Bit 7 - PRTWI: P ower Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When
waking up the TWI again, the TWI should be re initialized to ensure proper operation.
• Bit 6 - PRTIM2: Power Reduction Timer/Counter2
Writing a logic on e to t his bit shut s down the Timer /Coun ter2 module in synchrono us mode ( AS2
is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.
• Bit 5 - PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 mo dule. When the Timer/Counter0
is enabled, operation will continue like before the shutdown.
• Bit 4 - Res: Reserved bit
This bit is reserved and will always read as zero.
• Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 mo dule. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to
the module. When waking up the SPI again, the SPI should be re initialized to ensure proper
operation.
• Bit 1 - Res: Reserved bit
These bits are reserve d and will always read as zero.
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to th is bit shuts down t he ADC. The ADC must be disabled before sh ut down.
The analog comparator cannot use the ADC input MUX when the ADC is shut down.
7.7.2 Power Reduction Register 1 - PRR1
Bit 7654321 0
PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI - PRADC PRR0
Read/Write R/W R/W R/W R R/W R/W R R/W
Initial Value0000000 0
Bit 7 6543 210
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• Bit 7 - PRUSB: Po wer Reduction USB
Writing a logic one to this bit shuts down the USB by stopping the clock to the m odule. When
waking up the USB again, the USB should be re initialized to ensure proper ope ration.
• Bit 6..4 - Res: Reserved bits
These bits are reserve d and will always read as zero.
• Bit 3 - PRTIM3: Power Reduction Timer/Counter3
Writing a logic one to this bit shuts down the Timer/Counter3 mo dule. When the Timer/Counter3
is enabled, operation will continue like before the shutdown.
• Bit 2..1 - Res: Reserved bits
These bits are reserve d and will always read as zero.
• Bit 0 - PRUSART1: Power Reduction USART1
Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module.
When waking up the USART1 again, the USART1 should be re initialized to ensure proper
operation.
7.8 Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possi ble of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
7.8.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to “Analog to Digi tal Converter - ADC” on page
313 for details on ADC operation.
7.8.2 Analog Co mp arato r
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,
the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up
to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all
sleep modes. Otherwise, the Inte rnal Voltage Reference will be enabled, indepe ndent of sleep
mode. Refer to “Analog Comparator” on page 310 for details on how to configure the Analog
Comparator.
7.8.3 Brown-out Detector
If the Brown-ou t Detector is not needed by th e application, this mo dule should be turned off . If
the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-
PRUSB–––PRTIM3––PRUSART1PRR1
Read/WriteR/WRRRR/W RRR/W
Initial Value0 0000 0 00
56 7593J–AVR–03/09
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nificantly to the total current consumption. Refer to “Brown-out Detec tion” on page 60 for details
on how to configure the Brown-out Detector.
7.8.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disable d as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-
age Reference” on page 62 for details on the start-up time.
7.8.5 Watchdog Timer
If the Watchdog Timer is not needed in the application , the module should be turned off. If th e
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to “Interrupts” on page 68 for details on how to configure the Watchdog Timer.
7.8.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 76 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to VCC/2 on an input pin can cause significan t current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to “Digital Input Disable Register 1 – DIDR1” on page 312 and “Digital Input Dis-
able Register 0 – DIDR0” on page 331 for details .
7.8.7 On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode,
the main clock source is enabled, and hence, always consumes power. In the deeper sleep
modes, this will contribute significantly to the total current consumption.
There are three alternative ways to disable the OCD system:
• Disable the OCDEN Fuse.
• Disable the JTAGEN Fuse.
• Write one to the JTD bit in MCUCR.
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8. System Control and Reset
8.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. This is also the case if the Reset Vector is in the Application section while the Interrupt
Vectors are in the Boot section or vice versa. The circuit diagram in Figure 8-1 shows the reset
logic. Table 8-1 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are im mediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have g one inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections f or the delay period are presented in “Clock Sources” on page 40.
8.2 Reset SourcesThe ATmega32U6/AT90USB64/128 has five sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
threshold (VPOT).
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
than the minim um pulse length.
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires an d the
Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out
Reset threshold (VBOT) and the Brown-out Detector is enabl ed.
• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register , one
of the scan chain s of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-
scan” on page 338 for details.
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Figure 8-1. Reset Logic
Notes: 1. The POR will not work unless the supply voltage has been below VPOT (falling)
8.3 Power-on Reset
A Power-on Reset (POR) pulse is ge nerated by an On-chip detection circuit. The detection level
is defined in Table 8-1. The POR is activated when ever VCC is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is properly reset from Power-on if Vcc
started from VPOR with a rise rate upper than VCCRR. Reaching the Power-on Reset threshold
Table 8-1. Reset Characteristics
Symbol Parameter Condition Min Typ Max Units
VPOT Power-o n Re se t Th re sh ol d Voltage (rising) 1.4 2.3 V
Pow er-on Reset Threshold Voltage (falling)(1) 1.3 2.3 V
VPOR VCC Start V oltage to ensure internal P ower-on
Reset signal -0.1 0.1 V
VCCRR VCC Rise Rate to ensure inter nal Power_on
Reset signal 0.3 V/ms
VRST RESET Pin Threshold Voltage 0.2
Vcc 0.85
Vcc V
tRST Minimum pulse width on RESET Pin 5V, 25°C 400 ns
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BU S
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
JTRF
JTAG Reset
Register
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
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voltage invokes the delay counter, which det ermin es how long the device is kept in RESET after
VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below
the detection level.
Figure 8-2. MCU Start-up, RESET Tied to VCC
Figure 8-3. MCU Start-up, RESET Extended Externally
Note: If VPOR or VCCRR parameter range can not be follo wed, an External Reset is required.
8.4 External ResetAn External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see Table 8-1) will generate a reset, even if the clock is not running.
Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after
the Time-out period – tTOUT – has expired.
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
V
POR
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC
V
POR
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Figure 8-4. External Reset During Operation
8.5 Brown-out Detection
ATmega32U6/AT90USB64/128 has an On-chip Br own-out Detection (BOD) circuit for monitor-
ing the VCC level du ring op er ation b y compa rin g it t o a fixed tr igg er level. The t rigger leve l fo r the
BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure
spike free Brown-o ut Detection. The hyster esis on the detection lev el should be interpret ed as
VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2..
When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure
8-5), the Brown-out Reset is immediately activated. When VCC increases above the trigger level
(VBOT+ in Figure 8-5), the delay counter starts the MCU after the Time-out period tTOUT has
expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for lon-
ger than tBOD given in Table 8-1.
CC
Table 8-2. BODLEVEL Fuse Coding
BODLEVEL 2..0 Fuses Min VBOT Typ VBOT Max VBOT Units
111 BOD Disabled
110
Reserved101
100
011 2.4 2.6 2.8 V
010 3.2 3.4 3.6
001 3.3 3.5 3.7
000 4.1 4.3 4.5
Table 8-3. Brown-out Characteristics
Symbol Parameter Min Typ Max Units
VHYST Brown-out Detector Hysteresis 50 mV
tBOD Min Pulse Width on Brown-out Reset ns
Ibod Brown-out Detector Consumption 25 µA
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Figure 8-5. Brown-out Reset During Operation
8.6 Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to
page 63 fo r details on operation of the Watchdog Timer.
Figure 8-6. Watchdog Rese t Du rin g Oper a tion
8.6.1 MCU Status Register – MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
VCC
RESET
TIME-OUT
INTERNAL
RESET
VBOT- VBOT+
tTOUT
CK
CC
Bit 76543210
––– JTRF WDRF BORF EXTRF PORF MCUSR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description
62 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Po wer-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occu rs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
8.7 Internal Voltage Reference
ATmega32U6/AT90USB64/128 features an internal bandgap reference. This reference is used
for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.
8.7.1 Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time tha t may influence the way it should be used. T he
start-up time is given in Table 8-4. To save power, the reference is not always turned on. The
reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the bandg ap reference is connected to the Analog Comparator (by setting the
AC BG b it in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
Table 8-4. Internal Voltage Reference Characteristics
Symbol Parameter Condition Min Typ Max Units
VBG Bandgap reference v oltage 1.0 1.1 1.2 V
tBG Bandgap reference start-u p time 40 70 µs
IBG Bandgap reference current
consumption 10 µA
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8.8 Watchdog Timer
ATmega32U6/AT90USB64/128 has an Enhanced Watchdog Timer (WDT). The main features
are:
•Clocked fr om separate On-chip Oscillator
•3 Operating modes
–Interrupt
– System Reset
– Interrupt and System Reset
•Selectable Time-out period from 16ms to 8s
•Possible Hardware fuse Watchdog al ways on (WDTON) for fail-safe mode
Figure 8-7. Watchdog Timer
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator.
The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.
In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset
- instruction to restart the counter before the time-out value is reached. If the system doesn't
restart the counter, an interrupt or system reset will be issued.
In Interrupt mo de, the WDT gives an int errupt wh en the time r expires. This int errupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than e xpected. In System Reset mode, th e WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The Watchdog always on (WD T ON) fuse, if programmed, w ill force the W atchdog Timer to Sys-
tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt
mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera-
tions to the Watch dog set-u p must f ollow time d sequen ces. Th e sequen ce for cle aring WDE and
changing time-out configuration is as follows:
128kHz
OSCILLATOR
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP0
WDP1
WDP2
WDP3
WATCHDOG
RESET
WDE
WDIF
WDIE
MCU RESET
INTERRUPT
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1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)
and WDE. A logic one must be written to WDE regardless of the previous value of the
WDE bit.
2. Within the ne xt f our cloc k cycles, write the WDE and W atchd og prescaler bits (WDP) as
desired, but with the WDCE bit cleared. This must be done in one operation.
The following code example shows one assembly and one C function for turning off the Watch-
dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts
globally) so that no interrupts will occur during the execution of these functions.
Note: 1. The example code assumes that the part specific header file is included.
Assembly Code Example(1)
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in r16, MCUSR
andi r16, (0xff & (0<<WDRF))
out MCUSR, r16
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional time-out
in r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
out WDTCSR, r16
; Turn off WDT
ldi r16, (0<<WDE)
out WDTCSR, r16
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out
*/
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
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Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out
condition, the device will be reset and the Watchdog Timer will stay enabled. If the cod e is not
set up to handle t he Watchdog , this might lead t o an eternal loop o f time-out r esets. To avoid this
situation, the application software should always clear the Watchdog System Reset Flag
(WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.
The following code example shows one assembly and one C function for changing the time-out
value of the Watchdog Timer.
Note: 1. The example code assumes that the part specific header file is included.
Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change
in the WDP bits can result in a time -out when switching to a shorter time-out perio d.
8.8.1 Watchdog Timer Control Register - WDTCSR
Assembly Code Example(1)
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
in r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
out WDTCSR, r16
; -- Got four cycles to set the new values from here -
; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
out WDTCSR, r16
; -- Finished setting new values, used 2 cycles -
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed equence */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
Bit 76543210
WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value0000X000
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• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Altern atively, WDIF is cle ared by writ ing a logic on e to the flag. Whe n the I -bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to o ne and the I-bit in t he Status Regist er is set, the Watchdog Interrupt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchd og Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-
ful for keeping the Watchdog Timer security while usin g the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must b e set after each interr upt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-
tem Reset will be applied.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared fir st. This feature ensures multiple r esets during con-
ditions causing failure, and a safe start-up after the failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdo g Timer prescaling when the Wa tchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 8-6 on page 67.
Table 8-5. Watchdog Timer Configuration
WDTON WDE WDIE Mode Action on Time-out
0 0 0 Stopped None
0 0 1 Interrupt Mode Interrupt
0 1 0 System Reset Mode Reset
011
Interrupt and System
Reset Mode Interrupt, then go to
System Reset Mode
1 x x System Reset Mode Reset
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.
Table 8-6. Watchdog Timer Prescale Select
WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator
Cycles Typical Time-out at
VCC = 5.0V
0 0 0 0 2K (2048) cycles 16 ms
0 0 0 1 4K (4096) cycles 32 ms
0 0 1 0 8K (8192) cycles 64 ms
0 0 1 1 16K (16384) cycles 0.125 s
0 1 0 0 32K (32768) cycles 0.25 s
0 1 0 1 64K (65536) cycles 0.5 s
0 1 1 0 128K (131072) cycles 1.0 s
0 1 1 1 256K (262144) cycles 2.0 s
1 0 0 0 512K (524288) cycles 4.0 s
1 0 0 1 1024K (1048576) cycles 8.0 s
1010
Reserved
1011
1100
1101
1110
1111
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9. Interrupts This section describes the specifics of the interrupt handling as performed in
ATmega32U6/ AT90USB64/128. For a general explanation of the AVR interrupt hand ling, refer
to “Reset and Interrupt Handling” on page 16.
9.1 Interrupt Vectors in ATmega32U6/AT90USB64/128
Table 9-1. Reset and Interrupt Vect or s
Vector
No. Program
Address(2) Source Interrupt Definition
1 $0000(1) RESET External Pin, Power-on Reset, Brown-out Reset,
Watchdog Reset, and JTA G AVR Reset
2 $0002 INT0 External Interrupt Requ est 0
3 $0004 INT1 External Interrupt Requ est 1
4 $0006 INT2 External Interrupt Requ est 2
5 $0008 INT3 External Interrupt Requ est 3
6 $000A INT4 External Interrupt Request 4
7 $000C INT5 External Interrupt Request 5
8 $000E INT6 External Interrupt Request 6
9 $0010 INT7 External Interrupt Requ est 7
10 $0012 PCINT0 Pin Change Interrupt Request 0
11 $0014 USB Ge neral USB General Interrupt request
12 $0016 USB
Endpoint/Pipe USB ENdpoint/Pipe Interrupt request
13 $0018 WDT Watchdog Time-out Interrupt
14 $001A TIMER2 COMPA Timer/Counter2 Compare Match A
15 $001C TIMER2 COMPB Timer/Counter2 Compare Match B
16 $001E TIMER2 OVF T imer/Counter2 Overflow
17 $0020 TIMER1 CAPT Timer/Counter1 Capture Event
18 $0022 TIMER1 COMPA Timer/Counter1 Compare Match A
19 $0024 TIMER1 COMPB Timer/Counter1 Compare Match B
20 $0026 TIMER1 COMPC Timer/Counter1 Compare Match C
21 $0028 TIMER1 OVF Timer/Counter1 Overflow
22 $002A TIMER0 COMPA Timer/Counter0 Compare Match A
23 $002C TIMER0 COMPB Timer/Counter0 Compare match B
24 $002E TIMER0 OVF T imer/Counter0 Overflow
25 $0030 SPI, STC SPI Serial Transfer Complete
26 $0032 USART1 RX USART1 Rx Complete
27 $0034 USART1 UDRE USART1 Data Register Empty
28 $0036 USART1TX USART1 Tx Complete
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Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at
reset, see “Memory Programming” on page 366.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot
Flash Section. The address of each Inte rrupt Vecto r wil l then be the address in this table
added to the start address of the Boot Flash Section.
Table 9-2 shows reset and Interrupt Vectors placement for the various combinations of
BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt
Vectors are not used , and regular progra m code can be placed at th ese locations. This is als o
the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the
Boot section or vice versa.
29 $0038 ANALOG COMP Analog Comparator
30 $003A ADC ADC Conversion Complete
31 $003C EE READY EEPROM Ready
32 $003E TIMER3 CAPT Timer/Counter3 Capture Event
33 $0040 TIMER3 COMPA Timer/Counter3 Compare Match A
34 $0042 TIMER3 COMPB Timer/Counter3 Compare Match B
35 $0044 TIMER3 COMPC Timer/Counter3 Compare Match C
36 $0046 TIMER3 OVF Timer/Counter3 Overflow
37 $0048 TWI 2-wire Serial Interface
38 $004A SPM READY Store Program Memory Ready
Table 9-1. Reset and Interr upt Vectors (Continued)
Vector
No. Program
Address(2) Source Interrupt Definition
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Note: 1. The Boot Reset Address is shown in Table 28-8 on page 364. For the BOOTRST Fuse “1”
means unprogrammed while “0” means programmed.
9.1.1 Moving Interrupts Between Application and Boot Space
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
9.1.2 MCU Cont rol Register – MCUCR
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual add ress of the start of the Boot Flash Section is deter-
mined by the BOOT SZ Fuses. Refer to the section “M emory Programming” on pag e 366 for
details. To avoid unin tentional chan ges of Interrupt Vector tables, a special write proced ure must
be followed to change the IVSEL bit:
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disa bled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while e x ecuting from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section “Memory Programming” on page 366
for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
Table 9-2. Reset and Interrupt Vect or s P lace m en t(1)
BOOTRST IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x0000 0x0002
1 1 0x0000 Boot Reset Address + 0x0002
0 0 Boot Reset Address 0x0002
0 1 Boot Reset Address Boot Reset Address + 0x0002
Bit 76543210
JTD – – PUD –– IVSEL IVCE MCUCR
Read/Write R/W R R R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explai ned in the IVSEL description above. See Code Example below.
Assembly Code Example
Move_interrupts:
; Get MCUCR
in r16, MCUCR
mov r17, r16
; Enable change of Interrupt Vectors
ori r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to Boot Flash section
ori r17, (1<<IVSEL)
out MCUCR, r17
ret
C Code Example
void Move_interrupts(void)
{
unsigned char temp;
/* Get MCUCR */
temp = MCUCR;
/* Enable change of Interrupt Vectors */
MCUCR = temp | (1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = temp | (1<<IVSEL);
}
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10. I/O-Ports
10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when chang-
ing drive value (if conf igured a s output) or enablin g/disabling o f pull-up resistors (if con figured as
input). Each output buffer has symmetrical drive characteristics with both hig h sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-
vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to both VCC and Ground as indicated in Figure 10-1. Refer to “Electrical Char-
acteristics for AT90USB64/128” on page 398 for a complete list of parameters.
Figure 10-1. I/O Pin Equivalent Schematic
All registers and bit references in this sect ion are written in g eneral form. A lower case “x” repre-
sents the numbering letter for the p ort, and a lower case “n” represe nts the bit numb er. However,
when using the regist er or bit defin es in a program , the precise f orm must be used. For examp le,
PORTB3 for bit no. 3 in Port B, her e docume nt ed ge ner ally as PO RT xn. The physical I /O Regis-
ters and bit locations are listed in “Register Description for I/O-Ports” on page 90.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-
ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all po rts when set.
Using the I/O port as G eneral Digital I/O is described in “Ports as General Digital I/O” on page
73. Most port pins are m ultiplexed with alternate function s for the peripheral features o n the
device. How each alternate function interferes with the port pin is described in “Alternate Port
Functions” on page 77. Refer to the individual module sections for a full description of the alter-
nate functions.
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Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the por t as general digital I/O.
10.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 show s a func-
tional description of one I/O-port pin, here generically called Pxn.
Figure 10-2. General Digital I/O(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
10.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description for I/O-Ports” on page 90, the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch t he pull-up resist or off, PORTxn h as to be written logic zero or the pi n has to
be configured as an output pin. The port pins are tr i-stated when rese t condition becomes a ctive,
even if no clocks are runn in g.
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clkI/O: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
Q
D
Q
QD
CLR
PORTxn
Q
QD
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
10.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
10.2.3 Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull- up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull -up enabled state is fully acceptable, as
a high-impedant environment will not notice the difference between a strong high driver and a
pull-up. If this is not t he case, the PUD bit in th e MCUCR Regis ter can be set to disable all pu ll-
ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use e ither the tri-st ate ({DDxn, PORTxn} = 0b00) or th e output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 10-1 summarizes the control signals for the pin value.
10.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit . As shown in Figur e 10-2, t he PINxn Register bit a nd the p recedin g latch con-
stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, bu t it also introduces a delay. Figure 1 0-3 shows a timing dia-
gram of the synchronization when reading an externally ap plied pin value. The maximum and
minimum prop a ga tio n dela ys ar e de no te d tpd,max and tpd,min respectively.
Table 10-1. P ort Pin Configurations
DDxn PORTxn PUD
(in MCUCR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled
low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
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Figure 10-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock pe riod depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 10-4. Synchronization when Rea ding a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd
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Note: 1. F or the assembly prog ram, two temporary registers are used to minimize the time from pull-
ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3
as low and redefining bits 0 and 1 as strong high drivers.
10.2.5 Digital Input Enable and Sleep Modes
As shown in Figure 10-2, the digital input signa l can be clamped to ground at the input of the
schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in
Power-down mode , Power-save mode, and Stan dby mode to avoid high powe r consumption if
some input signals are left float ing, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in “Alternate Port Functions” on page 77.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge , Falling Edge, or Any Logic Change on Pin” while the ext ernal interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
10.2.6 Unconnected Pins
If some pins are unused, it is recommended to ensur e that these pins have a def ined level. Even
though most of t he digital inputs are d isabled in the deep sleep modes as descr ibed above, fl oat-
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB,r16
out DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in r16,PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
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ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to VCC or GND is not recommended, sin ce this may ca use excess ive curr ents if the pin is
accidentally configured as an output.
10.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5
shows how the po rt pin control signals from the sim plified Figure 10-2 can be overridden by
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 10-5. Alternate Port Funct ions(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
clk
RPx
RRx
WRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
SET
CLR
0
1
0
1
0
1
DIxn
AIOxn
DIEOExn
PVOVxn
PVOExn
DDOVxn
DDOExn
PUOExn
PUOVxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
RESET
Q
QD
CLR
Q
QD
CLR
Q
Q
D
CLR
PINxn
PORTxn
DDxn
DATA BUS
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
Pxn
I/O
0
1
PTOExn
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
WPx: WRITE PINx
WPx
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Table 10-2 summarizes th e fu nction of the overri ding signals. The pin and p ort ind exes from Fig-
ure 10-5 are not sh own in the succeed ing tabl es. The over ridi ng signals ar e gen erat ed intern ally
in the modules having the alternate function.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Table 10-2. Generic Description of Overriding Signals for Alternate Functions
Signal Name Full Name Description
PUOE Pull-up Override
Enable
If this signal is set, the pull-up enable is controlled by the
PUOV signal. If this signal is cleared, the pull-up is
enabled when {DDxn, PORTxn, PUD} = 0b010.
PUOV Pull-up Override
Value
If PUOE is set, the pull-up is enabled/disabled when
PUOV is set/cleared, regardless of the setting of the
DDxn, PORTxn, and PUD Register bits.
DDOE Data Direction
Override Enable
If this signal is set, the Output Driver Enable is controlled
by the DDOV signa l. If this signal is cleared, the Ou tput
driver is enabled by the DDxn Register bit.
DDOV Data Direction
Override Value
If DDOE is set, the Output Driver is enabled/ disabled
when DDOV is set/cleared, regardless of the setting of
the DDxn Register bit.
PVOE Port Value
Override Enable
If this signal is set and the Output Driver is enabled, the
port value is controlled by the PVOV signal. If PVOE is
cleared, and the Output Driver is enabled, the port Value
is controlled by the PORTxn Register bit.
PVOV Port Value
Override Value If PVOE is set, the port value is set to PVOV, regardless
of the setting of the PORTxn Register bit.
PTOE Port Toggle
Override Enable If PTOE is set, the PORTxn Register bit is inverted.
DIEOE Digital Input
Enable Override
Enable
If this bit is set, the Digital Input Enable is controlled by
the DIEO V signal. If this signal is cleared, the Digital Input
Enable is determined b y MCU state (Normal mode, sleep
mode).
DIEOV Digital Input
Enable Override
Value
If DIEOE is set, the Digital Input is enabled/disab led when
DIEOV is set/cleared, regardless of the MCU state
(Nor mal mode, sleep mode).
DI Digital Input
This is the Digital Input to alternate functions. In the
figure, the signal is connected to the output of the schmitt
trigger but before the synchronizer. Unless the Digital
Input is used as a clock source, the module with the
alternate function will use its own synchronizer.
AIO Analog
Input/Output
This is the Analog Input/output to/from alternate
functions. The signal is connected directly to the pad, and
can be used bi-directionally.
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10.3.1 MCU Control Regist er – MCU C R
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disab led even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-
figuring the Pin” on page 73 for more details about this feature.
10.3.2 Alternate Functions of Port A
The Port A has an alternate functio n as the address low byte and data lines for the External
Memory Interface.
Table 10-4 and Table 10-5 relates the alternate functions of Port A to the overriding signals
shown in Figure 10-5 on page 77.
Bit 7 6 5 4 3 2 1 0
JTD ––PUD– – IVSEL IVCE MCUCR
Read/Write R/W R R R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 10-3. Port A Pins Alternate Functions
Port Pin Alternate Function
PA7 AD7 (External memory interface address and data bit 7)
PA6 AD6 (External memory interface address and data bit 6)
PA5 AD5 (External memory interface address and data bit 5)
PA4 AD4 (External memory interface address and data bit 4)
PA3 AD3 (External memory interface address and data bit 3)
PA2 AD2 (External memory interface address and data bit 2)
PA1 AD1 (External memory interface address and data bit 1)
PA0 AD0 (External memory interface address and data bit 0)
Table 10-4. Overriding Signals for Alternate Functions in PA7..PA4
Signal
Name PA7/AD7 PA6/AD6 PA5/AD5 PA4/AD4
PUOE SRE SRE SRE SRE
PUOV ~(WR | ADA(1)) •
POR TA7 • PUD ~(WR | ADA) •
PORTA6 • PUD ~(WR | ADA) •
PORTA5 • PUD ~(WR | ADA) •
PORTA4 • PUD
DDOE SRE SRE SRE SRE
DDOV WR | ADA WR | ADA WR | ADA WR | ADA
PVOE SRE SRE SRE SRE
PVOV A7 • ADA | D7
OUTPUT • WR A6 • ADA | D6
OUTPUT • WR A5 • ADA | D5
OUTPUT • WR A4 • ADA | D4
OUTPUT • WR
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DID7 INPUTD6 INPUTD5 INPUTD4 INPUT
AIO – – – –
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Note: 1. ADA is short for ADdress Active and represen ts the time when address is output. See “Exter-
nal Memory Interface” on page 30 f o r details .
10.3.3 Alternate Functions of Port B
The Port B pins with alternate functions are sh own in Table 10-6.
The alternate pin configuration is as follows:
• OC0A/OC1C/PCINT7, Bit 7
OC0A, Output Compare Match A output: The PB7 pin can serve as an external output for the
Timer/Counter 0 Outpu t Comp are. Th e pi n ha s to b e co nfigur ed a s an ou tput ( DDB7 set “on e”) to
serve this function . The OC0A pin is also the output pin for the PWM mode timer function.
Table 10-5. Overriding Signals for Alternate Functions in PA3..PA0
Signal
Name PA3/AD3 PA2/AD2 PA1/AD1 PA0/AD0
PUOE SRE SRE SRE SRE
PUOV ~(WR | ADA) •
PORTA3 • PUD ~(WR | ADA) •
PORTA2 • PUD ~(WR | ADA) •
PORTA1 • PUD ~(WR | ADA) •
PORTA0 • PUD
DDOE SRE SRE SRE SRE
DDOV WR | ADA WR | ADA WR | AD A WR | ADA
PVOE SRE SRE SRE SRE
PVOV A3 • ADA | D3
OUTPUT • WR A2• ADA | D2
OUTPUT • WR A1 • ADA | D1
OUTPUT • WR A0 • ADA | D0
OUTPUT • WR
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI D3 INPUT D2 INPUT D1 INPUT D0 INPUT
AIO – – – –
Table 10-6. Port B Pins Alternate Functions
Port Pin Alternate Functions
PB7 OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/Counter0,
Output Compare and PWM Output C for Timer/Counter1 or Pin Change Interrupt 7)
PB6 OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counter1 or Pin
Change Interrupt 6)
PB5 OC1A/PCINT5 (Output Compare and PWM Output A for Timer/Counter1 or Pin
Change Interrupt 5)
PB4 OC2A/PCINT4 (Output Compare and PWM Output A for Timer/Counter2 or Pin
Change Interrupt 4)
PB3 PDO/MISO/PCINT3 (Programming Data Output or SPI Bus Master Input/Slave
Output or Pin Change Interrupt 3)
PB2 PDI/MOSI/PCINT2 (Programming Data Input orSPI Bus Master Output/Slav e Input
or Pin Change Interrupt 2)
PB1 SCK/PCINT1 (SPI Bus Serial Clock or Pin Change Interrupt 1)
PB0 SS/PCINT0 (SPI Slave Select input or Pin Change Interrupt 0)
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OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the
Timer/Counter 1 Out put Compar e C. Th e pi n has to be co nf igured as a n o ut put ( DDB7 set ( one ))
to serve this function. The OC1C pin is also the output pin for the PWM mode timer function.
PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source.
• OC1B/PCINT6, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the
Timer/Counter1 Out pu t Compar e B. Th e pin ha s to be config ured as an out put (DDB6 se t ( one ))
to serve this function. The OC1B pin is also the output pin for the PWM mode timer fun ction.
PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt source.
• OC1A/PCINT5, Bit 5
OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the
Timer/Counter1 Out pu t Compar e A. Th e pin ha s to be config ured as an out put (DDB5 se t ( one ))
to serve this function. The OC1A pin is also the output pin for the PWM mode timer fun ction.
PCINT5, Pin Change Interrupt source 5: The PB5 pin can serve as an external interrupt source.
• OC2A/PCINT4, Bit 4
OC2A, Output Compare Match output: The PB4 pin can serve as an external output for the
Timer/Counter 2 Outpu t Comp are. Th e pi n ha s to b e co nfigur ed a s an ou tput ( DDB4 set (on e)) to
serve this function . The OC2A pin is also the output pin for the PWM mode timer function.
PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt source.
• PDO/MISO/PCINT3 – Port B, Bit 3
PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is
used as data output line for the ATmega32U6/AT90USB64/128.
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is
enabled as a slave, the da ta di rection of this pin is controlle d by DDB3 . When t he pin is forced to
be an input, the pull-up can still be controlled by the PORTB3 bit.
PCINT3, Pin Change Interrupt source 3: The PB3 pin can serve as an external interrupt source.
• PDI/MOSI/PCINT2 – Port B, Bit 2
PDI, SPI Serial Programming Data Inp ut. During Serial Program Downloadin g, this pin is used
as data input line for the ATmega32U6/AT90USB64/128.
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB2 bit.
PCINT2, Pin Change Interrupt source 2: The PB2 pin can serve as an external interrupt source.
• SCK/PCINT1 – Por t B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is
enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB1 bit.
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PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source.
•SS
/PCINT0 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 10-7 and Table 10-8 relate the alternate functions of Port B to the overriding signals
shown in Figure 10-5 on page 77. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source..
Table 10-7. Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name PB7/PCINT7/OC0A/
OC1C PB6/PCINT6/OC
1B PB5/PCINT5/OC
1A PB4/PCINT4/OC
2A
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE OC0/OC1C ENABLE OC1B ENABLE OC1A ENABLE OC2A ENABLE
PVOV OC0/OC1C OC1B OC1A OC2A
DIEOE PCINT7 • PCIE0 PCINT6 • PCIE0 PCINT5 • PCIE0 PCINT4 • PCIE0
DIEOV 1 1 1 1
DI PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT PCINT4 INPUT
AIO – – – –
Table 10-8. Overriding Signals for Alternate Functions in PB3..PB0
Signal
Name PB3/PD0/PCINT3/
MISO PB2/PDI/PCINT2/
MOSI PB1/PCINT1/
SCK PB0/PCINT0/
SS
PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD
DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
DDOV 0 0 0 0
PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0
PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT 0
DIEOE PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT1 •
PCIE0 PCINT0 •
PCIE0
DIEOV 1 1 1 1
DI SPI MSTR INPUT
PCINT3 INPUT SPI SLAVE INPUT
PCINT2 INPUT SCK INPUT
PCINT1 INPUT SPI SS
PCINT0 INPUT
AIO – – – –
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10.3.4 Alternate Functions of Port C
The Port C alternat e function is as follows:
Table 10-10 and Table 10- 11 relate the alternate functions of Port C to the overriding signals
shown in Figure 10-5 on page 77.
Table 10-9. Port C Pins Alternate Functions
Port Pin Alternate Function
PC7 A15/IC .3/CLK O(External Memory interface address bit 15 or
Input Capture Timer 3 or CLKO (Divided System Clock)
PC6 A14/OC.3A(External Memory interface address bit 14 or
Output Compare and PWM output A for Timer/Counter3)
PC5 A13/OC.3B(External Memory interface address bit 13 or
Output Compare and PWM output B for Timer/Counter3)
PC4 A12/OC .3C(External Memory interface address bit 12 or
Output Compare and PWM output C for Timer/Counter3)
PC3 A11/T.3(External Memory interface address bit 11or
Timer/Counter3 Clok Input)
PC2 A10(External Memory interface address bit 10)
PC1 A9(Extern al Memory interface address bit 9)
PC0 A8(Extern al Memory interface address bit 8)
Table 10-10. Overriding Signals for Alternate Fu nctions in PC7..PC4
Signal
Name PC7/A15/IC.3/CLK
O PC6/A14/OC.3A PC5/A13/OC.3B PC4/A12/OC.3C
PUOE SRE • (XMM<1) SRE •
(XMM<2)|OC3A
enable
SRE •
(XMM<3)|OC3B
enable
SRE •
(XMM<4)|OC3C
enable
PUOV 0 0 0 0
DDOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4)
DDOV 1 1 1 1
PVOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4)
PVOV A15 if (SRE.XMM<2)
then A14
else OC3A
if (SRE.XMM<2)
then A13
else OC3B
if (SRE.XMM<2)
then A12
else OC3C
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI ICP3 input – – –
AIO – – – –
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10.3.5 Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 10-12.
The alternate pin configuration is as follows:
• T0 – Port D, Bit 7
T0, Timer/Counter0 counter source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 counter source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock
is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1
operates in Synch ronous mode.
Table 10-11. Overriding Signals for Alternate Fu nctions in PC3..PC0
Signal
Name PC3/A11/T.3 PC2/A10 PC1/A9 PC0/A8
PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)
PUOV0000
DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)
DDOV 1 1 1 1
PVOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)
PVOV A11 A10 A9 A8
DIEOE0000
DIEOV0000
DI T3 input – – –
AIO––––
Table 10-12. Port D Pins Alternate Functions
Port Pin Alternate Function
PD7 T0 (Timer/Counter0 Clock Input)
PD6 T1 (Timer/Counter1 Clock Input)
PD5 XCK1 (USART1 External Clock Input/Output)
PD4 ICP1 (Timer/Counter1 Input Capture Trigger)
PD3 INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin)
PD2 INT2/RXD1 (Extern al Interrupt2 Input or USART1 Receive Pin)
PD1 INT1/SDA/OC2B (External Interrupt1 Input or TWI Serial DAta or Output
Compare f or Timer/Counter 2)
PD0 INT0/SCL/OC0B (External Interrupt0 Input or TWI Serial CLock or Output
Compare f or Timer/Counter 0)
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• ICP1 – Port D, Bit 4
ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin for Timer/Counter1.
•INT3
/TXD1 – Port D, Bit 3
INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the
MCU.
TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is
enabled, this pin is configured as an output re gardless of the value of DDD3.
•INT2
/RXD1 – Port D, Bit 2
INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the
MCU.
RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled
this pin is configured as an input regardless of the value of DDD2. When the USART forces this
pin to be an input, the pull-up can still be controlled by the PORTD2 bit.
•INT1
/SDA/OC2B – Port D, Bit 1
INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the
MCU.
SDA, 2-wire Serial Interface Da ta: When the TWEN bit in TWCR is set (one) to enable the 2-wire
Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for
the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes
shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-
rate limitation.
•INT0
/SCL/OC0B – Port D, Bit 0
INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the
MCU.
SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-
wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O
pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress
spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with
slew-rate limitation.
Table 10-13 and Table 10-14 relates the alte rnate functions o f Port D to the overrid ing signals
shown in Figure 10-5 on page 77.
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Note: 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
Table 10-13. Overriding Signals for Alternate Fu nctions PD7..PD4
Signal Name PD7/T0 PD6/T1 PD5/XCK1 PD4/ICP1
PUOE000 0
PUOV000 0
DDOE 0 0 XCK1 OUTPUT ENABLE 0
DDOV 0 0 1 0
PVOE 0 0 XCK1 OUTPUT ENABLE 0
PVOV 0 0 XCK1 OUTPUT 0
DIEOE000 0
DIEOV000 0
DI T 0 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT
AIO––– –
Table 10-14. Overriding Signals for Alternate Fu nctions in PD3..PD0(1)
Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1 PD1/INT1/SDA/
OC2B PD0/INT0/SCL/
OC0B
PUOE TXEN1 RXEN1 TWEN TWEN
PUOV 0 PORTD2 • PUD PORTD1 • PUD PORTD0 • PUD
DDOE TXEN1 RXEN1 TWEN TWEN
DDOV 1 0 SDA_OUT SCL_OUT
PVOE TXEN1 0 TWEN | OC2B
ENABLE TWEN | OC0B
ENABLE
PVOV TXD1 0 OC2B OC0B
DIEOE INT3 ENABLE INT2 ENABLE INT1 ENABLE INT0 ENABLE
DIEOV 1 1 1 1
DI INT3 INPUT INT2 INPUT/RXD1 INT1 INPUT INT0 INPUT
AIO – – SDA INPUT SCL INPUT
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10.3.6 Alternate Functions of Port E
The Port E pins with alternate functions are sh own in Table 10-15.
• INT7/AIN.1/UVCON – P ort E, Bit 7
INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source.
AIN1 – Analog Com parat or Neg ati ve input . This pi n is dire ctly connect ed to t he ne gat ive inpu t of
the Analog Comparator.
UVCON - When usin g USB host mode, this pin allows to contro l an external VBUS generato r
(active high).
• INT6/AI N.0 – Port E, Bit 6
INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source.
AIN0 – Analog Com parat or Neg ati ve input . This pi n is dire ctly connect ed to t he ne gat ive inpu t of
the Analog Comparator.
• INT5/TOSC2 – Po rt E, Bit 5
INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt source.
TOSC2, Timer/Counter2 Oscillator pin1. When the AS2 bit in ASSR is set to enable asynchro-
nous clocking of Timer/Co unter2, pin PE5 is disco nnecte d from the port, and becomes the ouput
of the inverting Oscillator amplifier. In this mode, a crystal is connected to this pin, and the pin
can not be used as an I/O pin.
• INT4/TOSC1 – Po rt E, Bit 4
INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt source.
TOSC1, Timer/Counter2 Oscillator pin2. When the AS2 bit in ASSR is set to enable asynchro-
nous clocking of Timer/Counter2, pin PE4 is disconnected from the port, and becomes the input
of the inverting Oscillator amplifier. In this mode, a crystal is connected to this pin, and the pin
can not be used as an I/O pin.
• UID – Port E, Bit 3
ID pin of the USB bus.
• ALE/HWB – Port E, Bit 2
Table 10-15. Port E Pins Alternate Functions
Port Pin Alternate Function
PE7 INT7/AIN.1/UVCON (External Interrupt 7 Input, Analog Comparator Positive Input
or VBUS Control)
PE6 INT6/AIN.0 (External Interrupt 6 Input or Analog Comparator Positive Input)
PE5 INT5/TOSC2 (External Interrupt 5 Input or RTC Oscillator Timer/Counter2))
PE4 INT4/TOSC2 (External Interrupt4 Input or RTC Oscillator Timer/Counter2)
PE3 UID
PE2 ALE/HWB (Address latch to extenal memory or Hardware bootloader activation)
PE1 RD (Read strobe to external memory)
PE0 WR (Write strobe to external memory)
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ALE is the external dat a memory Address latch enable.
HWB allows to execute the bootloader section after reset when tied to ground during external
reset pulse. The HWB mode of this pin is active only when the HWBE fuse is enable.
•RD
– Port E, Bit 1
RD is the external data memory read control enable.
•WR
– Port E, Bit 0
WR is the external data memory write control enable.
Table 10-16. Overriding Signals for Alternate Functions PE7..PE4
Signal
Name PE7/INT7/AIN.1/
UVCON PE6/INT6/AIN.0 PE5/INT5/
TOSC1 PE4/INT4/
TOSC2
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE UVCONE 0 0 0
DDOV UVCONE 0 0 0
PVOE UVCONE 0 0 0
PVOV UVCON 0 0 0
DIEOE INT7 ENABLE INT6 ENABLE INT5 ENABLE INT4 ENABLE
DIEOV 1 1 1 1
DI INT7 INPUT INT6 INPUT INT5 INPUT INT4 INPUT
AIO AIN1 INPUT AIN0 INPUT – –
Table 10-17. Overriding Signals for Alternate Functions in PE3..PE0
Signal
Name PE3/UID PE2/ALE/HWB PE1/RD PE0/WR
PUOE UIDE 0 SRE SRE
PUOV 1 0 0 0
DDOE UIDE SRE SRE SRE
DDOV 0 1 1 0
PVOE 0 SRE SRE SRE
PVOV 0 ALE RD WR
DIEOE UIDE 0 0 0
DIEOV 1 0 0 1
DI UID HWB – –
PE0 0 0 0 0
AIO – – – –
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10.3.7 Alternate Functions of Port F
The Port F has an alternate fu nction as analog input for the ADC as shown in Table 10-18. If
some Port F pins are configured as outputs, it is essential that these do not switch when a con-
version is in progress. This might corrupt the result of the conversion. If the JTAG interface is
enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even
if a Reset occurs.
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7.
TDI, JTAG Te st Data I n: Serial input d ata to be shifted in t o the I nstruction Register or Data Re g-
ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When
the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5.
TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state
machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is
enabled, this pin can not be used as an I/O pin.
• ADC3 – ADC0 – Port F, Bit 3..0
Table 10-18. Port F Pins Alternate Functions
Port Pin Alternate Function
PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
PF5 ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)
PF4 ADC4/TCK (ADC inpu t channel 4 or JTAG Test ClocK)
PF3 ADC 3 (ADC input channel 3)
PF2 ADC 2 (ADC input channel 2)
PF1 ADC 1 (ADC input channel 1)
PF0 ADC 0 (ADC input channel 0)
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Analog to Digital Converter, Channel 3..0.
10.4 Register Description for I/O-Ports
10.4.1 Port A Data Register – PORTA
Table 10-19. Overriding Signals for Alternate Functions in PF7..PF4
Signal
Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK
PUOE JTAGEN JTAGEN JTAGEN JTAGEN
PUOV 1 0 1 1
DDOE JTAGEN JTAGEN JTAGEN JTAGEN
DDOV 0 SHIFT_IR +
SHIFT_DR 00
PVOE 0 JTAGEN 0 0
PVOV 0 TDO 0 0
DIEOE JTAGEN JTAGEN JTAGEN JTAGEN
DIEOV 0 0 0 0
DI – – – –
AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5
INPUT TCK/ADC4
INPUT
Table 10-20. Overriding Signals for Alternate Functions in PF3..PF0
Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0
PUOE0000
PUOV0000
DDOE0000
DDOV0000
PVOE0000
PVOV0000
DIEOE0000
DIEOV0000
DI––––
AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT
Bit 76543210
PORTA
7PORTA
6PORTA
5PORTA
4PORTA
3PORTA
2PORTA
1PORTA
0PORTA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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10.4.2 Port A Data Direction Register – DDRA
10.4.3 Port A Input Pins Address – PINA
10.4.4 Port B Data Register – PORTB
10.4.5 Port B Data Direction Register – DDRB
10.4.6 Port B Input Pins Address – PINB
10.4.7 Port C Data Register – PORTC
10.4.8 Port C Data Direction Register – DDRC
10.4.9 Port C Input Pins Address – PINC
Bit 76543210
DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
PORTB
7PORTB
6PORTB
5PORTB
4PORTB
3PORTB
2PORTB
1PORTB
0PORTB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
PORTC
7PORTC
6PORTC
5PORTC
4PORTC
3PORTC
2PORTC
1PORTC
0PORTC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
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10.4.10 Port D Data Register – PORTD
10.4.11 Port D Data Direction Register – DDRD
10.4.12 Port D Input Pins Address – PIND
10.4.13 Port E Data Register – PORTE
10.4.14 Port E Data Direction Register – DDRE
10.4.15 Port E Input Pins Address – PINE
10.4.16 Port F Data Register – PORTF
10.4.17 Port F Data Direction Register – DDRF
Bit 76543210
PORTD
7PORTD
6PORTD
5PORTD
4PORTD
3PORTD
2PORTD
1PORTD
0PORTD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
PORTE
7PORTE
6PORTE
5PORTE
4PORTE
3PORTE
2PORTE
1PORTE
0PORTE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
PORTF
7PORTF
6PORTF
5PORTF
4PORTF
3PORTF
2PORTF
1PORTF
0PORTF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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10.4.18 Port F Input Pins Address – PINF
Bit 76543210
PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
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11. External Interrupts
The External Interrupts are triggered by the INT7:0 pin or any of the PCINT7..0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT7:0 or P CINT7..0 pins are configured as
outputs. This f eature provides a way of generat ing a software interrupt.
The Pin change interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK0 Regis-
ter control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT 7
..0 are detected asynchronously. This implies that these interrupts can be used for waking the
part also from sleep modes other than Idle mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the External Interrup t Control Registers – EICRA (INT3:0)
and EICRB (I NT7:4) . When t he exter nal int erru pt is e nab led and is co nf igured as level tr igge red,
the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising
edge interrupts on INT7:4 re quires the pr esence of an I/O clock, described in “System Clock and
Clock Options” on page 39. Low level interrupts and th e edge interrupt on INT3:0 are detected
asynchronously. This implies that these interrupts can be used for waking the part also from
sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level trigger ed interrupt is used for wake-up from Power-down, the required le vel
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in “System Clock and Clock Options” on page 39.
11.0.1 External Interrupt Control Register A – EICRA
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the
correspon ding inte rrup t mas k in the EI MS K is set. Th e level an d edg es on the ex ternal p ins that
activate the interrupts are defined in Table 11-1. Edges on INT3..INT0 are registered asynchro-
nously. Pulses on INT3:0 pins wider than the minimum puls e width given in Table 11-2 will
generate an interr upt. Shorter pulses are not gu aranteed to generate an int errupt. If low level
interrupt is selected, the low level must be held until the comple tion of the currently executing
instruction to generate an interrupt. If en abled, a level triggered interrupt will gene rate an inter-
rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.
Therefore, it is recommended to first d isable INT n by clearing its Interrupt Enable bit in the
EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be
cleared by writing a logica l one to its Interrupt Flag bit (INTFn) in the EIFR Register before the
interrupt is re-enabled.
Bit 76543210
ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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Note: 1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register . Otherwise an interrupt can occur when the bits are changed.
11.0.2 External Interrupt Control Register B – EICRB
• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the
correspon ding inte rrup t mas k in the EI MS K is set. Th e level an d edg es on the ex ternal p ins that
activate the interrupts are defined in Table 11-3. The value on the INT7:4 pins are sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled. If low level interrupt is selected, the low level must be held until the comple-
tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered
interrupt will generate an interrupt request as long as the pin is held low.
Note: 1. n = 7, 6, 5 or 4.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register . Otherwise an interrupt can occur when the bits are changed.
11.0.3 External Interrupt Mask Register – EIMSK
Table 11-1. Interrupt Sense Control(1)
ISCn1 ISCn0 Description
0 0 The low level of INTn generates an interrupt request.
0 1 Any edge of INTn generates asynchronously an interrupt request.
1 0 The falling edge of INTn generate s as ynchronously an interrupt request.
1 1 The rising edge of INTn generates asynchronously an interrupt request.
Table 11-2. Asynchronous External Interrupt Characteristics
Symbol Parameter Condition Min Typ Max Units
tINT Minimum pulse width for
asynchronous e xternal interrupt 50 ns
Bit 76543210
ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 EICRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Table 11-3. Interrupt Sense Control(1)
ISCn1 ISCn0 Description
0 0 The low level of INTn generates an interrupt request.
0 1 Any logical change on INTn generates an interrupt request
10
The falling edge between two samples of INTn generates an interrupt
request.
11
The rising edge between two samples of INTn generates an interrupt
request.
Bit 76543210
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• Bits 7..0 – INT7 – INT0: External Interrupt Requ est 7 - 0 Enable
When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the co rresponding ext ernal pin int errupt is ena bled. The Interru pt Sense Control bits in the
External Interrupt Control Registers – EICRA and EICRB – defines whether the external inter-
rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger
an interrupt request even if the pin is enabled as an output. This provides a way of generating a
software interrupt.
11.0.4 Externa l Interrupt Fl ag Registe r – EIFR
• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0
When an edge or logi c change o n the I NT7:0 pin tri ggers a n int errupt request , INTF7: 0 becom es
set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are
set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are
always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep
mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This
may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input
Enable and Sleep Modes” on page 76 for more information.
11.0.5 Pin Change Interrupt Control Register - PCICR
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. An y change on any enab led PCINT7..0 pin will cause an interrupt.
The corresponding int errupt of Pin Change Interrupt Request is e x ecute d from the PCI0 Int errupt
Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
11.0.6 Pin Change Interrupt Flag Register – PCIFR
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the
INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 EIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 EIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
– – – – –PCIE0PCICR
Read/WriteRRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
– – – – –PCIF0PCIFR
Read/WriteRRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0
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corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
11.0.7 Pin Change Mask Register 0 – PCMSK0
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interru pt is enabled on the corresponding I/O
pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I /O pin . If PCI NT7. .0 is cle ar ed, p i n ch ang e int errup t on t he correspo nd ing I/ O pin
is disabled.
Bit 76543210
PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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12. Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers
Timer/Counter0, 1, and 3 share the same prescaler module, but the Timer/Counters can have
different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a
general name, n = 0, 1 or 3.
12.1 Internal Clock Source
The Timer/Counter can be clocked d ire ctly by the system clock ( by se ttin g the CSn2 :0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a
clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or
fCLK_I/O/1024.
12.2 Prescaler Reset
The prescaler is free running , i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by
the Timer/Counter’s clock select, the state of the prescaler will ha ve implications for situations
where a prescaled clock is used. On e example of prescaling artifacts o ccurs when the timer is
enabled and clocked by th e prescaler (6 > CSn2:0 > 1). The number of syste m clock cycles from
when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles,
where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchron izing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
12.3 External Clock Source
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector. Figure 1 shows a functional
equivalent block diagram of the Tn synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the
high period of the internal system clock.
The edge detector ge nerat es o ne clkTn pulse f or ea ch p ositi ve (CSn 2:0 = 7 ) or ne ga tive (CSn2 :0
= 6) edge it detects.
Figure 1. Tn/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has bee n applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a ri sk that a false Timer/Counter clock pulse is generated.
Tn_sync
(To Clock
Select Logic)
Edge DetectorSynchronization
DQDQ
LE
DQ
Tn
clkI/O
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Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (fExtClk < fclk_I/O/2) give n a 50/50% duty cycle. Since th e edge detecto r uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, du e to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an exter nal clock source is less than fclk_I/O/2.5.
An external clock source can not be presca le d.
Figure 2. Prescaler for synchronous Timer/Counters
12.4 General Timer/Counter Control Register – GTCCR
• Bit 7 – TSM: Timer/Counte r Synchronization Mode
Writing the TSM b i t to on e a ctiva te s the Tim er/Counter Synchr on iza tio n mo d e. In th is m ode , the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-
ing prescaler reset signals asserted. This ensures that the corresponding Timer/Coun ters are
halted and ca n be conf igured to the same value without the risk of one of t hem adva ncing dur ing
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be
Reset. This bit is normally cleared immed iately by hardware , except if the TSM bit is set. Note
that Timer/Cou nter 0, Timer/ Co un te r1 and Timer / Count e r3 sha re the same pr esca ler and a r eset
of this prescaler will affect all timers.
PSR10
Clear
Tn
Tn
clkI/O
Synchronization
Synchronization
TIMER/COUNTERn CLOCK SOURCE
clkTn
TIMER/COUNTERn CLOCK SOURCE
clkTn
CSn0
CSn1
CSn2
CSn0
CSn1
CSn2
Bit 7 6 5 4 3 2 1 0
TSM – – – – – PSRA-
SY PSRSY
NC GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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13. 8-bit Timer/Counter0 with PWM
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and wit h PWM support. It allows accurate program execut ion timing (eve nt man-
agement) and wave ge neration. The main feature s are:
•Two Independent Output Compare Units
•Double Buffered Output Compare Registers
•Clear Timer on Compare Match (Auto Reload)
•Glitch Free, Phase Correct Pulse Width Modulator (PWM)
•Variable PWM Period
•Frequency Generator
•Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
13.1 Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 13-1. For the actual
placement of I/O pin s, refer to “Pinout ATmega3 2U6/AT90USB64/128-TQ FP” on page 3. CPU
accessible I/ O Registers, including I/O bit s and I/O pins, are shown in bold. The de vice-specific
I/O Register a nd bit locatio ns are listed in the “8-bit Timer/Count er Regist er Description” on page
110.
Figure 13-1. 8-bit Timer/Counter Block Diagram
13.1.1 Registers The T imer/Counter (TCNT0) and Output Comp are Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrup t Flag Regist er (T IFR0). All inte rrupts are ind ividually masked with the Timer Inte r-
rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked inter nally, via the pre scaler, or by an external clock source on
the T0 pin. T he Clock Se lect logic blo ck controls which clock so urce and edge the Timer/Cou nter
Clock Select
Timer/Counter
DATA BUS
OCRnA
OCRnB
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
=
Fixed
TOP
Value
Control Logic
=
0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TCCRnA TCCRnB
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See “Output Compare Un it” on page 102. for details. Th e Compare Match event will also
set the Compare Flag (OCF0A or OCF0B) which can be used to generate a n Output Compare
interrupt request.
13.1.2 Definitions Many register and bit reference s in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter 0 counter value and so on.
The definitions in the table below are also used extensively throu ghout the document.
13.2 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Tim er/Counter Cont rol Regi ster ( TCCR0B). For deta ils on clock sources an d pres-
caler, see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers” on page 98.
13.3 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
13-2 shows a block diagram of the counter and its surroundings.
Figure 13-2. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or de cre m en t TCNT0 by 1.
BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX The counter reach es its MAXimum wh en it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The
assignment is dependent on the mode of opera tion.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn
bottom
direction
clear
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direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clkTnTimer/Co un te r clo ck, re fe rr ed to as clk T0 in the following.
top Signalize that TCNT0 has reached maximum value.
bottom Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT0). clkT0 can be generated from an external or inte rnal clock source,
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides (has priority over ) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.
For more details about advanced counting sequences and waveform generation, see “Modes of
Operation” on page 105.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
13.4 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt . Th e Outp ut Co mpare Flag is aut om atica lly cleare d wh en the int errup t is exe-
cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGM02:0 bits and Co mpare Outpu t mode (COM0x1: 0) bits. The max
and bottom signals are used by the Waveform Generator for handling the special cases of the
extreme values in some modes of operation (“Modes of Operation” on page 105).
Figure 13-3 shows a block diagram of the Output Compare unit.
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Figure 13-3. Output Compare Unit, Block Diagram
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. Fo r the nor mal and Clear Tim er on Compare ( CTC) modes of operation, the dou-
ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare
Registers to either top or bottom of the coun ting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem co mplex, but this is not case. Wh en the double buff ering
is enabled, the CPU has access to the OC R0x Buffer Register, and if double buffering is dis-
abled the CPU will access the OCR0x directly.
13.4.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the
OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare
Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or
toggled).
13.4.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-
ized to the same value as TCNT0 wit hout trigg ering an inte rrupt when t he Timer/Coun ter clock is
enabled.
13.4.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer
clock cycle, there are risks involved when changing TCNT0 when using the Output Compare
Unit, independently of whet her the Timer/ Counter is runn ing or not. If the va lue written to TCNT0
equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform
OCFnx (Int.Req.)
= (8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform Generator
top
FOCn
COMnX1:0
bottom
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generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the count er is
down-counting.
The setup of the OC0x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-
pare (FOC0x) strobe bits in Normal mode. T he OC0x Registers keep their valu es even when
changing between Wa veform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value.
Changing the COM0x1:0 bits will take effect immediately.
13.5 Compare Match Output Unit
The Compare Outpu t mode (COM0x1: 0) bits ha ve two funct ions. The Wavef orm Genera tor uses
the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match.
Also, the COM0x1:0 bits control the OC0x pin output source. Figure 13-4 shows a simplified
schematic of th e logic affecte d by the COM0x1: 0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the
OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset
occur, the OC0x Register is reset to “0”.
Figure 13-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform
Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-
ble on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initializat ion of the OC0x state before t he out-
put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of
operation. See “8-bit Timer/Counter Register Description” on page 110.
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA BUS
FOCn
clk
I/O
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13.5.1 Compare Output Mode and Waveform Generation
The Waveform Generat or uses the COM0 x1:0 bits d ifferently in Nor mal, CTC, and PWM mo des.
For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the
OC0x Register is to be performed on the next Compare Match. For compare output actions in
the non-PWM modes refer to Table 13-1 on page 111. For fast PWM mode, refer to Table 13-2
on page 111, and for pha se co rr ect PWM refer to Table 13-3 on page 111.
A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0x strobe bits.
13.6 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the comb ination of the Wave form Generati on mode (WGM02: 0) and Compare Ou tput
mode (COM0x1:0) bits. T he Compare Output mode bits do no t affect the counting sequence,
while the Waveform Gener ation mode bits do . The COM0x1:0 bi ts control whether th e PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM0x1:0 bits control whether the output should be set, cleared, or tog gled at a Compare
Match (See “Compare Match Output Unit” on page 104.).
For detailed timing information see “Timer/Counter Timing Diagrams” on page 109.
13.6.1 Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflo w interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Co mpare Un it can be used t o generate interrupts at some given time . Using the Ou t-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
13.6.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to
manipulate the count er resolut io n. In CTC mode the counter is clear ed to zero wh en the counter
value (TCNT0) matches the OCR0A. The OCR0A de fines the top value for the counter, hence
also its resolution. This mode allows greater control of the Compare Match output frequency. It
also simplifies the op e ra tio n of coun tin g exte rn al ev en ts.
The timing diagram for the CTC mode is shown in Figure 13-5. The counter value (TCNT0)
increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.
106 7593J–AVR–03/09
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Figure 13-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
ning with none or a low pres caler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to
its maximum valu e (0xFF) and wrap around s tarting at 0x00 before the Comp are Match can
occur.
For generatin g a wavefor m out put in CT C mod e, t he OC0A ou tput can be se t to toggle it s logica l
level on each Compare Match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC0 =
fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of op erat ion, the T OV0 Flag is se t in the same tim er clock cycle tha t the
counter counts from MAX to 0x00.
13.6.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM02 :0 = 3 or 7) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-
inverting Compare Output mode, the O utput Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the out-
put is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the
operating fr equency of the fast PWM mode can be twice as high as the phase correct PWM
mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
TCNTn
OCn
(Toggle)
OCnx Interrupt Flag Set
1 4
Period
2 3
(COMnx1:0 = 1)
fOCnx fclk_I/O
2N1OCRnx+()⋅⋅
--------------------------------------------------=
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PWM mode is shown in Figure 13-6. The TCNT0 value is in the timing diagram shown as a his-
togram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The sm all horizontal line marks on the TCNT0 slopes represent Com-
pare Matches between OCR0x and TCNT0.
Figure 13-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare un it allows generation of PWM waveforms on the OC0x pins.
Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows
the OC0A pin to toggle on Compar e Matches if the WGM02 bit is set. This opt ion is no t available
for the OC0B pin (See Table 13-2 on page 111). The actual OC0x value will only be visible on
the port pin if the data direction for the port pin is set as output. The PWM waveform is gener-
ated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and
TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the pre scale factor (1, 8, 64, 256, or 1024).
The extreme values for th e OCR0A Re gister rep resents sp ecial cases wh en gen erating a PW M
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC0x to to ggle its logical level on each C ompare Match (COM 0x1:0 = 1). The wavefo rm
generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0 A is set to zero. This
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period 2 3
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
fOCnxPWM fclk_I/O
N256⋅
------------------=
108 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-
put Compare unit is enabled in the fast PWM mode.
13.6.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The coun ter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-
inverting Compare Output mode, the O utput Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-
counting. In inverting Outp ut Compar e mod e, the oper ation is in vert ed. The dual- slope o perat ion
has lower maximum operation frequency than single slope operation. However, due to the sym-
metric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correc t PWM mode the counter is increm ented until the counte r value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal
to TOP for one timer clo ck cycle. The tim ing dia gram fo r th e pha se correct PWM mode is shown
on F igure 13- 7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x
and TCNT0.
Figure 13-7. Phase Correct PWM Mode , Tim in g Dia gr am
The Timer/Counter Over flow Flag (TOV0) is set each time the counter reache s BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Update
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one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
not available for the OC0B pin (See Table 13-3 on page 111). The actual OC0x value will only
be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-
form is generated by clearing (or setting) the OC0x Register at the Compare Match between
OCR0x and TCNT0 when the counte r increment s, and sett ing (or clear ing) the OC0x Register at
Compare Match between OCR0x and TCNT0 when the counter decrements. The PWM fre-
quency for the output when using phase correct PWM can be calculated by the following
equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases wh en generating a PWM
waveform output in the phase correct PWM mo de. If the OCR0A is set equal to BO TTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 13-7 O Cnx has a transition from high to low even though
there is no Compare Match. The point of this transition is to guarantee sym metry around BOT-
TOM. There are two cases that give a transition without Compare Match.
• OCR0A changes its value from MAX, lik e in Figu re 13-7. When the OCR0A value is MAX the
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
• The timer starts counting from a v alue higher than the one in OCR0A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
13.7 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a
clock enable sign al in the following figures. Th e figures include information on whe n Interrupt
Flags are set. Figure 13-8 cont ains timing data for basic Timer/Counter op eration. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 13-8. Timer/Counter Timing Diagram, no Prescaling
Figure 13-9 shows the same timing data, but with the prescaler enabled.
fOCnxPCPWM fclk_I/O
N510⋅
------------------=
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
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Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
Figure 13-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode and PWM mode, where OCR0A is TOP.
Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
Figure 13-11 shows the setting of OCF0 A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (fclk_I/O/8)
13.8 8-bit Timer/Counter Register Description
13.8.1 Timer/Counter Control Register A – TCCR0A
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
Bit 76543210
COM0A
1COM0A
0COM0B
1COM0B
0––WGM0
1WGM0
0TCCR0A
Read/Write R/W R/W R/W R/W R R R/W R/W
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• Bits 7:6 – COM01A:0 : Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output dr iver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. Table 13- 1 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 13-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 106
for more details.
Table 13-3 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.
Initial Value 0 0 0 0 0 0 0 0
Table 13-1. Compare Output Mode, non-PWM Mode
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 Toggle OC0A on Compare Match
1 0 Clear OC0A on Compare Match
1 1 Set OC0A on Compare Match
Table 13-2. Compare Output Mode, Fast PWM Mode(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
01
WGM02 = 0: Nor m al Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Ma tch.
1 0 Clear OC0A on Compare Match, set OC0A at TOP
1 1 Set OC0A on Compare Match, clear OC0A at TOP
Table 13-3. Compare Output Mode, Phase Correct PWM Mod e(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
01
WGM02 = 0: Nor m al Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Ma tch.
10
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
11
Set OC0A on Compare Match wh en u p -co un ti n g. C l ea r OC0A on
Compare Match when down-counting.
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Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at T OP. See “Phase Correct PWM Mode” on
page 108 for more details.
• Bits 5:4 – COM0B1:0 : Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0
bits are set, the OC0B outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output dr iver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting. Table 13- 1 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 13-2 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 106
for more details.
Table 13-3 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.
Table 13-4. Compare Output Mode, non-PWM Mode
COM01 COM00 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Toggle OC0B on Compare Match
1 0 Clear OC0B on Compare Match
1 1 Set OC0B on Compare Match
Table 13-5. Compare Output Mode, Fast PWM Mode(1)
COM01 COM00 Description
0 0 Normal port operation, OC0B disconnected.
01Reserved
1 0 Clear OC0B on Compare Match, set OC0B at TOP
1 1 Set OC0B on Compare Match, clear OC0B at TOP
Table 13-6. Compare Output Mode, Phase Correct PWM Mod e(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0B disconnected.
01Reserved
10
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
11
Set OC0B on Compare Match wh en u p -co un ti n g. C l ea r OC0B on
Compare Match when down-counting.
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Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at T OP. See “Phase Correct PWM Mode” on
page 108 for more details.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the ATmega32U6/AT90USB64/128 and will always read as zero.
• Bits 1:0 – WGM01: 0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 13-7. Modes of operation supported by th e Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) mod es (s ee “Modes of Operation” on page 105).
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
13.8.2 Timer/Counter Control Register B – TCCR0B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A1:0 bits setting. Note th at the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the
forced compare.
Table 13-7. Wa ve fo rm Ge ne ra tion Mo d e Bit Des crip tio n
Mode WGM2 WGM1 WGM0
Timer/Counter
Mode of
Operation TOP Update of
OCRx at TOV Flag
Set on(1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
10 0 1
PWM, Phase
Correct 0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF TOP MAX
41 0 0Reserved – – –
51 0 1
PWM, Phase
Correct OCRA TOP BOTTOM
61 1 0Reserved – – –
7 1 1 1 Fast PWM OCRA TOP TOP
Bit 76543210
FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B
Read/Write W W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is
changed according to its COM0B1:0 bits setting. Note th at the FOC0B bit is implemented as a
strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the
forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the descript ion in the “Timer/Counter Control Register A – TCCR0A” on page 110.
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
13.8.3 Timer/Counter Register – TCNT0
Table 13-8. Clock Select Bit Description
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/Counter stopped)
001clk
I/O/(No prescaling)
010clk
I/O/8 (From prescaler)
011clk
I/O/64 (F rom prescaler)
100clk
I/O/256 (From prescaler)
101clk
I/O/1024 (From prescaler)
1 1 0 External clock source on T0 pin. Clock on falling edge.
1 1 1 External clock source on T0 pin. Clock on rising edge.
Bit 76543210
TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
13.8.4 Output Compare Register A – OCR0A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0 ). A match can be used to generate an Output Com pare interrupt, or to
generate a waveform output on the OC0A pin.
13.8.5 Output Compare Register B – OCR0B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0 ). A match can be used to generate an Output Com pare interrupt, or to
generate a waveform output on the OC0B pin.
13.8.6 Timer/Counter Interrupt Mask Register – TIMSK0
• Bits 7..3, 0 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compar e Match B inte rrupt is enab led. The correspondin g interrup t is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counte r0 Compare M a tch A in te rr up t is enabled. T h e co rr es po nd in g int er ru p t is e xe c u te d
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer /Counter0 occurs, i.e., when th e TOV0 bit is set in the Timer/ Counter 0 Inter-
rupt Flag Register – TIFR0.
Bit 76543210
OCR0A[7:0] OCR0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR0B[7:0] OCR0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
–––––OCIE0BOCIE0ATOIE0TIMSK0
Read/WriteRRRRRR/WR/WR/W
Initial Value00000000
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13.8.7 Timer/Counter 0 Interrupt Flag Register – TIFR0
• Bits 7..3, 0 – Res: Reserved Bits
These bits are reserved bits in the ATmega32U6/AT90USB64/128 and will always read as zero.
• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Ma tch occurs be tween th e Timer/Co unter and the da ta in
OCR0B – Output Compare Reg ister0 B. O CF0B is cleared by ha rdware when execut ing the cor-
responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Regist er0. OCF0A is cleared by har dware when executin g the cor-
responding interrupt handling vector. Alternatively, OCF 0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this fl ag is depen dent of t he WGM02: 0 bit set ting. Re fer t o Ta ble 13-7 , “Waveform
Generation Mode Bit Description” on page 113.
Bit 76543210
–––––OCF0BOCF0A
TOV0 TIFR0
Read/WriteRRRRRR/WR/WR/W
Initial Value00000000
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14. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
•True 16-bit Design (i.e., Allows 16-bit PWM)
•Three independent Output Compare Units
•Double Buffered Output Compare Registers
•One Input Capture Unit
•Input Capture Noise Canceler
•Clear Timer on Compare Match (Auto Reload)
•Glitch-free, Phase Correct Pulse Width Modulator (PWM)
•Variable PWM Period
•Frequency Generator
•External Event Counter
•Ten independent interrupt sources (TOV1, OCF1A, OCF1B, OCF1C, ICF 1, TOV3, OCF3A, OCF3B,
OCF3C and ICF3)
14.1 Overview Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a progra m, the precise form must be
used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 14-1. For the actual
placement of I/O pins, see “Pinout ATmega32U6/AT90USB64/128-TQFP” on page 3. CPU
accessible I/ O Registers, including I/O bit s and I/O pins, are shown in bold. The de vice-specific
I/O Register and bit locations are listed in the “16-bit Timer/Counter (Timer/Counter1 and
Timer/Counter 3)” on page 117.
The Power Reduc tion Ti mer/Coun ter1 b it, PR TIM1, in “Pow er Reductio n Register 0 - PRR0” o n
page 54 must be written to zero to enable Timer/Counter1 module.
The Power Reduc tion Ti mer/Coun ter3 b it, PR TIM3, in “Pow er Reductio n Register 1 - PRR1” o n
page 54 must be written to zero to enable Timer/Counter3 module.
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Figure 14-1. 16-bit Timer/Counter Block Diagram(1)
Note: 1. Refer to Figure 1-1 on page 3, Table 10-6 on page 80, and Table 10-9 on page 83 for
Timer/Counter1 and 3 and 3 pin placement and description.
14.1.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg-
ister (ICRn) are all 16-bit registers. Specia l procedures mu st be followed when accessin g the 16-
bit registers. These proced ures are described in the section “Accessing 16-bit Registers” on
page 119. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no
CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the
Timer Interrup t Flag Regist er (T IFRn). All inte rrupts are ind ividually masked with the Timer Inte r-
rupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these
registers are shared by other timer units.
The Timer/Counter can be clocked inter nally, via the pre scaler, or by an external clock source on
the Tn pin. T he Clock Se lect logic blo ck controls which clock so urce and edge the Timer/Cou nter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clkTn).
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the
Timer/Counter valu e at all tim e. T he r esult of the co mpare can b e used b y t he Wave fo rm Gene r-
ator to generate a PWM or variab le frequency output on the Output Com pare pin (OCnA/B/C).
ICFn (Int.Req.)
TOVn
(Int.Req.)
Clock Select
Timer/Counter
DATABUS
ICRn
=
=
=
TCNTn
Waveform
Generation
Waveform
Generation
Waveform
Generation
OCnA
OCnB
OCnC
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
=
0
TOP BOTTOM
Count
Clear
Direction
OCFnA
(Int.Req.)
OCFnB
(Int.Req.)
OCFnC
(Int.Req.)
TCCRnA TCCRnB TCCRnC
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
TCLK
OCRnC
OCRnB
OCRnA
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See “Output Compare Units” on pa ge 126.. The comp ar e mat ch event wil l also set th e Co mpa re
Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt re quest.
The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-
gered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See
“Analog Comparator” on page 310.) The Input Capture unit includes a dig ital filtering unit (Nois e
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using
OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for genera ting a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in ru n ti me. I f a fixed TOP valu e is req uired , t he ICRn Reg i ster ca n be used
as an alternative, freeing the OCRnA to be used as PWM output.
14.1.2 Definitions The following definitions are used extensively throughout the document:
14.2 Accessing 16-bit Registers
The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU
via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write opera-
tions. Each 16-bit timer has a single 8-bit re gister for t emporary stor ing of the hi gh byte of the 1 6-
bit access. The same Temporary Register is shared between all 16-bit registers within each 16-
bit timer. Accessing the low byte trigg ers the 16-bit read or write op eration. When the low byt e of
a 16-bit register is written by the CPU, the high byte stored in the Temporary Register, and the
low byte written are both copied into the 16-bit register in the same clock cycle. When the low
byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the
Temporary Register in the same clock cycle as the low byte is read.
Not all 16-bit access es uses the Tempor ar y Re gi ster for the high byte. Reading the OCRnA/B/C
16-bit registers does not involve using the Temporary Register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
The following code examples show how to access the 16-bit timer registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for accessing
the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit
access.
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be one of the fixed values:
0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn
Register. The assignment is dependent of the mode of operation.
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Note: 1. See “About Code Examples” on page 9.
The assembly code examp le returns the TCNTn value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-
ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both
the main code and the inte rrupt code updat e th e te mpora ry reg iste r, th e main code must di sable
the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNTn Register contents.
Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
Assembly Code Examples(1)
...
; Set TCNTn to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNTnH,r17
out TCNTnL,r16
; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH
...
C Code Examples(1)
unsigned int i;
...
/* Set TCNTn to 0x01FF */
TCNTn = 0x1FF;
/* Read TCNTn into i */
i = TCNTn;
...
Assembly Code Example(1)
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Note: 1. See “About Code Examples” on page 9.
The assembly code examp le returns the TCNTn value in the r17:r16 register pair.
The following code examples show how to do an atomic write of the TCNTn Register contents.
Writing any of the OCRnA/B/C or I CRn Registers can be done by using the same pr inciple.
TIM16_ReadTCNTn:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNTn( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Read TCNTn into i */
i = TCNTn;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Assembly Code Example(1)
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Note: 1. See “About Code Examples” on page 9.
The assembly code example requires that the r17:r16 register pair contains the value to be writ-
ten to TCNTn.
14.2.1 Reusing the Temporary High Byte Register
If writing to more t han one 16 -bit regist er where the high byte is the same f or all regi sters writte n,
then the high byte on ly needs to be written once. However, note that the same rule of atomic
operation described previously also applies in this case.
14.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits
located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and
prescaler, see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers” on page 98.
14.4 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 14-2 shows a block diagram of the counter and its surroundings.
TIM16_WriteTCNTn:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNTn to r17:r16
out TCNTnH,r17
out TCNTnL,r16
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNTn( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Set TCNTn to i */
TCNTn = i;
/* Restore global interrupt flag */
SREG = sreg;
}
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Figure 14-2. Counter Unit Block Diagram
Signal description (internal signals):
Count Increment or de cre m en t TCNTn by 1.
Direction Select between increment and decrement.
Clear Clear TCNTn (set all bits to zero).
clkTnTimer/Counter clock.
TOP Signalize that TCNTn has reached maximum value.
BOTTOM Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-
taining the upper ei ght bits of the co unter, an d Counter Low (TCNTnL) containing the lower eight
bits. The TCNTnH Regist er can only be ind irect ly accessed by the CPU. When the CPU d oes an
access to the TCNTnH I/O locat ion, the CPU accesses the h igh byte tempor ary register (TEMP).
The temporary register is updated with the TCNTnH value when the T CNTnL is read, and
TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNTn Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mo de o f oper at ion us ed, the cou nt er is cleared , in cr eme nted , o r decr em ent ed
at each timer clock (clkTn). The clkTn can be generated from an external or internal clock source,
selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the
timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of
whether clkTn is present or not. A CPU write overrides (h as priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).
There are close connectio ns between how the counter behaves (counts) and how wavefor ms
are generate d on the Out put Compare ou tputs OCnx. For more details abo ut advanced co unting
sequences and waveform generation, see “ Modes of Operation” on page 129.
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by
the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.
TEMP (8-bit)
DATA BUS
(8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit) Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP BOTTOM
Tn
Edge
Detector
( From Prescaler )
clkTn
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14.5 Input Capture Unit
The Timer/Counter incorporates an input capture unit that can capture external events and give
them a time -stamp in dicating t ime o f occurre nce. The externa l signal indica ting an e vent, or mul-
tiple events, ca n b e applie d via th e IC Pn pi n or alternatively, for t he Timer / Co un ter1 only, via t he
Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle,
and other featu res of the signal a pplied. Alt ernatively th e time- stamps can b e used fo r creating a
log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 14-3. The elements of
the block diagram th at are not di rectly a part of the input capture unit are gray shaded . The small
“n” in register and bit names indicates the Timer/Counter number.
Figure 14-3. Input Capture Unit Block Diagram
Note: The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not
Timer/Counter3, 4 or 5.
When a change of th e logic leve l (an event) occur s on the I nput Capt ure Pin (ICPn) , alternatively
on the analog Comparator output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNTn) is written to the Input Capture Re gister (ICRn). The Input Capture Flag (ICFn) is set at
the same system clock as the TCNTn value is copied into ICRn Register. If enabled (TICIEn =
1), the input capture flag generates an input capture interrupt. The ICFn flag is automatically
cleared when the interrupt is executed. Alternatively the ICFn flag can be cle ar ed by sof tware by
writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low
byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied
into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it
will access the TEMP Register.
ICFn (Int.Req.)
Analog
Comparator
WRITE ICRn (16-bit Register)
ICRnH (8-bit)
Noise
Canceler
ICPn
Edge
Detector
TEMP (8-bit)
DATA BUS (8-bit)
ICRnL (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ACIC* ICNC ICES
ACO*
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The ICRn Register can only be written when using a Waveform Generation mode that utilizes
the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera-
tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn
Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location
before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 119.
14.5.1 Input Capture Trigger Source
The main trigger source for the input capture unit is the Input Capture Pin (ICPn).
Timer/Counter1 can alterna tively use the analog comparator output as trigger sou rce for the
input capture unit. The Analog Comparator is selected as trig ger source by setting the analog
Comparator In put Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The input captu re flag
must therefore be cleared after the change.
Both the Input Capture Pin (ICPn) an d t he Analog Comparator output (ACO) inputs are sampled
using the same technique as for the Tn pin (Figure 1 on page 98). The edge detector is also
identical. However, when the noise canceler is ena bled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-
form Generation mode that uses ICRn to define TOP.
An input capture can be triggered by software by controlling the port of the ICPn pin.
14.5.2 Noise Cancel er
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monit ored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in
Timer/Counter Control Register B (TCCRnB). When enabled t he noise can celer intr oduces addi-
tional four system clock cycles of delay from a change applied to the input, to the update of the
ICRn Register. The noise canceler uses the sy stem clock and is therefore not affected by the
prescaler.
14.5.3 Using the Input Capture Unit
The main challeng e when using the Inpu t Capture unit is to assign enoug h processor capacity
for handling the incoming events. The time between two events is critica l. If the processor has
not read the captured value in the ICRn Register before the next event occurs, the ICRn will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dep endent on the maximum number of clock
cycles it takes to hand le an y of th e ot he r int er ru pt req ue sts .
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during op eration, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changin g the edge sensing must be done as early as po ssible after the ICRn
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Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICFn Flag is not required (if an interrupt handler is used).
14.6 Output Compare Units
The 16-bit comparator continuously compares TCNTn with the Output Compare Register
(OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set th e Output
Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Com-
pare Flag generates an Output Compare interru pt. The OCFnx Flag is auto matically cleared
when the inter rupt is executed. Alternatively the OCFnx Flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (See “Modes of Oper ation” on page 129.)
A special feature of Output Co mpare unit A allows it to def ine the Timer/Coun ter TOP value (i.e.,
counter resolution). In addition to the counter resolution, the TOP value defines the period time
for waveforms generated by the Waveform Generator.
Figure 14-4 shows a b lock diagram o f the Ou tput Comp are u nit. The small “n” in the re gister and
bit names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output
Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Out-
put Compare unit are gray shaded.
Figure 14-4. Output Compare Unit, Block Diagram
The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Time r on Compare (CTC) modes of ope ration, the
double buffering is disabled. The double buffering synchronizes the update of the OCRnx Com-
pare Register to either TOP or BOTTOM of the counting sequence. The synchronization
OCFnx (Int.Req.)
=
(16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS
(8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
COMnx1:0WGMn3:0
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM
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prevents the occurrence of odd-length, non-symm etrical PWM pulses, thereby making the out-
put glitch-free.
The OCRnx Register access may seem co mplex, but this is not case. Wh en the double buff ering
is enabled, the CPU has access to the OC Rnx Buffer Register, and if double buffering is dis-
abled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare)
Register is only chan ged by a w rite operation ( the Timer/Counter does not upda te this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). Howeve r, it is a good practice to read the low byte first as whe n
accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Reg-
ister since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
updated by the va lue written. Then whe n the low byte (OCRnxL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare
Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 119.
14.6.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the
OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare
match had occurred (the COMn1:0 bits settings define wheth er the OCnx pin is set, cleared or
toggled).
14.6.2 Compare Match Blocking by TCNTn Write
All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the
same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.
14.6.3 Using the Output Compare Unit
Since writing TCNTn in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNTn when using any of the Output Compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect wave-
form generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP
values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting.
The setup of the OCnx should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com-
pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when
changing between Wa veform Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value.
Changing the COMnx1:0 bits will take effect immediately.
14.7 Compare Match Output Unit
The Compare Outpu t mode (COMnx1: 0) bits ha ve two funct ions. The Wavef orm Genera tor uses
the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match.
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Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 14-5 shows a simplified
schematic of th e logic affecte d by the COMnx1: 0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the
OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset
occur, the OCnx Register is reset to “0”.
Figure 14-5. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform
Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visi-
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to Table 14-1, Table 14-2 and Table 14-3 for
details.
The design of the Output Compare pin logic allows initializat ion of the OCnx state before t he out-
put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of
operation. See “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page 117.
The COMnx1:0 bi ts have no effect on the Input Capture unit.
14.7.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the
OCnx Register is t o be performed on the next com pare match. F or compare output actions in t he
non-PWM modes refer to Table 14-1 on pag e 140. For fast PWM mode refer to Table 14-2 on
page 140, and for phase correct and phase and frequency correct PWM refer to Table 14-3 on
page 141.
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA BU S
FOCnx
clk
I/O
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A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOCnx strobe bits.
14.8 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the comb ination of the Wave form Generati on mode (WGMn 3:0) and Compare Output
mode (COMnx1: 0) bits. The Compare Output mode bits do no t affect the counting sequence,
while the Waveform Gener ation mode bits do . The COMnx1:0 bi ts control whether th e PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COMnx1:0 bits control whe ther the output should be set, cleared or to ggle at a compare
match (See “Compare Match Output Unit” on page 127.)
For detailed timing information refer to “ T imer/Counter Timing Diagrams” on page 136.
14.8.1 Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in
the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by soft-
ware. There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, obse rve that the maximum
interval betwee n the e xtern al event s must not exceed the r esolutio n of t he count er. If the inter val
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
14.8.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CT C mode (WGMn3:0 = 4 or 12), the O CRnA or ICRn Register
are used to manipulat e th e counte r re so lut ion . I n CT C mode t he coun te r is cleare d to zero when
the counter value (TCNTn) matche s either th e OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =
12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This
mode allows greate r contr ol of the co mpa re mat ch out put f reque ncy. I t also simpl ifie s the o per a-
tion of counting exter nal events.
The timing diagram for the CTC mode is shown in Figure 14-6. The counter value (TCNTn)
increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn)
is cleared.
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Figure 14-6. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reach es the TOP value by either
using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How-
ever, changing th e TOP to a value close to BOTTOM when the cou nter is run ning with no ne or a
low prescaler value must be done with care since the CTC mode does not have the double buff-
ering feature. If the new value written to OCRnA or ICRn is lower than the current value of
TCNTn, the counter will miss the compare match. The counter will then have to count to its max-
imum value (0xFFFF) and wr ap around startin g at 0x0000 before the compare match can occur.
In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.
For generatin g a wavefor m out put in CT C mod e, t he OCnA ou tput can be se t to toggle it s logica l
level on each compare match by setting the Compare Output mode bits to toggle mode
(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum fre-
quency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The wavefo rm frequency is
defined by the fo llow i ng equation:
The N variable represents th e pr escaler factor (1, 8, 64 , 25 6, or 10 24 ).
As for the Normal mode of op erat ion, the T OVn Flag is se t in the same tim er clock cycle tha t the
counter counts from MAX to 0x0000.
14.8.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation optio n. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Com pare Output mode, the Outpu t Compare (OCnx) is set on
the compare match between TCNTn and OCRnx, and cleared at TOP. In inverting Compare
Output mode output is cleared on compare match and set at TOP. Due to the single-slope oper-
ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct
and phase and frequency correct PWM modes that use dual-slope operation. This high fre-
quency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capaci-
tors), hence reduces total system cost.
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 4
Period
2 3
(COMnA1:0 = 1)
fOCnA fclk_I/O
2N1OCRnA+()⋅⋅
---------------------------------------------------=
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or
OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max-
imum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolutio n in bits can be
calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 =
14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer
clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-7. The figure
shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the
timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-invert ed an d inver ted PWM ou tput s. The small ho rizonta l lin e m arks on th e TCNTn
slopes represent compare matches between OCRnx a nd TCNTn. The OCnx Interrupt Flag will
be set when a comp ar e m atch occurs.
Figure 14-7. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition
the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA
or ICRn is used fo r defining t he TOP value. If o ne of the inte rrupts are enab led, the interr upt han-
dler routine can be used for updating the TOP and compare values.
When changing the TOP value the prog ram must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCRnx Registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP
value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low
value when the counter is ru nning wit h none or a low prescaler value, there is a r isk that t he new
ICRn value written is lower than the current value of TCNTn. The result will then be that the
counter will miss the compare match at the TOP value. The counter will then have to count to the
MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location
RFPWM TOP 1+()log 2()log
-----------------------------------=
TCNTn
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)
1 7
Period 2 3 4 5 6 8
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
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to be written anytime. When the OCRnA I/O location is written the value written will be put into
the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done
at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set.
Using the ICRn Regis ter for defining TOP work s well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow ge neration of PWM waveforms on the OCnx pins.
Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COMnx1:0 to three (see Table on page 140). The actual OCnx
value will only be visible o n the port pin if the data direction for the port pin is set a s output
(DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at
the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable re pr esents the prescale r divider (1, 8, 64, 25 6, or 10 24 ).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output i n the fast PWM mode. If the OCRnx is set equal to BOTT OM (0x0000) the ou t-
put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COMnx1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies only
if OCR1A is used to define the TOP v alue (WGM13:0 = 15). The waveform generated will have
a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). This feature is
similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output Com-
pare unit is enabled in the fast PWM mode.
14.8.4 Phase Correct PWM Mode
The ph ase correct Pulse Width Modulation or phase co rrect PWM mode (WGMn3:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and fre quency correct PWM m ode, based on a du al-
slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is
cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower m aximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferre d for motor control applications.
The PWM resolution for the phase corre ct PWM mode can be fixed t o 8-, 9-, or 10-b it, or defined
by either ICRn or OCRn A. The minimum resolution allowed is 2 -bit (ICRn or OCRnA set to
fOCnxPWM fclk_I/O
N1TOP+()⋅
-----------------------------------=
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0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolu-
tion in bits can be calcul ated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn
(WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock
cycle. The timing dia gram for the phase correct PWM mode is shown on Figure 14-8. The figure
shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNTn slopes repre sent compare matches betwe en OCRnx and TCNTn. The OCnx Inter-
rupt Flag will be set when a compare match occurs.
Figure 14-8. Phase Correct PWM Mode , Tim in g Dia gr am
The Timer/Count er Ove rfl ow Flag (TOVn) is se t each t ime th e co unte r r ea ches BO TTOM. When
either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accord-
ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer
value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the prog ram must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCRnx Registers are written. As the third period shown in Figure 14-8 illustrates, changing the
TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical out put. T he rea son for this can be fo und in th e time of up date of the OCRnx Re g-
RPCPWM TOP 1+()log 2()log
-----------------------------------=
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
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ister. Since the OCR nx update occurs at TOP, the PWM period starts and ends at TOP. Th is
implies that the length of the falling slo pe is determined by the previous TOP value, while the
length of the rising slope is determined by the new TOP value. When these two values differ the
two slopes of the period will differ in length. The difference in length gives the unsymmetrical
result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changin g the TOP value while the Timer/ Counter is running. When using a static
TOP value there are pr actically no differences betw een the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to tw o will produce a non-inverted PWM and an inverted
PWM output can be gener at ed by sett in g th e COMnx1: 0 to t hree (Se e Tab l e 14- 3 on page 141).
The actual OCnx value will only be visible on the port pin if the data direction for the port pin is
set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx
Register at the compare matc h between OCRnx and TCNTn when the counte r increments , and
clearing (or setting) the OCn x Register at compare match between OCRnx and TCNTn when
the counter decreme nts. The PWM fre quency for the output when using phase correct PWM can
be calculated by the following equation:
The N variable re pr esents the prescale r divider (1, 8, 64, 25 6, or 10 24 ).
The extreme values for the OCRnx Register represent special cases when generating a PWM
waveform output in the phas e correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
14.8.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct Pu lse Width Mod ulation, or phase and frequen cy correct PWM
mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-
form generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TO P to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while
upcounting, and set on the com pare match while downcounting. In inverting Comp are Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-
quency compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM mo de s, th es e mo de s ar e pr eferred for moto r co ntr o l app lica tio ns.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 14-
8 and Figure 14-9).
The PWM resolution for the phase and frequency correct PWM m ode can be defin ed by either
ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and
fOCnxPCPWM fclk_I/O
2NTOP⋅⋅
----------------------------=
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the maximum resolution is 16-bit (ICRn or OCRnA set t o MAX). The PWM resolution in bits can
be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). Th e
counter has then reached the TOP and changes the count direction. The TCNTn value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on Figure 14-9. Th e figure shows phase and frequency correct
PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing dia-
gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-
inverted and in verted PWM o utputs. The small horizonta l line marks on the TCNTn slopes repre-
sent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a
compare match occurs.
Figure 14-9. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx
Registers are updat ed with the doub le buffer value ( at BOTTO M). Wh en either OCRnA o r ICRn
is used for defining the TO P value, the OCnA or ICFn Flag set when TCNTn has reached TOP.
The Interrupt Flags can then be used to generate an int er rup t ea ch ti me t he count er re aches the
TOP or BOTTOM value.
When changing the TOP value the prog ram must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
As Figure 14-9 shows the output generated is, in contrast to the phase correct mode, symmetri-
cal in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising
and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore
frequency correct.
RPFCPWM TOP 1+()log 2()log
-----------------------------------=
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
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Using the ICRn Regis ter for defining TOP work s well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is a ctively changed by chang ing the TOP value, using t he OCRnA as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be g enera ted by setting the COM nx1:0 to three (See Table 14-3 on
page 141). The actual OCnx value will only be visible on the port pin if the data direction for the
port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing)
the OCnx Register at the compare match between OCRnx and TCNTn when the counter incre-
ments, and clearing (or setting) the OCnx Register at compare match between OCRnx and
TCNTn when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable re pr esents the prescale r divider (1, 8, 64, 25 6, or 10 24 ).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the phas e correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A
is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle
with a 50% duty cycle.
14.9 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a
clock enable sign al in the following figures. Th e figures include information on whe n Interrupt
Flags are set, and when the OCRnx Register is up dated with the OCRnx buffer value (only for
modes utilizing double buffering). Figure 14-10 shows a timing diagra m for the setting of OCFnx.
Figure 14-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
Figure 14-11 shows the same timing data, but with th e prescaler enabled.
fOCnxPFCPWM fclk_I/O
2NTOP⋅⋅
----------------------------=
clk
Tn
(clkI/O/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx V alue
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
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Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)
Figure 14-12 shows the count seq uen ce close to TO P in vari ou s modes. When using ph ase and
frequency correct PWM mode t he OCRnx Register is updated at BOTTOM. The timin g diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTO M+1 and so on.
The same renaming applies for modes that set the TOVn Flag at BOTTOM.
Figure 14-12. Timer/Counter Timing Diagram, no Prescaling
Figure 14-13 shows the same timing data, but with th e prescaler enabled.
OCFnx
OCRnx
TCNTn
OCRnx V alue
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
TOVn (FPWM)
and ICFn (if used
as T OP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
Tn
(clk
I/O
/1)
clkI/O
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Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
14.10 16-bit Timer/Counter Register Description
14.10.1 Timer/Counter1 Control Register A – TCCR1A
14.10.2 Timer/Counter3 Control Register A – TCCR3A
•Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
•Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
•Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1 :0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit correspondin g to the OCnA, OCnB or
OCnC pin must be set in order to enable the output d river.
TOVn
(FPWM)
and ICFn
(if used
as T OP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
Bit 76543210
COM1A
1COM1A
0COM1B
1COM1B
0COM1C
1COM1C
0WGM1
1WGM1
0TCCR1
A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
COM3A
1COM3A
0COM3B
1COM3B
0COM3C
1COM3C
0WGM3
1WGM3
0TCCR3
A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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.
Table 14-2 shows the COMnx1 :0 bit functionality when the WGMn3:0 bits are set to the fast
PWM mode.
Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear
is done at TOP. See “Fast PWM Mode” on page 106. for more details.
Table 14-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
correct and frequency correct PWM mode.
Table 14-1. Compare Output Mode, non-PWM
COMnA1/COMnB1/
COMnC1 COMnA0/COMnB0/
COMnC0 Description
00
Nor m al port operation, OCnA/OCnB/OCnC
disconnected.
01
Toggle OCnA/OCnB/OCnC on compare
match.
10
Clear OCnA/OCnB/OCnC on compare
match (set output to low level).
11
Set OCnA/OCnB/OCnC on compare match
(set output to high lev el).
Table 14-2. Compare Output Mode, Fast PWM
COMnA1/COMnB1/
COMnC0 COMnA0/COMnB0/
COMnC0 Description
00
Nor m al port operation, OCnA/OCnB/OCnC
disconnected.
01
WGM13:0 = 14 or 15: Toggle OC1A on
Compare Match, OC1B and OC1C
disconnected (normal port operation). For all
other WGM1 settings, normal port operation,
OC1A/OC1B/OC1C disconnected.
10
Clear OCnA/OCnB/OCnC on compare
match, set OCnA/OCnB/ OCnC at TOP
11
Set OCnA/OCnB/OCnC on compare match,
clear OCnA/OCnB/OCnC at TOP
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Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1//COMnC1 is set. See “Phase Correct PWM Mode” on page 108. for more
details.
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3: 2 bit s found in t he TCCRnB Register, these bit s contr ol the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 14-4. Modes of operation supported by th e Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 105.).
Table 14-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
COMnA1/COMnB/
COMnC1 COMnA0/COMnB0/
COMnC0 Description
00
Nor m al port operation, OCnA/OCnB/OCnC
disconnected.
01
WGM13:0 = 8, 9 10 or 11: Toggle OC1A on
Compare Match, OC1B and OC1C
disconnected (normal port operation). For all
other WGM1 settings, normal port operation,
OC1A/OC1B/OC1C disconnected.
10
Clear OCnA/OCnB/OCnC on compare
match when up-counting. Set
OCnA/OCnB/OCnC on compare match
when downcounting.
11
Set OCnA/OCnB/OCnC on compare match
when up-counting. Clear
OCnA/OCnB/OCnC on compare match
when downcounting.
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Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functiona lity and
location of these bits are compatible with previous versions of the timer.
14.10.3 Timer/Counter1 Control Register B – TCCR1B
14.10.4 Timer/Counter3 Control Register B – TCCR3B
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The input capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICESn: Input Capture Edge Select
Table 14-4. Waveform Generation Mode Bit Description(1)
Mode WGMn3 WGMn2
(CTCn) WGMn1
(PWMn1) WGMn0
(PWMn0) Timer/Counter Mode of
Operation TOP Update of
OCRnx at TOVn Flag
Set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCRnA Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP T OP
6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP T OP
7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP T OP
81000
PWM, Phase and Frequency
Correct ICRn BOTTOM BOTTOM
91001
PWM, Phase and Frequency
Correct OCRnA BOTTOM BOTTOM
10 1 0 1 0 PWM, Phase Correct ICRn TOP BOTTOM
11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM
12 1 1 0 0 CTC ICRn Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICRn TOP TOP
15 1 1 1 1 Fast PWM OCRnA T OP TOP
Bit 76543210
ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value00000000
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This bit selects which edge on the Inp ut Capture Pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (pos itive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this int errupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA Register description.
• Bit 2:0 – CSn2:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure
13-8 and Figure 13-9.
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If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
14.10.5 Timer/Counter1 Control Register C – TCCR1C
14.10.6 Timer/Counter3 Control Register C – TCCR3C
•Bit 7 – FOCnA: Force Output Compare for Channel A
•Bit 6 – FOCnB: Force Output Compare for Channel B
•Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare
match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-
mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
•Bit 4:0 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero w hen TC CRnC is written.
14.10.7 Timer/Counter1 – TCNT1H and TCNT1L
Table 14-5. Clock Select Bit Description
CSn2 CSn1 CSn0 Description
0 0 0 No clock source. (Timer/Counter stopped)
001clk
I/O/1 (No prescaling
010clk
I/O/8 (From prescaler)
011clk
I/O/64 (From prescaler)
100clk
I/O/256 (From prescaler)
101clk
I/O/1024 (From prescaler)
1 1 0 External clock source on Tn pin. Clock on falling edge
1 1 1 External clock source on Tn pin. Clock on rising edge
Bit 76543210
FOC1A FOC1B FOC1C – – – – – TCCR1C
Read/Write W W W R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
FOC3A FOC3B FOC3C – – – – – TCCR3C
Read/Write W W W R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
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14.10.8 Timer/Counter3 – TCNT3H and TCNT3L
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
Registers” on page 119.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks ( rem oves) the comp ar e matc h on the followin g timer clock
for all compare units.
14.10.9 Output Compare Register 1 A – OCR1AH and OCR1AL
14.10.10 Output Compare Register 1 B – OCR1BH and OCR1BL
14.10.11 Output Compare Register 1 C – OCR1CH and OCR1CL
14.10.12 Output Compare Register 3 A – OCR3AH and OCR3AL
TCNT1[15:8] TCNT1H
TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
TCNT3[15:8] TCNT3H
TCNT3[7:0] TCNT3L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR1A[15:8] OCR1AH
OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR1B[15:8] OCR1BH
OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR1C[15:8] OCR1CH
OCR1C[7:0] OCR1CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR3A[15:8] OCR3AH
OCR3A[7:0] OCR3AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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14.10.13 Output Compare Register 3 B – OCR3BH and OCR3BL
14.10.14 Output Compare Register 3 C – OCR3CH and OCR3CL
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn ). A match can be used to generate an Output Com pare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compa re Register s are 16-b it in size. To ensure t hat both the high and low bytes are
written simultaneously when th e CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEM P). This temporary register is shared by all the other
16-bit register s. See “Accessing 16-bit Registers” on page 119.
14.10.15 Input Capture Register 1 – ICR1H and ICR1L
14.10.16 Input Capture Register 3 – ICR3H and ICR3L
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or opt ionally on t he Analo g Comparat or o utput f or Timer/ Counter 1). The Input Capture
can be used for defining the counter TOP value.
The Input Captur e Registe r is 16-bit in size . To en sure tha t both the high and low byt es are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). Th is temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 119.
14.10.17 Timer/Counter1 Interrupt Mask Register – TIMSK1
Bit 76543210
OCR3B[15:8] OCR3BH
OCR3B[7:0] OCR3BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR3C[15:8] OCR3CH
OCR3C[7:0] OCR3CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
ICR3[15:8] ICR3H
ICR3[7:0] ICR3L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
––ICIE1–OCIE1
COCIE1B OCIE1A TOIE1 TIMSK1
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value00000000
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14.10.18 Timer/Counter3 Interrupt Mask Register – TIMSK3
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Coun tern Input Capture interrupt is enable d. The corresponding Interrupt
Vector (See “Interrupts” on page 68.) is executed when the ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), th e Time r/Coun t ern Ou tput Co mpa re C Mat ch inter ru pt is enab led . Th e cor resp on ding
Interrupt Vector (See “Interrupts” on page 68.) is executed when the OCFnC Flag, located in
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), th e Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 68.) is executed when the OCFnB Flag, located in
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), th e Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 68.) is executed when the OCFnA Flag, located in
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page 68.) is executed when the TOVn Flag, located in TIFRn, is set.
14.10.19 Timer/Counter1 Interrupt Flag Register – TIFR1
14.10.20 Timer/Counter3 Interrupt Flag Register – TIFR3
• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
Bit 76543210
––ICIE3–OCIE3
COCIE3B OCIE3A TOIE3 TIMSK3
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
––ICF1– OCF1C OCF1B OCF1A TOV1 TIFR1
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
––ICF3– OCF3C OCF3B OCF3A TOV3 TIFR3
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value00000000
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This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register
(ICRn) is set by the WGMn 3:0 t o be used as the TOP value, the ICFn F lag is set when the coun-
ter reaches the TO P value.
ICFn is automatically cleared when the Input Ca pture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by wr iting a logic one to its bit location.
• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register C (OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe-
cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.
• Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register B (OCRnB).
Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag.
OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Matc h Flag
This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Com-
pare Register A (OCRnA).
Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag.
OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCFnA can be cleared by writing a logic one to its bit location.
• Bit 0 – TOVn: Timer/Countern, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOVn Flag is se t when the timer overflows. Refer to Table 14-4 on page 142 for the TOVn
Flag behavior when using another WGMn3:0 bit setting.
TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed.
Alternatively, TOVn can be cleared by writing a logic one to its bit location.
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15. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main
features are:
•Single Channel Counter
•Clear Timer on Compare Match (Auto Reload)
•Glitch-free, Phase Correct Pulse Width Modulator (PWM)
•Frequency Generator
•10-bit Clock Prescaler
•Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
•Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
15.1 Overview A simplified bl ock diagram of the 8-bit Timer/Co unter is shown in Figure 15-1.. For th e actual
placement of I/O pins, se e “Pin Configurations” o n page 3. CPU accessible I/O Registers, includ-
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the “8-bit Timer/Counter Register Descrip tion” on page 160.
The Power Reduc tion Ti mer/Coun ter2 b it, PR TIM2, in “Pow er Reductio n Register 0 - PRR0” o n
page 54 must be written to zero to enable Timer/Counter2 module.
Figure 15-1. 8-bit Timer/Counter Block Diagram
Timer/Counter
DATA BUS
OCRnA
OCRnB
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
=
Fixed
TOP
Value
Control Logic
=
0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TCCRnA TCCRnB
clk
Tn
ASSRn
Synchronization Unit
Prescaler
T/C
Oscillator
clk
I/O
clk
ASY
asynchronous mode
select (ASn)
Synchronized Status flags
TOSC1
TOSC2
Status flags
clk
I/O
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15.1.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg-
isters. Interrupt request (abbreviated to Int.Req.) signals are all visible in t he Timer Inte rrupt Flag
Register (TIFR2) . All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from
the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by
the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock
source the Timer/Cou nter uses to incremen t (or decrement) its value. The Timer/ Counter is inac-
tive when no clo ck source is selected. The out put from th e Clock Select logic is referre d to as the
timer clock (clkT2).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and
OC2B). See “O ut pu t Co mpare Un it” o n p age 15 1. for details. The compare match event will also
set the Compare Flag (OCF2A or OCF2B) which can be used to generate a n Output Compare
interrupt request.
15.1.2 Definitions Many register and bit references in this document a re written in general form. A lowe r case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2
counter value and so on.
The definitions in the table below are also used extensively throughout the section.
15.2 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. W hen the A S2
bit in the ASSR Register is written to logic one, th e clock sour ce is taken fr om the Timer /Counter
Oscillator connected to TOS C1 and TOSC2. For details on asy nchronous operation, see “Asyn-
chronous Statu s Register – ASSR” on pa ge 165. For details on clock sources and prescaler , see
“Timer/Counter Prescaler” on page 168.
15.3 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
15-2 shows a block diagram of the counter and its surrounding environment.
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reach es its MAXimum wh en it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The
assignment is dependent on the mode of opera tion.
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Figure 15-2. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or de cre m en t TCNT2 by 1.
direction Selects between increment and decrement.
clear Clear TCNT2 (set all bits to zero).
clkTn Timer/Co un te r clo ck, re fe rr ed to as clk T2 in the following.
top Signalizes that TCNT2 has reached maximum value.
bottom Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mo de o f oper at ion us ed, the cou nt er is cleared , in cr eme nted , o r decr em ent ed
at each timer clock (clkT2). clkT2 can be generated from an external or inte rnal clock source,
selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clkT2 is present or not. A CPU write overrides (has priority over ) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter
Control Register B (TCCR2B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.
For more details about advanced counting sequences and waveform generation, see “Modes of
Operation” on page 154.
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by
the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.
15.4 Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2A and OCR2B). Whenever TCNT2 equa ls OCR2A or OCR2B, the comparator signals a
match. A match will set the Output Compar e Flag (OCF2A or OCF2 B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt . Th e Outp ut Co mpare Flag is aut om atica lly cleare d wh en the int errup t is exe-
cuted. Alternatively, the Output Com pare Flag can be cleared by software by writing a logical
one to its I/O bit location. The Waveform G enerator uses the match signal to generate an output
according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0)
bits. The max and bottom signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation (“Modes of Operation” on page 154).
Figure 14-10 on page 136 shows a block diagram of the Output Compare unit.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
topbottom
direction
clear
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clk
I/O
clk Tn
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Figure 15-3. Output Compare Unit, Block Diagram
The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Nor mal and Clear Timer on Compare (CTC ) modes of operation, the double
buffering is di sabled. The double buffering sync hronizes the update of the OCR2x Compare
Register to either top o r bottom of the counting sequence . The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2x Register access may seem co mplex, but this is not case. Wh en the double buff ering
is enabled, the CPU has access to the OC R2x Buffer Register, and if double buffering is dis-
abled the CPU will access the OCR2x directly.
15.4.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the
OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare
match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or
toggled).
15.4.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initial-
ized to the same value as TCNT2 wit hout trigg ering an inte rrupt when t he Timer/Coun ter clock is
enabled.
15.4.3 Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock
cycle, there are r isks involved when changing TCNT 2 when using the Output Compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT2
equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the count er is
downcounting.
OCFnx (Int.Req.)
= (8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform Generator
top
FOCn
COMnX1:0
bottom
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The setup of the OC2x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com-
pare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when
changing between Wa veform Generation modes.
Be aware that the COM2x1:0 bits are not double buffered together with the compare value.
Changing the COM2x1:0 bits will take effect immediately.
15.5 Compare Match Output Unit
The Compare Outpu t mode (COM2x1: 0) bits ha ve two funct ions. The Wavef orm Genera tor uses
the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match.
Also, the COM2x1:0 bits control the OC2x pin output source. Figure 15-4 shows a simplified
schematic of th e logic affecte d by the COM2x1: 0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the
OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.
Figure 15-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform
Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visi-
ble on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initializat ion of the OC2x state before t he out-
put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of
operation. See “8-bit Timer/Counter Register Description” on page 160.
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA BUS
FOCnx
clk
I/O
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15.5.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the
OC2x Register is t o be performed on the next com pare match. F or compare output actions in t he
non-PWM modes refer to Table 15-4 on page 161. For fast PWM mode, refer to Table 15-5 on
page 162, and for phase correct PWM refer to Table 15-6 on page 162 .
A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC2x strobe bits.
15.6 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the comb ination of the Wave form Generati on mode (WGM22: 0) and Compare Ou tput
mode (COM2x1:0) bits. T he Compare Output mode bits do no t affect the counting sequence,
while the Waveform Gener ation mode bits do . The COM2x1:0 bi ts control whether th e PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare
match (See “Compare Match Output Unit” on page 153.).
For detailed timing information refer to “ T imer/Counter Timing Diagrams” on page 158.
15.6.1 Normal Mode The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same
timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflo w interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compar e u nit can be used to ge nerat e int errup t s at so me given time . Usin g the Ou t-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
15.6.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to
manipulate the count er resolut io n. In CTC mode the counter is clear ed to zero wh en the counter
value (TCNT2) matches the OCR2A. The OCR2A de fines the top value for the counter, hence
also its resolution. This m ode allows greater control of the compare ma tch output frequency. It
also simplifies the op e ra tio n of coun tin g exte rn al ev en ts.
The timing diagram for the CTC mode is shown in Table 15-5. The counter value (TCNT2)
increases until a compare match occurs between TCNT2 and OCR2A, and then counter
(TCNT2) is cleared.
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Figure 15-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
ning with none or a low pres caler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR2A is lower than the current
value of TCNT2, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generatin g a wavefor m out put in CT C mod e, t he OC2A ou tput can be se t to toggle it s logica l
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC2A =
fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following
equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cy cle that the
counter counts from MAX to 0x00.
15.6.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM22 :0 = 3 or 7) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-
TOM. TOP is defined as 0xFF when WGM22:0 = 3 , and OCR2A when MGM22:0 = 7. In non-
inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match
between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the out-
put is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the
operating fr equency of the fast PWM mode can be twice as high as the phase correct PWM
mode that uses dual-slop e operation. This hig h frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
TCNTn
OCnx
(Toggle)
OCnx Interrupt Flag Set
1 4
Period 2 3
(COMnx1:0 = 1)
fOCnx fclk_I/O
2N1OCRnx+()⋅⋅
--------------------------------------------------=
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In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 15-6. The TCNT2 value is in the timing diagram shown as a his-
togram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. Th e small horizo ntal line marks on th e TCNT2 slopes represe nt compare
matches between OCR2x and TCNT2.
Figure 15-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveform s on the OC2x pin.
Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generate d by setting the COM2x1:0 to three. TOP is de fined as 0xFF whe n WGM2:0 = 3,
and OCR2A when WGM2:0 = 7 (See Table 15-2 on page 161). The actual OC2x value will only
be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-
form is generated by setting (o r clearing) the OC2x Reg ister at the compare match between
OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the
counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases wh en generating a PWM
waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period
2 3
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
fOCnxPWM fclk_I/O
N256⋅
------------------=
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generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This fea-
ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
15.6.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The coun ter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-
TOM. TOP is defined as 0xFF when WGM22:0 = 1 , and OCR2A when MGM22:0 = 5. In non-
inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match
between TCNT2 and OCR2 x while upco unting, and set on the compar e match while do wncoun t-
ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the symmet-
ric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correc t PWM mode the counter is increm ented until the counte r value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal
to TOP for one timer clo ck cycle. The tim ing dia gram fo r th e pha se correct PWM mode is shown
on F igure 15- 7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x
and TCNT2.
Figure 15-7. Phase Correct PWM Mode , Tim in g Dia gr am
The Timer/Counter Over flow Flag (TOV2) is set each time the counter reache s BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Update
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output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when
WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 15-3 on page 161). The actual OC2x
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match
between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x
Register at compare match between OCR2x and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation :
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases wh en generating a PWM
waveform output in the phase correct PWM mo de. If the OCR2A is set equal to BO TTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 15-7 O Cnx has a transition from high to low even though
there is no Compare Match. The point of this transition is to guarantee sym metry around BOT-
TOM. There are two cases that give a transition without Compare Match.
• OCR2A changes its value from MAX, lik e in Figu re 15-7. When the OCR2A value is MAX the
OCn pin value is the same as the result of a down-counting compare match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
• The timer starts counting from a v alue higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
15.7 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2)
is therefore shown as a clock en able signal. In asynchronous mode, clkI/O should be replaced by
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set. Figure 15-8 contains timing data for basic Timer/Counter operation. The figure shows the
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 15-8. Timer/Counter Timing Diagram, no Prescaling
fOCnxPCPWM fclk_I/O
N510⋅
------------------=
clk
Tn
(clk
I/O/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
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Figure 15-9 shows the same timing data, but with the prescaler enabled.
Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
Figure 15-10 shows the setting of OCF2A in all modes except CTC mode.
Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)
Figure 15-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx V alue
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clk
I/O
/8)
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Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (fclk_I/O/8)
15.8 8-bit Timer/Counter Register Description
15.8.1 Timer/Counter Control Register A – TCCR2A
• Bits 7:6 – COM2A1:0 : Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin
must be set in order to enable the output dr iver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting. Table 15- 1 shows the COM2A1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clk
I/O
/8)
Bit 76543210
COM2A
1COM2A
0COM2B
1COM2B
0––WGM2
1WGM2
0TCCR2A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 15-1. Compare Output Mode, non-PWM Mode
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
0 1 Toggle OC2A on Compare Match
1 0 Clear OC2A on Compare Match
1 1 Set OC2A on Compare Match
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Table 15-2 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 155
for more details.
Table 15-3 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at T OP. See “Phase Correct PWM Mode” on
page 157 for more details.
• Bits 5:4 – COM2B1:0 : Compare Match Output B Mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0
bits are set, the OC2B outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin
must be set in order to enable the output dr iver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the
WGM22:0 bit setting. Table 15- 4 shows the COM2B1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
Table 15-2. Compare Output Mode, Fast PWM Mode(1)
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
01
WGM22 = 0: Nor m al Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Ma tch.
1 0 Clear OC2A on Compare Match, set OC2A at TOP
1 1 Set OC2A on Compare Match, clear OC2A at TOP
Table 15-3. Compare Output Mode, Phase Correct PWM Mod e(1)
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
01
WGM22 = 0: Nor m al Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Ma tch.
10
Clear OC2A on Compare Match when up-counting. Set OC2A on
Compare Match when down-counting.
11
Set OC2A on Compare Match wh en u p -co un ti n g. C l ea r OC2A on
Compare Match when down-counting.
Table 15-4. Compare Output Mode, non-PWM Mode
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
0 1 Toggle OC2B on Compare Match
1 0 Clear OC2B on Compare Match
1 1 Set OC2B on Compare Match
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Table 15-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 155
for more details.
Table 15-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at T OP. See “Phase Correct PWM Mode” on
page 157 for more details.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the ATmega32U6/AT90USB64/128 and will always read as zero.
• Bits 1:0 – WGM21: 0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 15-7. Modes of operation supported by th e Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) mod es (s ee “Modes of Operation” on page 154).
Table 15-5. Compare Output Mode, Fast PWM Mode(1)
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
01Reserved
1 0 Clear OC2B on Compare Match, set OC2B at TOP
1 1 Set OC2B on Compare Match, clear OC2B at TOP
Table 15-6. Compare Output Mode, Phase Correct PWM Mod e(1)
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
01Reserved
10
Clear OC2B on Compare Match when up-counting. Set OC2B on
Compare Match when down-counting.
11
Set OC2B on Compare Match wh en u p -co un ti n g. C l ea r OC2B on
Compare Match when down-counting.
Table 15-7. Wa ve fo rm Ge ne ra tion Mo d e Bit Des crip tio n
Mode WGM2 WGM1 WGM0
Timer/Counter
Mode of
Operation TOP Update of
OCRx at TOV Flag
Set on(1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
10 0 1
PWM, Phase
Correct 0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
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Notes: 1. MAX= 0xFF
2. BOTTOM= 0x00
15.8.2 Timer/Counter Control Register B – TCCR2B
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is
changed according to its COM2A1:0 bits setting. Note th at the FOC2A bit is implemented as a
strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the
forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6 – FOC2B: Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is
changed according to its COM2B1:0 bits setting. Note th at the FOC2B bit is implemented as a
strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the
forced compare.
A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2B as TOP.
The FOC2B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega32U6/AT90USB64/128 and will always read as zero.
3 0 1 1 Fast PWM 0xFF TOP MAX
41 0 0Reserved – – –
51 0 1
PWM, Phase
Correct OCRA TOP BOTTOM
61 1 0Reserved – – –
7 1 1 1 Fast PWM OCRA TOP TOP
Table 15-7. Wa ve fo rm Ge ne ra tion Mo d e Bit Des crip tio n
Mode WGM2 WGM1 WGM0
Timer/Counter
Mode of
Operation TOP Update of
OCRx at TOV Flag
Set on(1)(2)
Bit 76543210
FOC2A FOC2B – – WGM22 CS22 CS21 CS20 TCCR2B
Read/Write W W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 3 – WGM22: Waveform Generation Mode
See the descript ion in the “Timer/Counter Control Register A – TCCR2A” on page 160.
• Bit 2:0 – CS22:0: Clock Select
The three Clock Se lect bits select the cl ock source to be use d by the Timer/Co unter, see Table
15-8.
15.8.3 Timer/Counter Register – TCNT2
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.
15.8.4 Output Compare Register A – OCR2A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Outp ut Compare interrupt, or to
generate a waveform output on the OC2A pin.
15.8.5 Output Compare Register B – OCR2B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Outp ut Compare interrupt, or to
generate a waveform output on the OC2B pin.
Table 15-8. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
001clk
T2S/(No prescaling)
010clk
T2S/8 (From prescaler)
011clk
T2S/32 (From prescaler)
100clk
T2S/64 (From prescaler)
101clk
T2S/128 (From prescaler)
110clk
T2S/256 (From prescaler)
111clk
T2S/1024 (From prescaler)
Bit 76543210
TCNT2[7:0] TCNT2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR2A[7:0] OCR2A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
OCR2B[7:0] OCR2B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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15.9 Asynchronous operation of the Timer/Counter
15.9.1 Asynchronous Status Register – ASSR
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, an d asynchronous clock is select ed, the e xternal clo ck input buf-
fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a
32 kHz crystal. Writing to EXCLK should be done before asynchronou s operation is selected.
Note that the crystal Oscillator will only run when this bit is zero.
• Bit 5 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is
written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil-
lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A,
OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchrono usly and TCNT2 is written, this bit becomes set.
When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.
When OCR2A has been updated f rom the tem porary st orage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.
When OCR2B has been updated f rom the tem porary st orage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.
When TCCR2A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new
value.
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set.
When TCCR2B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new
value.
If a write is performed to any of the five Time r/Counter2 Registers while its update busy fla g is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
Bit 7 6 5 4 3 2 1 0
– EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR
Read/Write R R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0
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The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.
When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A
and TCCR2B the value in the temporary storage register is read.
15.9.2 Asynchronous Operation of Timer/Counter2
When Timer/Coun ter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A
safe procedure for switching clock source is:
a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
b. Select clock source by setting AS2 as appropriate.
c. Write new values to TCNT2, OCR2x, and TCCR2x.
d. To s witch t o asynchronous o peration: Wait for TCN2UB , OCR2xUB , and T CR2xUB .
e. Clear the Timer/Counter2 Interrupt Flags.
f. Enable interrupts, if needed.
• The CPU main clock frequency must be more than four times the Oscillator frequency.
• When writing to one of the registe rs TCNT2, OCR2x, or TCCR2x, the v alue is tr ansf erred to a
temporary register, and latched after two positive edges on TOSC1. The user should not
write a new value before the contents of the temporary register have been transferred to its
destination. Each of the five mentioned registers have their individual temporary register,
which means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. To
detect that a transfer to the destination register has taken place, the Asynchronous Status
Register – ASSR has been implemented.
• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,
OCR2x, or TCCR2x, the user must wait until the written register has been upd ated if
Timer/Counter2 is used to wake up the de vice. Otherwise, the MCU will enter sleep mode
bef ore the change s are eff ective . This is particularly important if any of the Output Comp are2
interrupt is used to wake up the de vice, since the Output Compare function is d isab led during
writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode
before the corresponding OCR2xUB bit returns to zero, the device will never receive a
compare match interrupt, and the MCU will not wake up.
• If Timer/Counter2 is used to wake the device up from Power-sa ve or ADC Noise Reduction
mode, precautions must be taken if the user wants to re-enter one of these modes: The
interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-
entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the
device will fail to wake up. If the user is in doubt whether the time before re-entering Power-
save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to
ensure that one TOSC1 cycle has elapsed:
a. Write a value to TCCR2x, TCNT2, or OCR2x.
b. Wait until the corresponding Update Busy Flag in ASSR returns to zero.
c. Enter Power-save or ADC Noise Reduction mode.
• When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2
is always running, except in Power-down and Standby modes. After a Power-up Reset or
wake-up from Power-down or Standby mode, the user should be aware of the fact that this
Oscillator might take as long as one second to stabilize. The user is advised to wait for at
least one second before using Timer/Counter2 after power-up or wake-up from Power-down
or Standb y mode. The contents of all Timer/Coun ter2 Registers m ust be considered lost after
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a wake-up from Power -do wn or Stan dby mode due to unsta b le clock signal upon start-up , no
matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is
clocked asynchronously: When the interrupt condition is me t, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counte r value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution fr om the instruction following
SLEEP.
• Reading of the TCNT2 Re gister shortly after wak e-up from Power-sa v e ma y giv e an incorrect
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchr oniz ed to the internal I/O cloc k domain. Synchronizatio n tak es
place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O
clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering
sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from
Power-save mode is essentially un predictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
a. Write any value to either of the registers OCR2x or TCCR2x.
b. Wait for the corr esponding Update Busy Flag to be cleared.
c. Read TCNT2.
• During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
adv anced by at lea st one bef ore the processor ca n read the timer v alue causing the setting of
the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not
synchroniz ed to the processor clock.
15.9.3 Timer/Counter2 Interrupt Mask Register – TIMSK2
• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counte r2 Compare M a tch B in te rr up t is enabled. T h e co rr es po nd in g int er ru p t is e xe c u te d
if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Coun-
ter 2 Interrupt Flag Register – TIFR2.
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counte r2 Compare M a tch A in te rr up t is enabled. T h e co rr es po nd in g int er ru p t is e xe c u te d
if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Coun-
ter 2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Cou nter2 occur s, i.e., when the TOV2 bit is se t in the Tim er/Count er2 Int errupt
Flag Register – TIFR2.
Bit 765432 1 0
–––––OCIE2BOCIE2ATOIE2TIMSK2
Read/WriteRRRRRR/W R/WR/W
Initial Value 0 0 0 0 0 0 0 0
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15.9.4 Timer/Counter2 Interrupt Flag Register – TIFR2
• Bit 2 – OCF2B: Out put Compare Flag 2 B
The OCF2B bit is set ( one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counte r2 Compare match Interrupt
Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 1 – OCF2A: Out put Compare Flag 2 A
The OCF2A bit is set ( one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counte r2 Compare match Interrupt
Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflo w occurs in Time r/Coun te r2 . TO V2 is clear ed by har d-
ware when executing the corre spon ding int erru pt han dling vecto r. Alt ernat ively, TOV2 is clear ed
by writing a logic one to th e flag. When t he SREG I- bit, TO IE2 A (Timer /Co unte r2 Ove rfl ow Inte r-
rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
15.10 Timer/Counter Prescaler
Figure 15-12. Prescaler for Timer/Counter2
Bit 76543210
–––––OCF2BOCF2ATOV2TIFR2
Read/WriteRRRRRR/WR/WR/W
Initial Value00000000
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clkI/O clkT2S
TOSC1
AS2
CS20
CS21
CS22
clk
T2S
/8
clk
T2S
/64
clk
T2S
/128
clk
T2S
/1024
clk
T2S
/256
clk
T2S
/32
0
PSRASY
Clear
clkT2
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The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main
system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be conne cted between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Apply-
ing an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,
clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
15.10.1 General Timer/Counter Control Register – GTCCR
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is writ ten when Timer/Counter2 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the “General Timer/Counter Control
Register – GTCCR” on page 99 for a description of the Timer/Counter Synchronization mode.
Bit 7 6 5 4 3 2 1 0
TSM – – – – –PSRA-
SY PSRSY
NC GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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16. Output Compare Modulator (OCM1C0A)
16.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier
frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit
Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details
about these Timer/Counters see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 Pres-
calers” on page 98 and “8-bit Timer/Counter2 with PWM and Asynchronous Operation” on page
149.
Figure 16-1. Output Compare Modulator, Block Diagram
When the modulator is enabled, the two output com pare channels are modulated together as
shown in the block diagram (Figure 16-1).
16.2 Description The Output Compare un it 1C and O utput Compa re unit 2 sha res the PB7 port pin for outp ut. The
outputs of the Outpu t Compare units (OC1C and OC0A) overr ides the nor mal PORTB7 Register
when one of them is enabled (i.e., when COMnx1:0 is not equal to zero). When both OC1C and
OC0A are enabled at the same time, the modulator is automatically enabled.
The functional equivalent schematic of the modulator is shown on Figure 16-2. The schematic
includes part of the Timer/Counter unit s and the port B pin 7 output driver circuit.
Figure 16-2. Output Compare Modulator, Schematic
OC1C
Pin
OC1C /
OC0A / PB7
Timer/Counter 1
Timer/Counter 0
OC0A
PORTB7 DDRB7
DQDQ
Pin
COMA01
COMA00
DATABUS
OC1C /
OC0A/ PB7
COM1C1
COM1C0
Modulator
1
0
OC1C
DQ
OC0A
DQ
( From Waveform Generator )
( From Waveform Generator )
0
1
Vcc
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When the modulator is enabled the type of modulation (logical AND or OR) can be selected by
the PORTB7 Registe r. Note th at the DDRB7 co ntro ls th e d ire ct io n of th e p or t inde pen de nt of t he
COMnx1:0 bit setting.
16.2.1 Timing Example
Figure 16-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to oper-
ate in fast PWM mode (non-inverted ) and Timer/Coun ter0 uses CTC wave form mode with toggle
Compare Output mode (COMnx1:0 = 1).
Figure 16-3. Output Compare Modulator, Timing Diagram
In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated
by the Output Compare unit C of the Timer/Counter1.
The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is
equal to the number of system clock cycles of one period of the carrier (OC0A). In this example
the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure
16-3 at the second and thir d period of the PB 7 output wh en PORTB 7 equals zero. The p eriod 2
high time is one cycle longer than the period 3 high time, but the result on the PB7 output is
equal in both periods.
1 2
OC0A
(CTC Mode)
OC1C
(FPWM Mode)
PB7
(PORTB7 = 0)
PB7
(PORTB7 = 1)
(Period) 3
clk
I/O
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17. Serial Peripheral Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega32U6/AT90USB64/128 and periph eral devices or between several AVR de vices. The
ATmega32U6/AT90USB64/128 SPI includes the following features:
•Full-duplex, Three-wire Synchronous Data Transfer
•Master or Slave Operation
•LSB Fir st or MSB First Data Transfer
•Seven Programmable Bit Rates
•End of Transmission Interrupt Flag
•Write Collision Flag Protection
•Wake-up from Idle Mode
•Double Speed (CK/2) Master SPI Mode
USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 206.
The Power Reduction SPI bit, PRSPI, in “Power Reduction Register 0 - PRR0” on page 54 on
page 50 must be written to zero to enable SPI module.
Figure 17-1. SPI Block Diagram(1)
Note: 1. Refer to Figure 1-1 on page 3, and Table 10-6 on page 8 0 for SPI pin placement.
The interconnect ion between Mast er and Slave CPUs with SPI is shown in Figure 17-2. The sys-
tem consists of two shift Register s, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
SPI2X
SPI2X
DIVIDER
/2/4/8/16/32/64/128
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Slave prepare the data to be sent in their respective shift Regist ers, and the Master generates
the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-
ter to Slave on t he Ma ster Out – Slave In, M OSI, line , and f rom Slave t o Maste r on th e M aste r In
– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling
high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, an d the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this sta te, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission
Flag, SPIF is set. If the SPI Inte rrupt Enable bit, SPIE , in the SPCR Register is set, an interrupt
is requested. The Slave may continue to place new data to be sent into SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 17-2. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Oth-
erwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed fosc/4.
SHIFT
ENABLE
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When the SPI is enab led, th e data di rection of the MO SI, MISO , SCK, and SS pins is overrid den
according to Table 17-1. For more details on automatic port overrides, refer to “Alternate Port
Functions” on page 77.
Note: 1. See “Alternate Functions of Port B” on page 80 for a detailed description of how to define the
direction of the user defined SPI pi ns.
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction
Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be re placed by the
actual data direction bits for these pins. E.g. if M OSI is placed on pin PB5, replace DD_MOSI
with DDB5 and DDR_SPI with DDRB.
Table 17-1. SPI Pin Overrides(1)
Pin Direction, Master SPI Direction, Slave SPI
MOSI User Defined Inp ut
MISO Input User Defined
SCK User Define d Input
SS User Defined Input
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Note: 1. See “About Code Examples” on page 9.
Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)
out DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out SPCR,r17
ret
SPI_MasterTransmit:
; Start transmission of data (r16)
out SPDR,r16
Wait_Transmit:
; Wait for transmission complete
sbis SPSR,SPIF
rjmp Wait_Transmit
ret
C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
void SPI_MasterTransmit(char cData)
{
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)))
;
}
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The following code examples show how to initialize the SPI as a Slave and how to perform a
simple reception.
Note: 1. See “About Code Examples” on page 9.
17.1 SS Pin Functionality
17.1.1 Slave Mode When the SPI is config ured as a Slave, the Sla ve Select (SS) pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which
Assembly Code Example(1)
SPI_SlaveInit:
; Set MISO output, all others input
ldi r17,(1<<DD_MISO)
out DDR_SPI,r17
; Enable SPI
ldi r17,(1<<SPE)
out SPCR,r17
ret
SPI_SlaveReceive:
; Wait for reception complete
sbis SPSR,SPIF
rjmp SPI_SlaveReceive
; Read received data and return
in r16,SPDR
ret
C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)))
;
/* Return Data Register */
return SPDR;
}
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means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin
is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in th e Shift Register.
17.1.2 Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured a s an inpu t, it m ust be held h igh to ensu re Mast er SPI operat ion. If the SS pin
is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starti ng to se nd data t o it. To avoid bus con t ention , th e SPI syst em takes t he fo llowing
actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of
the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enab led, and the I-bit in SREG
is set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-
bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the
MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master
mode.
17.1.3 SPI Control Register – SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to on e, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
Bit 76543210
SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable S PI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL functionality is sum-
marized below:
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL
functionality is summarized below:
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits contr ol the SCK ra te of t he dev ice configur ed as a Mast er. SPR1 and SPR0 ha ve
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is
shown in the following table:
17.1.4 SPI Status Register – SPSR
• Bit 7 – SPIF: SPI Interrupt Flag
Table 17-2. CPOL Functionality
CPOL Leading Edge Trailing Edge
0 Rising Falling
1 Falling Rising
Table 17-3. CPHA Functionality
CPHA Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample
Table 17-4. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1 SPR0 SCK Frequency
000
fosc/4
001fosc/16
010
fosc/64
011
fosc/128
100
fosc/2
101
fosc/8
110
fosc/32
111
fosc/64
Bit 76543210
SPIF WCOL – – – – – SPI2X SPSR
Read/WriteRRRRRRRR/W
Initial Value00000000
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When a serial transfer is complete, the SPIF Flag is set. An interrupt is generate d if SPIE in
SPCR is set and global interru pts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and t he SPI F b it) ar e cleare d b y fi r st r eading t h e SPI Stat u s Regi ste r wit h WCOL set ,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega32U6/AT90USB64/128 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 17-4). This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4
or lower.
The SPI interface on the ATmega32U6/AT90USB64/128 is also used for program memory and
EEPROM downloading or uploading. See page 380 for serial programming and verification.
17.1.5 SPI Data Register – SPDR
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shif t Reg i ste r Rece ive bu ffer to be read.
17.2 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure
17-3 and Figure 17-4. Data bits are shifted out and latch ed in on op posite ed ges of the SCK sig-
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 17-2 and Table 17-3, as don e be low :
Bit 76543210
MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial ValueXXXXXXXXUndefined
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Figure 17-3. SPI Transfer Format with CPHA = 0
Figure 17-4. SPI Transfer Format with CPHA = 1
Table 17-5. CPOL Functionality
Leading Edge Traili ng eDge SPI Mode
CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0
CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1
CPOL=1, CPHA=0 Sample (F alling) Setup (Rising) 2
CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3
Bit 1
Bit 6
LSB
MSB
SCK (CPOL = 0)
mode 0
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 1)
mode 2
SS
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
MSB first (DORD = 0)
LSB first (DORD = 1)
SCK (CPOL = 0)
mode 1
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 1)
mode 3
SS
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
MSB first (DORD = 0)
LSB first (DORD = 1)
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18. USART The Universal Synchronous and Asynchronou s serial Receiver and Transmitter (USART) is a
highly flexible serial co mmunication device. The main feat ures are:
•Full Duplex Operation (Independent Serial Receive and Transmit Registers)
•Asynchronous or Synchronous Op eration
•Master or Slave Clocked Synchronous Operation
•High Resolution Baud Rate Generator
•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
•Odd or Even Parity Generation and Parity Check Supported by Hardware
•Data OverRun Detection
•Framing Error Detection
•Noise Filterin g Includes False Start Bit Detection and Dig ital Low Pass Filter
•Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
•Multi-processor Communication Mode
•Double Speed Asynchronous Communication Mode
.
18.1 Overview A simplified block diagram of th e USART Tran smitter is shown in Figur e 18-1 on page 18 2. CPU
accessible I/O Registers and I/O pins are shown in bold.
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Figure 18-1. USART Block Diagram(1)
Note: 1. See Figure 1-1 on page 3, Table 10-12 on page 84 and for USART pin placement.
The dashed boxe s in the blo ck diagr am se parat e th e thr ee main pa rts of the USART ( list ed fro m
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is
only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a
serial Shift Register, Parity Generator and Control logic for handling different serial frame for-
mats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception . In addition to the recovery
units, the Receiver includes a Parity Che cker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
18.2 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchron ous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
PARITY
GENERATOR
UBRR[H:L]
UDR (Transmit)
UCSRA UCSRB UCSRC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxD
TxD
PIN
CONTROL
UDR (Receive)
PIN
CONTROL
XCK
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATA BUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver
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for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 18-2 shows a block diagram of the clock generation logic.
Figure 18-2. Clock Generation Logic, Block Diagram
Signal description:
txclk Transmitter clock (Internal Signal).
rxclk Receiver base clock (Internal Signal).
xcki Input from XCK pin (internal Signal). Used for synchronous slave
operation.
xcko Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
fOSC XTAL pin frequency (System Clock).
18.2.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The descrip tion in this section refers to Figure 18-2.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or bau d rate generator. The down-counter, running at system clock
(fosc), is loaded with the UBRRn value each time the counter has counted down to zero or when
the UBRRLn Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= fosc/(UBRRn+1)). The Transmitter divides th e
baud rate g enerato r clock outpu t by 2, 8 or 16 d epending on mode. Th e baud r ate genera tor ou t-
put is used directly by the Re ceiver’s clo c k and data recovery units. Howe ver, th e re co very unit s
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
Prescaling
Down-Counter /2
UBRR
/4 /2
fosc
UBRR+1
Sync
Register
OSC
XCK
Pin
txclk
U2X
UMSEL
DDR_XCK
0
1
0
1
xcki
xcko
DDR_XCK rxclk
0
1
1
0
Edge
Detector
UCPOL
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Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculat-
ing the UBRRn value for each mode of operation using an internally gen erated clock source.
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
fOSC System Oscillator clock frequency
UBRRn Contents of the UBRRHn and UBRRLn Regi sters, (0-4095)
Some examples of UBRRn values for some system clock frequencies are found in Table 18-9 on
page 203.
18.2.2 Double Speed Operation (U2Xn)
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will red uce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchro nous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
Table 18-1. Equations for Calculating Baud Rate Register Setting
Operating Mode Equation for Calculating
Baud Rate(1) Equatio n for Calculating
UBRR Value
Asynchronous Nor mal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn =
1)
Synchronous Master
mode
BAUD fOSC
16 UBRRn1+()
------------------------------------------=
UBRRnfOSC
16BAUD
------------------------1–=
BAUD fOSC
8UBRRn1+()
---------------------------------------=
UBRRnfOSC
8BAUD
-------------------- 1–=
BAUD fOSC
2UBRRn1+()
---------------------------------------=
UBRRnfOSC
2BAUD
-------------------- 1–=
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18.2.3 External ClockExternal clocking is used by the synchronous sl ave modes of operation. The description in this
section refers to Figure 18-2 for details.
External clock input from the XCKn pin is sampled by a synchronizat ion re giste r to m inimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector b efore it can be used by the Transmitter and Rece iver. This process intro-
duces a two CPU clo ck peri od delay and t here fore the maximu m ext ernal XCKn clock fre quency
is limited by the following equation:
Note that fosc depends on the stability of the system clock source. It is therefore recommended to
add some margin to avoid possible loss of data due to frequency variations.
18.2.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 18-3. Synchronous Mode XCKn Timing.
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is
used for data change. As Figure 18-3 shows, when UCPOLn is zero the data will be changed at
rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed
at falling XCKn edge and sampled at rising XCKn edge.
18.3 Frame Formats
A serial frame is define d to be o ne char acter of da ta bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as va lid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, ev en or odd parity bit
• 1 or 2 stop bits
fXCK fOSC
4
-----------
<
RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample
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A frame starts w ith the s tart bit f ollowe d by t he leas t signif icant da ta b it. Then the next da ta bit s,
up to a total of nin e, are succeed ing, endin g with t he most sig nificant bit. If enab led, the pa rity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 18-4 illustrates the possible combinations of the frame formats. Bits inside brackets are
optional.
Figure 18-4. Frame Formats
St Start bit, always low.
(n) Data bits (0 to 8).
PParity bit. Can be odd or even.
Sp Stop bit, always high.
IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line
must be high.
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitt er use t he same se tting. Not e that changing
the setting of any of these bits will corrupt all ongoing communication for both the Receiver and
Transmitter.
The USART Character SiZe (UCSZn 2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between
one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores
the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the
first stop bit is zero.
18.3.1 Parity Bit Calculation
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows::
Peven Parity bit using even parity
Podd Parity bit using odd parity
dnData bit n of the character
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)
FRAME
Peven dn1–…d3d2d1d00
Podd
⊕⊕⊕⊕⊕⊕
dn1–…d3d2d1d01⊕⊕⊕⊕⊕⊕
=
=
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18.4 USART Initialization
The USART has to be initialized bef ore any communication can take place. The init ialization pro-
cess normally consists of setting the baud rate, setting frame format and enabling the
Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the
Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the
initialization.
Before doing a re -in itia liza tio n with cha ng ed bau d rat e o r fr ame form at , be sure th at ther e are no
ongoing transmissions dur ing the per iod the reg ist ers are ch ang ed. Th e TXCn Flag can be used
to check that the Transmitter has completed all transfers, and the RXC Flag can be used to
check that there are no unread data in the receive buffer. Note that the TXCn Flag must be
cleared befo re eac h tra n s m issio n (b ef or e UDRn is written) if it is used for this purpose.
The following simple USART initializatio n code examples show one assembly and one C func-
tion that are equal in functionality. The examples assume asynchronous operation using polling
(no interru pts enable d) and a fixed fr ame format . The bau d rate is given as a funct ion paramet er.
For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16
Registers.
Note: 1. See “About Code Examples” on page 9.
More advanced initialization ro ut ines can be mad e th at include fr ame forma t a s para met ers , dis-
able interrupts and so on. However, many applications use a fixed setting of the baud and
control registers, and for these types of applications the initialization code can be placed directly
in the main routine, or be combined with initialization code for other I/O modules.
Assembly Code Example(1)
USART_Init:
; Set baud rate
out UBRRHn, r17
out UBRRLn, r16
; Enable receiver and transmitter
ldi r16, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r16
; Set frame format: 8data, 2stop bit
ldi r16, (1<<USBSn)|(3<<UCSZn0)
out UCSRnC,r16
ret
C Code Example(1)
void USART_Init( unsigned int baud )
{
/* Set baud rate */
UBRRHn = (unsigned char)(baud>>8);
UBRRLn = (unsigned char)baud;
/* Enable receiver and transmitter */
UCSRnB = (1<<RXENn)|(1<<TXENn);
/* Set frame format: 8data, 2stop bit */
UCSRnC = (1<<USBSn)|(3<<UCSZn0);
}
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18.5 Data Transmission – The USART Transmitter
The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UC SRnB
Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid-
den by the USART and given the function as the Transmitter’s serial output. The baud rate,
mode of operation and fram e format must be set up once befor e doing any tran smissions. I f syn-
chronous operation is used, the clock on the XCKn pin will be overridden and used as
transmission clock.
18.5.1 Sending Frames with 5 to 8 Data Bit
A data transmission is in itiated by loa ding the transmit buffer with t he data to be t ransmitted. The
CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the
transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new
frame. The Shif t Regi ster is loaded wit h new dat a if it is in id le stat e ( no ongoin g tr ansmission ) or
immediately after the last sto p bit of the pr evious frame is transmitte d. When th e Shift Register is
loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,
U2Xn bit or by XCKn depending on mode of operation.
The following code examples show a simple USART transmit function based on polling of the
Data Register Empty (UDREn) Flag. When using frames with less than eight bits, the most sig-
nificant bits written to the UDRn are ignored. The USART has to be initialized before the function
can be used. For the assembly code, the data to be sen t is assumed to be store d in Register
R16
Note: 1. See “About Code Examples” on page 9.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,
before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized,
the interrupt routine writes the data into the buffer.
18.5.2 Sending Frames with 9 Data Bit
If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in
UCSRnB before the low byte of the character is written to UDRn. The following code examples
Assembly Code Example(1)
USART_Transmit:
; Wait for empty transmit buffer
sbis UCSRnA,UDREn
rjmp USART_Transmit
; Put data (r16) into buffer, sends the data
out UDRn,r16
ret
C Code Example(1)
void USART_Transmit( unsigned char data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) )
;
/* Put data into buffer, sends the data */
UDRn = data;
}
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show a transmit function that handles 9-bit characters. For the assembly code, the data to be
sent is assumed to be stored in registers R17:R16.
Notes: 1. These transmit functions are written to be general functions. They can be optimized if the con-
tents of th e UCSRn B is static . F or exam ple , only the TXB8 bit of the UCSRnB Register is used
after initialization.
2. See “About Code Examples” on page 9.
The ninth bit can be used for indicating an address frame when using multi processor communi-
cation mode or for ot he r pr ot oc ol ha nd lin g as fo r ex a m ple syn chr o niza tio n.
18.5.3 Transmitter Flags and Interrupts
The USART Transmitter has two flags that indicate its state: USART Data Register Empty
(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.
The Data Register Empty (U DREn) Flag indicates whether the tran smit buffer is ready to re ceive
new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer
contains data to be transmitted that has not yet been moved into the Shift Re gister. For compat-
ibility with future devices, always write this bit to zero when writing the UCSRnA Register.
When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the
USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that
global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data
transmission is used, the Data Register Empty interrupt routine must either write new data to
Assembly Code Example(1)(2)
USART_Transmit:
; Wait for empty transmit buffer
sbis UCSRnA,UDREn
rjmp USART_Transmit
; Copy 9th bit from r17 to TXB8
cbi UCSRnB,TXB8
sbrc r17,0
sbi UCSRnB,TXB8
; Put LSB data (r16) into buffer, sends the data
out UDRn,r16
ret
C Code Example(1)(2)
void USART_Transmit( unsigned int data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn))) )
;
/* Copy 9th bit to TXB8 */
UCSRnB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRnB |= (1<<TXB8);
/* Put data into buffer, sends the data */
UDRn = data;
}
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UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new
interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift
Register has been shifted out and there are no new data currently present in the transmit buffer.
The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it
can be cleared by writin g a one to its b it locatio n. The TXCn Flag is useful in half-duplex commu-
nication interfaces (like the RS-485 standard), where a transmitting application must enter
receive mode and free the communication bus immediately after completing the tra nsmission.
When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART
Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that
global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-
dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt
is executed.
18.5.4 Parity Generator
The Parity Gene rator calculat es the par ity bit f or the serial frame data. When parity bit is enabled
(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the
first stop bit of the frame that is sent.
18.5.5 Disabling the Transmitter
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-
ing and pending transmissions are completed, i.e., when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter
will no longer override the TxDn pin.
18.6 Data Reception – The USART Receiver
The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the
UCSRnB Register to one. When th e Receiver is enabled, the normal pin operation of the RxDn
pin is overridden by the USART and given the function as the Rec eiver’s ser ial input. The bau d
rate, mode of operation and frame format must be set up once before an y serial reception can
be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer
clock.
18.6.1 Receiving Frames with 5 to 8 Data Bits
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start
bit will be sampled at the baud rate or XCKn clock, and shifted into the Re ceive Shift Register
until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.
When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift
Register, the contents of the Shift Register will be moved into the receive buffer. The receive
buffer can then be read by reading the UDRn I/O location.
The following code example shows a simple USART receive function based on polling of the
Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant
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bits of the data read from the UDRn will be masked to zero. The USART has to be initi alized
before the function can be used.
Note: 1. See “About Code Examples” on page 9.
The function simply waits for data to be present in the receive buffer by checking the RXCn Flag,
before readin g the buffer and returning the value.
18.6.2 Receiving Frames with 9 Data Bits
If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in
UCSRnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and
UPEn Status Flags as well. Read status from UCSRnA, then data from UDRn. Reading the
UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n,
FEn, DORn and UPEn bits, which all are stored in the FIFO, will change.
The following code example shows a simple USART receive function that handles both nine bit
characters and the status bits.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
sbis UCSRnA, RXCn
rjmp USART_Receive
; Get and return received data from buffer
in r16, UDRn
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get and return received data from buffer */
return UDRn;
}
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Note: 1. See “About Code Examples” on page 9.
The rece ive function example r eads all th e I/O Registers into the Register File before any com-
putation is done. This gives an optimal receive buffer utilization since the buffer location read will
be free to accept new data as early as possible.
18.6.3 Receive Compete Flag and Interrupt
The USART Receiver has one flag that indicates the Receiver state.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
sbis UCSRnA, RXCn
rjmp USART_Receive
; Get status and 9th bit, then data from buffer
in r18, UCSRnA
in r17, UCSRnB
in r16, UDRn
; If error, return -1
andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn)
breq USART_ReceiveNoError
ldi r17, HIGH(-1)
ldi r16, LOW(-1)
USART_ReceiveNoError:
; Filter the 9th bit, then return
lsr r17
andi r17, 0x01
ret
C Code Example(1)
unsigned int USART_Receive( void )
{
unsigned char status, resh, resl;
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get status and 9th bit, then data */
/* from buffer */
status = UCSRnA;
resh = UCSRnB;
resl = UDRn;
/* If error, return -1 */
if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) )
return -1;
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
}
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The Receive Complet e (RXCn) Flag ind icates if t here are unre ad data presen t in the receive buf-
fer. This flag is one when unread data exist in the receive buffer, and zero when the receive
buffer is empty (i.e., doe s not co ntain any unr ead data) . If the Receive r is disabled (RXENn = 0),
the receive buffer will be flushed and consequently the RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receiv e
Complete interrupt will be executed as long as the RXCn Flag is se t (provided that global inter-
rupts are enabled). When interrupt-driven data reception is used, the receive complete routine
must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new inter-
rupt will occur once the interrupt routine terminates.
18.6.4 Receive r Error Flags
The USART Receiver has three Error Flag s: Frame Er ror (FEn), Data OverRun (DORn) and
Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is
that they are located in the receive buffer together with the frame for which they indicate the
error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the
receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location.
Another equality for the Error Flags is that they can not be alte red by software doing a write to
the flag location. However, all flags must be set to zero when the UCSRnA is written for upward
compatibility of future USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn ) Flag indicates the state of the first stop bit of the next read able frame
stored in th e rec eive b uffer. The FEn Flag is zero when t he st op b it was c orre ctly re ad ( as on e),
and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for
detecting out-of -sync conditions, detecting br eak conditions and protocol h andling. The FEn
Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,
except for the first, stop bits. For com patibility with future devices, always set this bit to zero
when writing to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver bu ffer full condition. A
Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait-
ing in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there
was one or more serial frame lost between the frame last read from UDRn, and the next frame
read from UDRn. For compatibility with future devices, alway s write this bit to zero when writing
to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates tha t the next frame in the receive buffer had a Parity
Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For
compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more
details see “Parity Bit Calculation” on pa ge 186 and “Parity Checker” on page 193.
18.6.5 Parity CheckerThe Parity Checker is acti ve when the high USART Parity mode (UPMn1) bit is set. Typ e of Par-
ity Check to be performed (odd or even) is selected by the UPMn0 bit. When en abled, the Parity
Checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit f rom the serial fr ame. The resu lt of the ch eck is stored in the rece ive buffe r together
with the rece ive d da ta an d sto p bit s. T h e Par i ty E rr or (UPEn) Flag ca n th en b e rea d by software
to check if the frame had a Parity Error.
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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is
valid until the receive buffer (UDRn) is read.
18.6.6 Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immed iate. Data from ongoing
receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will
no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost
18.6.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be
emptied of its contents. Unrea d data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag
is cleared. The following code example shows how to flush the receive buffer.
Note: 1. See “About Code Examples” on page 9.
18.7 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asyn ch ronou s se rial fram es at t he RxDn pin . T he data re co very lo gic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
18.7.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 18-5
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
izontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples
denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).
Assembly Code Example(1)
USART_Flush:
sbis UCSRnA, RXCn
ret
in r16, UDRn
rjmp USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;
}
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Figure 18-5. Start Bit Sampling
When the cl ock recove ry logic detects a high ( idle) to low (start) transition on the Rx Dn line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sampl e as shown in
the figure. T he clock re covery logic then uses sam ples 8 , 9, and 1 0 for Nor mal mod e, and sam -
ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
figure), t o decide if a valid start bit is re ceive d. If two or m ore o f these thre e samples have log ical
high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts
looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-
ery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
18.7.2 Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data
recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight
states for each bit in Double Spee d mode. Figure 18-6 shows the sampling of the data bits and
the parity bit. Each of the samples is given a number that is equal to the state of the recovery
unit.
Figure 18-6. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples ar e emphasized
on the figure by ha ving th e samp le num ber inside boxes. The majority vo t ing pr ocess is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the Receiver only uses the first stop bit of a frame.
Figure 18-7 sh ows th e sampling of the st op bit an d the ea rlie st po ssib le begin ning of the st art bit
of the next frame.
12345678 9 10 11 12 13 14 15 16 12
STARTIDLE
00
BIT 0
3
1234 5 678120
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
12345678 9 10 11 12 13 14 15 16 1
BIT n
1234 5 6781
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
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Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done fo r the other bits in the fr ame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low tr ansit ion ind i cating the start bit of a n ew fra me can com e r igh t aft er the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in Figure 18-7. For Double Speed mode the first low level must be delayed to
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
18.7.3 Asynchronous Operational Range
The operational ra nge of the Receiver is dependent on the mism atch between the received bit
rate and the inter nally gene rated baud ra te. If the Tra nsmitter is sending f rames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 18-2) base frequency, the Receiver will not be able to synchronize the frames to the start
bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
DSum of character size and parity size (D = 5 to 10 bit)
SSamples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
SFFirst sample number used for majority voting. SF = 8 for normal speed and SF = 4
for Double Speed mode.
SMMiddle sample number used for majority voting. SM = 9 for normal speed and
SM= 5 for Double Speed mode.
Rslow is the ratio of the slowest in coming data rat e that can be accepted in relat ion to the
receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be
accepted in relation to the receiver baud rate.
Table 18-2 and Ta ble 18-3 list the maximum receiver baud rate error that can be tolerated. Note
that Normal Speed mode has higher tolerati on of baud rate variations.
12345678 9 10 0/1 0/1 0/1
STOP 1
1234 5 6 0/1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
(A) (B) (C)
Table 1.
Rslow D1+()S
S1–DS⋅SF
++
-------------------------------------------=
Rfast D2+()S
D1+()SS
M
+
-----------------------------------=
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The recommendations of the maximum receiver baud rate error was made under the assump-
tion that the Receiver and Transmitter equally divides the maximum total err or.
There are two possible sources for the receivers baud rate error. The Receiver’s system clock
(XTAL) will always have some minor instability over the supply voltage range and the tempera-
ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a
resonator th e syste m clock ma y diff er more t han 2% dep en ding o f th e reson ator s t oler ance . The
second source for the error is more controllable. The baud rate generator can not always do an
exact division of the system frequency to get the baud rate wanted. In this case an UBRR value
that gives an acceptable low error can be used if possible.
18.8 Multi-processor Communication Mode
Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering
function of incoming frames received b y the USART Receiver. Frames that do not contain
address information will be ignored and not put into the receive buffer. This effectively reduces
the number of incoming frames that has to be handled by the CPU, in a system with multiple
MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn
setting, but has to be used differently when it is a part of a system utilizing the Multi-processor
Communication mode.
If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-
cates if the frame contains data or address information. If the Receiver is set up for frames with
Table 18-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode
(U2Xn = 0)
D
# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max
Receiver Error (%)
5 93.20 106.67 +6.67/-6.8 ± 3.0
6 94.12 105.79 +5.79/-5.88 ± 2.5
7 94.81 105.11 +5.11/-5.19 ± 2.0
8 95.36 104.58 +4.58/-4.54 ± 2.0
9 95.81 104.14 +4.14/-4.19 ± 1.5
10 96.1 7 103.78 +3.78/-3.83 ± 1.5
Table 18-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode
(U2Xn = 1)
D
# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max
Receiver Error (%)
5 94.12 1 05.66 +5.66/-5.88 ± 2.5
6 94.92 1 04.92 +4.92/-5.08 ± 2.0
7 95.52 1 04,35 +4.35/-4.48 ± 1.5
8 96.00 1 03.90 +3.90/-4.00 ± 1.5
9 96.39 1 03.53 +3.53/-3.61 ± 1.5
10 96.7 0 103.23 +3.23/-3.30 ± 1.0
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nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When
the frame type bit (the first sto p or t he ninth b it) is o ne, th e f rame con tai ns a n add ress. When t he
frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several slave MCUs to receive data from a
master MCU. This is done by first decoding an address frame to find out which MCU has been
addressed. If a particular slave MCU has been addressed, it will receive the following data
frames as normal, while the other slave MCUs will ignore the received frames until another
address frame is received.
18.8.1 Using MPCMn For an MCU to act as a ma ster MCU, it can use a 9-bit char acter frame format (U CSZn = 7). The
ninth bit (TXB8n) must be set when an a ddress frame (TXB8n = 1) or cle ared when a data frame
(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character
frame format.
The following proce dure should be used to exchang e data in Multi-processor Communicatio n
mode:
1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is
set).
2. The Master MCU sends an address frame, and all slaves receive and read this frame.
In the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.
3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If
so , it clears the MPCMn bit in UCSRnA, otherwise it w aits f or the ne xt address b yte and
keeps the MPCMn setting.
4. The addressed MCU will receiv e all data fr am es until a new address frame is received.
The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.
5. When the last da ta f rame is received by t he ad dre sse d MCU, the addressed MCU sets
the MPCMn bit and waits for a new address frame from master. The process then
repeats from 2.
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the
Receiver must change between using n and n+1 character frame formats. This makes full-
duplex operation difficult since the Transmitter and Receiver uses the same character size set-
ting. If 5- to 8-bit character frames ar e used, the Transmitter must be set to use two sto p bit
(USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The
MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be
cleared when using SBI or CBI instructions.
18.9 USART Register Description
18.9.1 USART I/O Data Register n– UDRn
The USART Transmit Data Buffer Regist er and USART Receive Data Buffer Regist ers share t he
same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-
Bit 76543210
RXB[7:0] UDRn (Read)
TXB[7:0] UDRn (Write)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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ister (TXB) will be the destination for data written to the UDRn Register location. Reading the
UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-
ter. When data is written to the transmit buffer, and the Transmitter is en abled, the Transmitter
will load the data into the Transmit Shift Register when the Shift Register is empty. Then the
data will be serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO w ill change its state whenever the
receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-
Write instructions (SBI and CBI) on this location. Be careful when using bit test in structions
(SBIC and SBIS), since these also will change the state of the FIFO.
18.9.2 USART Control and Status Register A – UCSRnA
• Bit 7 – RXCn: USART Receive Complete
This flag bit is set when th ere are unr ead data in the rece ive buffer a nd cleared whe n the rece ive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
used to generate a Receive Complete int errupt (see description of the RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buff er (UDRn). The TXCn Fl ag bit is auto-
matically cleared when a transmit comple te interrup t is execut ed, or it can be clea red by writin g
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCI En bit).
• Bit 5 – UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDR En
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIEn bit).
UDREn is set after a reset to indicate that the Transmitter is ready.
• Bit 4 – FEn: Frame Error
This bit is set if the next character in the re ceive buffer had a Frame Error when received. I.e.,
when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the
receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.
Always set this bit to zero when writing to UCSRnA.
• Bit 3 – DORn: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive
buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
Bit 76543210
RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn UCSRnA
Read/WriteRR/WRRRRR/WR/W
Initial Value00100000
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new start bit is detected. This bit is valid until the receive buffer (UDRn) is read . Always set this
bit to zero when writing to UCSRnA.
• Bit 2 – UPEn: USART Parity Error
This bit is set if the next character in the receive buffer h ad a Parity Error when received and the
Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer
(UDRn) is read. Always set this bit to zero when writing to UCSRnA.
• Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous ope ration. Write this bit to zero when using syn-
chronous operatio n.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-
bling the transfer r ate for asynchronous communication.
• Bit 0 – MPCMn: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mod e. When the MPCMn bit is written to
one, all the incoming fra mes received by the USART Receiver that do not contain address infor-
mation will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed
information see “Multi-processor Communication Mode” on page 197.
18.9.3 USART Control and Status Register n B – UCSRnB
• Bit 7 – RXCIEn: RX Complete Interrupt Enable n
Writing this bit t o one e nables in terrup t on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable n
Writing this bit to one enables in terrupt on the TXCn Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
• Bit 5 – UDRIEn: USART Data Register Empty Inte rrupt Enable n
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated on ly if the UDRIEn bit is written to one, the Global Inter rupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set .
• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to
Bit 7 6 5 4 3 2 1 0
RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n UCSRnB
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 0 0
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zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the rece ived char acter when op erating wit h serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
18.9.4 USART Control and Status Register n C – UCSRnC
• Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in Table 18-4..
Note: 1. See “USART in SPI Mode” on page 206 for full description of the Master SPI Mode (MSPIM)
operation
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Bit 7 6 5 4 3 2 1 0
UMSELn1 UMSELn0 UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn UCSRnC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
Table 18-4. UMSELn Bits Settings
UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 (Reserved)
1 1 Master SPI (MSPIM)(1)
Table 18-5. UPMn Bits Settings
UPMn1 UPMn0 Parity Mode
0 0 Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
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• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bi t sets the relat ionship be tween dat a output change an d dat a input samp le,
and the synchronous clock (XCKn).
18.9.5 USART Baud Rate Registers – UBRRLn and UBRRHn
• Bit 15:12 – Reserved Bits
Table 18-6. USBS Bit Settings
USBSn Stop Bit(s)
01-bit
12-bit
Table 18-7. UCSZn Bits Settings
UCSZn2 UCSZn1 UCSZn0 Character Size
0005-bit
0016-bit
0107-bit
0118-bit
100Reserved
101Reserved
110Reserved
1119-bit
Table 18-8. UCPOLn Bit Settings
UCPOLn Transmitted Data Changed (Output
of TxDn Pin) Received Data Sampled (Input on
RxDn Pin)
0 Rising XCKn Edge Falling XCKn Edge
1 Falling XCKn Edge Rising XCKn Edge
Bit 1514131211109 8
––––UBRR[11:8] UBRRHn
UBRR[7:0] UBRRLn
76543210
Read/WriteRRRRR/WR/WR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000
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These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four
most significant bit s, a nd the UBRRL co nt ain s the eight least significant bits of the USART baud
rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is
changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
18.10 Examples of Baud Rate Setting
For standard crystal and resona tor frequencies, the most commonly us ed baud rates for asyn-
chronous operation can be generated by using the UBRR settings in Table 18-9 to Table 18-12.
UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate,
are bold in the table. Higher error ratin gs are acceptable, but the Receiver will have less noise
resistance when the error r ating s are hig h, especia lly for la rge serial f rame s (see “Asynchronous
Operational Range” on page 196). The error values are calculated using the following equation:
Error[%] BaudRateClosest Match
BaudRate
-------------------------------------------------------- 1–
⎝⎠
⎛⎞
100%•=
Table 18-9. Examples of UBRR n Settings for Commonly Used Oscillator Frequencies
Baud
Rate
(bps)
fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz
U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1
UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error
2400 250.2%510.2%470.0%950.0%510.2%1030.2%
4800 120.2%250.2%230.0%470.0%250.2%510.2%
9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%
14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1%
19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2%
28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5%
38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0%
57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5%
76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5%
115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5%
230.4k––––––00.0%––––
250k––––––––––00.0%
Max. (1) 62.5 kbps 125 kbps 115.2 kbps 2 30.4 kbps 125 kbps 25 0 kbps
1. UBRR = 0, Error = 0.0%
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Table 18-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz
U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1
UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error
2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%
4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%
9600 230.0%470.0%250.2%510.2%470.0%950.0%
14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%
19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0%
28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%
38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%
57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0%
76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0%
115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0%
230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0%
250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8%
0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8%
1M ––––––––––0-7.8%
Max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 Mbps 460.8 kbps 921.6 kbps
1. UBRR = 0, Error = 0.0%
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Table 18-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
fosc = 8.0000 MHz fosc = 11.0592 MHz fosc = 14.7456 MHz
U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1
UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error
2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%
4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%
9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%
14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%
19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0%
28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%
38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0%
57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%
76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0%
115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0%
230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0%
250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%
0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8%
1M – – 0 0.0% – – – – 0 -7.8% 1 -7.8%
Max. (1) 0.5 Mbps 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kbps 1.8432 Mbps
1. UBRR = 0, Error = 0.0%
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19. USART in SPI Mode
The Universal Synchronous and Asynchronous serial Receiver an d Transmitter (U SART) can be
set to a master SPI comp liant mode of o peration. Th e Master SPI Mo de (MSPIM) has the f ollow-
ing features:
•Full Duplex, Three-wire Synchronous Data Transfer
•Master Operation
•Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
•LSB First or MSB First Data Transfer (Configurable Data Order)
•Queued Operation (Double Buffered)
•High Resolution Baud Rate Generator
•High Speed Operation (fXCKmax = fCK/2)
•Flexible Interrupt Generation
19.1 Overview Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-
tion the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate gen-
erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX
Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz
U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1
UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error
2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%
4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%
9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%
14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%
19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%
28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%
38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2%
57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%
76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4%
115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4%
230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4%
250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0%
0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0%
1M 0 0.0% 1 0.0% – – – – – – – –
Max. (1) 1 Mbps 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps
1. UBRR = 0, Error = 0.0%
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control logic is disabled. The USART RX and TX control logic is replaced by a common SPI
transfer control logic. However, the pin control logic and interrupt generation logic is identical in
both modes of operation.
The I/O register locati ons ar e t he sa me in b oth mo des. However , so me of the f u nctionalit y of t he
control registers changes when using MSPIM.
19.2 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-
ported. The Da ta Directi on Register for the XCKn pin (D DR_XCKn) must the refo re be set t o one
(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should
be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).
The internal cloc k genera tion use d in MSPIM mode is identical t o the USART synchr onous mas-
ter mode. The baud rate or UBRRn setting can therefore be calculated using the same
equations, see Table 19-1:
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
fOSC System Oscillator clock frequency
UBRRn Contents of the UBRRnH and UBRRnL Regi sters, (0-4095)
19.3 SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polar ity with respect to seria l data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in Figure 19-1. Data bits are shifted out and latched in on opposite edges of the XCKn
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
Table 19-1. Equations for Calculating Baud Rate Register Setting
Operating Mode Equation for Calculating Baud
Rate(1) Equation for Calculating
UBRRn Value
Synchronous Master
mode
BAUD fOSC
2UBRRn1+()
---------------------------------------=
UBRRnfOSC
2BAUD
-------------------- 1–=
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ality is summarized in Table 19-2. Note that changing the setting of any of these bits will corrupt
all ongoing communication for both the Receiver and Transmitter.
Figure 19-1. UCPHAn and UCPOLn data transfer timing diagrams.
19.4 Frame Formats
A serial frame f or the MSPIM is def ined to be one character of 8 da ta bits. The USART in MSPIM
mode has two valid frame formats:
• 8-bit data with MSB first
• 8-bit data with LSB first
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of
eight, are succeeding, ending with the most or least significant bit accordingly. When a complete
frame is transmitted, a new frame can directly follow it, or the communication line can be set to
an idle (high) state.
The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The
Receiver and Transmitter use the same setting. Note that changing the setting of any of these
bits will corrupt all ongoing communication for both the Receiver and Transmitter.
16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit com-
plete interrupt will then signal that the 16-bit value has been shifted out.
19.4.1 USART MSPIM Initializ at ion
The USART in MSPIM mode has to be initialized before any communication can take place. The
initialization process nor mally consists of sett ing the baud r ate, setting ma ster mode of o peration
(by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the
Receiver. Only the transmitter can operate independ ently. For interrupt driven USART opera-
Table 19-2. UCPOLn and UCPHAn Functionality-
UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge
0 0 0 Sample (Rising) Setup (Falling)
0 1 1 Setup (Rising) Sample (Falling)
1 0 2 Sample (Falling) Setup (Rising)
1 1 3 Setup (Falling) Sample (Rising )
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
UCPOL=0 UCPOL=1
UCPHA=0 UCPHA=1
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tion, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when
doing the initialization.
Note: To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be
zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the
UBRRn must then be written to the desired value after the transmitter is enabled, but before the
first transmission is started. Setting UBRRn to zero before enab ling the transmitter is not neces-
sary if the initialization is done immediately after a reset since UBRRn is reset to zero.
Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that
there is no ongoing transmissions during the period the registers are changed. The TXCn Flag
can be used to check that the Transmitter has completed all transfers, and the RXCn Flag can
be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag
must be cleared before each transmission (before UDRn is written) if it is used for this purpose.
The following simple USART initializatio n code examples show one assembly and one C func-
tion that are equal in functionality. The exam ples assume polling (no interrupts enabled). Th e
baud rate is given as a function parameter. For the assembly code, the baud rate parameter is
assumed to be stored in the r17:r16 registers.
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Note: 1. See “About Code Examples” on page 9.
19.5 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in
the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation
of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling
the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given
the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer
clock.
Assembly Code Example(1)
USART_Init:
clr r18
out UBRRnH,r18
out UBRRnL,r18
; Setting the XCKn port pin as output, enables master mode.
sbi XCKn_DDR, XCKn
; Set MSPI mode of operation and SPI data mode 0.
ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)
out UCSRnC,r18
; Enable receiver and transmitter.
ldi r18, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r18
; Set baud rate.
; IMPORTANT: The Baud Rate must be set after the transmitter is
enabled!
out UBRRnH, r17
out UBRRnL, r18
ret
C Code Example(1)
void USART_Init( unsigned int baud )
{
UBRRn = 0;
/* Setting the XCKn port pin as output, enables master mode. */
XCKn_DDR |= (1<<XCKn);
/* Set MSPI mode of operation and SPI data mode 0. */
UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);
/* Enable receiver and transmitter. */
UCSRnB = (1<<RXENn)|(1<<TXENn);
/* Set baud rate. */
/* IMPORTANT: The Baud Rate must be set after the transmitter is
enabled */
UBRRn = baud;
}
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After initialization the USART is ready for doing dat a tran sfers. A data transfer is init iated by wr it-
ing to the UDRn I/O location. This is the case for both sending and receiving data since the
transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buf-
fer to the shift register when the shift register is ready to send a new frame.
Note: To keep the input buff er in sync with the number of data bytes transmitted, the UDRn register must
be read once for each byte transmitted. Th e input buffer operation is identical to normal USART
mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the buf-
fer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the UDRn
is not read before all transfers are completed, then byte 3 to be received will be lost, and not byte
1.
The following code examples show a sim ple U SART in MSPIM mode t ransfe r fu ncti on based on
polling of the Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The
USART has to be initialize d befor e t he funct ion can be used. For the assembly code, the dat a to
be sent is assumed to be stored in Register R16 and the data received will be available in the
same register (R16) after the function returns.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,
before loadin g it with new da ta to be transm itted. The func tion then waits for data to be pr esent
in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the
value..
Assembly Code Example(1)
USART_MSPIM_Transfer:
; Wait for empty transmit buffer
sbis UCSRnA, UDREn
rjmp USART_MSPIM_Transfer
; Put data (r16) into buffer, sends the data
out UDRn,r16
; Wait for data to be received
USART_MSPIM_Wait_RXCn:
sbis UCSRnA, RXCn
rjmp USART_MSPIM_Wait_RXCn
; Get and return received data from buffer
in r16, UDRn
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) );
/* Put data into buffer, sends the data */
UDRn = data;
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) );
/* Get and return received data from buffer */
return UDRn;
}
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Note: 1. See “About Code Examples” on page 9.
19.5.1 Transmitter and Receiver Flags and Interrupts
The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode
are identi cal in fu nct ion to the no rma l USART op erat ion. Howe ver, t he r eceiver er ror st at us fla gs
(FE, DOR, and PE) are not in use and is always read as zero.
19.5.2 Disabling the Transmitter or Receiver
The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to
the normal USART oper ation.
19.6 USART MSPIM Register Description
The following section de scr ib es th e re gis te rs us ed for SPI op er a tion usin g the USART .
19.6.1 USART MSPIM I/O Data Regi st e r - UDRn
The function an d b it d escript io n of t he USART dat a r egi ster ( UDRn) in M SPI mode is iden tica l to
normal USART operation. See “USART I/O Data Register n– UDRn” on page 198.
19.6.2 USART MSPIM Control and Status Register n A - UCSRnA
• Bit 7 - RXCn: USART Receive Complete
This flag bit is set when th ere are unr ead data in the rece ive buffer a nd cleared whe n the rece ive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
used to generate a Receive Complete int errupt (see description of the RXCIEn bit).
• Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buff er (UDRn). The TXCn Fl ag bit is auto-
matically cleared when a transmit comple te interrup t is execut ed, or it can be clea red by writin g
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCI En bit).
• Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDR En
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
• Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnA is written.
Bit 765 4 3 2 1 0
RXCn TXCn UDREn - - - - - UCSRnA
Read/Write R/W R/W R/W R R R R R
Initial Value 0 0 0 0 0 1 1 0
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19.6.3 USART MSPIM Control and Status Register n B - UCSRnB
• Bit 7 - RXCIEn: RX Complete Interrupt Enable
Writing this bit t o one e nables in terrup t on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
• Bit 6 - TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables in terrupt on the TXCn Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set .
• Bit 4 - RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override
normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the
receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and TXENn=0)
has no meaning since it is the transmitter that controls the transfer clock and since only master
mode is supported.
• Bit 3 - TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to
zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnB is written.
19.6.4 USART MSPIM Control and Status Register n C - UCSRnC
• Bit 7:6 - UMSELn1:0: USART Mode Select
Bit 7 6 5 4 3 2 1 0
RXCIEn TXCIEn UDRIE RXENn TXENn - - - UCSRnB
Read/Write R/W R/W R/W R/W R/W R R R
Initial Value 0 0 0 0 0 1 1 0
Bit 76543210
UMSELn1 UMSELn0 - - - UDORDn UCPHAn UCPOLn UCSRnC
Read/Write R/W R/W R R R R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
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These bits select the mode of operation of the USART as shown in Table 19-3. See “USART
Control and Status Register n C – UCSRnC” on page 201 for full description of the normal
USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The
UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is
enabled.
• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing section page 4 for det ails.
19.6.5 USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See “USART Baud Rate Registers – UBRRLn and UBRRHn” on page 202.
19.7 AVR USART MSPIM vs. AVR SPI
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
• Master mode tim ing diagram.
• The UCPOLn bit functionality is identical to the SPI CPOL bit.
• The UCPHAn bit functionality is identical to the SPI CPHA bit.
• The UDORDn bit functionality is identical to the SPI DORD bit.
However, since the USART in MSPIM mode reuses the USART resources, the use of the
USART in MSPIM mode is some what d iff er ent co mpa re d to th e SPI . In ad dit ion t o d iff er ence s of
the control register bits, and that only master operation is supported by the USART in MSPIM
mode, the following features differ between the two modules:
• The USART in MSPIM mode includes (double) buf fering of the transmitter. The SPI has no
buffer.
Table 19-3. UMSELn Bits Settings
UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 (Reserved)
1 1 Master SPI (MSPIM)
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• The USART in MSPIM mode receiver includes an additional buffer level.
• The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.
• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is
achieved by setting UBRRn accordingly.
• Interrupt timing is not compatible.
• Pin control differs due to the master only operation of the USART in MSPIM mode.
A comparison of the USART in MSPIM mode and the SPI pins is shown in Tabl e 19-4 on page
215.
Table 19-4. Comparison of USART in MSPIM mode and SPI pins.
USAR T_MSPIM SPI Comment
TxDn MOSI Master Out only
RxDn MISO Master In only
XCKn SCK (Functionally identical)
(N/A) SS Not supported by USART in MSPIM
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20. 2-wire Serial Interface
20.1 Features •Simple Yet Powerful and Flexible Communicati on Interface, on ly two Bus Lines Needed
•Both Master and Slave Operation Supported
•Device can Operate as Transmitter or Receiver
•7-bit Address Space Allows up to 128 Different Slave Addresses
•Multi-master Arbitration Support
•Up to 400 kHz Data Transfer Speed
•Slew-rate Limited Output Drivers
•Noise Suppression Circuitry Rejects Spikes on Bus Lines
•Fully Programmable Slave Address with General Call Support
•Address Recognition Causes Wake-up When AVR is in Sleep Mode
20.2 2-wire Serial Interface Bus Definition
The 2-wire Se rial Interface ( TWI) is ideally suite d for typical micr ocontroller applications. The
TWI protoc ol allows t he syste ms desig ner to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connec ted to the bus have individual add resses, and mechanisms for reso lving bus
contention are inh erent in the TWI protocol.
Figure 20-1. TWI Bus Interconne ct ion
20.2.1 TWI Terminology
The following definit ions are frequently encount ered in this section.
Device 1 Device 2 Device 3 Device n
SDA
SCL
........ R1 R2
V
CC
Table 20-1. TWI Terminology
Term Description
Master The device that initiates and ter mi nates a transmission. The Master also
generates the SCL clock.
Slave The de vice addressed by a Master.
Transmitter The device placing data on the bus.
Receiver The device reading data from the bus.
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The Power Reduction TWI bit , PRTWI bit in “Power Reduction Register 0 - PRR0” on page 54
must be written to zero to enable the 2-wire Serial Interface.
20.2.2 Electrical Interconnection
As depicted in Figure 20- 1, both bus lines are connected to the positive supply voltage through
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TW I devices trim-state their outputs, allowing the pull-up resistors to pull th e
line high. Note t hat all AVR devices con nected to the T WI bus m ust be power ed in or der to a llow
any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in “SPI Timing Characteristics” on page 403. Two different se ts of
specifications are presente d there, one relevant for b us speeds below 100 kHz, and one valid for
bus speeds up to 400 kHz.
20.3 Data Transfer and Frame Format
20.3.1 Transferring Bits
Each data b it tran sfer red o n the T WI bus is acco mpa nied by a p ulse on th e cloc k line. The lev el
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating st art and stop conditions.
Figure 20-2. Data Validity
20.3.2 START and STOP Conditions
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
other master should try to seize control of the bus. A special case occurs when a new START
condition is issued between a START and STOP condition. This is referred to as a REPEATED
START condition, and is used when the Master wishes to initiate a new transfer without relin-
quishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both
START and REPEATED START for the r emainde r of t his datashe et, un less oth erwise note d. As
SDA
SCL
Data Stable Data Stable
Data Change
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depicted below, START an d STOP conditions are signalled by cha nging the level of the SDA
line when the SCL line is high.
Figure 20-3. START, REPEATED START and STOP conditions
20.3.3 Address Packet Format
All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 addre ss bits, one
READ/WRITE control bit and an acknowledge bit. If the READ/WRIT E bit is set, a read opera-
tion is to be performed, otherwise a write operation should be performed. When a Slave
recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL
(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas-
ter’s request, the SDA line should be left high in the ACK clock cycle. The Master can then
transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An
address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or
SLA+W, respectively.
The MSB of the add ress b yte is tra nsm it ted firs t. Slave addresses can freely be allocated by the
designer, but the address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK
cycle. A general call is used when a Master wishes to transmit the same message to several
slaves in the system. When the general call addre ss followed by a Write bit is transmitted on t he
bus, all slaves set up to ackn owledge the general call will pull the SDA line low in the ack cycle.
The following data packets will then be received by al l the slaves that acknowledged the general
call. Note that transmitting the general call address followed by a Read bit is meaningless, as
this would cause contention if several slaves started transmitting different data.
All addresses of the format 1111 xxx should be reserved for future purposes.
Figure 20-4. Address Packet Format
SDA
SCL
START STOPREPEATED START
STOP START
SDA
SCL
START
12 789
Addr MSB Addr LSB R/W ACK
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20.3.4 Data Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Rece iver leaves the SDA line high, a NACK is signalled. When th e Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 20-5. Data Packet Format
20.3.5 Combining Address and Data Packets into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An emp ty message, consisting of a START followed by a STOP cond i-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a conseq uence , t he Slave can red uce t he TWI dat a tr an sfe r sp ee d by prol ong ing the
SCL duty cycle.
Figure 20-6 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP con dition, depending on the software protocol imple-
mented by the application software.
Figure 20-6. Typical Data Transmission
12 789
Data MSB Data LSB ACK
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
SLA+R/W Data Byte
STOP, REPEATED
START or Next
Data Byte
12 789
Data Byte
Data MSB Data LSB ACK
SDA
SCL
START
12 789
Addr MSB Addr LSB R/W ACK
SLA+R/W STOP
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20.4 Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
• An algorithm must be impleme nted allowing only one of the masters to complete the
transmission. All other masters should cease transmission when they disco v er that they hav e
lost the selection process. This selection process is called arbitration. When a contending
master discovers that it has lost the arbitration process, it should immediately s witch to Sla ve
mode to check whether it is being addresse d by the winning master. The fact that multiple
masters have started transmission at the same time should not be detectable to the slave s,
i.e. the data being transferre d on the bus must not be corrupted.
• Different masters may use different SCL frequencies. A scheme must be devised to
synchronize the serial clocks from all masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.
The wired-ANDing of the bus lines is us ed to solve both these problems. The serial clocks from
all masters will be wired-ANDed, yielding a co mbined clock with a high period equal to the one
from the Master with the shortest high period. The low period of the combined clock is equal to
the low period of the Master with the longest low period. Note that all masters listen to the SCL
line, effectively starting to count their SCL high and low time-out periods when the combined
SCL line goes high or low, respectively.
Figure 20-7. SCL Synchronization Between Multiple Masters
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting
data. If the value read from the SDA line does not match the value the Master had output, it has
lost the arbitra tion. Not e that a Ma ster can only lo se arbitr ation wh en it outputs a high SDA value
while another Master outputs a low value. The losing Master should immediately go to Slave
mode, checking if it is being addressed by the winning Master. The SDA line should be left high,
but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Mas ter remains, and this may take many
TA
low
TA
high
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TB
low
TB
high
Masters Start
Counting Low Period
Masters Start
Counting High Period
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bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 20-8. Arbitration Between Two Masters
Note that arbitration is not allowed between:
• A REPEATED START condition and a data bit.
• A STOP conditio n an d a da ta bit.
• A REPEATED START and a STOP condition.
It is the user software’s responsibility to ensure that these illegal arbitration cond itions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
20.5 Overview of the TWI Module
The TWI module is comprised of several submodule s, as shown in Figure 20-9. All registers
drawn in a thick line are accessible through the AVR data bus.
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
START Master A Loses
Arbitration, SDA
A
SDA
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Figure 20-9. Overview of the TWI Module
20.5.1 SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The outpu t drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external on es.
20.5.2 Bit Rate Generator Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the Slave must be at least 16 time s higher than the SCL frequen cy. Note
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
TWI Unit
Address Register
(TWAR)
Address Match Unit
Address Comparator
Control Unit
Control Register
(TWCR)
Status Register
(TWSR)
State Machine and
Status control
SCL
Slew-rate
Control
Spike
Filter
SDA
Slew-rate
Control
Spike
Filter
Bit Rate Generator
Bit Rate Register
(TWBR)
Prescaler
Bus Interface Unit
START / STOP
Control
Arbitration detection Ack
Spike Suppression
Address/Data Shift
Register (TWDR)
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• TWBR = Value of the TWI Bit Rate Register.
• TWPS = Value of the prescaler bits in the TWI Status Register.
Note: TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than 10, the
Master may produce an incorrect output on SDA and SCL for the reminder of the byte. The prob-
lem occurs when operating the TWI in Master mode, sending Start + SLA + R/W to a Slave (a
Slave does not need to be connected to the bus for the condition to happen).
20.5.3 Bus Interface Unit
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration det ection ha rdwa re . The TWDR con ta ins the a ddress or dat a byt es to be t ransmit ted,
or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also
contains a register containing the (N)ACK bit to be transmitt ed or receiv ed. This (N)ACK Regis-
ter is not directly accessible by the application software. Howeve r, whe n rec eiving, it can be set
or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the
value of the received (N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions. The START/STOP controller is able to detect START and STOP
conditions even when the AVR MCU is in one of the sle ep mode s, e nabling th e MCU to wa ke up
if addressed by a Mast er .
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-
ously monitor s the transmissio n trying to dete rmine if arbitrat ion is in pr ocess. If the TWI ha s lost
an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate
status codes generated.
20.5.4 Address Match Unit
The Address Match unit checks if received address bytes match the seven-bit address in the
TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the
TWAR is written to one, all incoming address bits will also be compared against the General Call
address. Upon an address match, the Control Unit is informed, allowing correct action to be
taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.
The Address Match unit is able to compare addresses even when the AVR MCU is in sleep
mode, enabling the MCU to wake up if addressed by a Master. If anothe r interrupt (e.g., INT0)
occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera-
tion and retu rn to it’s idle stat e. If this cause any p roblems, ensure that TWI Address Match is the
only enabled interrupt when entering Power-down.
20.5.5 Control Unit The Control unit moni tors the TWI bu s and genera tes responses cor responding to settings in the
TWI Control Register (TWCR). When an event requirin g the attention of the application occurs
on the TWI bus, t he TWI Interr upt Flag (TWINT) is asse rted. In the ne xt clock cycle, the TWI Sta-
tus Register (TWSR) is updated with a status code identifying the event. The TWSR only
contains relevant status information when the TWI Interrupt Flag is asserted. At all other times,
the TWSR contains a special status code indicating that no relevant status information is avail-
able. As long as the TW INT Flag is s et, the SCL line is held low. This allows the application
software to complete its tasks before allowing the TWI transmission to continue.
SCL frequency CPU Clock frequency
16 2(TWBR) 4TWPS
⋅+
-----------------------------------------------------------=
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The TWINT Flag is set in the following situations:
• After the TWI has transmitted a START/REPEATED START condition.
• After the TWI has transmitted SLA+R/W.
• After the TWI has transmitted an address byte.
• After the TWI has lost arbitration.
• After the TWI has been addressed by own slave address or general call.
• After the TWI has received a data byte.
• After a STOP or REPEATED START has been received while still addressed as a Slave.
• When a bus error has occurred due to an illegal START or STOP condition.
20.6 TWI Register Description
20.6.1 TWI Bit Rate Register – TWBR
• Bits 7..0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator
Unit” on page 222 fo r calculating bit rates.
20.6.2 TWI Control Register – TW CR
The TWCR is used to contr ol the operat ion of the TWI . It is us ed to enable the T WI, to in itiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt V ector . While the TWI NT Flag is se t, the SCL lo w perio d is stretch ed. The TWINT
Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-
cally cleared by hardware when executing the interr upt routine. Also note that clearing this flag
starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta-
tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this
flag.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to
one, the ACK pulse is generated on the TWI bus if the following conditions are met:
Bit 76543210
TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE TWCR
Read/Write R/W R/W R/W R/W R R/W R R/W
Initial Value00000000
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1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial
Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one
again.
• Bit 5 – TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire
Serial Bus. T he TWI hard ware checks if the bu s is available, and generates a START condition
on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is
detected, and then generates a new START condition to claim the bus Master status. TWSTA
must be cleared by soft ware when the START condition has b een transmitted.
• Bit 4 – TWSTO: TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire
Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto-
matically. In Slave mode, setting the TWST O bit can be used to recover from an error condition.
This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed
Slave mode and releases the SCL and SDA lines to a high impedance state.
• Bit 3 – TWWC: TWI Write Collision Flag
The TWWC bit is set whe n attempting to write to the TWI Dat a Register – TWDR when TWINT is
low. This flag is cleared by writing the TWDR Register when TWINT is high.
• Bit 2 – TWEN: TWI Enab le Bit
The TWEN bit enables TWI operat ion an d acti va te s t he TWI interf ace. When TWEN is writte n to
one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the
slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI
transmissions are terminated, regardless of any ongoing operation.
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit and will always read as zero.
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-
vated for as long as the TWINT Flag is high.
20.6.3 TWI Status Register – TWSR
• Bits 7..3 – TWS: TWI Status
These 5 bits reflect the status of the TWI logic and the 2 -wire Serial Bus. The different status
codes are descr ibed later in this sec tion. N ote that the va lue re ad from TW SR cont ains bo th the
5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-
Bit 76543210
TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 TWSR
Read/WriteRRRRRRR/WR/W
Initial Value11111000
226 7593J–AVR–03/09
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caler bits to zero when checking the Status bits. This makes status checking independent of
prescaler setting. This approach is used in this datasheet, unless otherwise noted.
• Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 1..0 – TWPS: TWI Prescaler Bits
These bits can be read and writ ten, and control the bit rate prescaler.
To calculate bit rates, se e “Bit Rate Generator Unit” on page 222. The value of TWPS1..0 is
used in the equation.
20.6.4 TWI Data Regist e r – TW DR
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in t he process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-
ter cannot be initialized b y the user before the first interrup t occurs. Th e data in TWD R remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatica lly by the TWI lo gic, the CPU cannot access the ACK bit dir ectly.
• Bits 7..0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
20.6.5 TWI (Slave) Addres s Re gi st er – TWAR
The TWAR should be loaded with the 7-bit Slave address (in the seven most significan t bits of
TWAR) to which the TWI will resp ond when programmed as a Slave T ransmitter or Receiver,
and not needed in the Master modes. In multimaster systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
Table 20-2. TWI Bit Rat e Presca le r
TWPS1 TWPS0 Prescaler Value
001
014
1016
1164
Bit 76543210
TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value11111111
Bit 76543210
TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value11111110
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The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7..1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TW I un i t.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
20.6.6 TWI (Slave) Addres s M as k Re gi st er – TWAMR
• Bits 7..1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can
mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask
bit is set to one then the address match logic ignores the compare between the incoming
address bit and the corresponding bit in TWAR. Figure 20-10 shows the address match logic in
detail.
Figure 20-10. TWI Address Match Logic, Block Diagram
• Bit 0 – Res: Reserved Bit
This bit is reserved and will always read as zero.
20.7 Using the TWIThe AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like
reception of a b yte or transmission of a ST ART condition. Because the TWI is interrupt-based,
the application soft war e is fre e to car ry o n oth er oper at ions dur ing a TWI byte t ransf er. Not e that
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in
SREG allow the applica tio n to de cide wh et he r or no t as se rtio n of th e T WINT F lag sho u ld ge n er -
ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in
order to detect actio ns on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current
Bit 76543210
TWAM[6:0] – TWAMR
Read/Write R/W R/W R/W R/W R/W R/W R/W R
Initial Value00000000
Addre
ss
Match
Address Bit Comparator 0
Address Bit Comparator 6..1
TWAR0
TWAMR0
Address
Bit 0
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state of the TWI bus. The application software can then decide how the TWI should behave in
the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
Figure 20-11 is a simple example of how th e application can interfa ce to the TWI hardware. In
this example, a Mast er wish es to tr ansm it a sing le data byte to a Slave. T his des cription is q uite
abstract, a more detailed explanation follows later in this section. A simple code example imple-
menting the desired be havior is also presented.
Figure 20-11. Interfacing the Application to the TWI in a Typical Transmission
1. The first step in a TWI transmission is to transmit a START cond ition. This is done by
writing a specific value into TWCR, instru cting the TWI hardware to transmit a START
condition. Which value to write is described later on. However, it is important that the
TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI
will not start any operation as long as the TWINT bit in TWCR is set. Immediately after
the application has cleared TWINT, the TWI will initiate transmission of the START
condition.
2. When the STAR T condition has been tr ansmitted , the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the START condition has success-
fully been sent.
3. The application sof tware should no w examine th e value o f TWSR, to make sure t hat the
START condition was successfully transmitted. If TWSR indicates otherwise, the appli-
cation software might take some special action, like calling an error routine. Assuming
that the status code is as e xpected, the application must load SLA+W into TWDR.
Remember that TWDR is used both f or address and data. After TWDR has been
loaded with the desired SLA+W, a specific value must be written to TWCR, instructing
the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is
described later on. Howe ver, it is important that the TWINT bit is set in the value written.
Writing a one to TWINT clears the flag. The TWI will not start any operation as long as
the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT,
the TWI will initiate transmission of the address packet.
4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the address packet has success-
fully been sent. The status code will also reflect whether a Slave acknowledged the
packet or not.
START SLA+W A Data A STOP
1. Application
writes to TWCR to
initiate
transmission of
START
2. TWINT set.
Status code indicates
START condition sent
4. TWINT set.
Status code indicates
SLA+W sent, ACK
received
6. TWINT set.
Status code indicates
data sent, ACK received
3. Check TWSR to see if START was
sent. Application loads SLA+W into
TWDR, and loads appropriate control
signals into TWCR, makin sure that
TWINT is written to one,
and TWSTA is written to zero.
5. Check TWSR to see if SLA+W was
sent and ACK received.
Application loads data into TWDR, and
loads appropriate control signals into
TWCR, making sure that TWINT is
written to one
7. Check TWSR to see if data was sent
and ACK received.
Application loads appropriate control
signals to send STOP into TWCR,
making sure that TWINT is written to one
TWI bus
Indicates
TWINT set
Application
Action
TWI
Hardware
Action
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5. The application sof tware should no w examine th e value o f TWSR, to make sure t hat the
address packet was successfully transmitted, and that the value of the ACK bit was as
e xpected. If TWSR indicates otherwise, the application software might take some spe-
cial action, like calling an error routine. Assuming that the status code is as expected,
the application must load a data packet into TWDR. Subsequently, a specific value
must be written to TWCR, instructing the TWI hardware to transmit the data packet
present in TWDR. Which value to write is described later on. However, it is important
that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag.
The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immedi-
ately after the application has cleared TWINT, the TWI will initiate transmission of the
data packet.
6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indi cating that the data packet has successfully
been sent. The status code will also reflect whether a Slave acknowledged the packet
or not.
7. The application sof tware should no w examine th e value o f TWSR, to make sure t hat the
data packet was successfully transmitted, and that the value of the ACK bit was as
e xpected. If TWSR indicates otherwise, the application software might take some spe-
cial action, like calling an error routine. Assuming that the status code is as expected,
the application must write a specific value to TWCR, instructing the TWI hardwar e to
transmit a STOP condition. Which value to write is described later on. However, it is
important that the TWINT bit is set in the value written. Writing a one to TWINT clears
the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
Immediately after the application has cleared TWINT, the TWI will initiate transmission
of the STOP condition. Note that TWINT is NOT set after a ST OP condition has been
sent.
Even though this example is sim ple, it shows the principles involved in all TWI transmissions.
These can be summarized as follows:
• When the TWI has finished an operation and expects application response, the TWINT Flag
is set. The SCL line is pulled low until TWINT is cleared.
• When the TWINT Flag is set, the user must update all TWI Registers with the value relevant
for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be
transm itted in the next bus cycle.
• After all TWI Register updates and other pending application software tasks have been
completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a
one to TWINT clears the flag. The TWI will then commenc e executing whatever operation
was specified by the TWCR setting.
In the following an assembly and C implementation of the example is given. Note that the code
below assumes that several definitions have been made, for example by using include-files.
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Table 2.
Assembly Code Example C Example Comments
1
ldi r16,
(1<<TWINT)|(1<<TWSTA)|
(1<<TWEN)
out TWCR, r16
TWCR = (1<<TWINT)|(1<<TWSTA)|
(1<<TWEN) Send START condition
2
wait1:
in r16,TWCR
sbrs r16,TWINT
rjmp wait1
while (!(TWCR & (1<<TWINT)))
;Wait for TW INT Flag set. This
indicates that the START
condition ha s be e n transmitted
3
in r16,TWSR
andi r16, 0xF8
cpi r16, START
brne ERROR
if ((TWSR & 0xF8) != START)
ERROR(); Check v alue of TWI Status
Register. Mask prescaler bits. If
status diff erent from STAR T go to
ERROR
ldi r16, SLA_W
out TWDR, r16
ldi r16, (1<<TWINT) |
(1<<TWEN)
out TWCR, r16
TWDR = SLA_W;
TWCR = (1<<TWINT) |
(1<<TWEN);
Load SLA_W into TWDR
Register. Clear TWINT bit in
TWCR to start transmission of
address
4
wait2:
in r16,TWCR
sbrs r16,TWINT
rjmp wait2
while (!(TWCR & (1<<TWINT)))
;Wait for TW INT Flag set. This
indicates that the SLA+W has
been transmitted, and
ACK/NACK has been received.
5
in r16,TWSR
andi r16, 0xF8
cpi r16, MT_SLA_ACK
brne ERROR
if ((TWSR & 0xF8) !=
MT_SLA_ACK)
ERROR();
Check v alue of TWI Status
Register. Mask prescaler bits. If
status different from
MT_SLA_ACK go to ERROR
ldi r16, DATA
out TWDR, r16
ldi r16, (1<<TWINT) |
(1<<TWEN)
out TWCR, r16
TWDR = DATA;
TWCR = (1<<TWINT) |
(1<<TWEN); Load DATA into TWDR Register .
Clear TWINT bit in TWCR to
start transmission of data
6
wait3:
in r16,TWCR
sbrs r16,TWINT
rjmp wait3
while (!(TWCR & (1<<TWINT)))
;Wait for TW INT Flag set. This
indicates that the D ATA has been
transmitted, and ACK/NACK has
been received.
7
in r16,TWSR
andi r16, 0xF8
cpi r16, MT_DATA_ACK
brne ERROR
if ((TWSR & 0xF8) !=
MT_DATA_ACK)
ERROR();
Check v alue of TWI Status
Register. Mask prescaler bits. If
status different from
MT_DATA_ACK go to ERROR
ldi r16,
(1<<TWINT)|(1<<TWEN)|
(1<<TWSTO)
out TWCR, r16
TWCR = (1<<TWINT)|(1<<TWEN)|
(1<<TWSTO); Transmit STOP condition
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20.8 Transmission Modes
The TWI can operate in one of four major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these
modes can be us ed in th e s am e ap p lication. As an example, the TWI can use MT mode to write
data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters
are present in the system, some of these might transmit data to the TWI, and then SR mode
would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described
along with figures detailing data transmission in each of the modes. These figures contain the
following abbrevia tions:
S: START condition
Rs: REPEATED START condition
R: Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition
SLA: Slave Address
In F igure 20-13 to Figure 20-19, circles are used to indicate that the TWINT Flag is set. The
numbers in the circles show the status code held in TWSR, with the prescaler bits masked to
zero. At these points, actions must be taken by the application to continue or complete the TWI
transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.
When the TWINT Flag is set, the status code in TWSR is used to dete rmine the ap propriat e soft-
ware action. F or each stat us code, the required software a ction and d etails of the following se rial
transfer are given in Table 20-3 to Table 20-6. Note that the p re scal er b it s are m asked to zer o in
these tables.
20.8.1 Master Transmitter Mode
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver
(see Figure 20-12). In order to enter a Master mode, a START condition must be transmitted.
The format of the following address packet determines whether Master Transmitter or Master
Receiver mode is to be enter ed. If SLA+W is tra nsmitted, MT mode is enter ed, if SLA+R is trans-
mitted, MR mode is entered. All the status codes mentioned in this section assume that the
prescaler bits are zero or are masked to zero.
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Figure 20-12. Data Transfer in Master Transmitter Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be set to en able t he 2-wire Ser ial In terface, TWSTA must be wr itten t o one to trans-
mit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will
then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes
free. After a START condition has be en tr ansmitt ed, the TWIN T Flag is se t by h ardware, and t he
status code in TWSR will be 0x08 (see Table 20-3). In order to enter MT mode, SLA+W must be
transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be
cleared (by writing it to one) to continue th e transfer. This is ac complished by writing the follow-
ing value to TWCR:
When SLA+W have been transmitte d and an acknowledgemen t bit has been received, T WINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x18, 0x20, or 0 x38. The a ppropriate action to b e taken for each of t hese status cod es
is detailed in Table 20-3.
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is
done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,
the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-
ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the
transfer. This is accomplished by writing the following value to TWCR:
This scheme is repeated until the last byte has been sent and the transfer is ended by generat-
ing a STOP condition or a repeated START condition. A STOP condition is generated by writing
the following value to TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 1 X10X10 X
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 1 X00X10 X
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 1 X00X10 X
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 1 X01X10 X
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 1 X10X10 X
Device 1
MASTER
TRANSMITTER
Device 2
SLAVE
RECEIVER
Device 3 Device n
SDA
SCL
........
R1 R2
V
CC
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After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same
Slave again, or a ne w Slave without transmitting a STOP condition. Repeated START en ables
the Master to switch betwee n Slaves, Master Transmitte r mode and Master Receiver mode with-
out losing control of the bus.
Table 20-3. Status codes for Master Transmitter Mode
Status Code
(TWSR)
Prescaler Bits
are 0
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR To TWCR
STA STO TWIN
TTWE
A
0x08 A START condition has been
transmitted Load SLA+W 0 0 1 X SLA+W will be transmitted;
ACK or NOT ACK will be received
0x10 A repeated START condition
has been transmitted Loa d SLA+W or
Load SLA+R
0
0
0
0
1
1
X
X
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
0x18 SLA+W has been transmitted;
ACK has been received Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
0
1
0
1
0
0
1
1
1
1
1
1
X
X
X
X
Data byte will be transmitted and A CK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START conditio n will be
transmitted and TWSTO Flag will be reset
0x20 SLA+W has been transmitted;
NOT ACK has been received Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
0
1
0
1
0
0
1
1
1
1
1
1
X
X
X
X
Data byte will be transmitted and A CK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START conditio n will be
transmitted and TWSTO Flag will be reset
0x28 Data byte has been transmit-
ted;
ACK has been received
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
0
1
0
1
0
0
1
1
1
1
1
1
X
X
X
X
Data byte will be transmitted and A CK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START conditio n will be
transmitted and TWSTO Flag will be reset
0x30 Data byte has been transmit-
ted;
NOT ACK has been received
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
0
1
0
1
0
0
1
1
1
1
1
1
X
X
X
X
Data byte will be transmitted and A CK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START conditio n will be
transmitted and TWSTO Flag will be reset
0x38 Arbitration lost in SLA+W or
data bytes No TWDR action or
No TWDR action
0
1
0
0
1
1
X
X
2-wire Serial Bus will be released and not addressed
Slave mode entered
A START condition will be transmitted when the bus
becomes free
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Figure 20-13. Formats and States in the Master Transmitter Mode
20.8.2 Master Receiver Mode
In the Master Receiver mode, a number of data bytes are rece ived from a Slave Transmitter
(Slave see Figure 20-14). In order to enter a Master mode , a START condition must be tr ansmit-
ted. The format of the following address packet determines whether Master Transmitter or
Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R
is transmitted, MR mode is entered. All the status codes mentioned in this section assume that
the prescaler bits are zero or are masked to zero.
S SLA W A DATA A P
$08 $18 $28
R SLA W
$10
AP
$20
P
$30
A or A
$38
A
Other master
continues
A or A
$38
Other master
continues
R
A
$68
Other master
continues
$78 $B0
To corresponding
states in slave mode
MT
MR
Successfull
transmission
to a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Not acknowledge
received after a data
byte
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
DATA A
n
From master to slave
From slave to master
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
S
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Figure 20-14. Data Transfer in Ma ster Receiver Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to
one to transmit a START co ndition and TWINT must b e set to clear the TWINT Flag . The TWI
will then test the 2-wire Serial Bus and generate a START condition as soon as the bus
becomes free. After a START condition has been transmitted, the TWINT Flag is set by hard-
ware, and the status code in TWSR will be 0x08 (See Table 20-3). In order to enter MR mode,
SLA+R must be transmitted. This is done by writing SLA+R to TW DR. Therea fter the T WIN T b it
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing
the following value to TWCR:
When SLA+R have been tr ansmitt ed and an acknowle dgemen t bi t has b een re ceived, TWI NT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x38, 0x40, or 0 x48. The a ppropriate action to b e taken for each of t hese status cod es
is detailed in Table 20-4. Received data can be read from the TWDR Register when the TWINT
Flag is set high by hardware. This scheme is repeated until the last byte has been received.
After the last by te has been re ce ived, th e MR sho uld inf orm th e ST b y sendin g a NACK af ter t he
last received data byte. The transfer is ended by generating a STOP condition or a repeated
START condition. A STOP condition is generated by writing the following value to TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same
Slave again, or a ne w Slave without transmitting a STOP condition. Repeated START en ables
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 1 X10X10 X
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 1 X00X10 X
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 1 X01X10 X
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 1 X10X10 X
Device 1
MASTER
RECEIVER
Device 2
SLAVE
TRANSMITTER
Device 3 Device n
SDA
SCL
........ R1 R2
V
CC
236 7593J–AVR–03/09
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the Master to switch betwee n Slaves, Master Transmitte r mode and Master Receiver mode with-
out losing control over the bus.
Table 20-4. Status codes for Master Receiver Mode
Status Code
(TWSR)
Prescaler Bits
are 0
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR To TWCR
STA STO TWIN
TTWE
A
0x08 A START condition has been
transmitted Load SLA+R 0 0 1 X SLA+R will be transmitted
ACK or NOT ACK will be received
0x10 A repeated START condition
has been transmitted Loa d SLA+R or
Load SLA+W
0
0
0
0
1
1
X
X
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to Master Transmitter mode
0x38 Arbitration lost in SLA+R or
NOT ACK bit No TWDR action o r
No TWDR action
0
1
0
0
1
1
X
X
2-wire Serial Bus will be released and not addressed
Slave mode will be entered
A START condition will be transmitted when the bus
becomes free
0x40 SLA+R has been transmitted;
ACK has been received No TWDR action or
No TWDR action
0
0
0
0
1
1
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
0x48 SLA+R has been transmitted;
NOT ACK has been received No TWDR action or
No TWDR action or
No TWDR action
1
0
1
0
1
1
1
1
1
X
X
X
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START conditio n will be
transmitted and TWSTO Flag will be reset
0x50 Data byte has been received;
ACK has been returned Read data byte or
Read data byte
0
0
0
0
1
1
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
0x58 Data byte has been received;
NOT ACK has been returned Read data byte or
Read data byte or
Read data byte
1
0
1
0
1
1
1
1
1
X
X
X
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START conditio n will be
transmitted and TWSTO Flag will be reset
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Figure 20-15. Formats and States in the Master Receiver Mode
20.8.3 Slave Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter
(see Figure 20-16). All the status codes mentioned in this section assume that the prescaler bits
are zero or are masked to zero.
Figure 20-16. Data transfer in Slave Receiver mode
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
S SLA R A DATA A
$08 $40 $50
SLA R
$10
AP
$48
A or A
$38
Other master
continues
$38
Other master
continues
W
A
$68
Other master
continues
$78 $B0
To corresponding
states in slave mode
MR
MT
Successfull
reception
from a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
DATA A
n
From master to slave
From slave to master
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
PDATA A
$58
A
R
S
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
value Device’s Own Sl ave Address
Device 3 Device n
SDA
SCL
........
R1 R2
V
CC
Device 2
MASTER
TRANSMITTER
Device 1
SLAVE
RECEIVER
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The upper 7 bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the TWI will respon d to the general ca ll address (0x00 ),
otherwise it will ignore the general call address.
TWEN must be wr itte n t o one t o en able t he TWI . The TWEA b it mu st be wr itt e n to on e to en able
the acknowledgement of the device’s own slave addr ess or the general call addre ss. TWSTA
and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addre ssed by its own
slave address (or the gen eral call address if enabled) follo wed by the data direction bit. If the
direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. A fter
its own slave address and the write bit have been received, the TWINT Flag is set and a valid
status code can be read from TWSR. The status code is used to determine the appropriate soft-
ware action. The appropriate action to be taken for each status code is detailed in Table 20-5.
The Slave Receiver mode may also b e entere d if arbit ration is lost wh ile the TWI is in t he Master
mode (see states 0x68 and 0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA
after the next received data byte. This can be used to indicate that the Slave is not able to
receive any more bytes. While T WEA is zero, the TWI does not acknowledge its own slave
address. However, the 2-wire Serial Bus is s till monitored and address recognition may resume
at any time by sett ing TWEA. T his implies that the TW EA bit may be us ed to tem porarily iso late
the TWI from the 2-wire Serial Bus.
In all sleep mo des other than Id le mode, the clo ck system to the TWI is t urned off. If the TWEA
bit is set, the interface can still acknowledge its own slave address or the general call address by
using the 2-wire Serial Bus clock as a clock source. The pa rt will then wake up from slee p and
the TWI will hold the SCL cloc k low during the wake up and until the TWIN T Flag is cleared (by
writing it to one). Further data reception will be carried out as normal, with the AVR clocks run-
ning as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be
held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present
on the bus when waking up from these Sleep modes.
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 0100010 X
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Table 20-5. Status Codes for Slave Receiver Mode
Status Code
(TWSR)
Prescaler Bits
are 0
Status of the 2-wire Serial Bus
and 2-wire Serial Interface Hard-
ware
Application Software Respon se
Next Action Taken by TWI Hardware
To/from TWDR To TWCR
STA STO TWIN
TTWE
A
0x60 Own SLA+W has been received;
ACK has been returned No TWDR action or
No TWDR action
X
X
0
0
1
1
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
0x68 Arbitration lost in SLA+R/W as
Master; own SLA+W has been
received; ACK has been returned
No TWDR action or
No TWDR action
X
X
0
0
1
1
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
0x70 General call address has been
received; ACK has been returned No TWDR action or
No TWDR action
X
X
0
0
1
1
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
0x78 Arbitration lost in SLA+R/W as
Master; General call address has
been received; ACK has been
returned
No TWDR action or
No TWDR action
X
X
0
0
1
1
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
0x80 Previously addressed with own
SLA+W; data has been received;
ACK has been returned
Read data byte or
Read data byte
X
X
0
0
1
1
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
0x88 Previously addressed with own
SLA+W; data has been received;
NOT ACK has been returned
Read data byte or
Read data byte or
Read data byte or
Read data byte
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitt ed when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitt ed when the bus
becomes free
0x90 Previously addressed with
general call; data has been re-
ceived; ACK has been returned
Read data byte or
Read data byte
X
X
0
0
1
1
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
0x98 Previously addressed with
general call; data has been
received; NOT ACK has been
returned
Read data byte or
Read data byte or
Read data byte or
Read data byte
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitt ed when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitt ed when the bus
becomes free
0xA0 A STOP condition or repeated
START condition has been
received while still addressed as
Slave
No action 0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitt ed when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitt ed when the bus
becomes free
240 7593J–AVR–03/09
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Figure 20-17. Formats and States in the Slave Receiver Mode
20.8.4 Slave Transmitter Mode
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver
(see Figure 20-18). All the status codes mentioned in this section assume that the prescaler bits
are zero or are masked to zero.
Figure 20-18. Data Transfer in Slave Transmitter Mode
S SLA W A DATA A
$60 $80
$88
A
$68
Reception of the own
slave address and one or
more data bytes. All are
acknowledged
Last data byte received
is not acknowledged
Arbitration lost as master
and addressed as slave
Reception of the general call
address and one or more data
bytes
Last data byte received is
not acknowledged
n
From master to slave
From slave to master
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
P or SDATA A
$80 $A0
P or SA
ADATAA
$70 $90
$98
A
$78
P or SDATA A
$90 $A0
P or SA
General Call
Arbitration lost as master and
addressed as slave by general call
DATA A
Device 3 Device n
SDA
SCL
........
R1 R2
V
CC
Device 2
MASTER
RECEIVER
Device 1
SLAVE
TRANSMITTER
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To initiate the Slave Transmit ter mode, TWAR and TWCR must be initialized as follows:
The upper seven bits are the addre ss to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the TWI will respon d to the general ca ll address (0x00 ),
otherwise it will ignore the general call address.
TWEN must be wr itte n t o one t o en able t he TWI . The TWEA b it mu st be wr itt e n to on e to en able
the acknowledgement of the device’s own slave addr ess or the general call addre ss. TWSTA
and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addre ssed by its own
slave address (or the gen eral call address if enabled) follo wed by the data direction bit. If the
direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. A fter
its own slave address and the write bit have been received, the TWINT Flag is set and a valid
status code can be read from TWSR. The status code is used to determine the appropriate soft-
ware action. The appropriate action to be taken for each status code is detailed in Table 20-6.
The Slave Transmitte r mode may also be entered if arbitration is lost while the TWI is in the
Master mode (see state 0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-
fer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver
transmits a NACK or ACK after the final b yte. The TWI is switched to the not addre ssed Slave
mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives
all “1” as serial data. State 0xC8 is entered if the Master demands additional data bytes (by
transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expect-
ing NACK from the Master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire
Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.
This implies that the TWEA b i t may be used to te mpo rarily isolat e th e TWI fr om th e 2- wire Seria l
Bus.
In all sleep mo des other than Id le mode, the clo ck system to the TWI is t urned off. If the TWEA
bit is set, the interface can still acknowledge its own slave address or the general call address by
using the 2-wire Serial Bus clock as a clock source. The pa rt will then wake up from slee p and
the TWI will hold the SCL clock will low during th e wake up and until the TWINT Flag is cleared
(by writing it to one). Further data tr ansmission will be carried out as normal, with the AVR clocks
running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may
be held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present
on the bus when waking up from these sleep modes.
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
value Device’s Own Sl ave Address
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE
value 0100010 X
Table 20-6. Status Codes for Slave Transmitter Mode
Status Code
(TWSR)
Prescaler
Bits
are 0
Status of the 2-wire Serial Bus
and 2-wire Serial Interface Hard-
ware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR To TWCR
STA STO TWIN
TTWE
A
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Figure 20-19. Formats and States in the Slave Transmitter Mode
20.8.5 Miscellaneous States
There are two stat us codes that do not correspond to a defined TWI state, see Table 20-7.
0xA8 Own SLA+R has been received;
ACK has been returned Load data byte or
Load data byte
X
X
0
0
1
1
0
1
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be re-
ceived
0xB0 Arbitration lost in SLA+R/W as
Master; own SLA+R has been
received; ACK has been ret urned
Load data byte or
Load data byte
X
X
0
0
1
1
0
1
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be re-
ceived
0xB8 Data byte in TWDR has been
transmitted; ACK has been
received
Load data byte or
Load data byte
X
X
0
0
1
1
0
1
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be re-
ceived
0xC0 Data byte in TWDR has been
transmitted; NOT ACK has been
received
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
Switched to the not addressed Sla ve mode;
no recognition of own SLA or GCA
Switched to the not addressed Sla ve mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Sla ve mode;
no recognition of own SLA or GCA;
a START condition will be transmitt ed when the bus
becomes free
Switched to the not addressed Sla ve mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitt ed when the bus
becomes free
0xC8 Last data byte in TWDR has been
transmitted (TWEA = “0”); ACK
has been received
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
Switched to the not addressed Sla ve mode;
no recognition of own SLA or GCA
Switched to the not addressed Sla ve mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Sla ve mode;
no recognition of own SLA or GCA;
a START condition will be transmitt ed when the bus
becomes free
Switched to the not addressed Sla ve mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitt ed when the bus
becomes free
Table 20-6. Status Codes for Slave Transmitter Mode
S SLA R A DATA A
$A8 $B8
A
$B0
Reception of the own
slave address and one or
more data bytes
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
Arbitration lost as master
and addressed as slave
n
From master to slave
From slave to master
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
P or SDATA
$C0
DATA A
A
$C8
P or SAll 1's
A
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Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
20.8.6 Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what locat ion should be read.
3. The reading must be performed.
4. The tr ansfer must be finished.
Note that data is tran smitted both fro m Master to Slave and vice versa. The Maste r must instr uct
the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read fr om the Slave, impl ying the use of the MR mode. Thus, the transf er direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomical o peration. If this principle is violated in a multimaster sys-
tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the Master keeps owne rship of the bus. The following
figure shows the flow in this transfer.
Figure 20-20. Combining Several TWI Modes to Access a Serial EEPROM
Table 20-7. Miscellaneous States
Status Code
(TWSR)
Prescaler Bits
are 0
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR To TWCR
STA STO TWIN
TTWE
A
0xF8 No relevant state information
available; TWINT = “0” No TWDR action No TWCR action Wait or proceed current transfer
0x00 Bus error due to an illegal
START or STOP condition No TWDR action 0 1 1 X Only the internal ha rdware is a ffected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
Master Transmitter Master Receiver
S = START Rs = REPEATED START P = STOP
Transmitted from master to slave Transmitted from slave to master
S SLA+W A ADDRESS A Rs SLA+R A DATA A P
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20.9 Multi-master Systems and Arbitration
If multiple master s are connected to the same bu s, transmissions may be initiated sim ultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a Slave Receiver.
Figure 20-21. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
• Two or more mast ers are performing identical commu nication with the same Slave . In this
case, neither the Slave nor any of the masters will know about the bus contention.
• Two or more mast ers are accessing the sam e Slav e with different dat a or directio n bit. In this
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
SLA bits. Masters trying to output a one on SD A while another Master outputs a zero will lose
the arbitra tion. Masters losing arbit ration in SLA will switch to Sla v e mode to chec k if the y are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slav e mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
This is summarized in Figure 20-22. Possible status values are given in circles.
Device 1
MASTER
TRANSMITTER
Device 2
MASTER
TRANSMITTER
Device 3
SLAVE
RECEIVER
Device n
SDA
SCL
........
R1 R2
V
CC
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Figure 20-22. Possible Status Codes Caused by Arbitratio n
Own
Address / General Call
received
Arbitration lost in SLA
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
No
Arbitration lost in Data
Direction
Ye s
Write Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Read
B0
68/78
38
SLASTART Data STOP
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21. USB controller
21.1 Features •Support full-speed and low-speed.
•Support ping-pong mode (dual bank)
•832 bytes of DPRAM :
– 1 endpoint 64 bytes max (default control endpoint),
– 1 endpoints of 256 bytes max, (one or two banks),
– 5 endpoints of 64 bytes max, (one or two banks)
21.2 Block Diagram
The USB controller provides the hardware to interface a USB link to a data flow stored in a dou-
ble port memo ry (DP R AM ).
The USB controller re quir es a 48 M Hz ±0.25 % re fere nce clock (f or Fu ll-Spe ed ope ra tion) , which
is the output of an internal PLL. The PLL generates the internal high frequency (48 MHz) clock
for USB interface , th e PL L in put is g ene rate d f rom a n e xte rn al lowe r f requ en cy ( the cr ystal o scil-
lator or external clock input pin from XTAL1; to satisfy the USB frequency accuracy and jitter,
only this clock source allows proper functionnality of the USB controller).
The 48MHz clock is used to generate a 12 MHz Full-speed (or 1.5 MHz Low-Speed) bit clock
from the received USB differential data and to transmit data according to full or low speed USB
device toler ance . Clo ck recover y is do ne by a Dig ital Phase Locked Lo op (DPLL) b lock, wh ich is
compliant with the jitter specification of the USB bus.
To comply with the USB Electrical specification, USB Pads (D+ or D-) should be powered within
the 3.0 to 3.6V range. As ATmega32U6/AT90USB64/128 can be powered up to 5.5V, an inter-
nal regulator provides the USB pads power supply.
Figure 21-1. USB controller Block Diagram overv iew
CPU
USB Regulator
USB
Interface
PLL
24x
clk
2MHz
clk
48MHz
PLL clock
Prescaler
On-Chip
USB DPRAM
DPLL
Clock
Recovery
UCAP
D-
D+
VBUS
UID
UVCC AVCC XTAL1
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21.3 Typical Application Implementation
Depending on the USB operating mode (Device only, Reduced Host or OTG mode) and on the
target application po wer supply, the ATmega32U 6/AT90USB64/128 require differe nt hardware
typical implementations.
Figure 21-2. Operating modes versus frequency and power-supply
21.3.1 Device mode
21.3.1.1 Bus Powered device
Figure 21-3. Typical Bus powered application with 5V I/O
VCC (V)
VCC min
0
3.0
3.4
5.5
USB not operational
USB compliant,
without internal regulator
USB compliant,
with internal regulator
4.5
2.7
Max
Operating Frequency (MHz)
8 MHz
16 MHz
2 MHz
3.6
1µF
UDP
UDM
VBUS
UVSS
UID
UCAP
D-
D+
VBUS
UID
UGND
UVCC AVCC VCC
XTAL1 XTAL2 GND GND
Rs=22
Rs=22
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Figure 21-4. Typical Bus powered application with 3V I/O
21.3.1.2 Self Powered device
Figure 21-5. Typical Self powered application with 3.4V to 5.5V I/O
1µF
UVSS
External
3V Regulator
UDP
UDM
VBUS
UVSS
UID
UCAP
D-
D+
VBUS
UID
UGND
UVCC AVCC VCC
XTAL1 XTAL2 GND GND
Rs=22
Rs=22
1µF
External 3.4V - 5.5V
Power Supply
UDP
UDM
VBUS
UVSS
UID
UCAP
D-
D+
VBUS
UID
UGND
UVCC AVCC VCC
XTAL1 XTAL2 GND GND
Rs=22
Rs=22
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Figure 21-6. Typical Self powered application with 3.0V to 3.6 I/O
21.3.2 Host / OTG mode
Figure 21-7. Host/OTG application with 3.0V to 3.6 I/O
1µF
External 3.0V - 3.6V
Power Supply
UDP
UDM
VBUS
UVSS
UID
UCAP
D-
D+
VBUS
UID
UGND
UVCC AVCC VCC
XTAL1 XTAL2 GND GND
Rs=22
Rs=22
UDM
UDP
VBUS
UVSS
UID
D-
D+
VBUS
UID
UGND
1µF
External 3.0V - 3.4V
Power Supply
UCAP
UVCC AVCC VCC
XTAL1 XTAL2 GND GND
UVCON
5V DC/DC
generator
5V
Rs=22
Rs=22
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Figure 21-8. Host/OTG application with 5V I/O
21.3.3 Design guidelines
• Serial resistors on USB Data lines must have 22 Ohms value (+/- 5%).
• Trace s fro m the inpu t USB recept able (or fro m t he ca ble connection in t he case of a tet here d
device) to the USB microcontro ller pads should be as short as possibles, and follow
differential traces routing rules (same length, as near as possible, avoid vias accumulation).
• Voltage transcie nt / ESD suppressors ma y also b e used to pre vent USB pads to be damaged
by external disturbances.
•U
cap capacitor should be 1µF (+/- 10%) for correct operation.
• A 10µF capacitor is highly recom mended on VBUS line
UDP
UDM
VBUS
UVSS
UID
D-
D+
VBUS
UID
UGND
1µF
External 5.0V
Power Supply
UCAP
UVCC AVCC VCC
XTAL1 XTAL2 GND GND
UVCON
5V
Rs=22
Rs=22
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21.4 General Operating Modes
21.4.1 Introduction After a hardware reset, the USB controller is disabled. When enabled, the USB controller has to
run the Device Controller or the Host Controller. This is performed using the USB ID detection.
• If the ID pin is not conne cted to groun d, the USB ID bit is set by hardw are (internal pull up on
the UID pad) and the USB Device controller is selected.
• The ID bit is cleared by hardwa re when a low level has been detected on the ID pin. The
Device controller is then disabled and the Host controller enabled.
The software anyway has to select the mode (Host, Device) in order to access to the Device
controller registers or to the Host controller registers, which are multiplexed. For example, even
if the USB controller has detected a Device mode (pin ID high), the software shall select the
device mode (bit HOST cleare d), otherwise it will access to the host registers. This is also true
for the Host mode .
Note: For the AT90USB646/1286 products the Host mode is not included in the USB controller, and the
ID pin is not used and should be configured and used as a general I/O.
21.4.2 Power-on and reset
The next diagram explains the USB controller main states on power- on:
Figure 21-9. USB controller states after reset
USB Controller stat e aft er an ha rd wa re reset is ‘Reset’. In this state :
• USBE is not set
• the USB controller clock is stopped in order to minimize the power consumption
(FRZCLK=1),
• the USB controller is disabled,
• the USB pad is in the suspend mode,
• the Host and Device USB controllers internal states are reset.
After setting USBE, t he USB Controller enters in the Host or in th e Device state (according to the
USB ID pin). The selected controller is ‘Idle’.
The USB Controller can at any time be ‘stopped’ by clearing USBE. In fact, clearing USBE acts
as an hardware reset.
Device
Reset
USBE=0 <any other
state>
USBE=1
ID=1
Clock stopped
FRZCLK=1
Macro off
USBE=0
USBE=0
Host
USBE=0
HW
RESET
USBE=1
ID=0
AT90USB647/1287 only
AT90USB646/1286 forced mode
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21.4.3 Interrupts Two interrupts vectors are assigned to USB interface.
Figure 21-10. USB Interrupt System
See Section 22.17, page 277 and Section 23.15, page 296 for more details on the Host and
Device interrupts.
USB General
& OTG Interrupt
USB Device
Interrupt
USB Host
Interrupt
USB General
Interrupt Vector
Endpoint
Interrupt
Pipe
Interrupt
USB Endpoint/Pipe
Interrupt Vector
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Figure 21-11. USB General interrupt vector sources
IDTE
USBCON.1
IDTI
USBINT.1
VBUSTI
USBINT.0 VBUSTE
USBCON.0
STOI
OTGINT.5 STOE
OTGIEN.5
HNPERRI
OTGINT.4
HNPERRE
OTGIEN.4
ROLEEXI
OTGINT.3 ROLEEXE
OTGIEN.3
BCERRI
OTGINT.2 BCERRE
OTGIEN.2
VBERRI
OTGINT.1 VBERRE
OTGIEN.1
SRPI
OTGINT.0 SRPE
OTGIEN.0
USB General
Interrupt Vector
UPRSMI
UDINT.6 UPRSME
UDIEN.6
EORSMI
UDINT.5 EORSME
UDIEN.5
WAKEUPI
UDINT.4
WAKEUPE
UDIEN.4
EORSTI
UDINT.3 EORSTE
UDIEN.3
SOFI
UDINT.2 SOFE
UDIEN.2
SUSPI
UDINT.0 SUSPE
UDIEN.0
HWUPE
UHIEN.6
HWUPI
UHINT.6
HSOFI
UHINT.5 HSOFE
UHIEN.5
RXRSMI
UHINT.4 RXRSME
UHIEN.4
RSMEDI
UHINT.3 RSMEDE
UHIEN.3
RSTI
UHINT.2 RSTE
UHIEN.2
DDISCI
UHINT.1 DDISCE
UHIEN.1
DCONNI
UHINT.0 DCONNE
UHIEN.0
USB Device
Interrupt
USB Host
Interrupt
USB General
Interrupt Vector
Asynchronous Interrupt source
(allows the CPU to wake up from power down mode)
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Figure 21-12. USB Endpoint/Pipe Interrupt vector sources
FLERRE
UEIENX.7
OVERFI
UESTAX.6
UNDERFI
UESTAX.5
NAKINI
UEINTX.6 NAKINE
UEIENX.6
NAKOUTI
UEINTX.4 TXSTPE
UEIENX.4
RXSTPI
UEINTX.3 RXSTPE
UEIENX.3
RXOUTI
UEINTX.2 RXOUTE
UEIENX.2
STALLEDI
UEINTX.1
STALLEDE
UEIENX.1
EPINT
UEINT.X
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
Endpoint 4
Endpoint 5
Endpoint Interrupt
TXINI
UEINTX.0
TXINE
UEIENX.0
FLERRE
UPIEN.7
UNDERFI
UPSTAX.5
OVERFI
UPSTAX.6
NAKEDI
UPINTX.6 NAKEDE
UPIEN.6
PERRI
UPINTX.4 PERRE
UPIEN.4
TXSTPI
UPINTX.3 TXSTPE
UPIEN.3
TXOUTI
UPINTX.2 TXOUTE
UPIEN.2
RXSTALLI
UPINTX.1
RXSTALLE
UPIEN.1
RXINI
UPINTX.0 RXINE
UPIEN.0
FLERRE
UPIEN.X
PIPE 0
PIPE 1
PIPE 2
PIPE 3
PIPE 4
PIPE 5
Pipe Interrupt
USB Endpoint/P
Interrupt Vecto
Endpoint 6
PIPE 6
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Figure 21-13. USB General and OTG Cont roller Interrupt System
There are 2 kind of interrupts: pr ocessing (i.e. the ir generation are part of the norm al processing)
and exception (errors).
Processing interrupts are generated when such events occur :
• USB ID Pad change detection (insert, remove)(IDTI)
• VBUS plug-in detection (insert, remove) (VBUSTI)
• SRP detected (SRPI)
• Role Exchanged(ROLEEXI)
Exception Inte rr up ts ar e ge n erat ed with th e follo win g even ts :
• Drop on VBus Detected(VBERRI)
• Error during the B-Connection(BCERRI)
• HNP Error(HNPERRI)
• Time-out detected during Suspend mode(STOII)
21.5 Po wer modes
21.5.1 Idle mode In this mode, the CPU core is halted (CPU clock stopped). The Idle mode is taken wether the
USB controller is running or not. The CPU “wakes up” on any USB interrupts.
21.5.2 Power down In this mode, the oscillator is stopped and halts all the clocks (CPU and peripherals). The USB
controller “wakes up” when:
• the WAKEUPI interrupt is triggered in the Per ipheral mode (HOST cleared),
IDTE
USBCON.1
IDTI
USBINT.1
VBUSTI
USBINT.0 VBUSTE
USBCON.0
STOI
OTGINT.5 STOE
OTGIEN.5
HNPERRI
OTGINT.4 HNPERRE
OTGIEN.4
ROLEEXI
OTGINT.3 ROLEEXE
OTGIEN.3
BCERRI
OTGINT.2 BCERRE
OTGIEN.2
VBERRI
OTGINT.1 VBERRE
OTGIEN.1
SRPI
OTGINT.0 SRPE
OTGIEN.0
USB General & OTG
Interrupt Vector
Asynchronous Interrupt source
(allows the CPU to wake up from power down mode)
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• the HWUPI interrupt is triggered in the Host mode (HOST set).
• the IDTI interrupt is triggered
• the VBUSTI interrupt is triggered
21.5.3 Freez e clock The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, whic h
freeze the clock of USB con troller. When FRZCLK is set, it is still possible to access to the fol-
lowing registers:
• USBCON, USBSTA, USBINT
• UDCON (detach, ...)
•UDINT
•UDIEN
•UHCON
•UHINT
•UHIEN
Moreover, when FRZCLK is set, only the following interrupts may be triggered:
• WAKEUPI
•IDTI
•VBUSTI
•HWUPI
21.6 Speed Contr o l
21.6.1 Device mode When the USB interface is configu red in device mode , the speed selection (Full Speed or Low
Speed) depends on the UDP/UDM pull-up. The LSM bit in UDCON register allows to select an
internal pull up on UDM (Low Speed mode) or UDP(Full Speed mode) data lines.
Figure 21-14. Device mode Speed Selection
RPU
DETACH
UDCON.0
UDP
UDM
RPU
LSM
UDCON.2
UCAP USB
Regulator
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21.6.2 Host mode When the USB interface is con figured in host mode, internal Pull Down resistor s are activat ed on
both UDP UDM lines and the interface detects the type of connected device.
21.7 Memory management
The controller does only support the following memory allocation management.
The reservation of a Pipe or an Endpoint can only be made in the increasing order (Pipe/End-
point 0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order.
The reservation of a Pipe or an Endpoint “ki” is done when its ALLOC bit is set. Then, the hard-
ware allocates the memory and inserts it between the Pipe/Endpoints “ki-1” and “ki+1”. The “ki+1”
Pipe/Endpoint memo ry “slides” up and its data is los t. Note that the “ki+2” and upper Pipe/End-
point memory does not slide.
Clearing a Pipe enable (PEN) or an Endpoint enable (EPEN) does not clear either its ALLOC bit,
or its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear
ALLOC. Then, the “ki+1” Pipe/Endpoint memory automatically “slides” down. Note that the “ki+2”
and upper Pipe/Endpoint memory does not slide.
The following figure illustrates the allocation and reorganization of the USB memory in a typical
example:
Table 21-1. Allocation and reorganization USB memory flow
• First, Pipe/Endpoint 0 to Pipe/Endpoint 5 are configured, in the growing order. The memory
of each is reserved in the DPRAM.
• Then, the Pipe/Endpo int 3 is disab led (EPEN=0), bu t its memory reservation is inte rnally kept
by the controller.
• Its ALLOC bit is cleared: the Pipe/ Endpoint 4 “sli des” down, b ut the Pipe/Endpoint 5 does not
“slide”.
• Finally, if the firmware chooses to reconfigure the Pipe/Endpoint 3, with a bigger size. The
controller reserved the memory after the endpoin t 2 memory and automatically “slide” the
Pipe/Endpoint 4. The Pipe/Endpoint 5 does not move and a memory conflict appear, in that
Free memory
0
1
2
3
4
5
EPEN=1
ALLOC=1
Free memory
0
1
2
4
5
EPEN=0
(ALLOC=1)
Free memory
0
1
2
4
5
Pipe/Endpoints
activation Pipe/Endpoint
Disable Free its memory
(ALLOC=0)
Free memory
0
1
2
3 (bigger size)
5
Pipe/Endpoint
Activatation
Lost memory 4Conflict
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both Pipe/Endpoint 4 and 5 use a common area. The data of those endpoints are potentially
lost.
Note that:
• the data of Pipe/Endpoint 0 are never lost whatever the activation or deactivation of the
higher Pipe/Endpoint. Its data is lost if it is deactivated.
• Deactivate and reactivate the same Pipe/Endpoint with the same parameters does not lead
to a “slide” of the higher endpoints. For those endpoints, the data are preserved.
• CFGOK is set by hardware even in the case where there is a “conflict” in the memory
allocation.
21.8 PAD suspend The next figures illustrates the pad behaviour:
• In the “idle” mode, the pad is put in low power consumption mode.
• In the “active” mode, the pad is working.
Figure 21-15. Pad behaviour
The SUSPI flag indicated that a suspend state has been detected on the USB bu s. This flag
automatically put the USB pad in Idle. The detection of a non-idle event sets the WAKEUPI flag
and wakes-up the USB pad.
Moreover, the pad can also be put in the “idle” mode if the DETACH bit is set. It come back in
the active mode when the DETACH bit is cleared.
Idle mode
Active mode
USBE=1
& DETACH=0
& suspend
USBE=0
| DETA CH=1
| sus pend
SUSPI
Suspend detected = USB pad power down Clear Suspend by software
Resume = USB pad wake-up Clear Resume by software
WAKEUPI
PAD status
Active
Power Down
Active
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21.9 OTG timers customizing
It is possible to refine some OTG timers thanks to the OTGTCON register that contains the
PAGE bits to select the timer and the VALUE bits to adjust the value. User should refer to lastest
releases of the OTG specification to select compliant timings.
• PAGE=00b: AWaitVrise time-out. [O TG]. In Host mode, once VBUSREQ has been set to “1”,
if no VBUS is dete cted on VBUS p in after this AW aitVrise dela y then the VBERRI error flag is
set.
– VALUE=00bTime-out is set to 20 ms
– VALUE=01bTime-out is set to 50 ms
– VALUE=10bTime-out is set to 70ms
– VALUE=11bTime-out is set to 100 ms
• PAGE=01b: VbBusPulsing. [OTG]. In Device mode, this delay corresponds to the pulse
duration on Vbus during a SRP.
– VALUE=00bTime-out is set to 15 ms
– VALUE=01bTime-out is set to 23 ms
– VALUE=10bTime-out is set to 31 ms
– VALUE=11bTime-out is set to 40 ms
• PAGE=10b: PdTmOutCnt. [OTG]. In Device mode, when a SRP has been requested to be
sent by the firmware, this delay is w aited by the hardware after VBUS has gone below the
“session_valid” threshold voltage and before initiating the first pulse. This delay should be
considered as an approximation of USB lines discharge (pull-down resistors vs. line
capacitance) in order to wait that VBUS has gone below the “b_session_end” threshold
voltae, as defined in th e OTG specification.
– VALUE=00bTime-out is set to 93 ms
– VALUE=01bTime-out is set to 105 ms
– VALUE=10bTime-out is set to 118 ms
– VALUE=11bTime-out is set to 131 ms
• PAGE=11b: SRPDetTmOut. [OTG]. In Host mode, this delay is the minimum pulse duration
required to detect and accept a valid SRP from a Device.
– VALUE=00bTime-out is set to 10 us
– VALUE=01bTime-out is set to 100 us
– VALUE=10bTime-out is set to 1 ms
– VALUE=11bTime-out is set to 11 ms
21.10 Plug-in detection
The USB connection is detected by the VBUS pad, thanks to the following architecture:
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Figure 21-16. Plug-in Detection In pu t Bl ock Diag ram
The control logic of the VBUS pad outputs a signal regarding the VBUS voltage level :
• The “Session_valid” signal is active high when the voltage on the VBUS pad is higher or
equal to 1.4V. If lower than 1.4V, the signal is not active.
• The “Vb us_v alid” signal is activ e high when the vo ltage on the VB US pad is higher or equal to
4.4V. If lower than 4.4V, the signal is not active.
• The VBUS status bit is set when VBUS is greater than “Vbus_v alid”. The VBUS status bit is
cleared when VBUS falls below “Session_ valid” (hysteresis behavior).
• The VBUSTI flag is set each time the VBUS bit state changes.
21.10.1 Peripheral mode
The USB peripheral cannot attach to the bus while VBUS bit is not set.
21.10.2 Host mode The Host must use the UVCON pin to drive an external power switch or regulator that powers
the Vbus line. The UVCON pin is automatically asserted and set high by hardware when
UVCONE and VBUSREQ bits are set by firmware.
If a device connects (pull-up on DP or DM) within 300ms of Vbus delivery, the DCONNI flag will
rise. But, once VBUSREQ bi t has been set, if no peripheral connectio n is detected within 300ms,
the BCERRI flag (and interrupt) will rise and Vbus delivery will be stopped (UVCON cleared).
If that behavior re presents a limitatio n for the Host applica tion, the following wor k-around may be
used :
1. UVCONE and VBUSREQ must be cleared
2. VBUSHWC must be set (to disable hardware control of UVCON pin)
3. PORTE,7 pin (alternate function of UVCON pin) must be set by firmware
4. a device connection will be detected thanks to the SRPI flag (that may usually be used
to detect a DP/DM pulse sent by an OTG B-Device that requ ests a new session)
21.11 ID detection The ID pin transition is detected thanks to the following architecture:
VBUSTI
USBINT.0
VBUS VBUS
USBSTA.0
VSS
VDD
Pad logic
Logic
Session_valid
RPU
RPU
VBus_pulsing
VBus_discharge
Vbus_valid
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Figure 21-17. ID Detection Input Block Diagram
The ID pin can be used to detect the USB mode (Peripheral or Host) or software selected. This
allows the UID pin to be used has general purpose I/O even when USB interface is enable.
When the UID pin is selected, by default, (no A-plug or B-plug), the macro is in the Peripheral
mode (internal pull-up). The IDTI interrupt is triggered when a A-plug (Host) is plugged or
unplugged. The interrupt is not triggered when a B-plug (Periph) is plugged or unplugged.
ID detection is independant of USB global interface enable.
21.12 Registers description
21.12.1 USB general registers
• 7 – UIMOD: USB Mode Bit
This bit has no effect when the UIDE bit is set (exter nal UID pin activated). Set to enable the
USB device mode. Clear to enable the USB host mode
• 6 – UIDE: UID pin Enable
Set to enable the USB mode selection (peripheral/host) through the UID pin. Clear to enable the
USB mode selection (peripheral/host) with UIMOD bit register.
UIDE should be modified only when the USB interface is disabled (USBE bit cleared).
• 5 – Reserved
The value read from this bit is always 0. Do not set this bit.
• 4 – UVCONE: UVCON pin Enable
Set to enable th e UVCON pin control. Clear to disab le the UVCON pin contro l. This bit sh ould be
set only when the USB interf ac e is ena b le.
• 3-1 – Reserved
The value read from these bits is always 0. Do not set these bits.
RPU
UIMOD
UHWCON.7
UID ID
USBSTA.1
Internal Pull Up
VDD
UIDE
UHWCON.6
1
0
Bit 765 4 321 0
UIMOD UIDE UVCONE UVREGE UHWCON
Read/Write R/W R/W R R/W R R R R/W
Initial Value 1 0 0 0 0 0 0 0
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• 0 – UVREGE: USB pad regulator Enable
Set to enable the USB pad regulator. Clear to disable the USB pad regulator.
• 7 – USBE: USB macro Enable Bit
Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the
USB transceiver and to disable the USB controller clock inputs.
• 6 – HOST: HOST Bit
Set to enable the Host mode. Clear to enable the device mode.
• 5 – FRZCLK: Freeze USB Clock Bit
Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power
consumption. Clear to enable the clock inputs.
• 4 – OTGPADE: OTG Pad Enable
Set to enable the OTG pad. Clear to disable the OTG pad. The OTG pad is actually the VBUS
pad.
Note that this bit can be set/cleared even if USBE=0. That allows the VBUS detection even if the
USB macro is disabled. This pad must be enabled in both Host and Device modes in order to
allow USB operation (attaching, transmitting...).
• 3-2 – Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 – IDTE: ID Transition Interrupt Enable Bit
Set this bit to ena ble the ID Transit ion interrupt generation . Clear this bi t to disable the I D Transi-
tion interrupt generation.
• 0 – VBUSTE: VBUS Transition Interrupt Enable Bit
Set this bit to ena ble the VBUS Transition interrupt generat ion.
Clear this bit to disable the VBUS Transition interrupt generation.
• 7-4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3 – SPEED: Speed Status Flag
This should be read only when the USB controller operates in host mode, in device mode the
value read from this bit is undeterminated.
Bit 7 6 5 4 321 0
USBE HOST FRZCLK OTGPADE - - IDTE VBUSTE USBCON
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 1 0 0 0 0 0
Bit 76543 210
----SPEED IDVBUSUSBSTA
Read/WriteRRRRRRRR
Initial Value00001 0 10
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Set by hardware when the controller is in FULL-SPEED mode. Cleared by hardware when the
controller is in LOW-SPEED mode.
• 2 – Reserved
The value read from this bit is always 0. Do not set this bit.
• 1 – ID: IUD pin Flag
The value read from this bit indicates the state of the UID pin.
• 0 – VBUS: VBus Flag
The value read from this bit indicates the state of the VBUS pin. This bit can be used in device
mode to monitor the USB bus connection state of the appication. See Section 21.10, page 259
for more details.
7-2 - Reserved
The value read from these bits is always 0. Do not set these bits.
1 – IDTI: D Transition Interrupt Flag
Set by hardware when a transition (high to low, low to high) has been detected on the UID pin.
Shall be cleared by softw ar e.
• 0 – VBUSTI: IVBUS Transition Interrupt Flag
Set by hardware when a transition (high to low, low to high) has been detected on the VBUS
pad.
Shall be cleared by softw ar e.
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 – HNPREQ: HNP Request Bit
Set to initiate the HNP when the controller is in the Device mode (B). Set to accept the HNP
when the controller is in the Host mode (A).
Clear otherwise.
• 4 – SRPREQ: SRP Request Bit
Set to initiate the SRP whe n the controller is in Device mode. Cleared by hardware when th e
controller is initiating a SRP.
Bit 76543210
------IDTIVBUSTIUSBINT
Read/WriteRRRRRRR/WR/W
Initial Value00000000
Bit 7 6 5 4 3 2 1 0
- - HNPREQ SRPREQ SRPSEL VBUSHWC VBUSREQ VBUSRQC OTGCON
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• 3 – SRPSEL: SRP Selection Bit
Set to choose VBUS pulsing as SRP method.
Clear to choose data line pulsing as SRP method.
• 2 – VBUSHWC: VBus Hardware Control Bit
Set to disable the hardware control over the UVCON pin.
Clear to enable the hardware control over the UVCON pin.
See for more details
• 1 – VBUSREQ: VBUS Request Bit
Set to assert the UVCON pin in order to enable the VBUS power supply generation. This bit
shall be used when the controller is in the Host mode.
Cleared by hardware when VBUSRQC is set.
• 0 – VBUSRQC: VBUS Request Clear Bit
Set to deassert the UVCON pin in order to enable the VBUS power supply generation. This bit
shall be used when the controller is in the Host mode.
Cleared by hardware immediately after the set.
• 7 – Reserved
This bit is reserved and always set.
• 6-5 – PAGE: Timer page access Bit
Set/clear to access a special timer register. See Section 21.9, page 259 for more details.
• 4-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1-0 – VALUE: Value Bit
Set to initialize the new value of the timer. See Section 21.9, page 259 for more details.
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 – STOE: Suspend Time-out Error Interrupt Enable Bit
Set to enable the STOI interrupt. Clear to disable the STOI interrupt.
Bit 7 6 5 4 3 2 1 0
- PAGE - - - VALUE OTGTCON
Read/Write R R/W R/W R R R/W R/W R/W
Initial Value 1 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - STOE HNPERRE ROLEEXE BCERRE VBERRE SRPE OTGIEN
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• 4 – HNPERRE: HNP Error Interrupt Enable Bit
Set to enable the HNPERRI interrupt. Clear to disable the HNPERRI interrupt.
• 3 – ROLEEXE: Role Exchange Interrupt Enable Bit
Set to enable the ROLEEXI interrupt. Clear to disable the R OLEEXI interrupt.
• 2 – BCERRE: B-Connection Error Interrupt Enable Bit
Set to enable the BCERRI interrupt. Clear to disable the BCERRI interrupt.
• 1 – VBERRE: VBus Error Interrupt Enable Bit
Set to enable the VBERRI interrupt. Clear to disable the VBERRI interrupt.
• 0 – SRPE: SRP Interrupt Enable Bit
Set to enable the SRPI interrupt. Clear to disable the SRPI interrupt.
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 – STOI: Suspend Time-out Error Interrupt Flag
Set by hardware when a time-out error (more than 150 ms) has been detected after a suspend.
Shall be cleared by softw ar e.
• 4 – HNPERRI: HNP Error Interrupt Flag
Set by hardware when an error has been detected during the protocol. Shall be cleared by
software.
• 3 – ROLEEXI: Role Exchange Interrupt Flag
Set by hardware when the USB controller has successfully swapped its mode, due to an HNP
negotiation: Host to Device or Device to Host. However the mode selection bit (Host/Device) is
unchanged and must be changed by firmware in order to reach the correct RAM locations and
events bits. Shall be cleared by software.
• 2 – BCERRI: B-Connection Error Interrupt Flag
Set by hardware when an error occur during the B-Connection (i.e. if Peripheral has not con-
nected after 300ms of Vbus delivery request). Shall be clear ed by software.
• 1 – VBERRI: V-Bus Error Interrupt Flag
Set by hardware when a drop on VBus has been detected. Shall be cleared by software.
• 0 – SRPI: SRP Interrupt Flag
Set by hardware when a SRP has been detected. Shall be used in the Host mode only. Shall be
cleared by softw ar e.
Bit 7654 3 210
- - STOI HNPERRI ROLEEXI BCERRI VBERRI SRPI OTGINT
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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21.13 USB Software Operating modes
Depending on the USB operating mode, the software should perform some the following
operations:
Power On the USB interface
• Power-On USB pads regulator
• Configure PLL interface
• Enable PLL and wait PLL lock
• Enable USB interface
• Configure USB interface (USB speed, Endpoints configuration...)
• Wait for USB VBUS information connection
• Attach USB device
Power Off the USB interface
• Detach USB interface
• Disable USB interface
• Disable PLL
• Disable USB pad regulator
Suspending the USB interface
• Clear Suspend Bit
• Freeze USB clock
• Disable PLL
• Be sure to have interrupts enable to exit sleep mode
• Make the MCU enter sleep mode
Resuming the USB interface
•Enable PLL
• Wait PLL lock
• Unfreeze USB clock
• Clear Resume information
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22. USB Device Operating modes
22.1 Introduction The USB device controller supports full speed and low speed data transfers. In addition to the
default control en dpoint, it prov ides six other en dpoint s, which ca n be config ured in co ntrol, bulk,
interrupt or isochronous modes:
• Endpoint 0:programmable size FIFO up to 64 bytes, default control endpoint
• Endpoints 1 programmable size FIFO up to 256 bytes in ping-pong mode.
• Endpoints 2 to 6: programmable size FIFO up to 64 bytes in ping-pong mode.
The controller starts in the “idle” mode. In this mode, the pad consumption is reduced to the
minimum.
22.2 Po wer-on and reset
The next diagram explains the USB device controller main states on power-on:
Figure 22-1. USB device controller states after reset
The reset state of the Device controller is:
• the macro clock is stopped in order to minimi ze the power consumption (FRZCLK set),
• the USB device controller internal state is reset (all the re gisters are reset to their default
value. Note that DETACH is set.)
• the endpoint ba nks are reset
• the D+ or D- pull up are not acti vated (mode Detach)
The D+ or D- pull-up will be activated as soon as the DETACH bit is cleared and VBUS is
present.
The macro is in the ‘Idle’ state after reset with a minimum power consumption and does not
need to have th e PLL activated to enter in this state.
The USB device controller can at any time be reset by clearing USBE (disable USB interface).
22.3 Endpoint reset
An endpoint can be reset at any time by setting in the UERST register the bit corresponding to
the endpoint (EPRSTx). This resets:
• the internal state machine on that endpoint,
• the Rx and Tx banks are cleared and their internal pointers are restored,
Reset
Idle
HW
RESET
USBE=0
<any
other
state>
USBE=0
USBE=1
UID=1
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• the UEINTX, UESTA0X and UESTA1X are restored to their reset value.
The data toggle field remains unchanged.
The other registers remain unchanged.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as
an answer to the CLEAR_FEATURE USB command.
22.4 USB reset When an USB reset is detected on the USB line, the next operations are performed by the
controller:
• all the endpoints are disabled
• the default contro l endpoint remains configured (see Section 22.3, page 267 for more
details).
22.5 Endpoint selection
Prior to any operation performed by the CPU, the endpoint must first be selected. This is done
by setting the EPNUM2:0 bits (UENUM register) with the endpoint number which will be man-
aged by the CPU.
The CPU can then access to the various endpoint registers and data.
22.6 Endpoint activation
The endpoint is maintained under reset as long as the EPEN bit is not set.
The following flow must be respect ed in order to activate an endpoint:
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Figure 22-2. Endpoint activation flow:
As long as the endpoint is not correctly configured (CFGOK cleared), the hardware does not
acknowledge the packets sent b y the host.
CFGOK is will not be sent if the Endpoin t size par ame te r is bigg e r tha n the DPRAM size .
A clear of EPEN acts as an endpoint reset (see Section 22.3, page 267 for more details). It also
performs the next operation:
• The configuration of the endpoint is kept (EPSIZE, EPBK, ALLOC k ept)
• It resets the data toggle field.
• The DPRAM memory associated to the endpoint is still reserved.
See Section 21.7, page 257 for more details about the memory allocation/reorganization.
22.7 Address Setup
The USB device address is set up according to the USB protocol:
• the USB device, after power-up, responds at addre ss 0
• the host sends a SETUP command (SET_ADDRESS(addr)),
• the firmware records that address in UADD, but keep ADDEN cleared,
• the USB device sends an IN command of 0 bytes (IN 0 Zero Length Packet),
• then, the fi rmware can ena ble the USB de vice address b y setting ADDEN. The only acce pted
address by the controller is the one stored in UADD.
ADDEN and UADD shall not be written at the same time.
UADD contains the default address 00h after a power-up or USB reset.
Endpoint
Activation
CFGOK=1
ERROR
No
Yes
Endpoint a ctivated
Activate the endpoint
Select the endpoint
EPEN=1
UENUM
EPNUM=x
Test the correct endpoint
configuration
UECFG1X
ALLOC
EPSIZE
EPBK
Configure:
- the endpoint size
- the bank parametrization
Allocation and reorganization of
the memory is made on-the-fly
UECFG0X
EPDIR
EPTYPE
...
Configure:
- the endpoint direction
- the endpoint type
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ADDEN is cleared by hardware:
• after a powe r- up res et ,
• when an USB reset is received,
• or when the macro is disabled (USBE cleared)
When this bit is cleared, the default device address 00h is used.
22.8 Suspend, Wake-up and Resume
After a period of 3 ms during which the USB line was inactive, the controller switches to the full-
speed mode and triggers (if enabled) the SUSPI (suspend) interrupt. The firmware may then set
the FRZCLK bit.
The CPU can also, depen ding on software architect ure, ente r in the idle mod e to lower again t he
power consumption.
There are two ways to recover from the “Suspend” mode:
• First one is to clear th e FRZCLK bit. This is possible if the CPU is not in the Idle mode.
• Second way, if the CPU is “idle”, is to enable the WAKEUPI interrupt (WAKEUPE set). Then,
as soon as an non-idle signal is seen by the controller, the WAKEUPI interrupt is triggered.
The firmware shall then clear the FRZCLK bit to restart the transfer.
There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the WA KE-
UPI interrupt is triggered as soon a s there are non-idle patterns o n the data lines. Thus, the
WAKEUPI interrupt can occurs eve n if the controller is not in the “suspend” mo de.
When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was alread y set, it is cleared
by hardware.
When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is cleared
by hardware.
22.9 Detach The reset value of the DETACH bit is 1.
It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit.
• Setting DETACH will disconnect the pull-up on the D+ or D- pad (depending on full or low
speed mode selected). Then, clearing DETACH will connect the pull-up on the D+ or D- pad.
Figure 22-3. Detach a device in Full-speed:
EN=1
D +
UVREF
D -
Detach, then
Attach EN=1
D +
UVREF
D -
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22.10 Remote Wake-up
The “Remote Wake-up” (or “upstream resume”) request is the only operation allowed to be sent
by the device on its own initiative. Anyway, to do that, the device should first have received a
DEVICE_REMOTE_WAKEUP request from the host.
• First, the USB cont roller must ha v e detected the “suspend” state of th e line: the remot e wak e-
up can only be sent when a SUSPI flag is set.
• The firmware has then the ability to set RMWKUP to send the “upstream resume” stream.
This will automatically be done by the controller after 5ms of inactivity on the USB line.
• When the controller st arts to send the “upstream resume ”, t he UPRSM I inter rupt is triggered
(if enabled). SUSPI is cleared by hardware.
• RMWKUP is cleared by hardware at the end of the “upstream resume”.
• If the controller detects a good “End Of Resume” signal from the host, an EORSMI interrupt
is triggered (if enabled).
22.11 STALL request
For each endpoint, the STALL management is performed using 2 bits:
– STALLRQ (enable stall request)
– STALLRQC (disable stall request)
– STALLEDI (stall sent interrupt)
To send a STALL ha ndshake at t he next re quest, the ST ALLRQ req uest bit has to be set. All fol-
lowing requests will be handshak’ed with a STALL until the STALLRQC bit is set.
Setting STALLRQC automatically clears the STALLRQ bit. The STALLRQC bit is also immedi-
ately cleared by hardware after being set by software. Thus, the firmware will never read this bit
as set.
Each time the STALL handsha ke is sent , the ST AL LEDI fla g is set by th e USB contro ller and t he
EPINTx interrupt will be triggered (if enabled).
The incoming packets will be discarded (RXOUTI and RWAL will not be set).
The host will then send a command to reset the STALL: the firmware just has to set the STALL-
RQC bit and to reset the endpoint.
22.11.1 Special consideration for Control Endpoints
A SETUP request is always ACK’ed.
If a STALL request is set for a Control Endpoint and if a SETUP request occurs, the SETUP
request has to be ACK’e d and the STALLRQ request a nd STALLEDI sent flags are automati-
cally reset (RXSETUPI set, TXIN cleared, STALLED cleared, TXINI cleared...).
This management simplifies the enumeration process management. If a command is not sup-
ported or contains an error, the firmware set the STALL request flag and can return to the main
task, waiting for the next SETUP request.
This function is compliant with the Chapter 8 test that may send extra status for a
GET_DESCRIPTOR. The firmware sets the STALL request just after receiving the status. All
extra status will be automatically STALL’ed until the next SETUP request.
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22.11.2 STALL handshake and Retry mechanism
The Retry mechanism has prior ity over the STALL h andshake. A STALL handsha ke is sent if the
STALLRQ request bit is set and if there is no retry required.
22.12 CONTROL endpoint management
A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI inter-
rupt is triggered (if enabled). The RXOUTI interrupt is not triggered.
The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints. The firmware shall
thus never use the m on that endpoints. When read, their value is always 0.
CONTROL endpoints are managed by the following bits:
• RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to
acknowledge the packet and to clear the endpoint bank.
• RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to
acknowledge the packet and to clear the endpoint bank.
• TXINI is set when the bank is ready to accept a new IN pack et. It shall be cleared by firmware
to send the packet and to clear the endpoint bank.
22.12.1 Control Write The next figure shows a control write transaction. During the status stage, the controller will not
necessary send a NAK at the first IN token:
• If the firmware knows the exact number of descriptor bytes that must be read, it can then
anticipate on the status stage and send a ZLP for the next IN to ken,
• or it can read the bytes and poll NAKINI, which tells that all the bytes have been sent by the
host, and the transaction is now in the status stage.
SETUP
RXSTPI
RXOUTI
TXINI
USB li ne
HW SW
OUT
HW SW
OUT
HW SW
IN IN
NAK
SW
DATASETUP STATUS
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22.12.2 Control Read The next figure shows a cont rol read transa ction. The USB contr oller has to manag e the simulta-
neous write requests from the CPU and the USB host:
A NAK handshake is always gener ated at the first status stage command.
When the controller detect the status stage, all the data writen by the CPU are erased, and
clearing TXINI has no effects.
The firmware checks if the transmission is complete or if the re ception is complete.
The OUT retry is always ack’ed. This reception:
- set the RXOUTI flag (received OUT data)
- set the TXINI flag (data sent, ready to accept new data)
software algorithm:
set transmit ready
wait (transmit complete OR Receive complete)
if receive complete, clear flag and return
if transmit complete, continue
Once the OUT status stage has been received, the USB controller waits for a SETUP request.
The SETUP request have priorit y over any othe r request and has to be ACK’ed. T his means that
any other flag should be cleared and the fifo reset when a SETUP is received.
WARNING: the byte counter is reset whe n the OUT Zero Length Packet is received. The firm-
ware has to take care of this.
22.13 OUT endpoint management
OUT packets are sent by the host. All the data can be read by the CPU, which acknowledges or
not the bank when it is empty.
22.13.1 Overview The Endpoint must be configured first.
Each time the current b ank is full, the RXOUTI and the FIFOCON bits are set. This trigg ers an
interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing
the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the cur-
rent bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will
SETUP
RXSTPI
RXOUTI
TXINI
USB line
HW SW
IN
HW SW
IN OUT OUT
NAK
SW
SW
HW
Wr Enabl e
HOST
Wr Enabl e
CPU
DATASETUP STATUS
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switch to the next bank. The RXOUTI and FIFOCON bits are then upd ated b y hardw are in a ccor-
dance with the status of the new bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
read data from the bank, and clear ed by hardware when the bank i s empty.
22.13.2 Detailed description
22.13.2.1 The data are read by the CPU, following the next flow:
• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled
(RXOUTE set) and RXOUTI is set. Th e CPU can also poll RXOUTI or FIFOCO N, depen ding
on the software architecture,
• The CPU acknowledges the interrupt by clearing RXOUTI,
• The CPU can read the number of byte (N) in the curren t bank (N=BYCT),
• The CPU can read the data from the current bank (“N” read of UEDATX),
• The CPU can free the ban k by clearing FIFOCON when all the data is read, that is:
– after “N” read of UEDATX,
– as soon as RWAL is cleared by hardware.
If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is
being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already
ready and RXOUTI is set immediately.
OUT DATA
(to bank 0) ACK
RXOUTI
FIFOCON
HW
OUT DATA
(to bank 0) ACK
HW
SW
SW
SW
Example with 1 OUT data bank
read data from CPU
BANK 0
OUT DATA
(to bank 0) ACK
RXOUTI
FIFOCON
HW
OUT DATA
(to bank 1) ACK
SW
SW
Example with 2 OUT data banks
read data from CPU
BANK 0
HW SW
read data from CPU
BANK 0
read data from CPU
BANK 1
NAK
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22.14 IN endpoint management
IN packets are sent by the USB device controller, upon an IN request from the host. All the data
can be written by the CPU, which acknowledge or not the bank when it is full.O verview
The Endpoint must be configured first.
The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt
if the TXINE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO
and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is
composed of multiple banks, this also switches to the next data bank. The TXINI and FIFOCON
bits are automat ically updated by hardware regarding the status of the next bank.
TXINI shall always be clea red before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
write data to the bank, and cleared by hardware when the ba nk is full.
22.14.1 Detailed description
The data are written by the CPU, following the next flow:
• When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled (TXINE set)
and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending the software
architecture choice,
• The CPU acknowledges the interrupt by clearing TXINI,
• The CPU can write the data into the current bank (write in UEDATX),
• The CPU can free the bank by clearing FIFOCON when all the data are written, that is:
IN DATA
(bank 0) ACK
TXINI
FIFOCON
HW
Example with 1 IN data bank
write data from CPU
BANK 0
Example with 2 IN dat a banks
SW
SW SW
SW
IN
IN DATA
(bank 0) ACK
TXINI
FIFOCON write data from CPU
BANK 0 SW
SW SW
SW
IN DATA
(bank 1) ACK
write data from CPU
BANK 0
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
NAK
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• after “N” write into UEDATX
• as soon as RWAL is cleared by hardware.
If the endpoint uses 2 banks, the second one can be read by the HOST while the current is
being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already
ready (free) an d TXINI is set immediately.
22.14.1.1 Abort An “abort” stage can be produced by the host in some situations:
• In a control transaction: ZLP data OUT received during a IN stage,
• In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN
stage on the IN endpoint
•...
The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to per-
form the following operations:
Table 22-1. Abort flow
22.15 Isochronous mode
22.15.1 Underflow An underflow can occur during IN stage if the host attempts to read a bank which is empty. In
this situation, the UNDERFI interrupt is triggered.
An underflow can also occur during OUT stage if the host send a packet while the banks are
already full. Typically, he CPU is not fast enough. The packet is lost.
It is not possible to have underflow error during OUT stage , in the CPU side, since the CPU
should read only if the ba nk is ready to give data (RXOUTI=1 or RWAL=1)
Endpoint
Abort
Abort done
Abort is based on the fact
that no banks are busy,
meaning that nothing has to
be sent.
Disable the TXINI interrupt.
Endpoint
reset
NBUSYBK
=0 Yes
Clear
UEIENX.
TXINE
No
KILLBK=1
KILLBK=1
Yes
Kill the last written
bank.
Wait for the end of the
procedure.
No
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22.15.2 CRC Error A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI interru pt is triggered. This do es not prevent the RXOUTI interru pt
from being triggered.
22.16 Overflow In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if
the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI
interrupt is tr iggered (if enabled). The packet is hacknowledg ed and the RXOUTI interrupt is also
triggered (if enabled). The bank is filled with the first bytes of the packet.
It is not possible to have overflow error during IN stage, in the CPU side, since the CPU should
write only if the bank is ready to access data (TXINI=1 or RWAL=1).
22.17 Interrupts The next figure shows all the interrupts sources:
Figure 22-4. USB Device Controller Interrupt System
There are 2 kind of interrupts: pr ocessing (i.e. the ir generation are part of the norm al processing)
and exception (errors).
Processing inter rupts are generated when:
• VBUS plug-in detection (insert, remove)(VBUSTI)
• Upstream resume(UPRSMI)
• End of resume(EORSMI)
• Wake up(WAKEUPI)
• End of reset (Speed Initialization)(EORSTI)
• Start of frame(SOFI, if FNCERR=0)
• Suspend detected after 3 ms of inactivity(SUSPI)
Exception Interrupts are generated when:
• CRC error in frame number of SOF(SOFI, FNCERR=1)
UPRSMI
UDINT.6 UPRSME
UDIEN.6
EORSMI
UDINT.5 EORSME
UDIEN.5
WAKEUPI
UDINT.4
WAKEUPE
UDIEN.4
EORSTI
UDINT.3 EORSTE
UDIEN.3
SOFI
UDINT.2 SOFE
UDIEN.2
SUSPI
UDINT.0 SUSPE
UDIEN.0
USB Device
Interrupt
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Figure 22-5. USB Device Controller Endpoint Interrupt System
Processing inter rupts are generated when:
• Ready to accept IN data(EPINTx, TXINI=1)
• Received OUT data(EPINTx, RXOUTI=1)
• Received SETUP(EPINTx, RXSTPI=1)
Exception Interrupts are generated when:
• Stalled packet(EPINTx, STALLEDI=1)
• CRC error on OUT in isochronous mode(EPINTx, STALLEDI=1)
• Overflow in isochronous mode(EPINTx, OVERFI=1)
• Underflow in isochronous mode(EPINTx, UNDERFI=1)
• NAK IN sent(EPINTx, NAKINI=1)
• NAK OUT sent(EPINTx, NAKOUTI=1)
22.18 Registers
22.18.1 USB devic e general registers
EPINT
UEINT.X
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
Endpoint 4
Endpoint 5
Endpoint Interrupt
Endpoint 6
FLERRE
UEIENX.7
OVERFI
UESTAX.6
UNDERFI
UESTAX.5
NAKINI
UEINTX.6 NAKINE
UEIENX.6
NAKOUTI
UEINTX.4 TXSTPE
UEIENX.4
RXSTPI
UEINTX.3 TXOUTE
UEIENX.3
RXOUTI
UEINTX.2 RXOUTE
UEIENX.2
STALLEDI
UEINTX.1
STALLEDE
UEIENX.1
TXINI
UEINTX.0
TXINE
UEIENX.0
Bit 765432 1 0
-----LSM RMWKUP DETACH UDCON
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 1
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• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2 - LSM - USB Device Low Speed Mode Selection
When configured USB is configured in device mode, this bit allows to select the USB the USB
Low Speed or Full Sp ee d Mo d .
Clear to select full speed mode (D+ internal pull-up will be activate with the ATTACH bit will be
set) .
Set to select low speed mode (D- internal pu ll-up will be activate with the ATTACH bit will be
set). This bit has no effect when the USB interface is configured in HOST mode.
• 1- RMWKUP - Remote Wake-up Bit
Set to send an “upstream-resume” to the host for a remote wake-up (the SUSPI bit must be set).
Cleared by hardware when signalling finished. Clearing by software has no effect.
See Section 22.10, page 271 for more details.
• 0 - DETACH - Detach Bit
Set to physically detach de device (disconnect internal pull-up on D+ or D-).
Clear to reconnect th e device. See Section 22.9, page 270 for more details.
• 7 - Reserved
The value read from this bits is always 0. Do not set this bit.
• 6 - UPRSMI - Upstream Resume Interrupt Flag
Set by hardware when the USB controller is sending a resume signal called “Upstream
Resume”. This triggers an USB interrupt if UPRSME is set.
Shall be cleared by software (USB clocks must be enabled before). Setting by software has no
effect.
• 5 - EORSMI - End Of Resume Interrupt Flag
Set by hardware when the USB controller detects a good “End Of Resume” signal initiated by
the host. This triggers an USB interrupt if EORSME is set.
Shall be cleared by software. Setting by software has no effect.
• 4 - WAKEUPI - Wake-up CPU Interrupt Flag
Set by hardware when the USB controller is re-activated by a filtered non-idle signal from the
lines (not by an upstream resume). This trigger s an interrupt if WAKEUPE is set. This interrupt
should be enable only to wake up the CPU core from powe r down mode.
Shall be cleared by software (USB clock inputs must be enable d before). Setting by software
has no effect.
Bit 76543210
-UPRSMI EORSMI WAKEUPI EORSTI SOFI - SUSPI UDINT
Read/Write
Initial Value00000000
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See Section 22.8, page 270 for more details.
• 3 - EORSTI - End Of Reset Interrupt Flag
Set by hardware when an “End O f Reset” has been d etected b y the USB cont roller. T his trigge rs
an USB interrupt if EORSTE is set.
Shall be cleared by software. Setting by software has no effect.
• 2 - SOFI - Start Of Frame Interrupt Flag
Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected (every 1 ms).
This triggers an USB interrupt if SOFE is set..
• 1 - Reserved
The value read from this bits is always 0. Do not set this bit
• 0 - SUSPI - Suspend Interrupt Flag
Set by hardware when an USB “Suspend” ‘idle bus for 3 frame periods: a J state for 3 ms) is
detected. This triggers an USB interrupt if SUSPE is set.
Shall be cleared by software. Setting by software has no effect.
See Section 22.8, page 270 for more details.
The interrupt bits are set even if their corresponding ‘Enable’ bits is not set.
• 7 - Reserved
The value read from this bits is always 0. Do not set this bit.
• 6 - UPRSME - Upstream Resume Interrupt Enable Bit
Set to enable the UPRSMI interrupt.
Clear to disable the UPRSMI interrupt.
• 5 - EORSME - End Of Resume Interrupt Enable Bit
Set to enable the EORSMI interrupt.
Clear to disable the EORSMI interrupt.
• 4 - WAKEUPE - Wake-up CPU Interrupt Enable Bit
Set to enable the WAKEUPI interrupt. For correct interrupt handle execution, this interrupt
should be enable only befor e entering power-down mode.
Clear to disable the WAKEUPI interrupt.
• 3 - EORSTE - End Of Reset Interrupt Enable Bit
Set to enable the EORSTI interrupt. This bit is set after a reset.
Clear to disable the EORSTI interrupt.
Bit 76543210
- UPRSME EORSME WAKEUPE EORSTE SOFE - SUSPE UDIEN
Read/Write
Initial Value 0 0 0 0 0 0 0 0
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• 2 - SOFE - Start Of Frame Interrupt Enable Bit
Set to enable the SOFI interrupt.
Clear to disable the SO FI interrupt.
• 1 - Reserved
The value read from this bits is always 0. Do not set this bit
• 0 - SUSPE - Suspend Interrupt Enable Bit
Set to enable the SUSPI interrupt.
Clear to disable the SUSPI interrupt.
• 7 - ADDEN - Address Enable Bit
Set to activate the UADD (USB address).
Cleared by hardware. Clearing by software has no effect.
See Section 22.7, page 269 for more details.
• 6-0 - U ADD6:0 - USB Address Bits
Load by software to configure the device address.
.
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - FNUM10: 8 - Fra m e Nu mbe r Uppe r Value
Set by hardware. These bits are the 3 MSB of the 11-bits Frame Number information. They are
provided in the last received SOF packet. FNUM is updated if a corrupted SOF is received.
• Frame Number Lower Value
Set by hardware. These bits are the 8 LSB of the 11-bits Fra me Number information.
Bit 76543210
ADDEN UADD6:0 UDADDR
Read/Write W R/W R/W R/W R/W R/W R/W R/W
Initial Val-
ue 00000000
Bit 765432 1 0
----- FNUM10:8 UDFNUMH
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
FNUM7:0 UDFNUML
Read/WriteRRRRRRRR
Initial Value00000000
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• 7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - FNCERR -Frame Number CRC Error Flag
Set by hardware when a corrupted Frame Number in start of frame packet is received.
This bit and the SOFI interrupt are updated at the same time.
• 3-0 - Reserved
The value read from these bits is always 0. Do not set these bits.
22.18.2 USB device endpoint registers
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - EPNUM2:0 Endpoint Number Bits
Load by software to sele ct the numbe r of the endpo int which sh all be accessed by the CPU. See
Section 22.5, page 268 for more details.
EPNUM = 111b is forbidden.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - EPRST6:0 - Endpoint FIFO Reset Bits
Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or
when an USB bus reset has been received. See Section 22.3, page 267 for more information
Then, clear by software to complete the reset operation and start using the endpoint.
Bit 76543210
- - - FNCERR - - - - UDMFN
Read/W
rite R
Initial
Value 00000000
Bit 76543210
- - - - - EPNUM2:0 UENUM
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
- EPRST6 EPRST5 EPRST4 EPRST3 EPRST2 EPRST1 EPRST0 UERST
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 - STALLRQ - STALL Request Handshake Bit
Set to request a STALL an swer to the host for the next handshake.
Cleared by hardware when a new SETUP is received. Clearing by software has no effect.
See Section 22.11, page 271 for more details.
• 4 - STALLRQC - STALL Request Clear Handshake Bit
Set to disable the STALL handshake mechanism.
Cleared by hardware immediately after the set. Clearing by software has no effect.
See Section 22.11, page 271 for more details.
3
• RSTDT - Reset Data Toggle Bit
Set to automatically clear the data toggle sequence:
For OUT endpoint: the next received packet will have the data toggle 0.
For IN endpoint: the next packet to be sent will have the data toggle 0.
Cleared by hard ware instantaneously. T he firmware does not have to wait that the bit is cleared.
Clearing by software has no effect.
• 2 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 - EPEN - Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall always be
enabled after a hardware or USB reset and participate in the device configuration.
Clear this bit to disable the endpoint. See Section 22.6, page 268 for more details.
• 7-6 - EPTYPE1:0 - Endpoint Type Bits
Set this bit according to the endpoint configuration:
Bit 76543210
- - STALLRQ STALLRQC RSTDT - - EPEN UECONX
Read/Write R R W W W R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
EPTYPE1:0 - - - - - EPDIR UECFG0X
Read/WriteR/WR/WRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0
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00b: Control10b: Bulk
01b: Isochronous11b: Interrupt
• 5-4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-2 - Reserved for test purpo s e
The value read from these bits is always 0. Do not set these bits.
• 1 - Reserved
The value read from this bits is always 0. Do not set this bit.
• 0 - EPDIR - Endpoint Direction Bit
Set to configure an IN direction for bulk, interrupt or isochronous endpoints.
Clear to configure an OUT direction for bulk, interrupt, isochronous or control endpoints.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-4 - EPSIZE2:0 - Endpoint Size Bits
Set this bit according to the endpoint size:
000b: 8 bytes 100b: 128 bytes (only for endpoint 1)
001b: 16 bytes 101b : 256 bytes (only for endpoint 1)
010b: 32 bytes 110b : Reserved. Do not use this configuration.
011b: 64 bytes 111b : Reserved. Do not use this configuration.
• 3-2 - EPBK1:0 - Endpoint Bank Bits
Set this field accordin g to the endpoint size:
00b: One bank
01b: Double bank
1xb: Reserved . Do no t us e this conf igu r atio n .
• 1 - ALLOC - Endpoint Allocation Bit
Set this bit to allocate the endpoint memory.
Clear to free the endpoint memory.
See Section 22.6, page 268 for more details.
• 0 - Reserved
The value read from these bits is always 0. Do not set these bits.
Bit 7 6 5 4 3 2 1 0
- EPSIZE2:0 EPBK1:0 ALLOC - UECFG1X
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial Value 0 0 0 0 0 0 0 0
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• 7 - CFGOK - Configuration Status Flag
Set by hardware when the endpoint X size parameter (EPSIZE) and the bank parametrization
(EPBK) are correct compared to the max FIFO capacity and the max number of allowed bank.
This bit is updated when th e bit ALLOC is set.
If this bit is cleared, the user should reprogram the UECFG1X register with correct EPSIZE and
EPBK values.
• 6 - OVERFI - Overflow Error Interrupt Flag
Set by hardware when an overflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if ena bled).
See Section 22.15, page 276 for more details.
Shall be cleared by software. Setting by software has no effect.
• 5 - UNDERFI - Flow Error Interrupt Flag
Set by hardware when an underflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if ena bled).
See Section 22.15, page 276 for more details.
Shall be cleared by software. Setting by software has no effect.
• 4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-2 - DTSEQ1:0 - Data Toggle Sequen ci n g Flag
Set by hardware to indicate the PID data of the current bank:
00b Data0
01b Data1
1xb Reserved.
For OUT transfer, this value indicates the last data toggle received on the current bank.
For IN transfer, it indicates the Toggle that will be used for the next packet to be sent. This is not
relative to the current bank.
• 1-0 - NBUSYBK1:0 - Busy Bank Flag
Set by hardware to indicate the number of busy bank.
For IN endpoint, it indicates the number of busy bank(s), filled by the user , ready for IN transfer.
For OUT endpoin t, it indicates the number of bu sy bank(s) filled by OUT transactio n from the
host.
00b All banks are free
Bit 76543210
CFGOK OVERFI UNDERFI - DTSEQ1:0 NBUSYBK1:0 UESTA0X
Read/Write R R/W R/W R/W R R R R
Initial Value 0 0 0 0 0 0 0 0
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01b 1 busy bank
10b 2 busy banks
11b Reserved.
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2 - CTRLDIR - Control Direction (Flag, and bit for debug purpose)
Set by hardware after a SETUP packet, and give s the direction of the following packet:
- 1 for IN endpoint
- 0 for OUT endpoint.
Can not be set or clea re d by softw ar e.
• 1-0 - CURRBK1:0 - Current Bank (all endpoints except Control endpoint) Flag
Set by hardware to indi ca te th e nu m be r of the cu rr en t ba nk :
00b Bank0
01b Bank1
1xb Reserved.
Can not be set or clea re d by softw ar e.
• 7 - FIFOCON - FIFO Control Bit
For OUT and SETUP Endpoint:
Set by hardware when a new OUT message is stored in the current bank, at the same time than
RXOUT or RXSTP.
Clear to free the current ba nk and to switch to the following bank. Sett ing by software has no
effect.
For IN Endpoint:
Set by hardware when the current bank is free, at the same time than TXIN.
Clear to send the FIFO data and to switch the bank. Setting by softwar e has no effect.
• 6 - NAKINI - NAK IN Received Interrupt Flag
Bit 76543210
- - - - - CTRLDIR CURRBK1:0 UESTA1X
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLEDI TXINI UEINTX
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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Set by hardware when a NAK handshake h as been sent in response of a IN request from the
host. This triggers an USB interrupt if NAKINE is sent.
Shall be cleared by software. Setting by software has no effect.
• 5 - R WAL - Read/Write Allowed Flag
Set by hardware to signal:
- for an IN endpoint : the current bank is not full i.e. the firmware can push data int o the FIFO,
- for an OUT endpoint: the current bank is not empty, i.e. the firmware can read data from the
FIFO.
The bit is never set if STALLRQ is set, or in case of error.
Cleared by hardware otherwise.
This bit shall not be used for the control endpoint.
• 4 - NAKOUTI - NAK OUT Received Interrupt Flag
Set by hardware when a NAK handshake has been sen t in response of a OUT/PING reque st
from the host. This triggers an USB interrupt if NAKOUTE is sent.
Shall be cleared by software. Setting by software has no effect.
• 3 - RXSTPI - Received SETUP Interrupt Flag
Set by hardware to signal that the current bank contains a new valid SETUP packet. An inter-
rupt (EPINTx) is triggered (if enabled).
Shall be cleared by softw ar e to han ds ha ke the interr up t. Set tin g by so ftware has no effect.
This bit is inactive (cleared) if t he endpoint is an IN endpoint.
• 2 - RXOUTI / KILLBK - Received OUT Data Interrupt Flag
Set by hardware to signal that the current bank contains a new packet. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by softw ar e to han ds ha ke the interr up t. Set tin g by so ftware has no effect.
Kill Bank IN Bit
Set this bit to kill the last written bank.
Cleared by hardware when the bank is killed. Clearing by software has no effect.
See page 276 for more details on the Abort.
• 1 - STALLEDI - STALLEDI Interrupt Flag
Set by hardware to sign al that a STALL h andshake has been sent , or th at a CRC e rror has b een
detected in a OUT isochronous endpoint.
Shall be cleared by software. Setting by software has no effect.
• 0 - TXINI - Transmit te r Ready Interrupt Flag
Set by hardware to signal that the current bank is free and can be filled. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by softw ar e to han ds ha ke the interr up t. Set tin g by so ftware has no effect.
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This bit is inactive (cleared) if t he endpoint is an OUT endpoint.
• 7 - FLERRE - Flow Error Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
• 6 - NAKINE - NAK IN Interrupt Enable Bit
Set to enable an endpoint interrupt (EPINTx) when NAKINI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set.
• 5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - NAKOUTE - NAK OUT Interrupt Enable Bit
Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set.
• 3 - RXSTPE - Received SETUP Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent.
• 2 - RXOUTE - Received OUT Data Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when RXOUTI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXOUTI is sent.
• 1 - STALLEDE - Stalled Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when STALLEDI is sent.
Clear to disable an endpoint int errupt (EPINTx) when STALLEDI is sent.
• 0 - TXINE - Tran s m it te r Re ady Interru p t Ena ble Fl ag
Set to enable an endpoint interrupt (EPINTx) when TXINI is sent.
Clear to disable an endpoint interrupt (EPINTx) when TXINI is sent.
• 7-0 - DAT7:0 -Data Bits
Set by the software to read/write a byte from/to the endpoint FIFO selected by EPNUM.
Bit 76543210
FLERRE NAKINE - NAKOUTE RXSTPE RXOUTE STALLEDE TXINE UEIENX
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
DAT D7 DAT D6 DAT D5 DAT D4 DAT D3 DAT D2 DAT D1 DAT D0 UEDATX
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - BYCT10:8 - Byte coun t (hig h ) Bit s
Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. T he LSB part is
provided by the UEBCLX register.
• 7-0 - BYCT7:0 - Byte Count (low) Bits
Set by the hardware. BYCT10:0 is:
- (for IN endpoint) increased after each writing into the endpoint and decremented after each
byte sent,
- (for OUT endpoint) increased after each byte sent by the host, and decremented after each
byte read by the software.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - EPINT6:0 - Endpoint Interrupts Bits
Set by hardw are when an inte rrupt is trig gered by the U EINTX re gister an d if the co rrespo nding
endpoint interrupt enable bit is set.
Cleared by hardware when the interrupt source is served.
Bit 765432 1 0
- - - - - BYCT D10 BYCT D9 BYCT D8 UEBCHX
Read/WriteRRRRRR R R
Initial Value000000 0 0
Bit 76543210
BYCT D7 BYCT D6 BYCT D5 BYCT D4 BYCT D3 BYCT D2 BYCT D1 BYCT D0 UEBCLX
Read/WriteRRRRRRRR
Initial Value00000000
Bit 76543210
- EPINT D6 EPINT D5 EPINT D4 EPINT D3 EPINT D2 EPINT D1 EPINT D0 UEINT
Read/WriteRRRRRRRR
Initial Value00000000
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23. USB Host Operating Modes
This mode is available only on AT90USB647/1287 products.
23.1 Pipe description
For the USB Host controller, the term of Pip e is used instead of Endpoint for the USB Device
controller. A Host Pipe corr esponds to a De vice End point, as describ ed in the USB specifica tion:
Figure 23-1. Pipes and Endpoints in a USB system
In the USB Host controller, a Pipe will be associated to a Device Endpoint, considering the
Device Configuration Descriptors.
23.2 Detach The reset value of the DETACH bit is 1. Thus, the firmware has the responsibility of clearing this
bit before switching to the Host mode (HOST set).
23.3 Po wer-on and Reset
The next diagram explains the USB host controller main states on power-o n:
Figure 23-2. USB host controller states after reset
Host
Ready
Host
Idle
Device
disconnection <any
other
state>
Device
connection
Clock stopped
Macro off
Device
disconnection
Host
Suspend
SOFE=1
SOFE=0
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USB host controller state after an hardwar e reset is ‘Reset’. When the USB controller is ena bled
and the USB Host controller is selected, the USB controller is in ‘Idle’ state. In this state, the
USB Host controller waits for the Device connection, with a minimum power consumption.
The USB Pad should be in Idle mode. The macro does not need to have the PLL activated to
enter in ‘Host Ready’ state.
The Host controller ente rs in Suspend state when th e USB bus is in Suspend stat e, i.e. when the
Host controller doesn’t generate the Start of Frame. In this state, the USB consumption is mini-
mum. The Host co ntro ller exit s to th e Su sp end sta te when start ing t o g enera te t he SOF o ver t he
USB line.
23.4 Device Detection
A Device is detected by the USB controller when the USB bus if different from D+ and D- low. In
other words, when the USB Host Controller detects the Device pull-up on the D+ lin e. To enable
this detection, the Host Controller has to provide the Vbus power supply to the Device.
The Device Disconnection is detect ed by th e USB Host controller whe n the USB Idle correspond
to D+ and D- low on the USB line.
23.5 Pipe SelectionPrior to any operation performed by the CPU, the Pipe must first be selected. This is done by
setting PNUM2:0 bits (UPNUM register) with the Pipe n umber which will be managed by the
CPU.
The CPU can then access to the various Pipe registers and data.
23.6 Pipe Configuration
The following flow must be respected in order to activate a Pipe:
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Figure 23-3. Pipe activation flow:
Once the Pipe is activated (EPEN set) and, the hardware is ready to send requests to the
Device.
When configured (C FGOK = 1), only t he Pipe T oken (PTOKEN) and t he polling inter val for Inte r-
rupt pipe can be modified.
A Control type pipe supports only 1 bank. Any other value will lead to a configuration error
(CFGOK = 0).
A clear of PEN will reset the configuration of the Pipe. All the corresponding Pipe registers are
reset to there reset values. Please refers to the Memory Management chapter for more details.
Note: The firmware has to configure the Default Control Pipe with the following parameters:
• Type: Control
• Token: SETUP
• Data bank: 1
• Size: 64 Bytes
The firmware asks for 8 bytes of the Device Descriptor sending a GET_DESCRIPTOR request.
These bytes cont ains the MaxPacketSize of the Device de fault control endpoint and the firm -
ware re-configures the size of the Default Control Pipe with this size parameter.
Pipe
Activation
UPCONX
PENABLE=1
UPCFG0X
PTYPE
PTOKEN
PEPNUM
CFGOK=1
ERROR
No
Yes
UPCFG2X
INTFRQ
(i nterrupt only)
Pipe activated
and freezed
UPCFG1X
PSIZE
PBK
CFGMEM
Enable the pipe
Select the Pi pe type:
* Type (Control, Bulk, Interrupt
)
* Token (IN, OUT, SETUP)
* E nd point number
Configure the Pipe memory:
* P ipe size
* Number of banks
Configure the pol ling interval
for Interrupt pipe
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23.7 USB Reset The USB controller sends a USB Reset when the firmware set the RESET bit. The RSTI bit is
set by hardware when the USB Reset has been sent. This triggers an interrupt if the RSTE has
been set.
When a USB Reset has been sent, all the Pipe configuration and the memory allocation are
reset. The General Host interrupt enable register is left unchanged.
If the bus was previously in suspend mode (SOFEN = 0), the USB controller automatically
switches to the resume mode (HWUPI is set) and the SOFEN bit is set by hardware in order to
generate SOF immediately after the USB Reset.
23.8 Address Setup
Once the Device has answer to the first Host requests with the default address (0), the Host
assigns a new address to the device. The Host controller has to send a USB reset to the device
and perform a SET ADDRESS control request, with the new address to be used by the Device.
This control request ended, the firmware write the new address into the UHADDR register. All
following requests, on every Pipes, will be performed using this new address.
When the H ost con trolle r send a USB rese t, th e UHAD DR regis ter is reset by ha rdwa re an d th e
following Host requests will be performed using the default address (0).
23.9 Remote Wake-Up detection
The Host Controller enters in Suspend mode when clearing the SOFEN bit. No more Start Of
Frame is sent on the USB bus and the USB Device enters in Suspend mode 3ms later.
The Device awak es the Host Controller by sending an Upstream Resume (Remote Wake-U p
feature). The Host Controller detects a non-idle state on the USB bus and set the HWUPI bit. If
the non-Idle correspond to an Upstream Resume (K state), the RXRSMI bit is set by hardware.
The firmware has to generate a downstream resume within 1ms and for at least 20ms by setting
the RESUME bit.
Once the downstrea m Resume has been ge nerated, the SOFEN bi t is autom atically set by har d-
ware in order to generate SOF immediately after the USB resume.
23.10 USB Pipe Reset
The firmware can reset a Pipe using the pipe reset register. The configuration of the pipe and
the data toggle remains unchanged. Only the bank management and the status bits are reset to
their initial values.
To completely reset a Pipe, the firmware has to disable and then enable the pipe.
23.11 Pipe Data Access
In order to read or to write into the Pipe Fifo, the CPU selects the Pipe number with the UPNUM
register and performs read or write action on the UPDATX register.
Host
Ready
Host
Suspend
SOFE=1
or HWUP=1
SOFE=0
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23.12 Control Pipe management
A Control transacti on is composed of 3 phases:
• SETUP
• Data (IN or OUT)
• Status (OUT or IN)
The firmware has t o change the Token for each phase.
The initial data toggle is set for the corresponding token (ONLY for Control Pipe):
• SETUP: Data0
• OUT: Data1
• IN: Data1 (expected data toggle)
23.13 OUT Pipe management
The Pipe must be config ured and not frozen first.
Note: if the firmware decides to switch to suspend mode (clear SOFEN) even if a bank is ready
to be sent, the USB controller will automatically exit from Suspend mode and the bank will be
sent.
The TXOUT bit is set by hardware when the current bank becomes free. This triggers an inter-
rupt if the TXOUTE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the
FIFO and clears the FIFOCON bit to allow the USB controller to send the data.
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If the OUT Pipe is comp osed of multiple banks, this also switches to the nex t data bank. The
TXOUT and FIFOCON bits are automatically updated by hardware regarding the status of the
next bank.
23.14 IN Pipe management
The Pipe must be configured first.
When the Host requires data from the device, the firmware has to determine first the IN mode to
use using the INMODE bit:
• INMODE = 0. The INRQX register is taken in account. The Host controller will perform
(INRQX+1) IN requests on the selected Pipe before freezing the Pipe. This mode avoids to
have extra IN requests on a Pipe.
• INMODE = 1. The USB controller will perf orm infinite IN request until the firmware freeze s the
Pipe.
The IN request generation will start when the firmware clear the PFREEZE bit.
OUT DATA
(bank 0) ACK
TXOUT
FIFOCON
HW
Example with 1 OUT data bank
write data from CPU
BANK 0
Example with 2 OUT data banks
SW
SW SW
SW
OUT
OUT DATA
(bank 0) ACK
TXOUT
FIFOCON write data from CPU
BANK 0
SW
SW SW
SW
OUT DATA
(bank 1) ACK
write data from CPU
BANK 0
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
Example with 2 OUT data banks
OUT DATA
(bank 0) ACK
TXOUT
FIFOCON write data from CPU
BANK 0
SW
SW SW
SW
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
OUT DATA
(bank 1) ACK
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Each time the curre nt bank is full, t he RXIN an d the FIFOCON bits are set. This trigg ers an inte r-
rupt if the RXINE bit is set. The firmware can acknowledge the USB interrupt by clearing the
RXIN bit. The Firmware read the data and clear the FIFOCON bit in order to free the current
bank. If the IN Pipe is composed of multiple banks, clearing the FIFOCON bit will switch to the
next bank. The RXIN and FIFOCON bits are then updated by hardware in accordance with the
status of the new bank.
23.14.1 CRC Error (isochronous only)
A CRC error can occur during IN stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not prevent the RXINI
interrupt from being triggered.
23.15 Interrupt system
IN DATA
(to bank 0) ACK
RXIN
FIFOCON
HW
IN DATA
(to bank 0) ACK
HW
SW
SW
SW
Exampl e with 1 IN dat a ban k
read data from CPU
BANK 0
IN DATA
(to bank 0) ACK
RXIN
FIFOCON
HW
IN DATA
(to bank 1) ACK
SW
SW
Example with 2 IN da t a banks
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 0
read data from CPU
BANK 1
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Figure 23-4. USB Host Controller Interrupt System
Figure 23-5. USB Device Controller Pipe Interrupt System
23.16 Registers
HWUPE
UHIEN.6
HWUPI
UHINT.6
HSOFI
UHINT.5 HSOFE
UHIEN.5
RXRSMI
UHINT.4 RXRSME
UHIEN.4
RSMEDI
UHINT.3 RSMEDE
UHIEN.3
RSTI
UHINT.2 RSTE
UHIEN.2
DDISCI
UHINT.1 DDISCE
UHIEN.1
DCONNI
UHINT.0 DCONNE
UHIEN.0
USB Host
Interrupt
FLERRE
UPIEN.7
UNDERFI
UPSTAX.5
OVERFI
UPSTAX.6
NAKEDI
UPINTX.6 NAKEDE
UPIEN.6
PERRI
UPINTX.4 PERRE
UPIEN.4
TXSTPI
UPINTX.3 TXSTPE
UPIEN.3
TXOUTI
UPINTX.2 TXOUTE
UPIEN.2
RXSTALLI
UPINTX.1
RXSTALLE
UPIEN.1
RXINI
UPINTX.0 RXINE
UPIEN.0
FLERRE
UPIEN.7
PIPE 0
PIPE 1
PIPE 2
PIPE 3
PIPE 4
PIPE 5
Pipe Interrupt
PIPE 6
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23.16.1 General USB Host registers
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2 - RESUME - Send USB Resume
Set this bit to generate a USB Resume on the USB bus.
Cleared by hardwar e when t h e USB Resume ha s bee n se nt. Cle ar ing by sof tware ha s n o ef fe ct .
This bit should be set only when the start of frame generation is enable (SOFEN bit se t).
• 1 - RESET - Send USB Reset
Set this bit to generate a USB Reset on the USB bus.
Cleared by hardware when the USB Reset has been sent. Clearing by software has no effect.
Refer to the USB reset section for more details.
• 0 - SOFEN - Start Of Frame Generation Enable
Set this bit to generate SOF on the USB bus in full speed mode and keep-alive in low speed
mode.
Clear this bit to disable the SOF generation and to leave the USB bus in Idle state.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
•6 - HWUPI
Host Wake-Up Interrupt
Set by hardware when a non-idle state is detected on the USB bus.This interrupt should be
enable only to wake up the CPU core from power down mode.
Shall be clear by software to acknowledge the interrupt. Setting by software has no effect.
• 5 - HSOFI - Host Start Of Frame Interrupt
Set by hardware when a SOF is issued by the Host controller. This triggers a USB interrupt
when HSOFE is set. When using the host controller in low speed mode, this bit is also set when
a keep-alive is sent.
Shall be cleared by software to acknowledge the interrupt. Setting by software has no effect.
Bit 76543210
-----RESUME RESET SOFEN UHCON
Read/Write RRRRRR/WR/WR/W
Initial Value00000 000
Bit 76543210
-HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI UHINT
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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• 4 - RXRSMI - Upstream Resume Received Interrupt
Set by hardware when an Upstream Resume has been received from the Device.
Shall be cleared by software. Setting by software has no effect.
• 3 - RSMEDI - Downstream Resume Sent Interrupt
Set by hardware when a Downstream Resume has been sent to the Device.
Shall be cleared by software. Setting by software has no effect.
• 2 - RSTI - USB Reset Sent Interrupt
Set by hardware whe n a USB Res et has be en sen t to th e De vice .
Shall be cleared by software. Setting by software has no effect.
• 1 - DDISCI Device Disconnection Interrupt
Set by hardware when the device has been removed from the USB bus.
Shall be cleared by software. Setting by software has no effect.
• 0 - DCONNI - Device Connection Interrupt
Set by hardware when a new device has been connected to the USB bus.
Shall be cleared by software. Setting by software has no effect.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6 - HWUPE - Host Wake-Up Interrupt Enable
Set this bit to ena ble HWUP inte rrupt .For cor rect inte rrupt h andle e xecution, this inte rrupt sh ould
be enable only before entering power-down mode.
Clear this bit to disable HWUP interrupt.
• 5 - HSOFE - Host Start Of frame Inte rru p t En able
Set this bit to enable HSOF interrupt.
Clear this bit to disable HSOF interrupt.
• 4 - RXRSME -Upstream Resume Received Interrupt Enable
Set this bit to enable the RXRSMI interrupt.
Clear this bit to disable the RXRSMI interrupt.
• 3 - RSMEDE - Downstream Resume Sent Interrupt Enable
Set this bit to enable the RSMEDI interrupt.
Clear this bit to disable the RSMEDI interrupt.
Bit 76543210
HWUPE HSOFE RXRSME RSMEDE RSTE DDISCE DCONNE UHIEN
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• 2 - RSTE - USB Reset Sent Interrupt Enable
Set this bit to enable the RSTI interrupt.
Clear this bit to disable the RSTI interrupt.
• 1 - DDISCE - Device Disconnection Interrupt Enable
Set this bit to enable the DDISCI interrupt.
Clear this bit to disable the DDISCI interrupt.
• 0 - DCONNE - Device Connection Interrupt Enable
Set this bit to enable the DCONNI interrupt.
Clear this bit to disable the DCONNI interrupt.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - HADDR6:0 - USB Host Address
These bits contain the address of the USB Device.
• 7-4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-0 - FNUM10: 8 - Fra me Nu mbe r
The value contained in this register is the current SOF number.
This value can be modif ied by software.
• 7-0 - FNUM7:0 - Frame Number
The value contained in this register is the current SOF number.
This value can be modif ied by software.
Bit 76543210
HADDR6 HADDR5 HADDR4 HADDR3 HADDR2 HADDR1 HADDR0 HADDR6 UHADDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543 2 1 0
- - - - - FNUM10 FNUM9 FNUM8 UHFNUMH
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0 UHFNUML
Read/WriteRRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
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• 7-0 - FLEN7:0 - Frame Length
The value contained the data frame length transmited.
23.16.2 USB Host Pipe registers
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - PNUM2:0 - Pipe Number
Select the pipe using th is regist er . The USB Host regist ers ende d by a X corr espond t hen to this
number.
This number is used for the USB controller following the value of the PNUMD bit.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6 - P6RST - Pipe 6 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 6.
• 5 - P5RST - Pipe 5 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 5.
• 4 - P4RST - Pipe 4 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 4.
• 3 - P3RST - Pipe 3 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 3.
• 2 - P2RST - Pipe 2 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 2.
Bit 76543210
FLEN7 FLEN6 FLEN5 FLEN4 FLEN3 FLEN2 FLEN1 FLEN0 UHFLEN
Read/WriteRRRRRRRR
Initial Value00000000
Bit 765432 1 0
PNUM2 PNUM1 PNUM0 UPNUM
Read/Write RW RW RW
Initial Value000000 0 0
Bit 76543210
- P6RST P5RST P4RST P3RST P2RST P1RST P0RST UPRST
Read/Write RW RW RW RW RW RW RW
Initial Value00000000
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• 1 - P1RST - Pipe 1 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 1.
• 0 - P0RST - Pipe 0 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 0.
• 7 - Reserved
The value read from this bit is always 0. Do not set this bit.
• 6 - PFREEZE - Pipe Freeze
Set this bit to Freeze the Pipe requests generation.
Clear this bit to enable the Pipe request generation.
This bit is set by hardware when:
- the pipe is not configur ed
- a STALL handshake has been received on this Pipe
- An error occurs on the Pipe (UP INT X. PERRI = 1)
- (INRQ+1) In requests have been processed
This bit is set at 1 by hardware after a Pipe reset or a Pipe enable.
• 5 - INMODE - IN Request mode
Set this bit to allow the USB controller to perform infinite IN requests when the Pipe is not frozen.
Clear this bit to perform a pre-defined number of IN requests. This number is stored in the UIN-
RQX register.
• 4 - Reserved
The value read from this bit is always 0. Do not set this bit.
• 3 - RSTDT - Reset Data Toggle
Set this bit to reset the Data Toggle to its initial value for the current Pipe.
Cleared by hardwa re w he n proceed. Clearin g by soft war e ha s no effe ct .
• 2 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 - PEN - Pipe Enable
Set to enable the Pipe.
Bit 76543210
- PFREEZE INMODE - RSTDT - - PEN UPCONX
Read/Write RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
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Clear to disable and reset the Pipe.
• 7-6 - PTYPE1:0 - Pipe Type
Select the type of the Pipe:
- 00: Control
- 01: Isochronous
- 10: Bulk
- 11: Interrup t
• 5-4 - PTOKEN1:0 - Pipe Token
Select the Token to ass oc i at e to th e Pipe
- 00: SETUP
- 01: IN
- 10: OUT
- 11: reserved
• 3-0 - PEPNUM3:0 - Pipe Endpoint Number
Set this field according to t he Pipe co nf igura tion. Set t he numbe r o f th e En dpoint t arget ed by t he
Pipe. This value is from 0 and 15.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-4 - PSIZE2:0 - Pipe Size
Select the size of the Pipe:
- 000: 8 - 100: 128 (only for endpoint 1)
- 001: 16 - 101: 256 (only for endpoint 1)
- 010: 32 - 110: Reserved. Do not use this configuration.
- 011: 64 - 111: Reserved. Do not use this configuration.
• 3-2 - PBK1:0 - Pipe Bank
Select the number of bank to declare for the curr ent Pipe.
Bit 76543210
PTYPE1 PTYPE0 PTOKEN1 PTOKEN0 PEPNUM3 PEPNUM2 PEPNUM1 PEPNUM0 UPCFG0X
Read/Write RW RW RW RW RW RW RW RW
Initial Value00000000
Bit 7 6 5 4 3 2 1 0
- PSIZE2:0 PBK1:0 ALLOC - UPCFG1X
Read/Write R RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
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- 00: 1 bank
- 01: 2 banks
- 10: invalid
- 11: invalid
• ALLOC
Configure Pipe Memory
Set to configure the pipe memory with the charact eristics.
Clear to update the memory allocation. Refer to the Memory Management chapter for more
details.
7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 7 - INTFRQ7:0 - Interrupt Pipe Request Frequency
These bits are the maximum value in millisecond of the polling period for an Interrupt Pipe.
This value has no effect fo r a non-Interrupt Pipe.
• 7 - CFGOK - Configure Pipe Memory OK
Set by hardware if the requ ire d mem o ry co nf igu ra tio n ha s be en suc c e ssfu lly pe rf or me d .
Cleared by hardware when th e pipe is disabled. The USB reset and the reset pip e have no effect
on the configuration of the pipe.
• 6 - OVERFI - Overflow
Set by hardware when a the current Pipe has received more data than the maximum length of
the current Pipe. An interrupt is triggered if the FLERRE bit is set.
Shall be cleared by software. Setting by software has no effect.
• 5 - UNDERFI - Underflow
Set by hardware when a transaction underflow occurs in the current isochronous or interrupt
Pipe. The Pipe can’t send the data flow required by the device. A ZLP will be sent instead. An
interrupt is triggered if the FLERRE bit is set.
Shall be cleared by software. Setting by software has no effect.
Bit 76543210
INTFRQ7 INTFRQ6 INTFRQ5 INTFRQ4 INTFRQ3 INTFRQ2 INTFRQ1 INTFRQ0 UPCFG2X
Read/WriteRWRWRWRWRWRWRWRW
Initial Value00000000
Bit 76543210
CFGOK OVERFI UNDERFI - DTSEQ1:0 NBUSYBK UPSTAX
Read/WriteRRWRW RRRR
Initial Value00000000
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Note: the Host controller has to send a OUT packet, but the bank is empty. A ZLP will be sent
and the UNDERFI bit is set.
• 4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-2 - DTSEQ1:0 - Toggle Sequencing Flag
Set by hardware to indicate the PID data of the current bank:
00b Data0
01b Data1
1xb Reserved.
For OUT Pipe, this value indicates the next data toggle that will be sent. This is not relative to the
current ban k.
For IN Pipe, this value indicates the last data toggle received on the current bank.
• 1-0 - NBUSYBK1:0 - Busy Bank Flag
Set by hardware to indicate the number of busy bank.
For OUT Pipe, it ind icates t he numb er of bu sy ban k(s), fi lled b y the u ser, r eady for OUT tran sfer.
For IN Pipe, it indicates the number of busy bank(s) filled by IN transaction from the Device.
00b All banks are free
01b 1 busy bank
10b 2 busy banks
11b Reserved.
• 7-0 - INRQ7:0 - IN Request Number Before Freeze
Enter the number of IN transactions before the USB controller freezes the pipe. The USB con-
troller will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically
decreased by 1 each time a IN request has been successfully performed.
This register has no effect when the INMODE bit is set (infinite IN requests generation till th e
pipe is not frozen).
• 7-6 - Reserved
Bit 76543210
INRQ7 INRQ6 INRQ5 INRQ4 INRQ3 INRQ2 INRQ1 INRQ0 UPINRQX
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
- COUNTER1:0 CRC16 TIMEOUT PID DATAPID DATATGL UPERRX
Read/Write RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
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The value read from these bits is always 0. Do not set these bits.
• 5 - COUNTER1:0 - Error counter
This counte r is increased by t he USB contro ller each ti me an erro r occurs on the Pipe. When this
value reaches 3, the Pipe is automatically frozen.
Clear these bits by software.
• 4 - CRC16 - CRC16 Error
Set by hardware when a CRC16 error has been detected.
Shall be cleared by software. Setting by software has no effect.
• 3 - TIMEOUT - Time-out Error
Set by hardware when a time-out error has been detected.
Shall be cleared by software. Setting by software has no effect.
• 2 - PID - PID Error
Set by hardware when a PID error has been detected.
Shall be cleared by software. Setting by software has no effect.
• 1 - DATA PID - Data PID Error
Set by hardware when a data PID error has been detect ed.
Shall be cleared by software. Setting by software has no effect.
• 0 - DATATGL - Bad Data Toggle
Set by hardware when a data toggle error has been detected.
Shall be cleared by software. Setting by software has no effect.
• 7 - FIFOCON - FIFO Control
For OUT and SETUP Pipe:
Set by hardware when the current bank is free, at the same time than TXOUT or TXSTP.
Clear to send the FIFO data and to switch the bank. Setting by softwar e has no effect.
For IN Pipe:
Set by hardware when a new IN message is stored in the current bank, at the same time than
RXIN.
Clear to free the current ba nk and to switch to the following bank. Sett ing by software has no
effect.
• 6 - NAKEDI - NAK Handshake received
Bit 765432 1 0
FIFOCON NAKEDI RWAL PERRI TXSTPI TXOUTI RXSTALLI RXINI UPINTX
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
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Set by hardware when a NAK has been received on the current bank of the Pipe. This triggers
an interrupt if the NAKEDE bit is set in the UPIENX register.
Shall be clear to handshake the interrupt. Setting by software has no effect.
• 5 - R WAL - Read/Write Allowed
OUT Pipe:
Set by hardware when the firmware can write a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is full.
IN Pipe:
Set by hardware when the firmware can read a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is empty.
This bit is also cleared by hardware when the RXSTALL or the PERR bit is set
• 4 - PERRI -PIPE Error
Set by hardwar e wh en an erro r occurs on the curr en t ba n k of th e Pip e. Th is trig ge r s an inte rr up t
if the PERRE bit is set in the UPIENX register. Refers to the UPERRX register to determine the
source of the error.
Automatically cleared by hardware when the error source bit is cleared.
• 3 - TXSTPI - SETUP Bank ready
Set by hardware when the current SETUP bank is free and can be filled. This triggers an inter-
rupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 2 - TXOUTI -OUT Bank ready
Set by hardware when the current OUT bank is free and can be filled. This triggers an interrupt if
the TXOUTE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 1 - RXSTALLI / CRCERR - STALL Received / Isochronous CRC Error
Set by hardware when a STALL handshake has been received on the current bank of the Pipe.
The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set in the UPI-
ENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
For Isochronous Pipe:
Set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an inter-
rupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 0 - RXINI - IN Data received
Set by hardware when a new USB message is stored in the current bank of the Pipe. This trig-
gers an interrupt if the RXINE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
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• 7 - FLERRE - Flow Err or Interrupt enable
Set to enable the OVERFI and UNDERFI interrupts.
Clear to disable the OVERFI and UNDERFI interrupts.
• 6 - NAKEDE -NAK Handshake Received Interrupt Enable
Set to enable the NAKEDI interrupt.
Clear to disable the NAKEDI interrupt.
• 5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - PERRE -PIPE Error Interrupt Enable
Set to enable the PERRI interrupt.
Clear to disable the PERRI inte rrupt.
• 3 - TXSTPE - SETUP Bank ready Interrupt Enable
Set to enable the TXSTPI interrupt.
Clear to disable the TXSTPI inte rrupt.
• 2 - TXOUTE - OUT Bank read y Interrupt Enable
Set to enable the TXOUTI interrupt.
Clear to disable the TXOUTI interrupt.
• 1 - RXSTALLE - STALL Received Interrupt Enable
Set to enable the RXSTALLI interrupt.
Clear to disable the RXSTALLI interrupt.
• 0 - RXINE - IN Data received Interrupt Enable
Set to enable the RXINI interrupt.
Clear to disable the RXINI interrupt.
• 7-0 - PDAT7:0 - Pipe Data Bit s
Set by the software to read/write a byte from/to the Pipe FIFO selected by PNUM.
Bit 7 6 5 4 3 2 1 0
FLERRE NAKEDE - PERRE TXSTPE TXOUTE RXSTALLE RXINE UPIENX
Read/Write RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
PDAT7 PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 UPDATX
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
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• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - PBYCT10 :8 - Byte coun t (h ig h ) Bits
Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. T he LSB part is
provided by the UPBCLX register.
• 7-0 - PBYCT7:0 - Byte Count (low) Bits
Set by the hardware. PBYCT10:0 is:
- (for OUT Pipe) increased after each writing into the Pipe and decrem ented after each byte
sent,
- (for IN Pipe) increased after each byte received by the host, and decremented after each byte
read by the software.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - PINT6:0 - Pipe Interrupts Bits
Set by hardw are when an inte rrupt is trig gered by the U PINTX re gister an d if the co rrespo nding
endpoint interrupt enable bit is set.
Cleared by hardware when the interrupt source is served.
Bit 765432 1 0
- - - - - PBYCT10 PBYCT9 PBYCT8 UPBCHX
Read/Write R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
PBYCT7 PBYCT6 PBYCT5 PBYCT4 PBYCT3 PBYCT2 PBYCT1 PBYCT0 UPBCLX
Read/WriteRRRRRRRR
Initial Value00000000
Bit 76543210
- PINT6 PINT5 PINT4 PINT3 PINT2 PINT1 PINT0 UPINT
Read/Write
Initial Value00000000
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24. Analog Comparator
The Analog Comparat or compares the input values on the positive pin AIN0 and negative pin
AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin
AIN1, the Analog Comparator output, ACO, is set. The comparator’s ou tput can be set to trigger
the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate
interrupt, exclusive to the Analog Comparator. Th e user can select Interrupt triggering on com-
parator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is
shown in Figure 24-1.
The Power Reduction ADC bit, PRADC, in “Power Reduction Register 0 - PRR0 ” on page 54
must be disabled by writing a logical zero to be able to use the ADC input MUX.
Figure 24-1. Analog Comparator Block Diagram(2)
Notes: 1. See Table 24-2 on page 312.
2. Refer to Figure 1-1 on page 3 and Table 10-6 on page 80 for Analog Comparator pin
placement.
24.0.1 ADC Control and Status Register B – ADCSRB
• Bit 6 – ACME: Analog Compar ator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (A DEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
description of this bit, see “Analog Comparator Multiplexed Input” on page 312.
24.0.2 Analog Comparator Control and Status Register – ACSR
• Bit 7 – ACD: Analog Comparat or Disable
ACBG
BANDGAP
REFERENCE
ADC MULTIPLEXER
OUTPUT
ACME
ADEN
(1)
Bit 7 6543210
–ACME– – - ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W R R R R/W R/W R/W
Initial Value0 0000000
Bit 76543210
ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 N/A 0 0 0 0 0
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When this bit is written logic one, the power to the Ana log Comparator is swit ched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog
Comparator. When this bit is cleared, AI N0 is ap plied to the positive input of the Analog Compar-
ator. See “Internal Voltage Reference” on page 62.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Fla g
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is ex ecut ed if the ACIE bit is se t
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling ve ctor. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is writte n logic one and t he I-bit in the Status Register is set, the Analog Com-
parator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input ca pture function in Timer/Cou nter1 to be trig-
gered by the Ana log Comp arat or. The compar ator o utput is in this case directly connecte d to the
input capture front-end logic, making the comparator utilize the noise canceler and edge select
features of the Timer/Cou nter1 Input Capture interru pt. When written logic zero, no connection
between the Analog Comparator and the input capture function exists. To make the comparator
trigger the Time r/Counter1 Input Ca pture interrupt, the IC IE1 bit in the Timer Interrup t Mask
Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determin e which comparator even ts that trigger the Analog Compa rator interr upt. The
different settings are shown in Table 24 -1.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Inte rrupt Enable bit in the ACSR Reg ister. Ot herwise an inter rupt can occu r when the
bits are changed.
Table 24-1. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle.
01Reserved
1 0 Comparator Interrupt on Falling Output Edge.
1 1 Comparator Interrupt on Risi ng Output Edge.
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24.1 Analog Comparator Multiplexed Input
It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Com-
parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be
switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in
ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), and MUX2..0 in
ADMUX select the input p in to repla ce the ne gative in put to the An alog Compara tor, as shown in
Table 24-2. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Ana-
log Compara tor .
24.1.1 Digital Input Disable Register 1 – DIDR1
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disa ble
When this bit is writte n logic one , the digita l input buf fer on the AI N1/0 pin is disa bled. The corr e-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
Table 24-2. Analog Comparator Mulitiplexed Input
ACME ADEN MUX2..0 Analog Com parator Negati ve Inp ut
0xxxxAIN1
11xxxAIN1
1 0 000 ADC0
1 0 001 ADC1
1 0 010 ADC2
1 0 011 ADC3
1 0 100 ADC4
1 0 101 ADC5
1 0 110 ADC6
1 0 111 ADC7
Bit 76543210
–––––– AIN1D AIN0D DIDR1
Read/WriteRRRRRRR/WR/W
Initial Value00000000
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25. Analog to Digital Converter - ADC
25.1 Features •10-bit Resolution
•0.5 LSB Integral Non-linearity
•± 2 LSB Absolute Accuracy
•65 - 260 µs Conversion Time
•Up to 15 kSPS at Maximum Resolution
•Eight Multiplexed Single Ended Input Channels
•Seven Differential input channels
•Optional Left Adjust men t for ADC Result Readout
•0 - VCC ADC Input Voltage Range
•Selectable 2.56 V ADC Reference Voltage
•Free Running or Single Conversion Mode
•ADC Start Conversion by Auto Triggering on Interrupt Sources
•Interrupt on ADC Conversion Complete
•Sleep Mode Noise Canceler
The ATmega32U6/AT90USB64/128 features a 10-bit successive approximation ADC. The ADC
is connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs
constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND).
The device also suppor ts 16 differenti al voltage input co mbinations. Two of the differe ntial inputs
(ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing
amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage
before the A/D conversion. Seven differential analog in put channels share a common negative
terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x
or 10x gain is used, 8-bit resolu tion can be expec ted. If 200x gain is used, 7 -bit resol ution can be
expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 25-1.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±
0.3V from VCC. See the paragraph “ADC Noise Canceler” on page 320 on how to connect this
pin.
Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage refer-
ence may be externally decoupled at the AREF pin by a capacitor for bett er noise performance.
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Figure 25-1. Analog to Digital Converter Block Schematic
25.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-
mation. The minimum value represents GND and the maximum value represents the voltage on
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
15 0
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADC DATA REGISTER
(ADCH/ADCL)
MUX2
ADIE
ADATE
ADSC
ADEN
ADIF ADIF
MUX1
MUX0
ADPS0
ADPS1
ADPS2
MUX3
CONVERSION LOGIC
10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
INTERNAL
REFERENCE
MUX DECODER
MUX4
AVCC
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
REFS0
REFS1
ADLAR
+
-
CHANNEL SELECTION
GAIN SELECTION
ADC[9:0]
ADC MULTIPLEXER
OUTPUT
DIFFERENTIAL
AMPLIFIER
AREF
BANDGAP
REFERENCE
PRESCALER
SINGLE ENDED / DIFFERENTIAL SELECTION
GND
POS.
INPUT
MUX
NEG.
INPUT
MUX
TRIGGER
SELECT
ADTS[2:0]
INTERRUPT
FLAGS
ADHSM
START
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the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V re ference voltage may be co n-
nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal
voltage reference may thus be deco upled by an external capacitor at the AREF pin to im prove
noise immunity.
The analog input channel and differential gain are selected by writing to the MUX bits in
ADMUX. Any of the ADC inp ut pins, a s well as GND and a fixe d band gap voltag e refer ence, can
be selected as single ended inputs t o the ADC. A selection of ADC input pins can be selected as
positive and negative inputs to the differential amplifier.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage refe rence and
input channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared, so it is recommende d to switch off the ADC befor e entering power
saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right ad justed, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left ad justed and no more than 8-bit precision is requ ired, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers
is blocked. This means that if ADCL has been read, an d a conversion completes b efore ADCH is
read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. The ADC
access to the Data Registers is prohibited be tween reading of ADCH and ADCL, the interrupt
will trigger even if the result is lost.
25.3 Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and w ill be cleared by hardware
when the conversio n is com pleted . If a dif fere nt data channel is selected while a co nversion is in
progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,
the ADC prescaler is reset and a conversion is started. This provides a method of starting con-
versions at fixed intervals. If the trigger signal is still set when the conversion completes, a new
conversion will not be started. If another positive edge occurs on the trigger signal during con-
version, the edge will be ignored. Note that an interrupt flag will be set even if the specific
interrupt is di sabled or t he Global In terr upt Enable b it in SREG is cleared. A conversion can th us
be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to
trigger a new conversion at the next interrupt event.
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Figure 25-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source make s the ADC start a new conver sion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and up dating the ADC Data Register . The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be us ed to determine if a conversion is in pr ogress. The ADSC bit will be
read as one during a conversion, independently of how the conversio n was started.
25.4 Prescaling and Conversion Timing
Figure 25-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. Alter-
natively, setting the ADHSM bit in ADCSRB allows an increased ADC clock frequency at the
expense of higher power consumption.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START CLK
ADC
.
.
.
.EDGE
DETECTOR
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START
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in ADCSRA. The prescaler keeps runnin g for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. See “Differential Channels” on page
318 for details on differential conversion timing.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample- and-h old ta kes pla ce 1. 5 ADC clock cycles aft er t he sta rt of a norma l con ver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conver sion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchr onization logic.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high . For a summary of conversion times, see Table 25-1.
Figure 25-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 25-5. ADC Timing Diagram, Single Conversion
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1212
13 14 15 16 17 18 19 20 21 22 23 24 25 1 2
First Conversion Next
Conversion
3
MUX and REFS
Update
MUX
and REFS
Update
Conversion
Complete
123456789 10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number 12
One Conversion Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete MUX and REFS
Update
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Figure 25-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 25-7. ADC Timing Diagram, Free Running Conversion
25.4.1 Differential Channels
When using differential channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CKADC2 equal to ha lf the ADC
clock frequency. This synchronization is done automatically by the ADC interface in such a way
that the sample-and-hold occurs a t a specific phase of CKADC2. A conversion initiated by the
user (i.e., all single conversions, and the first free running conversio n) when CKADC2 is low will
take the same amount of time as a s ingle ended conversion (13 ADC clock cycles from the next
prescaled cl ock cycle) . A conv ersion initia ted by the use r when CK ADC2 is high will take 14 ADC
Table 25-1. ADC Conversion Time
Condition First
Conversion
Normal
Conversion,
Single Ended Auto Triggered
Convertion
Sample & Hold
(Cycles from Start of Convertion) 14.5 1.5 2
Conversion Time
(Cycles) 25 13 13.5
12345678910 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number 12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number 12
One Conversion Next Conversion
34
Conversion
Complete Sample & Hold
MUX and REFS
Update
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clock cycles due to the synchroniza tion mech anism . In Free Runn ing mod e, a new co nversion is
initiated immediately aft er the previous conversion com pletes, and since CKADC2 is high at this
time, all automatically started (i.e., all but the first) Free Running conversions will take 14 ADC
clock cycles.
If differential channels are used and conversions are started by Auto Triggering, the ADC must
be switched off be twe en co nv er sio ns. Whe n Auto Tr igg e ring is used, the ADC presc ale r is re set
before the conv er sio n is sta rt ed . Sinc e th e st ag e is de p en d ent of a sta ble ADC clock prior to the
conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between
each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are
performed. The result from the extended conversions will be valid. See “Prescaling and Conver-
sion Timing” on page 316 for timing details.
The gain stage is optimized f or a bandwidth of 4 kHz at all gain sett ings. Highe r frequencies may
be subjected to non-linear amplification. An external low-pass filter should be used if the input
signal contains higher frequency components than the gain stage bandwidth. Note that the ADC
clock frequency is indepe nd ent o f the gain stage bandwidth lim ita tion. E.g. t he ADC clo ck per iod
may be 6 µs, allowing a channel to be sampled at 12 kSPS, regardless of the bandwidth of this
channel.
25.5 Changing Channel or Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continu ously updated until a conve rsion is started. Once the conver sion starts, the
channel and reference se lection is locked to e nsure a sufficient sampling t ime for the ADC. Co n-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set). Note tha t the conversion starts on the following rising ADC clock edge after
ADSC is written. The user is thus advised not to write new channel or refe rence select ion values
to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact tim e of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot te ll if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the interrupt flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
Special care should be taken when changing differential channels. Once a differential channel
has been selected, the stage may take as much as 125 µs to stabilize to the new value. Thus
conversions should not be started within the first 125 µs after selecting a new differential chan-
nel. Alternatively, conversion results obtained within this period should be discarded.
The same settling time should be observed for the first differential conversion after changing
ADC reference (by changing the REFS1:0 bits in ADMUX).
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The settling time and gain stage bandwidth is independent of the ADHSM bit setting.
25.5.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
• In Single Conversion mode, alw ays select the channel before starting the conversion. The
channel selection may be changed o ne ADC cloc k cycle after writing one to ADSC. Ho w e v er,
the simplest method is to wait for the conversion to complete before changing the channel
selection.
• In Free Running mode, always sele ct the channel before starting the first conversion. The
channel selection may be changed o ne ADC cloc k cycle after writing one to ADSC. Ho w e v er,
the simplest method is to wait for the first conversion to complete, and then change the
channel selection. Since the next conversion has already started automatically, the next
result will reflect the previous channel selection. Subsequent con versions will reflect the new
channel selection.
When switching to a differential gain channel, the first conversion result may have a poor accu-
racy due to the required settling time for the automatic offset cance llation circuitry. The user
should preferably disregard the first conversion result.
25.5.2 ADC Voltage Reference
The referenc e voltage for the ADC (VREF) indicates the conversion range for the ADC. Single
ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as
either AVCC, internal 2.56V reference, or external AREF pin.
AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is gener-
ated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the
external AREF pin is directly connected to the ADC, and the reference voltage can be made
more immune to noise by connecting a capacitor between the AREF pin and gro und. VREF can
also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high
impedant sour ce, and only a capacitive load should be connected in a system.
If the user has a fixed volt age source connect ed to the AREF pin, the user ma y not use the oth er
reference voltage options in the application, as they will be shorted to the external voltage. If no
external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56V as
reference selection. The first ADC conversion result after switching reference voltage source
may be inaccurate, and the user is advised to discard this result.
If differential channels are used, the selected reference should not be closer to AVCC than indi-
cated in Table 30-5 on page 405.
25.6 ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise
induced from the CPU core and o ther I/O pe ripherals. The noise ca nceler can be used with ADC
Noise Reduc tion an d Id le m ode. To m ake use of th is fe atur e, th e fo llowing proce dur e sh ould b e
used:
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a. Make sure that the ADC is enabled and is not busy converting. Single Conversion
mode must be selected and the ADC conversion complete interrupt must be
enabled.
b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion
once the CPU has been halted.
c. If no other interrupts occur before the ADC conversion completes, the ADC inter-
rupt will wake up the CPU and execute the ADC Conversion Complete interrupt
routine. If another interrupt wakes up the CPU before the ADC conversion is com-
plete, that interrupt will be executed, and an ADC Conversion Complete interrupt
request will be generated when the ADC conversion completes. The CPU will
remain in active mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-
ing such sleep modes to avoid excessive power consumption.
If the ADC is enabled in such sleep modes and the user wants to perform d ifferential conver-
sions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an
extended conversion to get a valid result.
25.6.1 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 25-8. An ana log
source applied to ADCn is subjecte d to the pin ca pacitance and inp ut leakage of that pin, re gard-
less of whether that channel is selected as input for the ADC. When the channel is selected, the
source must dr ive the S/H capacitor th rough the series re sistance (combined resistance in the
input path).
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the samp ling time wi ll be n egligible . I f a sour ce with higher impe d-
ance is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources
with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
If differential gain channels are used, the input circuitry looks somewhat different, although
source impedances of a few hundred kΩ or less is recommended.
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either
kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised
to remove high frequency components with a low-pass filter before applying the signals as
inputs to the ADC.
Figure 25-8. Analog Input Circuitry
ADCn
I
IH
1..100 kΩ
C
S/H
= 14 pF
V
CC
/2
I
IL
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25.6.2 Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
a. Keep analog signal paths as short as possible. Make sure analog tracks run ov er
the analog ground plane, and keep them well away from high-speed switching digi-
tal tracks.
b. The AVCC pin on the device should be connected to the digital VCC supply voltage
via an LC network as shown in Figure 25-9.
c. Us e the ADC no ise ca nceler function to redu ce indu ce d no ise fro m the CPU.
d. If any ADC port pins are used as digit al outputs, it is essential that these do not
switch while a conversion is in progress.
Figure 25-9. ADC Power Connections
25.6.3 Offset Compensation Schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-
surements as much as possible. The remaining offset in the analog path can be measured
directly by selecting the same channe l for both d ifferent ial inputs. T his offset resid ue can be then
subtracted in software from the measurement results. Using this kind of software based offset
correction, offset on any channel can be reduced below one LSB.
25.6.4 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
VCC
GND
100nF
Analog Ground Plane
(ADC0) PF0
(ADC7) PF7
(ADC1) PF1
(ADC2) PF2
(ADC3) PF3
(ADC4) PF4
(ADC5) PF5
(ADC6) PF6
AREF
GND
AVCC
52
53
54
55
56
57
58
59
60
6161
6262
6363
6464
1
51
NC
(AD0) PA0
10μH
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• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5 LSB). Idea l value: 0 LSB.
Figure 25-10. Offset Error
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
transit ion (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB
Figure 25-11. Gain Error
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal t ransition for any code. Ideal value: 0
LSB.
Output Code
VREF Input Voltage
Ideal ADC
Actual ADC
Offset
Error
Output Code
V
REF
Input Voltage
Ideal ADC
Actual ADC
Gain
Error
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Figure 25-12. Integral Non-linearity (INL)
• Diff erential Non-line arity (DNL): The maximum de via tion of the actual code width ( the interval
between two adjacent tr ansitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
Figure 25-13. Differential Non-linearity (DNL)
• Quantization Error: Due to the quantization of the input voltage into a finite n umber of codes ,
a range of input v oltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
• Absolute Accuracy: The m aximum deviation of an actual (una djusted) tr ansitio n compared to
an ideal transition for any code. This is the compound effect of offset, gain error, diff erential
error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB.
25.7 ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC
Result Registers (ADCL, ADCH).
For single ended conversion, the result is:
Output Code
V
REF
Input Voltage
Ideal ADC
Actual ADC
INL
Output Code
0x3FF
0x000
0VREF Input Voltage
DNL
1 LSB
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where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see
Table 25-3 on page 327 an d Table 25-4 on page 327). 0x 000 represents analog ground, and
0x3FF represents the selected reference voltage minus one LSB.
If differential channels are used, the result is:
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative inp ut pin,
GAIN the selected gain factor and VREF the selected voltage reference. The result is presented
in two’s complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user
wants to perform a quick polarity check of the result, it is sufficient to read the MSB of the result
(ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is posi-
tive. Figure 25-14 shows the decoding of the differential input range.
Table 82 shows the resulting output codes if th e differential input chan nel pair (ADCn - ADCm) is
selected with a reference voltage of VREF.
Figure 25-14. Differential Measurement Range
ADC VIN 1023⋅
VREF
--------------------------=
ADC VPOS VNEG
–()GAIN 512⋅⋅
VREF
------------------------------------------------------------------------=
0
Output Code
0x1FF
0x000
V
REF
Differential Input
Voltage (Volts)
0x3FF
0x200
- V
REF
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Example 1:
– ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)
– Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
– ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270
– ADCL will thus read 0x00, and ADCH will read 0x9C.
Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02.
Example 2:
– ADMUX = 0xFB (ADC3 - ADC2, 1x gain, 2.56V reference, lef t adjusted result)
– Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
– ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x0 29.
– ADCL will thus read 0x40, and ADCH will read 0x0A.
Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29.
25.8 ADC Register Description
25.8.1 ADC Multiplexer Selection Register – ADMUX
• Bit 7:6 – REFS1:0 : Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 25-3. If these b its are
changed during a conversion, the change will not go in effect until this conversion is complete
Table 25-2. Correlation Between Input Voltag e and Output Codes
VADCn Read code Corresponding decimal value
VADCm + VREF /GAIN 0x1FF 511
VADCm + 0.999 VREF /GAIN 0x1FF 511
VADCm + 0.998 VREF /GAIN 0x1FE 510
... ... ...
VADCm + 0.001 VREF /GAIN 0x001 1
VADCm 0x000 0
VADCm - 0.001 VREF /GAIN 0x3FF -1
... ... ...
VADCm - 0.999 VREF /GAIN 0x201 -511
VADCm - VREF /GAIN 0x200 -512
Bit 76543210
REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADL AR to left adjust the resu lt. Oth erwise, the r esult is ri ght adju sted. Changing t he
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complet e description of this bit, see “The ADC Data Register – ADCL and ADCH” on
page 329.
• Bits 4:0 – MUX4:0: Analog Channel Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differe ntial channels. See T able 25-4 for details. If these
bits are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Table 25-3. Voltage Reference Selections for ADC
REFS1 REFS0 Voltage Refere nce Selection
0 0 AREF, Internal Vref turned off
01AV
CC with external capacitor on AREF pin
10Reserved
1 1 Internal 2.56V Voltage Reference with external capacitor on AREF pin
Table 25-4. Input Channel and Gain Selections
MUX4..0 Single End e d
Input Positive Differential
Input Negative Differential
Input Gain
00000 ADC0
N/A
00001 ADC1
00010 ADC2
00011 ADC3
00100 ADC4
00101 ADC5
00110 ADC6
00111 ADC7
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25.8.2 ADC Control and Status Register A – ADCSRA
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mod e, write this bit t o one to start ea ch conversion. In Free Running mode,
write this bit to one to st art th e first conversion. Th e first conversion af ter ADSC ha s been writt en
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
01000
N/A
(ADC0 / ADC0 / 10x)
01001 ADC1 ADC0 10x
01010 (ADC0 / ADC0 / 200x)
01011 ADC1 ADC0 200x
01100 (Reserv ed - ADC2 / ADC2 / 10x)
01101 ADC3 ADC2 10x
01110 (ADC2 / ADC2 / 200x)
01111 ADC3 ADC2 200x
10000 ADC0 ADC1 1x
10001 (ADC1 / ADC1 / 1x)
10010 ADC2 ADC1 1x
10011 ADC3 ADC1 1x
10100 ADC4 ADC1 1x
10101 ADC5 ADC1 1x
10110 ADC6 ADC1 1x
10111 ADC7 ADC1 1x
11000 ADC0 ADC2 1x
11001 ADC1 ADC2 1x
11010 (ADC2 / ADC2 / 1x)
11011 ADC3 ADC2 1x
11100 ADC4 ADC2 1x
11101 ADC5 ADC2 1x
11110 1.1V (VBand Gap)N/A
11111 0V (GND)
Table 25-4. Input Channel and Gain Selections (Continued)
MUX4..0 Single End e d
Input Positive Differential
Input Negative Differential
Input Gain
Bit 76543210
ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC A uto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive e dge of the select ed trigger signal. The trigger sou rce is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Re gisters are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, ADIF is cleared by writing a logical one to the fl ag. Beware that if doing a Read-Modify-
Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI
instructions ar e used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is wr itte n to on e a n d t he I- bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the
ADC.
25.8.3 The ADC Data Register – ADCL and ADCH
25.8.3.1 ADLAR = 0
Table 25-5. ADC Prescaler Selections
ADPS2 ADPS1 ADPS0 Division Factor
000 2
001 2
010 4
011 8
100 16
101 32
110 64
1 1 1 128
Bit 151413121110 9 8
– – – – – – ADC9 ADC8 ADCH
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
Bit 76543210
Read/Write RRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
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25.8.3.2 ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input
channels) is required, it is sufficient to read AD CH. Otherwise, ADCL must be read first, then
ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLA R is set, the result is left adjusted. If ADLAR is cleared (default), th e result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on
page 324.
25.8.4 ADC Control and Status Register B – ADCSRB
• Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. This mode enables higher conversion
rate at the expense of higher power consumption.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected interrupt flag. Note that switc hing from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Bit 151413121110 9 8
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1 ADC0 – –––––ADCL
Bit 76543210
Read/Write RRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
Bit 76543210
ADHSM ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R/W R/W R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 25-6. ADC Auto Trigger Source Selections
ADTS2 ADTS1 ADTS0 Trigger Source
0 0 0 Free Running mode
0 0 1 Analo g Comparator
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare Match
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25.8.5 Digital Input Disable Register 0 – DIDR0
• Bit 7:0 – ADC7D ..ADC0D: ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this
bit should be written logic one to r educe power consumption in the digital input buffer.
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter1 Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event
Table 25-6. ADC Auto Trigger Source Selections
ADTS2 ADTS1 ADTS0 Trigger Source
Bit 76543210
ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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26. JTAG Interface and On-chip Debug System
26.0.1 Features •JTAG (IEEE std. 1149.1 Compliant) Interface
•Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
•Debugger Access to:
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
–Program Counter
– EEPROM and Flash Memories
•Extensive On-chip Debug Support for Break Conditions, Including
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Break Points on Single Address or Address Range
– Data Memory Break Points on Single Address or Address Range
•Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
•On-chip Debugging Suppor ted by AV R Studi o ®
26.1 Overview The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
• Testing PCBs by using the JTAG Boundary-scan capability
• Programming the non-volatile memories, Fuses and Lock bits
• On-chip de bugging
A brief description is given in the following sections. Detailed descriptions for Pro gramming via
the JTAG interface, and using the Boundary-scan Chain can be found in the sections “Program-
ming via the JTAG Interface” on page 385 and “IEEE 1149.1 (JTAG) Boundary-scan” on page
338, r espectively. The On-chip Debug support is considered being private JTAG instr uctions,
and distributed within ATMEL and to select ed third party vendors only.
Figure 26-1 shows a block diagram of the JTAG interface and the On-chip Debug system. The
TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan chain
(Shift Register) betwe en th e T DI – inp ut and TDO – o utpu t. T he In str uctio n Reg iste r hold s JTAG
instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used
for board-leve l te sting . The JTAG Pr og ram ming In te rface ( actually consisting of several physical
and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal
Scan Chain and Break Point Scan Chain are used for On-chip debugging only.
26.2 Test Access Port – TAP
The JTAG interface is accessed t hrough fou r of t he AVR’s pins . In JTAG ter minology, t hese pins
constitute the Test Access Port – TAP. These pins are:
• TMS: Test mode select. This pin is used for navigating through the TAP-controller state
machine.
• TCK: Test Clock. JTAG operation is synchronous to TCK.
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• TDI: Test Data In. Serial input data to be shift ed in to the Instruction Register or Data Register
(Scan Chains).
• TDO: Test Data Out. Serial output data fr om Instruction Register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
When the JTAGEN Fu se is unprogrammed, the se four TAP pins are normal po rt pins, and the
TAP controller is in reset. When programmed, the input TAP signals are internally pulled high
and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this
fuse programmed .
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-
tored by the debugger to be able to detect external reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the reset line
are used in the application.
Figure 26-1. Block Diagram
TAP
CONTROLLER
TDI
TDO
TCK
TMS
FLASH
MEMORY
AVR CPU
DIGITAL
PERIPHERAL
UNITS
JTAG / AVR CORE
COMMUNICATION
INTERFACE
BREAKPOINT
UNIT FLOW CONTROL
UNIT
OCD STATUS
AND CONTROL
INTERNAL
SCAN
CHAIN
M
U
X
INSTRUCTION
REGISTER
ID
REGISTER
BYPASS
REGISTER
JTAG PROGRAMMING
INTERFACE
PC
Instruction
Address
Data
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
ANALOG
PERIPHERIAL
UNITS
I/O PORT 0
I/O PORT n
BOUNDARY SCAN CHAIN
Analog inputs
Control & Clock lines
DEVICE BOUNDARY
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Figure 26-2. TAP Controller State Diagram
26.3 TAP ControllerThe TAP contro ller is a 1 6- sta te f i nite st ate m achin e tha t cont ro ls the o per at ion o f t he Bou nd ary-
scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions
depicted in Figure 26-2 depend on the signal present on TMS (shown adjacent to each state
transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-
Logic-Reset.
As a definition in this docum e nt, the LSB is shifte d in an d out firs t for all Shift Reg ist er s.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
• At the TMS input , ap ply the se qu en ce 1, 1, 0, 0 at the rising edges of TCK to ente r th e Shif t
Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG
instructions into the JTAG Instruction Re gister from the TDI input at the rising edge of TCK.
The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR
state. The MSB of the instruction is shifted in when this state is left by setting TMS high.
While the instructio n is shifted in f rom the TDI pin, th e captured IR-state 0x01 is shifted out on
the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI
and TDO and controls the circuitry surrounding the selected Data Register.
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
011 1
00
00
11
10
1
1
0
1
0
0
10
1
1
0
1
0
0
00
11
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• Apply the TMS sequen ce 1, 1, 0 to re-e nter the Run-Test/Idle state . The instruction is latched
onto the parallel output from the Shift Register path in the Update-IR state. The Exit- IR,
Pause-IR, and Exit2-IR states are only used for navigating the state machine.
• At the TMS input , ap ply the se qu en ce 1, 0, 0 at the rising edge s of TCK to ente r the Shift
Data Register – Shift-DR state. While in this state, upload the selected Data Register
(selected b y the present JTA G instruction in the JTA G Instruction Register) from th e TDI input
at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be
held low during input of all bits except the MSB. The MSB of the data is shifted in when this
state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the
parallel inpu ts to the Data Register captured in the Capture-DR state is shifted out on the
TDO pin.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
Register has a latched parallel-output, the latching takes place in the Update-DR state. The
Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered betwe en selecting
JTAG instruction and using Data Registers, and some JTAG instructions may select certain
functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note: Independent of the initial state of th e TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for five TCK clock periods.
For detailed information on the JTAG specification, refer to the literature listed in “Bibliography”
on page 337.
26.4 Using the Boundary-scan Chain
A complete description of the Boundary-scan capabilities are given in the section “IEEE 1149.1
(JTAG) Boundary-scan” on page 338.
26.5 Using the On-chip Debug System
As shown in Figure 26-1, the hardware sup po rt for On -c hi p Debugging consists mainly of
• A scan chain on the interface between the internal AVR CPU and the internal peripheral
units.
• Break Point unit.
• Communication interface between the CPU and JTAG system.
All read or modify/write operations needed for implementing the Debugger are done by applying
AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O
memory mapped locat ion which is par t of the communicat ion interface be tween the CPU and t he
JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two
Program Memory Break Points, and two combined Break Points. Together, the four Break
Points can be configured as either:
• 4 single Program Memory Break Points.
• 3 Single Program Memory Break Point + 1 single Data Memory Break Point.
• 2 single Program Memory Break Points + 2 single Data Memory Break Points.
• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range
Break Point”).
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• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range
Break Point”).
A debugger, like the AVR Studio, may however use one or more of these resources for its inter-
nal purpose, leaving less flexibility to the end-user.
A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG
Instructions” on page 336.
The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the
OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system
to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or
LB2 Lock bits are set. Otherwise, the O n-chip debug system would have provided a back-door
into a secured device.
The AVR Studio enables the user to fully control execution of programs on an AVR device with
On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator.
AVR Studio® supports source level execution of Assembly programs assembled with Atmel Cor-
poration’s AVR Assembler and C programs compiled with third party vendors’ compilers.
AVR Studio runs under Microsoft® Windows® 95/98/2000 and Microsoft Windows NT®.
For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only high-
lights are presen ted in this document.
All necessary executio n commands are available in AVR Stud io, both on source level and on
disassembly level. T he user can execute the pr ogram, single step throug h the code either by
tracing into or stepping over functions, st ep out of funct ions, place the cur sor on a stateme nt and
execute until the statement is reached, stop the execution, and reset the execution target. In
addition, the user can have an unlimited number of code Break Points (using the BREAK
instruction) and up to two data memory Break Points, alternatively combined as a mask (range)
Break Point.
26.6 On-chip Debug Specific JTAG Instructions
The On-chip debug su pport is considered be ing privat e JTAG instruction s, and dist ribut ed within
ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference.
26.6.1 PRIVATE0; 0x8Private JTAG instruction for accessing On-chi p debug system.
26.6.2 PRIVATE1; 0x9Private JTAG instruction for accessing On-chi p debug system.
26.6.3 PRIVATE2; 0xAPrivate JTAG inst ruction for accessing On-chip debug system.
26.6.4 PRIVATE3; 0xBPrivate JTAG inst ruction for accessing On-chip debug system.
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26.7 On-chip Debug Related Register in I/O Memory
26.7.1 On-chip Debug Register – OCDR
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the reg ist er has been wr it te n. When th e CPU re ads the OCDR Regist er the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shar ed with a standard I/O location . In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is pro grammed, and the debugger ena bles
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for furthe r information on how to use this register.
26.8 Using the JTAG Programming Capabilities
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and
TDO. These are the only pins that need to be controlled/observed to perform JTAG program-
ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse
must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the
JTAG Test Access Port.
The JTAG programming capability supports:
• Flash programming an d verifying.
• EEPROM programming and verifying.
• Fuse programming and verifying.
• Lock bit programmin g and verifying.
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a
security feature that ensures no back-door exists for reading out the content of a secured
device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section “Programming via the JTAG Interface” on page 385.
26.9 Bibliography For more information about general Boundary-scan, the follo wing literature can be consulted:
• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993.
• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,
1992.
Bit 7 6543210
MSB/IDRD LSB OCDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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27. IEEE 1149.1 (JTAG) Boundary-scan
27.1 Features •JTAG (IEEE std. 1149.1 compliant) Interface
•Boundary-scan Capabil ities According to the JTAG Standard
•Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections
•Supports the Optional IDCODE Instruction
•Additional Public AVR_RESET Instruction to Reset the AVR
27.2 System Overview
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, Boundary-scan pro-
vides a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the four TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be
used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the
ID-Code of the device, since IDCODE is the default JTAG instruction. It may be desirable to
have the AVR device in reset during test mode. If not reset, inputs to the de vice may be deter-
mined by the scan operations, and the internal software may be in an undetermined state when
exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high
impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction
can be issued to make the shortest possible scan chain through the device. The device can be
set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET
instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and lo ading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial value s to the scan r ing, to avoid da maging the board when issuing the EXT EST
instruction for the first tim e. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins duri ng normal operation of the part.
The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR must be
cleared to enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG T CK clock frequency higher
than the internal chip frequency is possible. The chip clock is not required to run .
27.3 Data Registers
The Data Registers relevant for Boundary-scan operations are:
• Bypass Register
• Device Identification Regist er
• Reset Register
• Boundary-scan Chain
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27.3.1 Bypas s Regi st er
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass Register can be used to shorten the scan chain on a system when
the other devices are to be tested.
27.3.2 Device Identification Register
Figure 27-1 shows the structure of the Device Identification Register.
Figure 27-1. The Format of the Device Identification Register
27.3.2.1 Version Version is a 4-bit number identifying the revision of the component. The JTAG version numb er
follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.
27.3.2.2 Part Numb e rThe part number is a 16-bit code identifying the component. The JTAG Part Number for
ATmega32U6/AT90USB64/128 is listed in Table 27-1 .
27.3.2.3 Manufacturer ID
The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID
for ATMEL is listed in Table 27-2.
27.3.3 Reset RegisterThe Reset Register is a test Data Register used to reset the part. Since the AVR tri-states Port
Pins when reset, the Reset Re gister can a lso replace t he functi on of th e unimplement ed opt ional
JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the external Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the fuse set-
tings for the clock options, the part will remain reset for a reset tim e-out period (refer to “Clock
Sources” on page 40) after releasing the Reset Register. The output from this Data Register is
not latched, so the reset will take place immediately, as shown in Figure 27-2.
MSB LSB
Bit 31 28 27 12 11 1 0
Device ID Version Part Number Manufacturer ID 1
4 bits 16 bits 11 bits 1-bit
Table 27-1. AVR JTAG Part Number
Part Nu mber JTAG Part Num ber (H ex)
AVR USB 0x9782
Table 27-2. Manufacturer ID
Manufacturer JTAG Manufactor ID (Hex)
ATMEL 0x01F
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Figure 27-2. Reset Register
27.3.4 Boundary-scan Chain
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections.
See “Boundary-scan Chain” on page 342 for a comple te desc rip tio n.
27.4 Boundary-scan Specific JTAG Instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the
JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction
is not implemented, but all outputs with tri-state capability can be set in high-impedant state by
using the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Re gister is selected as path between TDI and TDO for each instruction.
27.4.1 EXTEST; 0x0 Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing
circuitry external to the AVR package . For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip
connections, the int erface be tween t he analog an d th e digita l logic is in the scan chain . The con-
tents of the latche d outputs of the Bound ary-scan chain is driven out as soon as the JTAG IR-
Register is loaded with the EXTEST instruction.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from th e scan chain is applied to output pins.
27.4.2 IDCODE; 0x1 Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register
consists of a version number, a device number an d the manufacturer code chosen by JEDEC.
This is the default instruction after power-up.
DQ
From
TDI
ClockDR · AVR_RESET
To
TDO
From Other Internal and
External Reset Sources
Internal reset
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The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
27.4.3 SAMPLE_PRELOAD; 0x2
Mandatory JTAG instruction for pre-loa ding the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from th e Boundary-scan chain is applied to the output latches. However,
the output latches are not connected to the pins.
27.4.4 AVR_RESET; 0xC
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as Data Register. Note that the reset will be active as long as there is
a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
27.4.5 BYPASS; 0xF Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
• Capture-DR: Loads a logic “0” into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
27.5 Boundary-scan Related Register in I/O Memory
27.5.1 MCU Control Regist er – MCU C R
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
Bit 76543210
JTD ––PUD – – IVSEL IVCE MCUCR
Read/Write R/W R R R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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27.5.2 MCU Status Register – MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
27.6 Boundary-scan Chain
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
27.6.1 Scanning the Digital Port Pins
Figure 27-3 shows the Boundary-scan Cell for a bi-directional port pin. The pull-up function is
disabled during Boundary-scan when the JTAG IC contains EXTEST or SAMPLE_PRELOAD.
The cell consists of a bi-directional pin cell that combines the three signals Output Control -
OCxn, Output Data - ODxn, and Input Da ta - IDxn , int o on ly a tw o- sta g e Shif t Reg ister. The port
and pin indexes are not used in the following description
The Boundary-scan logic is not included in the figures in the datasheet. Figure 27-4 shows a
simple digital port pin as described in the section “I/O-Ports” on p age 72. The Boundary-scan
details from Figure 27-3 replaces t he dashed box in Figure 27-4.
When no alternate por t functio n is present, t he Input Data - ID - correspond s to the PINxn Regis-
ter value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
Control corresponds to the Data Direction - DD Register, and the Pull-up Enable - PUExn - cor-
responds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 27-4 to make the
scan chain read the actual pin value. For analog function, there is a direct connection from the
external pin to th e a nalog circu it. Th ere is no sca n chain on t he inte rf ace bet wee n the digital and
the analog circ uitry, bu t som e di gital con trol signal to ana log circ uitry a re tu rned o f f to avoid driv-
ing contention on the pads.
When JTAG IR contains EXTEST o r SAMPLE_PRELOAD the clock is not sent out on the port
pins even if the CKOUT fuse is progr ammed. Ev en thou gh the clock is output when the JTAG IR
contains SAMPLE_PRELOAD, the clock is not sampled by the boundary scan.
Bit 76543210
–––JTRFWDRF BORF EXTRF PORF MCUSR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description
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Figure 27-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
DQ DQ
G
0
1
0
1
DQ DQ
G
0
1
0
1
0
1
Port Pin (PXn)
Vcc
EXTEST
To Next Cell
ShiftDR
Output Control (OC)
Output Data (OD)
Input Data (ID)
From Last Cell UpdateDRClockDR
FF1 LD1
LD0FF0
0
1
Pull-up Enable (PUE)
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Figure 27-4. General Port Pin Schematic Diagram
27.6.2 Scanning the RESET Pin
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active hig h
logic for High Voltage Parallel program ming. An observe-o nly cell as shown in Figure 27-5 is
inserted for the 5V reset signal.
Figure 27-5. Observe-only Cell
CLK
RPx
RRx
WRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
CLK : I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
Q
D
Q
QD
CLR
PORTxn
Q
QD
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
I/O
See Boundary-scan
Description for Details!
PUExn
OCxn
ODxn
IDxn
PUExn: PULLUP ENABLE for pin Pxn
OCxn: OUTPUT CONTROL for pin Pxn
ODxn: OUTPUT DATA to pin Pxn
IDxn: INPUT DATA from pin Pxn
0
1
DQ
From
Previous
Cell
ClockDR
ShiftDR
To
Next
Cell
From System Pin To System Logic
FF1
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27.7 ATmega32U6/AT90USB64/128 Boundary-scan Order
Table 27-3 shows the Scan ord er between TDI and TDO when the Boundar y-scan chain is
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and Port Fis
scanned in the opposite bit order of the other ports. Exceptions from the rules are the Scan
chains for the analog circuits, which constitute the most significant bits of the scan chain regard-
less of which p h ysica l p in th ey ar e connected to. In Figure 27-3, PXn. Data corres po n ds to FF0 ,
PXn. Control corresp onds to FF1 , PXn. Bit 4, 5, 6 and 7 of Port F is not in the scan ch ain, sinc e
these pins constitute the T AP p ins when t he JTAG is ena bled. The USB pads ar e not included in
the boundary-scan.
Table 27-3. ATmega32U6/AT90USB64/128 Boundary-scan Order
Bit Number Signal Name Module
88 PE6.Data
Port E
87 PE6.Control
86 PE7.Data
85 PE7.Control
84 PE3.Data
83 PE3.Control
82 PB0.Data
Port B
81 PB0.Control
80 PB1.Data
79 PB1.Control
78 PB2.Data
77 PB2.Control
76 PB3.Data
75 PB3.Control
74 PB4.Data
73 PB4.Control
72 PB5.Data
71 PB5.Control
70 PB6.Data
69 PB6.Control
68 PB7.Data
67 PB7.Control
66 PE4.Data
PORTE
65 PE4.Control
64 PE5.Data
63 PE5.Control
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62 RSTT Reset Logic (Observe Only)
61 PD0.Data
Port D
60 PD0.Control
59 PD1.Data
58 PD1.Control
57 PD2.Data
56 PD2.Control
55 PD3.Data
54 PD3.Control
53 PD4.Data
52 PD4.Control
51 PD5.Data
50 PD5.Control
49 PD6.Data
48 PD6.Control
47 PD7.Data
46 PD7.Control
45 PE0.Data
Port E
44 PE0.Control
43 PE1.Data
42 PE1.Control
Table 27-3. ATmega32U6/AT90USB64/128 Boundary-scan Order (Continued)
Bit Number Signal Name Module
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41 PC0.Data
Port C
40 PC0.Control
39 PC1.Data
38 PC1.Control
37 PC2.Data
36 PC2.Control
35 PC3.Data
34 PC3.Control
33 PC4.Data
32 PC4.Control
31 PC5.Data
30 PC5.Control
29 PC6.Data
28 PC6.Control
27 PC7.Data
26 PC7.Control
25 PE2.Data Port E
24 PE2.Control
23 PA7.Data
Port A
22 PA7.Control
21 PA6.Data
20 PA6.Control
19 PA5.Data
18 PA5.Control
17 PA4.Data
16 PA4.Control
15 PA3.Data
14 PA3.Control
13 PA2.Data
12 PA2.Control
11 PA1.Data
10 PA1.Control
9PA0.Data
8 PA0.Control
Table 27-3. ATmega32U6/AT90USB64/128 Boundary-scan Order (Continued)
Bit Number Signal Name Module
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27.8 Boundary-scan Description Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. BSDL files are available for
ATmega32U6/AT90USB64/128.
7PF3.Data
Port F
6 PF3.Control
5PF2.Data
4 PF2.Control
3PF1.Data
2 PF1.Control
1PF0.Data
0 PF0.Control
Table 27-3. ATmega32U6/AT90USB64/128 Boundary-scan Order (Continued)
Bit Number Signal Name Module
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28. Boot Loader Support – Read-While-Write Self-Pr ogramming
The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for
downloading and up loading progr am code by the MCU itsel f. This feature allows flexible applica-
tion software updates controlled by the MCU using a Flash-resident Boot Loader program. The
Boot Loader program can use any availab le data interface and associated protocol to read code
and write (program) that code into the Flash memory, or read the code from the program mem-
ory. The program code within the Boot Loader section has the capability to write into the e ntire
Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it
can also erase itself from the code if the feature is not needed anymore. The size of the Boot
Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot
Lock bits which can be set independently. This gives the user a unique flexibility to select differ-
ent levels of protec tion. General information o n SPM and ELPM is provided in See “AVR CPU
Core” on page 10.
28.1 Boot Loader Features
•Read-While-Write Self-Programming
•Flexible Boot Memory Size
•High Security (Separate Boot Lock Bits for a Flexible Protection)
•Separate Fuse to Select Reset Vector
•Optimized P age(1) Size
•Code Efficient Algorithm
•Efficient Read-Modify-Write Support
Note: 1. A page is a section in the Flash consisting of several bytes (see Table 29-11 on page 372)
used during pr ogramming. The page organ ization does not affect normal operation.
28.2 Application and Boot Loader Flash Sections
The Flash memory is organized in two main sections, the Application section and the Boot
Loader section (see Figure 28-2). The size of the different sections is configured by the
BOOTSZ Fuses as shown in Table 28- 8 on page 364 and Figure 28-2. These two sections can
have different level of protection since they have different sets of Lock bits.
28.2.1 Application Section
The Application section is the section of the Flash that is used for storing the application code.
The protection level for the Application section can be selected by the applicat ion Boot Lock bits
(Boot Lock bits 0), see Table 28-2 on page 353. The Application section can never store any
Boot Loader code sin ce the SPM instruction is disab led when executed from the Application
section.
28.2.2 BLS – Boot Loader Section
While the Application section is used for storing the application code, the The Boot Loader soft-
ware must be located in the BLS since the SPM instruction can initiate a programming when
executing from the BLS only. The SPM instruction can access the entire Flash, including the
BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader
Lock bits (Boot Lock bits 1), see Table 28-3 on page 353.
28.3 Read-While-Write and No Read-While-Write Flash Sections
Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-
ware update is depende nt on which address that is being progr ammed. In addition to the two
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sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also
divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-
Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 28-
1 and Figure 28-1 on page 351. The main difference between the two sections is:
• When erasing or writing a page located inside the RWW section, the NRWW section can be
read during the operation.
• When erasing or writing a page located insid e the NRWW section, the CPU is halted during
the entire operation.
Note that the user software ca n never read any code th at is located in side the RWW section dur-
ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which
section that is being programmed (erased or written), not which section that actually is being
read during a Boot Loader software update.
28.3.1 RWW – Read-While-Write Section
If a Boot Loader software update is programming a page inside the RWW section, it is possible
to read code from the Flash, but only code that is located in the NRWW section. During an on-
going programming, the software must ensure that the RWW section never is being read. If the
user software is trying to read code that is l ocated inside the RWW se ction (i. e., by load prog ram
memory, call, or jump instructions or an interrupt) du ring programming, the so ftware might end
up in an unkn own state. To avoid this, th e interrupts should either be disabled or moved to the
Boot Loader section. The Boot Loader section is always located in the NRWW section. The
RWW Section Busy bit (RWWSB) in the Store Program Memory Control and Status Register
(SPMCSR) will be read as logica l one as long as the RWW sectio n is blocked for reading. After
a programming is completed, the RWWSB must be cleared by software before reading code
located in the RWW section. See “Store Program Memory Control and Status Register –
SPMCSR” on page 355. for details on how to clear RWWSB.
28.3.2 NRWW – No Read-While -W ri te Section
The code located in the NRWW section can be read when the Boot Loader software is updating
a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU
is halted during the entire Page Erase or Page Write operation.
Table 28-1. Read-While-Write Features
Which Section does the Z-
pointer Address During the
Programming?
Which Sect ion Can
be Read During
Programming? Is the CPU
Halted? Read-While-Write
Supported?
RWW Section NRWW Section No Yes
NRWW Section None Yes No
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Figure 28-1. Read-While-Write vs. No Read-While-Write
Read-While-Write
(RWW) Section
No Read-While-Write
(NRWW) Section
Z-pointer
Addresses RWW
Section
Z-pointer
Addresses NRWW
Section
CPU is Halted
During the Operation
Code Located in
NRWW Section
Can be Read During
the Operation
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Figure 28-2. Memory Sections
Note: 1. The parameters in the figure above are given in Table 28-8 on page 364.
28.4 Boot Loader Lock Bits
If no Boot Loader capability is needed, the entire Flash is available for application code. The
Boot Loader has two separ at e sets of Boot Lock bits which ca n be set indepen de ntly. This gives
the user a unique flexibility to select different levels of protection.
The user can select:
• To protect the entire Flash from a software update by the MCU.
• To protect only the Boot Loader Flash section from a software update by the MCU.
• To protect only the Application Flash section from a software update by the MCU.
• Allow software update in the entire Flash.
See Table 28-2 and Table 28-3 for fur ther deta ils. The Boot Lock bit s can be set by software and
in Serial or in Parallel Programming mode. They can only be cleared by a Chip Erase command
only. The general Write Lock (Lock Bit mod e 2) does not control the programming of the Flash
memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not
control reading nor writing by (E)LPM/SPM, if it is attempted.
0x0000
Flashend
Program Memory
BOOTSZ = '11'
Application Flash Section
Boot Loader Flash Section Flashend
Program Memory
BOOTSZ = '10'
0x0000
Program Memory
BOOTSZ = '01'
Program Memory
BOOTSZ = '00'
Application Flash Section
Boot Loader Flash Section
0x0000
Flashend
Application Flash Section
Flashend
End RWW
Start NRWW
Application Flash Section
Boot Loader Flash Section
Boot Loader Flash Section
End RWW
Start NRWW
End RWW
Start NRWW
0x0000
End RWW, End Application
Start NRWW, Start Boot Loader
Application Flash SectionApplication Flash Section
Application Flash Section
Read-While-Write SectionNo Read-While-Write Section Read-While-Write SectionNo Read-While-Write Section
Read-While-Write SectionNo Read-While-Write SectionRead-While-Write SectionNo Read-While-Write Section
End Application
Start Boot Loader
End Application
Start Boot Loader
End Application
Start Boot Loader
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Note: 1. “ 1” means unprogrammed, “0” means programmed
Note: 1. “ 1” means unprogrammed, “0” means programmed
28.5 Entering the Boot Loader Program
The bootloader can be executed with three different conditions:
28.5.1 Regular application conditions.
A jump or call from the application program. This may be initiated by a trigger such as a com-
mand received via USART, SPI or USB.
28.5.2 Boot Reset Fuse
The Boot R eset Fuse (BOOT RST) can be pr ogrammed so t hat the Rese t Vector is point ing to
the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset.
After the application code is loaded, the program can start executing the application code. Note
that the fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse
Table 28-2. Boot Lock Bit0 Protection Modes (Ap plication Section)(1)
BLB0 Mode BLB02 BLB01 Protection
111
No restrictions for SPM or (E)LPM accessing the
Application section.
2 1 0 SPM is not allowed to write to the Application section.
300
SPM is not allowed to write to the Application section, and
(E)LPM e xecuting from the Boot Loader section is not
allowed to read from the Application section. If Interrupt
Vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
401
(E)LPM e xecuting from the Boot Loader section is not
allowed to read from the Application section. If Interrupt
Vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
Table 28-3. Boot Lock Bit1 Protection Modes ( Boot Loader Section)(1)
BLB1 Mode BLB12 BLB11 Protection
111
No restrictions for SPM or (E)LPM accessing the Boot
Loader section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
300
SPM is not allowed to write to the Boot Loader section,
and (E)LPM executing from the Application section is not
allowed to read from the Boot Loader section. If Interrupt
Vectors are placed in the Appli c ation section, interrupts
are disabled while ex ecuting from the Boot Loader section.
401
(E)LPM e xecuting from the Application se ction is not
allowed to read from the Boot Loader section. If Interrupt
Vectors are placed in the Appli c ation section, interrupts
are disabled while ex ecuting from the Boot Loader section.
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is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can
only be changed through the serial or parallel programming interface.
Note: 1. “ 1” means unprogrammed, “0” means programmed
28.5.3 External Hardware conditions
The Hardware Boot Enable Fuse (HWBE) can be programmed (See Table 28-5 ) so that upon
special hardware conditions under reset, the bootloader execution is forced after reset.
Note: 1. “ 1” means unprogrammed, “0” means programmed
When the HWBE fuse is enable the ALE/HWB pin is configured as input during reset and sam-
pled during reset rising edge. When AL E/HWB pin is ‘0’ durin g reset rising edg e, the reset vect or
will be set as the Boot Loader Reset address and the Boot Loader will be executed (See Figures
28-3).
Table 28-4. Boot Reset Fuse(1)
BOOTRST Reset Address
1 Reset Vector = Appl ication Reset (address 0x0000)
0 Reset Vector = Boot Loader Reset (see Tabl e 28-8 on page 364)
Table 28-5. Hardware Boot Enable Fuse(1)
HWBE Reset Address
1ALE/HWB
pin can not be used to force Boot Loader execution after reset
0ALE/HWB
pin is used during reset to force bootloader execution after reset
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Figure 28-3. Boot Process Description
28.5.4 Store Program Memory Control and Status Register – SPMCSR
The Store Progr am Memory Contro l and Status Regist er contains the co ntrol bits nee ded to con-
trol the Boot Load e r oper at i on s.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Eras e or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. see “Reading
the Signature Row fro m Sof twa re” on pag e 360 fo r details. An SPM inst ruction within four cycles
HWBE
BOOTRST ?
Ext. Hardware
Conditions ?
Reset Vector = Application Reset Reset Vector =Boot Lhoader Reset
?
RESET
ALE/HWB
tSHRH tHHRH
Bit 7 6 5 4 3 2 1 0
SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR
Read/Write R/W R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use
and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SPMEN will be cleared). Then, if
the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while
the Flash is busy with a Page Erase or a Pa ge Write (SPMEN is set). If the RWWSRE bit is writ-
ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will
be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is writt en to one at the same t ime as SPMEN, t he next SPM instru ctio n within f our clock
cycles sets Boot Lock bits, accor ding t o the d ata in R0. The dat a in R1 and th e addr ess in th e Z-
pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock
bit set, or if no SPM instruction is executed within four clock cycles.
An (E)LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR
Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See “Reading the Fuse and Lock Bits from Software” on page 360 for
details.
• Bit 2 – PGWRT: Page Write
If this bit is writt en to one at the same t ime as SPMEN, t he next SPM instru ctio n within f our clock
cycles executes Page Write, with the data stored in the temporary buffer. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit
will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is
addressed.
• Bit 1 – PGERS: Page Erase
If this bit is writt en to one at the same t ime as SPMEN, t he next SPM instru ctio n within f our clock
cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The
data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,
or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation if the NRWW section is addressed.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSE T, PGWRT’ or PGERS, the followi ng SPM instruction will have a spe-
cial meaning, see description above. If only SPMEN is written, the following SPM instruction will
store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of
the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,
or if no SPM instruct ion is executed with in fo ur clo ck cycles. Durin g Page Era se and Pa ge Wr ite,
the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
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Note: Only one SPM instruction should be active at any time.
28.6 Addressing the Flash During Self-Programming
The Z-pointer is used to addr ess the SPM comm ands. The Z p ointer consists of the Z-regis ters
ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is
implementation dependent. Note that the RAMPZ register is only implemented when the pro-
gram space is larger tha n 64K byt es.
Since the Flash is organized in pages (see Table 29-11 on page 372), the Program Counter can
be treated as havin g two different sections. One sect ion, consisting of the least signif icant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is shown in Figure 28-4. Note that the Page Erase and Page Write operations are
addressed independently. Therefore it is of major importance that the Boot Loader software
addresses the same page in both the Page Erase and Pa ge Write operation. Once a program-
ming operation is initiated, the address is latched and the Z-pointer can be used for other
operations.
The (E)LPM instruction use the Z-pointer to store the address. Since this instruction addresses
the Flash byte-by-byte, also bit Z0 of the Z-pointer is used.
Figure 28-4. Addressing the Flash During SPM(1)
Bit 2322212019181716
15 14 13 12 11 10 9 8
RAMPZ RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0
ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8
ZL (R30)Z7Z6Z5Z4Z3Z2Z1Z0
76543210
PROGRAM MEMORY
0123
Z - POINTER
BIT
0
ZPAGEMSB
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
ZPCMSB
INSTRUCTION WORD
PAGE PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PAGE
PCWORDPCPAGE
PCMSB PAGEMSB
PROGRAM COUNTER
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Note: 1. The different variables used in Figure 28-4 are listed in Table 28-10 on page 365.
28.7 Self-Programming the Flash
The program memory is updated in a page by page fashion. Before programming a page with
the data stored in th e temporary page buf fer, the page must be erased. The temp orary page bu f-
fer is filled one word at a time using SPM and the buffer can be filled either before the Page
Erase command or between a Page Erase and a Page Writ e operation:
Alternative 1, fill the buffer before a Page Erase
• Fill temporary page buffer
• Perform a Page Erase
• Perform a Page Write
Alternative 2, fill the buffer after Page Erase
• Perform a Page Erase
• Fill temporary page buffer
• Perform a Page Write
If only a part of t he page needs to be changed, the rest of the page must be stored (for example
in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,
the Boot Loader pr ovides an effe ctive Rea d- Modify- Wr ite fe at ure which allo ws t he use r soft ware
to first read the page, do the necessary changes, and then write back the modified data. If alter-
native 2 is used, it is not p ossible to read the old data while loading since the page is already
erased. The temporary page buffer can be accessed in a random sequence. It is essential that
the page addre ss used in both the Page Er ase and Page Write operat ion is addressing th e same
page. See “Simple Assembly Code Example for a Boot Loader” on page 362 for an assembly
code example.
28.7.1 Performing Page Erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Othe r bits in the Z-pointer will
be ignored during this operation.
• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
• Page Erase to the NRWW section: The CPU is halted during the operation.
28.7.2 Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The
content of PCWORD in the Z-register is used to address the data in the temporary buffer. The
temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in
SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than
one time to each addr ess without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
28.7.3 Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
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The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
• Page Write to the RWW section: The NRWW section can be read during the Page Write.
• Page Write to the NRWW section: The CPU is halted during the operation.
28.7.4 Using the SPM Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling
the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should
be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
blocked for reading. How to move the interrupts is described in “Interrupts” on page 68.
28.7.5 Consideration While Updating BLS
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is r ecommended to progra m the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
28.7.6 Prevent Reading the RWW Section During Self-Programming
During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW
section is busy. During Se lf-Pro grammin g the In terr upt Vect or t able should b e move d to the BLS
as described in “Interrupts” on page 68, or the interrupts must be disabled. Before addressing
the RWW section after the programming is completed, the user software must clear the
RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on
page 362 for an example.
28.7.7 Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits
are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-
ware update by the MCU.
See Table 28-2 and Table 28-3 for how the different settings of the Boot Loader bits affect the
Flash acces s .
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with 0x0001 (same as used fo r reading t he lOck bits). For future compatibility it
is also recommended to set bit s 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When pro-
gramming the Lock bits the entire Flash can be read during the operation.
28.7.8 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
Bit 76543210
R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1
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is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleare d before writing to the SPMCSR Register.
28.7.9 Reading the Fuse and Lock Bits from Software
It is possib le to read bo th the Fuse and Loc k bits from so ftware. To read t he Lock bits, lo ad the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an (E)LPM
instruction is e xecuted within t hree CPU cycles af ter the BLBSET and SPM EN bits are set in
SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and
SPMEN bits will auto-clear upon completion of reading the Lock bits or if no (E)LPM instruction
is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles.
When BLBSET and SPMEN are cleared, (E)LPM will work as described in the Instruction set
Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read th e Fuse Low byte, load the Z-pointer with 0 x0000 and set the BLBSET
and SPMEN bits in SPMCSR. When an (E)LPM instruction is executed within three cycles after
the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will
be loaded in the destination register as shown below. Refer to Table 29-5 on page 368 for a
detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an (E)LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
shown below. Refe r t o Tab le 2 9- 4 o n pa ge 368 for detailed description and mapping of the Fuse
High byte.
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an (E)LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SP MCSR,
the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown
below. Refer to Table 29-3 on page 367 for detailed description and mapping of the Extended
Fuse byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
28.7.10 Reading the Signature Row from Software
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in Table 28-6 on page 361 and set the SIGRD and SPMEN bits in SPMCSR. When an
LPM instruction is execut ed within thr ee CPU cycles after the SI GRD and SPMEN b its ar e se t in
SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and
SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM
instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will
work as described in the Instruction set Manual
Bit 76543210
Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1
Bit 76543210
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Bit 76543210
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
Bit 76543210
Rd – – – – – EFB2 EFB1 EFB0
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ATmega32U6/AT90USB64 /128 includes a unique 10 bytes serial numb er located in the signa-
ture row. This unique serial number can be used as a USB serial number in the device
enumeration process. The pointer addresses to access this unique serial number are given in
Table 28-6 on page 361..
Note: All other addresses are reserved for future use.
28.7.11 Preventi n g Fl as h Cor ru pt io n
During periods of low VCC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and th e same design solutions should be applied.
A Flash program co rr up tion can be cau sed b y two situ a tions when th e voltag e is too low. F irst , a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendatio ns (one is
sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader
Lock bits to prevent any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enab ling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low VCC reset protection circuit
can be used. If a r eset occurs while a write oper atio n is in prog r ess , the write oper ation
will be completed provided that the power supply voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-
v ent the CPU from attempti ng to decode and e x ecute instructions , eff ectiv ely protecting
the SPMCSR Register and thus the Flash from unintentional writes .
28.7.12 Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 28-7 shows the typical pro-
gramming time for Flash accesses fr om the CPU.
Table 28-6. Signature Row Addressing
Signature Byte Z-P o inter Address
Device Signature Byte 1 0x0000
Device Signature Byte 2 0x0002
Device Signature Byte 3 0x0004
RC Oscillator Calibration Byte 0x0001
Unique Serial Number From 0x000E to 0x0018
Table 28-7. SPM Programming Time
Symbol Min Programming Time Max Programming Time
Flash write (Page Erase, Page Write,
and write Lock bits by SPM) 3.7 ms 4.5 ms
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28.7.13 Simple Assembly Code Example for a Boot Loader
;- the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y-pointer
; the first data location in Flash is pointed to by the Z-pointer
;- error handling is not included
;- the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;- registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcsrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;- it is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
Write_page:
; Page Erase
ldi spmcsrval, (1<<PGERS) | (1<<SPMEN)
call Do_spm
; re-enable the RWW section
ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN)
call Do_spm
; transfer data from RAM to Flash page buffer
ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
Wrloop:
ld r0, Y+
ld r1, Y+
ldi spmcsrval, (1<<SPMEN)
call Do_spm
adiw ZH:ZL, 2
sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256
brne Wrloop
; execute Page Write
subi ZL, low(PAGESIZEB) ;restore pointer
sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256
ldi spmcsrval, (1<<PGWRT) | (1<<SPMEN)
call Do_spm
; re-enable the RWW section
ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN)
call Do_spm
; read back and check, optional
ldi looplo, low(PAGESIZEB) ;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
subi YL, low(PAGESIZEB) ;restore pointer
sbci YH, high(PAGESIZEB)
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Rdloop:
lpm r0, Z+
ld r1, Y+
cpse r0, r1
jmp Error
sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256
brne Rdloop
; return to RWW section
; verify that RWW section is safe to read
Return:
in temp1, SPMCSR
sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet
ret
; re-enable the RWW section
ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN)
call Do_spm
rjmp Return
Do_spm:
; check for previous SPM complete
Wait_spm:
in temp1, SPMCSR
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcsrval determines SPM action
; disable interrupts if enabled, store status
in temp2, SREG
cli
; check that no EEPROM write access is present
Wait_ee:
sbic EECR, EEWE
rjmp Wait_ee
; SPM timed sequence
out SPMCSR, spmcsrval
spm
; restore SREG (to enable interrupts if originally enabled)
out SREG, temp2
ret
28.7.14 ATmega32U6/AT90USB64/128 Boot Loader Parameters
In Table 28-8 through Table 28-10, the parameters used in the description of the Self-Program-
ming are given.
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Note: 1. The different BOOTSZ Fuse configurations are shown in Figure 28-2
Note: 1. F or details about these two section, see “NRWW – No Read-While-Write Section” on pag e
350 and “RWW – Read-W hile-Write Section” on page 350.
Table 28-8. Boot Size Configuration (Word Addresses)(1)
Device
BOOTSZ1
BOOTSZ0
Boot Size
Pages
Application
Flash Section
Boot Loader
Flash Section
End
Application
Section
Boot
Reset Address
(Start Boot
Loader Section)
ATmega32U6
1 1 256 words 4 0x0000 - 0x3EFF 0x3F00 - 0x3FFF 0x3EFF 0x3F00
1 0 512 words 8 0x0000 - 0x3DFF 0x3E00 - 0x3FFF 0x3DFF 0x3E00
0 1 1024 words 16 0x0000 - 0x3BFF 0x3C00 - 0x3FFF 0x3BFF 0x3C00
0 0 2048 words 32 0x0000 - 0x37FF 0x3800 - 0x3FFF 0x37FF 0x3800
AT90USB64
1 1 512 words 4 0x0000 - 0x7DFF 0x7E00 - 0x7FFF 0x7DFF 0x7E00
1 0 1024 words 8 0x0000 - 0x7BFF 0x7C00 - 0x7FFF 0x7BFF 0x7C00
0 1 2048 words 16 0x0000 - 0x77FF 0x7800 - 0x7FFF 0x77FF 0x7800
0 0 4096 words 32 0x0000 - 0x6FFF 0x700 0 - 0x7FFF 0x6FFF 0x7000
AT90USB128
1 1 512 words 4 0x0000 - 0xFDFF 0xFE00 - 0xFFFF 0xFDFF 0xFE00
1 0 1024 words 8 0x0000 - 0xFBFF 0xFC00 - 0xFFFF 0xFBFF 0xFC00
0 1 2048 words 16 0x0000 - 0xF7FF 0xF800 - 0xFFFF 0xF7FF 0xF800
0 0 4096 words 32 0x0000 - 0xEFFF 0xF000 - 0xFFFF 0xEFFF 0xF000
Table 28-9. Read-While-Write Limit (Word Addresses)(1)
Device Section Pages Address
ATmega32U6 Read-While-Write section (RWW) 224 0x0000 - 0x37FF
No Read-While-Write section (NRWW) 32 0x3800 - 0x3FFF
AT90USB64 Read-While-Write section (RWW) 224 0x0000 - 0x6FFF
No Read-While-Write section (NRWW) 32 0x7000 - 0x7FFF
AT90USB28 Read-While-Write section (RWW) 480 0x0000 - 0xEFFF
No Read-While-Write section (NRWW) 32 0xF000 - 0xFFFF
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Note: 1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
See “Addressing the Flash During Self-Programming” o n page 357 for details about the use of
Z-pointer during Self-Programming.
Table 28-10. Explanation of different variables used in Figure 28-4 and the mapping to the Z-
pointer
Variable Corresponding
Z-value Description(1)
PCMSB 16 Most significant bit in the Program Counter. (The
Program Counter is 17 bits PC[16:0])
PAGEMSB 6 Most significant bit which is used to address the
words within one page (128 words in a page requires
seven bits PC [6:0]).
ZPCMSB Z17 Bit in Z-pointer that is mapped to PCMSB. Because
Z0 is not used, the ZPCMSB equals PCMSB + 1.
ZPAGEMSB Z7 Bit in Z-pointer that is mapped to PCMSB. Because
Z0 is not used, the ZPAGEMSB equals PAGEMSB +
1.
PCPAGE PC[16:7] Z17:Z8 Program Counter page address: Page select, for
Page Erase and Page Wr ite
PCWORD PC[6:0] Z7:Z1 Program Counter word address: Word select, for
filling temporary buffer (must be zero during Page
Write operation)
PCMSB 15 Most significant bit in the program counter. (The program
counter is 16 bits PC[15:0])
PAGEMSB 6 Most significant bit which is used to address the words
within one page (128 words in a page requires 7 bits PC
[6:0]).
ZPCMSB Z16 Bit in Z-register that is mapped to PCMSB. Because Z0 is
not used, the ZPCMSB equals PCMSB + 1.
ZPAGEMSB Z7 Bit in Z-register that is mapped to PAGEMSB. Because Z0
is not used, the ZPAGEMSB equals PAGEMSB + 1.
PCPAGE PC[15:7] Z16:Z7 Program counter page address: Page select, for Page
Erase and Page Write.
PCWORD PC[6:0] Z7:Z1 Program counter word address: Word select, for filling
temporary buffer (must be zero during PAGE WRITE
operation).
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29. Memory Programming
29.1 Program And Data Memory Lock Bits
The ATmega32U6/AT90USB64/128 provides six Lock bits which can be left unprogrammed
(“1”) or can be programmed (“0”) to obtain the additional features listed in Table 29-2. The Lock
bits can only be erased to “1” with the Chip Erase command.
Note: 1. “ 1” means unprogrammed, “0” means programmed
Table 29-1. Lock Bit Byte(1)
Lock Bit Byte Bit No Description Default Value
7 – 1 (unprogrammed)
6 – 1 (unprogrammed)
BLB12 5 Boot Lock bit 1 (unprogrammed)
BLB11 4 Boot Lock bit 0 (programmed)
BLB02 3 Boot Lock bit 1 (unprogrammed)
BLB01 2 Boot Lock bit 1 (unprogrammed)
LB2 1 Lock bit 0 (programmed)
LB1 0 Lock bit 0 (programmed)
Table 29-2. Lock Bit Protection Modes(1)(2)
Memory Lock Bi ts Protectio n Type
LB Mode LB2 LB1
1 1 1 No memory lock features enabled.
210
Further programming of the Flash and EEPROM is
disabled in Parallel and Serial Programming mode. The
Fuse bits are locked in both Serial and Parallel
Programming mode.(1)
300
Further programming and verification of the Flash and
EEPROM is disabled in Parallel and Serial Programming
mode. The Boot Lock bits and Fuse bits are lock ed in both
Serial and Parallel Programming mode.(1)
BLB0 Mode BLB02 BLB01
111
No restrictions for SPM or (E)LPM accessing the
Application section.
2 1 0 SPM is not allowed to write to the Application section.
300
SPM is not allowed to write to the Application section, and
(E)LPM e xecuting from the Boot Loader section is not
allowed to read from the Application section. If Interrupt
Vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
401
(E)LPM e xecuting from the Boot Loader section is not
allowed to read from the Application section. If Interrupt
Vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
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Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
29.2 Fuse Bits The ATm ega32U6/AT90USB64/128 has four Fuse bytes. Ta ble 29-3 - Table 29-5 describe
briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that
the fuses are read as logi cal zero, “0”, if they are programmed.
Note: 1. See Table 8-2 on page 60 for BODLEVEL Fuse decoding.
BLB1 Mode BLB12 BLB11
111
No restrictions for SPM or (E)LPM accessing the Boot
Loader section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
300
SPM is not allowed to write to the Boot Loader section,
and (E)LPM executing from the Application section is not
allowed to read from the Boot Loader section. If Interrupt
Vectors are placed in the Appli c ation section, interrupts
are disabled while ex ecuting from the Boot Loader section.
401
(E)LPM e xecuting from the Application se ction is not
allowed to read from the Boot Loader section. If Interrupt
Vectors are placed in the Appli c ation section, interrupts
are disabled while ex ecuting from the Boot Loader section.
Table 29-2. Lock Bit Protection Modes(1)(2) (Continued)
Memory Lock Bi ts Protectio n Type
Table 29-3. Extended Fuse Byte (0xF3)
Fuse Low Byte Bit No Description Default Value
–7– 1
–6– 1
–5– 1
–4– 1
HWBE 3 Hardware Boot Enable 0 (programmed)
BODLEVEL2(1) 2 Brown-out Detector trigger level 0 (programmed)
BODLEVEL1(1) 1 Brown-out Detector trigger level 1 (unprogrammed)
BODLEVEL0(1) 0 Brown-out Detector trigger level 1 (unprogrammed)
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Note: 1. The SPIEN Fuse is not accessible in serial programming mode.
2. See Table 28-8 on page 364 for details.
3. See “Watchdog Timer Control Register - WDTCSR” on page 65 for details.
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to
be running in all sle ep modes. This may increase the power consumption.
Note: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source
(258K CK + 4.1ms). See Table 8-1 on pag e 58 for details.
2. The default setting of CKSEL3..0 results in External Crystal Oscillator @ 8 MHz. See Table 6-
1 on page 40 for details.
3. The CKOUT Fuse allow the system clock to be output on PORTC7. See “Clock Output Buffer”
on page 46 for details.
4. See “System Clock Prescaler” on page 47 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
Table 29-4. Fuse High Byte (AT90USB128 : 0x99 - AT90USB64 : 0x9B)
Fuse High Byte Bit No Description Default Value
OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled)
JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled)
SPIEN(1) 5Enable Serial Program and Data
Downloading 0 (programmed, SPI prog. enabled)
WDTON(3) 4 Watchdog Timer always on 1 (unprogrammed)
EESAVE 3 EEPROM memory is preserved
through the Chip Erase 1 (unprogrammed, EEPROM not
preserved)
BOOTSZ1 2 Select Boot Size (see Table 29-6
for details) 0 (programmed)(2)
BOOTSZ0 1 Select Boot Size (see Table 29-6
for details)
0 (programmed)(2) (AT90USB128
and ATmega32U6)
1 (unprogrammed)(2) (AT90USB64)
BOOTRST 0 Sel ect Reset Vector 1 (unprogrammed)
Table 29-5. Fuse Low Byte (0x5E)
Fuse Low Byte Bit No Description Default Value
CKDIV8(4) 7 Divide clock by 8 0 (programmed)
CKOUT(3) 6 Clock output 1 (unprogrammed)
SUT1 5 Select start-up time 0 (p rogrammed)(1)
SUT0 4 Select start-up time 1 (unprogrammed)(1)
CKSEL3 3 Select Clock source 1 (unprogrammed)(2)
CKSEL2 2 Select Clock source 1 (unprogrammed)(2)
CKSEL1 1 Select Clock source 1 (unprogrammed)(2)
CKSEL0 0 Select Clock source 0 (programmed)(2)
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29.2.1 Latching of Fuses
The fuse values are latched when the device enters programming mode and chang es of the
fuse values will have no effect until the part leaves Programming mode. This does not apply to
the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on
Power-up in Normal mode.
29.3 Signature Bytes
All Atmel microcontrollers have a three- byte signature code which identifies the device. This
code can be read in both serial and parallel mode, also when the device is locked. The three
bytes reside in a separate address space.
AT90USB128x Signat ure Bytes:
1. 0x000: 0x1E (indicates manufactured by Atmel).
2. 0x001: 0x97 (indicates 128KB Flash memory).
3. 0x002: 0x82 (indicates AT90USB128x device).
AT90USB64x Signature Bytes:
1. 0x000: 0x1E (indicates manufactured by Atmel).
2. 0x001: 0x96 (indicates 64KB Flash memory).
3. 0x002: 0x82 (indicates AT90USB64x device).
ATMega32U6 Signature Bytes:
1. 0x000: 0x1E (indicates manufactured by Atmel).
2. 0x001: 0x95 (indicates 32KB Flash memory).
3. 0x002: 0x88 (indica tes ATMega32U6 device).
29.4 Calibration Byte
The ATmega32U6/AT90USB64/128 has a byte calibration value for the internal RC Oscillator.
This byte resid es in the high byte of addr ess 0x000 in the signat ure address space. Dur ing reset,
this byte is automatically written into the OSCCAL Register to ensure correct frequency of the
calibrated RC Oscillator.
29.5 Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits in the ATmega32U6/AT90USB64/128. Pulses
are assumed to be at least 250 ns unless otherwise noted.
29.5.1 Signal Names In this section, some pins of the ATmeg a32U6 /AT90USB64/128 are refere nced by signal names
describing their functionality during parallel programming, see Figure 29-1 and Table 29-6. Pins
not described in the following table are reference d by pi n names.
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The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in Table 29-9.
When pulsing WR or OE, the com mand loaded determines the action executed. The different
commands are shown in Table 29-10.
Figure 29-1. Parallel Programming(1)
Note: 1. Unused Pins should be left floating.
Table 29-6. Pin Name Mapping
Signal Name in
Programming Mode Pin Name I/O Function
RDY/BSY PD1 O 0: Device is busy programming, 1: Device is
ready for new command.
OE PD2 I Output Enable (Active low).
WR PD3 I Write Pulse (Active low).
BS1 PD4 I Byte Se lect 1.
XA0 PD5 I XTAL Action Bit 0.
XA1 PD6 I XTAL Action Bit 1.
PAGE L PD7 I Program Memory and EEPROM data P age Load.
BS2 PA0 I Byte Select 2.
DATA PB7-0 I/O Bi-directional Data bus (Output when OE is low).
VCC
+5V
GND
XTAL1
PD1
PD2
PD3
PD4
PD5
PD6
PB7 - PB0 DATA
RESET
PD7
+12 V
BS1
XA0
XA1
OE
RDY/BSY
PAGEL
PA0
WR
BS2
AVCC
+5V
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,
Table 29-7. BS2 and BS1 Encoding
BS2 BS1
Flash /
EEPROM
Address
Flash Data
Loading /
Reading Fuse
Programming Reading Fuse
and Lock Bits
0 0 Low Byte Low Byte Low Byte Fuse Low Byte
0 1 High Byte High Byte High Byte Lockbits
10Extended High
Byte Reserved Extended Byte Extended Fuse
Byte
1 1 Reser ved Reserved Reserved Fuse High Byte
Table 29-8. Pin Values Used to Enter Programming Mode
Pin Symbol Value
PAGEL Prog_enable[3] 0
XA1 Prog_enable[2] 0
XA0 Prog_enable[1] 0
BS1 Prog_enable[0] 0
Table 29-9. XA1 and XA0 Enoding
XA1 XA0 Action when XTAL1 is Pulsed
00
Load Flash or EEPROM Address (High or low address byte
deter mined by BS2 and BS1).
0 1 Load Data (High or Low data byte for Flash determined by BS1).
1 0 Load Command
1 1 No Action, Idle
Table 29-10. Command Byte Bit Encoding
Command Byte Command Executed
1000 0000 Chip Erase
0100 0000 Write Fuse bits
0010 0000 Write Lock bits
0001 0000 Write Flash
0001 0001 Write EEPROM
0000 1000 Read Signature Bytes and Calibration byte
0000 0100 Read Fuse and Lock bits
0000 0010 Read Flash
0000 0011 Read EEPROM
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29.6 Parallel Programming
29.6.1 Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply 4.5 - 5. 5V be twee n VCC and GND.
2. Set RESET to “0” and toggle XTAL1 at least six times.
3. Set the Prog_enable pins listed in Table 29-8 on page 371 to “0000” and wait at least
100 ns.
4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after
+12V has been applied to RESET, will cause the device to fail entering programming
mode.
5. Wait at least 50 µs before sending a new command.
29.6.2 Considerations for Efficient Programming
The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
• The command need s only be loaded once when writing or reading multiple memory
locations.
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the
EESAVE Fuse is programmed) and Flash after a Chip Erase.
• Address high byte needs only be loaded before programming or reading a new 256 word
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
29.6.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lo ck bit s are
not reset until the program memory has been completely erased. The Fuse bits are not
Table 29-11. No. of Words in a Page and No. of Pages in the Flash
Flash Size Page Size PCWORD No. of
Pages PCPAGE PCMSB
16K words (32K bytes) 64 words PC[6:0] 256 PC[13:7] 13
32K words (64K bytes) 128 words PC[6:0] 256 PC[14:7] 14
64K words (128K bytes) 128 words P C[6:0] 512 PC[1 5:7] 15
Table 29-12. No. of Words in a Page and No. of Pages in the EEPROM
EEPROM Size Page Size PCWORD No. of
Pages PCPAGE EEAMSB
1K bytes 4 bytes EEA[2:0] 256 EEA[9:3] 9
2K bytes 8 bytes EEA[2:0] 256 EEA[10:3] 10
4K bytes 8 bytes EEA[2:0] 512 EEA[11:3] 11
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changed. A Chip Erase must be performed before the Flash and/or EEPROM are
reprogrammed.
Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Load Command “Chip Erase”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.
6. Wait until RDY/BSY goes high before loading a new command.
29.6.4 Programming the Flash
The Flash is organized in pages, see Table 29-11 on page 372. When programming the Flash,
the program data is latched into a page buffer. This allows one page of program data to be pro-
grammed simultaneously. The following procedure describes how to program the entire Flash
memory:
A. Load Command “Write Flash”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte (Address bits 7..0)
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS2, BS1 to “00”. This selects the address low b yte.
3. Set DATA = Address low byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set D ATA = Data low byte (0x00 - 0xFF).
3. Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selec ts hig h da ta byte.
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selec ts hig h da ta byte.
2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 29-3 for signal
waveforms)
F. Repeat B through E unt il the entire buffer is filled or until all data within the page is loaded.
While the lower bits in t he addre ss are mapped t o words within the pa ge, th e higher b its addr ess
the pages within the FLASH. This is illustrated in Figure 29-2 on page 374. Note that if less than
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eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)
in the address low byte are used to address the page when performing a Page Write.
G. Load Address High byte (Address bits15..8)
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS2, BS1 to “01”. This selects the address high byte.
3. Set DATA = Address high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address high byte.
H. Load Address Extended High byte (Address bits 23..16)
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS2, BS1 to “10”. This selects the address extended high byte.
3. Set DATA = Address extended high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address high byte.
I. Program Page
1. Set BS2, BS1 to “00”
2. Give WR a negative pulse. This starts programming of the entire page of data.
RDY/BSY goes low.
3. Wait until RDY/BSY goes high (See Figure 29-3 for signal waveforms).
J. Repeat B through I until the entire Flash is programmed or until all data has been
programmed.
K. End Page Programming
1. 1. Set XA1, XA0 to “10”. This en ables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals
are reset.
Figure 29-2. Addressing the Flash Which is Organized in Pages(1)
PROGRAM MEMORY
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
INSTRUCTION WORD
PAG E PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PAG E
PCWORDPCPAGE
PCMSB PAGEMSB
PROGRAM
COUNTER
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Note: 1. PCPAGE and PCWORD are listed in Table 29-11 on page 372.
Figure 29-3. Programming the Flash Waveforms(1)
Note: 1. “XX” is don’t care. The letters refer to the programming description above.
29.6.5 Programming the EEPROM
The EEPROM is organized in pages, see Table 29-12 on page 372. When programming the
EEPROM, the program data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM data memory is as
follows (refer to “Programming the F lash” on page 373 for details on Com mand, Address and
Data loading):
1. A: Load Command “0001 0001”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. C: Load Data (0x00 - 0xFF).
5. E: Latch data (give PAGEL a positive pulse).
K: Repeat 3 through 5 until the entire buffer is filled.
L: Program EEPROM page
1. Set BS2, BS1 to “00”.
2. Give WR a negativ e pulse. This starts programming of the EEPROM page. RDY/BSY
goes low.
3. Wait until to RDY/BSY goes high before programming the next page (See Figure 29-4
for signal waveforms).
RDY/BSY
WR
OE
RESET +12V
PAGEL
BS2
0x10 ADDR. LOW ADDR. HIGH
DATA DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH
XA1
XA0
BS1
XTAL1
XX XX XX
ABCDEBCDEG
F
ADDR. EXT.H
HI
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Figure 29-4. Programming the EEPROM Waveforms
29.6.6 Reading the Flash
The algorithm for reading the Flash m emory is as follows (refer to “Programming the Flash” on
page 373 for details on Command and Address loading):
1. A: Load Command “0000 0010”.
2. H: Load Address Extended Byte (0x00- 0xFF).
3. G: Load Address High Byte (0x00 - 0xFF).
4. B: Load Address Low Byte (0x00 - 0xFF).
5. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
6. Set BS to “1”. The Flash word high byte can now be read at DATA.
7. Set OE to “1”.
29.6.7 Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash”
on page 373 for details on Command and Address loading):
1. A: Load Command “0000 0011”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.
5. Set OE to “1”.
29.6.8 Pro gramming the Fuse Low Bits
The algorith m for progr amming th e Fuse Lo w bits is as follows (ref er to “ Programmin g the Flash”
on page 373 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Give WR a negative pulse and wa it for RDY/BSY to go high.
RDY/BSY
WR
OE
RESET +12V
PAGEL
BS2
0x11 ADDR. HIGH
DATA ADDR. LOW DATA ADDR. LOW DATA XX
XA1
XA0
BS1
XTAL1
XX
AGBCEBC EL
K
377
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29.6.9 Programming the Fuse High Bits
The algorithm for programming the Fuse High bits is as follows (refer to “Programming the
Flash” on page 373 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS2, BS1 to “01”. This selects high data byte.
4. Give WR a negative pulse and wa it for RDY/BSY to go high.
5. Set BS2, BS1 to “00”. This selects low data byte.
29.6.10 Programming the Extended Fuse Bits
The algorithm for programming the Extended Fuse bits is as follows (refer to “Progr amming th e
Flash” on page 373 for details on Command and Data loading):
1. 1. A: Load Command “0100 0000”.
2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. 3. Set BS2, BS1 to “10”. This selects extended data byte.
4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. 5. Set BS2, BS1 to “00”. This selects low data byte .
Figure 29-5. Programming the FUSES Waveforms
29.6.11 Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on
page 373 for details on Command and Data loading):
1. A: Load Command “0010 0000”.
2. C: Load Data Lo w Byte. Bit n = “0” prog r a ms the Lock bit. If LB mode 3 is programmed
(LB1 and LB2 is programmed), it is not po ssible to program the Boot Lock bits by any
External Progr amming mode.
3. Give WR a negative pulse and wa it for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
RDY/BSY
WR
OE
RESET +12V
PAGEL
0x40
DATA
DATA XX
XA1
XA0
BS1
XTAL1
AC
0x40 DATA XX
AC
Write Fuse Low byte Write Fuse high byte
0x40 DATA XX
AC
Write Extended Fuse byte
BS2
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29.6.12 Reading the Fuse and Lock Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash”
on page 373 for details on Command loading):
1. A: Load Command “0000 0100”.
2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read
at DATA (“0” means programmed).
3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read
at DATA (“0” means programmed).
4. Set OE to “0”, and BS2, BS1 to “10”. The status of the Extended Fuse bits can now be
read at DATA (“0” means programmed).
5. Set OE to “0”, and BS2, BS1 to “01”. The status of the Lock bits can now be read at
DATA (“0” means programmed).
6. Set OE to “1”.
Figure 29-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
29.6.13 Reading the Signature Bytes
The algorithm for reading the Signature bytes is as follows (refer to “Programming t he F l as h” on
page 373 for details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS to “0”. The selected Signatur e byte can now be read at DATA.
4. Set OE to “1”.
29.6.14 Reading the Calibration Byte
The algorithm for reading the Calibration byte is as follows (refer to “Programming th e F lash” on
page 373 for details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibrati on byte can now be read at DATA.
4. Set OE to “1”.
Lock Bits 0
1
BS2
Fuse High Byte
0
1
BS1
DATA
Fuse Low Byte 0
1
BS2
Extended Fuse Byte
379
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29.6.15 Parallel Programming Characteris tics
Figure 29-7. Parallel Programming Timing, Including some General Timing Requirements
Figure 29-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
Note: 1. The timing requirements shown in Figure 29-7 (i.e., t DVXH, tXHXL, and tXLDX) also apply to load-
ing operation.
Figure 29-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(1)
Data & Contol
(DATA, XA0/1, BS1, BS2)
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
WLBX
t
BVWL
WLRL
XTAL1
PAGEL
t
PLXH
XLXH
tt
XLPH
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE) LOAD DATA
(LOW BYTE) LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE) READ DATA
(LOW BYTE) READ DATA
(HIGH BYTE) LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ
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Note: 1. The timing requirements shown in Figure 29-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-
ing operation.
Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2. tWLRH_CE is valid for the Chip Erase command.
29.7 Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using a serial programming
bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, PDI
(input) and PDO (output). After RESET is set low, th e Pro gramm ing En able inst ructio n ne eds to
be executed fir st before program/e rase operations c an be executed. NO TE, in Table 29-14 o n
page 381, the pin mapping for serial programming is listed. Not all packages use the SPI pins
dedicated for the internal Serial Peripheral Interface - SPI.
Table 29-13. Parallel Programming Characteristics, VCC = 5V ± 10%
Symbol Parameter Min Typ Max Units
VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enable Current 250 μA
tDVXH Data and Control Valid before XTAL1 High 67 ns
tXLXH XTAL1 Low to XTAL1 High 200 ns
tXHXL XTAL1 Pulse Width High 150 ns
tXLDX Data and Control Hold after XTAL1 Low 67 ns
tXLWL XTAL1 Low to WR Low 0 ns
tXLPH XTAL1 Low to PAGEL high 0 ns
tPLXH PAGEL low to XTAL1 high 150 ns
tBVPH BS1 Valid before PAGEL High 67 ns
tPHPL PAGEL Pulse Width High 150 ns
tPLBX BS1 Hold after PAGEL Low 67 ns
tWLBX BS2/1 Hold after WR Low 67 ns
tPLWL PAGEL Low to WR Low 67 ns
tBVWL BS2/1 Valid to WR Low 67 ns
tWLWH WR Pulse Width Low 150 ns
tWLRL WR Low to RDY/BSY Low 0 1 μs
tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms
tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 ms
tXLOL XTAL1 Low to OE Low 0 ns
tBVDV BS1 Valid to DATA valid 0 250 ns
tOLDV OE Low to DATA Valid 250 ns
tOHDZ OE High to DATA Tri-stated 250 ns
381
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29.8 Serial Programming Pin Mapping
Figure 29-10. Serial Programming and Verify(1)
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
29.8.1 Serial Programming Algorithm
When writing serial data to the ATmega32U6/AT90USB64/128 , data is clocked on the rising
edge of SCK.
When reading data from the ATmega32U6/AT90USB64/128, data is clocked on the falling edge
of SCK. See Figure 29-11 for timing details.
To program and verify the ATmega32U6/AT90USB64/128 in the serial programming mode, the
following sequence is recommended (See four byte instruction formats in Table 29-16):
Table 29-14. Pin Mapping Serial Programming
Symbol Pins
(TQFP-64) I/O Description
PDI PB2 I Serial Data in
PDO PB3 O Seria l Data out
SCK PB1 I Serial Clock
VCC
GND
XTAL1
SCK
PDO
PDI
RESET
+1.8 - 5.5V
AVCC
+1.8 - 5.5V
(2)
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1. Power-up sequence:
Apply po w er bet w een VCC and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a posit ive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programm ing
Enable serial instruction to pin PDI.
3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third by te of the Progr amming Enab le instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time b y supplying the 7 LSB of the address and data togethe r with the Loa d Prog r am
Memory Page instruction. To ensure correct loading of the page, the dat a low by te must
be loaded before data high byte is applied for a given address. The Program Memory
P age is st ored b y loading th e Write Program Mem ory Page in struction with the addr ess
lines 15..8. Before issuing this command, make sure the instruction Load Extended
Address Byte has been used to define the MSB of the address. The extended address
byte is stored until the command is re-issued, i.e., the command needs only be issued
f or the first page , and when crossing the 64KW ord boundary. If polling (RDY/BSY) is not
used, the user must wait at least tWD_FLASH before issu ing the next page . (See Table 29-
15.) Accessing the serial programming interface before the Flash write operatio n com-
pletes can result in incorrect programming.
5. The EEPROM array is programmed one b yte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased bef ore new data is written. If polling is not used, the user must
wait at least tWD_EEPROM before issuing the next byte. (See Table 29-15.) In a chip
erased device, no 0xFFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selecte d address at serial outp ut PDO . When reading th e Flash memory,
use the instr uction Load Extended Address Byte to define the upper address byte,
which is not included in the Read Program Memory instruction. The extended address
byte is stored until the command is re-issued, i.e., the command needs only be issued
for the first page, and when crossing the 64KWord boundary.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
Table 29-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FLASH 4.5 ms
tWD_EEPROM 9.0 ms
tWD_ERASE 9.0 ms
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Figure 29-11. Serial Programming Waveforms
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUT
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Table 29-16. Serial Programming Instruction Set
Instruction
Instruction Format
OperationByte 1 Byte 2 Byte 3 Byte4
Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after
RESET goes low.
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
Load Extended Address Byte 0100 1101 0000 0000 cccc cccc xxxx xxxx Defines Extended Address Byte for
Read Program Memory and Write
Program Memory Page.
Read Program Memory 0010 H000 aaaa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from
Program memory at word address
c:a:b.
Load Program Memory Page
0100 H000 xxxx xxxx xxbb bbbb iiii iiii Write H (high or low) data i to Program
Memory page at word address b. Data
low byte must be loaded before Data
high byte is applied within the same
address.
Write Program Memory Page 0100 1100 aaaa aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at
address c:a:b.
Read EEPROM Memory 1010 0000 0000 aaaa bbbb bbbb oooo oooo Read data o from EEPROM memory at
address a:b.
Write EEPROM Memory 1100 0000 0000 aaaa bbbb bbbb iiii iiii Write data i to EEPROM memory at
address a:b.
Load EEPROM Memory
Page (page access)
1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page
buffer. After data is loaded, program
EEPROM page.
Write EEPROM Memory
Page (page access) 1100 0010 0000 aaaa bbbb bb00 xxxx xxxx Write EEPROM page at address a:b.
Read Lock bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1”
= unprogrammed. See Table 29-1 on
page 366 for details.
Write Lock bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits . Set bits = “0” to
program Lock bits . See Table 29-1 on
page 366 for details.
Read Signatu re Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.
Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram.
Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram.
Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram. See Table 29-3 on page
367 for details.
Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = progr ammed, “1”
= unprogrammed.
Read Fuse High bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = pro-
grammed, “1” = unprogrammed.
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Note: a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in,
x = don’t care
29.8.2 Serial Programming Characteri stics
For characteristics of the Serial Programming module see “SPI Timing Characteristics” on page
403.
29.9 Programming via the JTAG Interface
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of t he reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is
default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared.
Alternatively, if the JTD bit is set, the external reset can be fo rced low. Then, the JTD bit will be
cleared after two chip clocks, and the JTAG pins are available for programming. This provides a
means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-
tem Programming via the JTAG interface. Note that this technique can not be used when using
the JTAG pins for Boundary-scan or On-chip Debug. In thes e cases the JTAG pins must be ded-
icated for this purpose.
During programming the clock frequency of the TCK Input must be less than the maximum fre-
quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input
into a sufficiently low freq ue n cy.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
29.9.1 Programming Specific JTAG Instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Re gister is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in Figure 29-12.
Read Extended Fuse Bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = pro-
grammed, “1” = unprogrammed. See
Table 29-3 on page 367 for details.
Read Calibration Byte 0011 1000 000x xxxx 0000 0000 oooo oooo Read Calibration Byte
Poll RDY/BSY 1111 0000 0000 0000 xxxx xxxx xxxx xxxoIf o = “1”, a programming operation is
still busy. Wait until this bit returns to
“0” before applyi ng another command.
Table 29-16. Serial Programming Instruction Set (Continued)
Instruction
Instruction Format
OperationByte 1 Byte 2 Byte 3 Byte4
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Figure 29-12. State Machine Sequence for Changing the In struction Word
29.9.2 AVR_RESET (0xC)
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking
the device out from the Reset mode. The TAP controller is not reset by this instruction. The one
bit Reset Register is selected as Data Register. Note that the reset will be active as long as there
is a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
29.9.3 PROG_ENABLE (0x4)
The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-
bit Programming Enable Register is selected as Data Register. The active states are the
following:
• Shift-DR: The programming enable signature is shifted into the Data Register.
• Update-DR: The programming enable signature is compared to the correct value, and
Programming mode is entered if the signature is valid.
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
011 1
00
00
11
10
1
1
0
1
0
0
10
1
1
0
1
0
0
00
11
387
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29.9.4 PROG_COMMANDS (0x5)
The AVR specific public JTAG instruction for entering programming commands via the JTAG
port. The 15-bit Programming Command Register is selected as Data Register. The active
states are the fo llowin g :
• Capture-DR: The result of the previous command is loaded into the Data Register.
• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous
command and sh iftin g in th e new command.
• Update-DR: The programming command is applied to the Flash inputs
• Run-Test/ Idle: One clock cycle is generated, executing the applied command
29.9.5 PROG_PAGELOAD (0x6)
The AVR specific public JTAG instruct ion to direct ly load the Flash data pag e via the JTAG port.
An 8-bit Flash Data Byte Register is select ed as the Data Register. This is physically the 8 LSBs
of the Prog ramming Command Register. The active states are the following:
• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
• Update-DR: The content of the Flash Data Byte Regist er is copied into a temporary register.
A write sequence is initiated that within 11 TCK cycles loads the content of the temporary
register into the Flash page b uffer. The AVR automat ically alte rnates between writing the low
and the high byte for each new Update-DR state, starting with the low byte for the first
Update-DR encountered after entering the PROG_PAGELOAD command. The Program
Counter is pre-incremented before writing the low byte, except for the first written byte. This
ensures that the first data is written to the address set up by PROG_COM MANDS, and
loading the last locati on in the page b uff er does not make the pr ogra m counter increment int o
the next page.
29.9.6 PROG_PAGEREAD (0x7)
The AVR specific public JTAG instruction to directly capture the Flash cont ent via the JTAG port.
An 8-bit Flash Data Byte Register is select ed as the Data Register. This is physically the 8 LSBs
of the Prog ramming Command Register. The active states are the following:
• Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte
Register. The AVR automatically alternates between reading the low and the high byte for
each new Capture-DR state, starting with the low byte for the first Capture-DR encountered
after entering the PROG_PAGEREAD command. The Program Counter is post-incremented
after reading each high byte, including the first read byte. This ensures that the first data is
captured from the first address set up by PROG_COMMANDS, and reading the last location
in the page makes the program counter increment into th e next pag e.
• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
29.9.7 Data RegistersThe Data Registers are selected by the JTAG instruction registers described in section “Pro-
gramming Specific JTAG Instructions” on page 385. The Data Registers relevant for
programming operations are:
• Reset Register
• Programming Enable Register
• Programming Command Register
• Flash Data Byte Register
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29.9.8 Reset RegisterThe Reset Register is a Test Data Register used to reset the part during programming. It is
required to reset the part before entering Programming mode.
A high value in the Reset Register corresponds to pulling the external reset low. The part is reset
as long as there is a high value present in the Reset Register. Depending on the Fuse settings
for the clock options, the part will remain reset for a Reset Time-out period (refer to “Clock
Sources” on page 40) after releasing the Reset Register. The output from this Data Register is
not latched, so the reset will take place immediately, as shown in Figure 8-1 on page 58.
29.9.9 Programming Enable Register
The Programming Enable Register is a 16-bit register. The contents of this register is compared
to the programming enable signature, binary code 0b1010_0011_0111_0000. When the con-
tents of the register is equal to the programming enable signature, programming via the JTAG
port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when
leaving Programming mode.
Figure 29-13. Programming Enable Register
29.9.10 Programming Command Register
The Programming Command Register is a 15-bit register. This register is used to serially shift in
programming co mmands, and to serially shift out the result of the pre vious command, if any. The
JTAG Programming Instruction Set is shown in Table 29-17. The state sequence when shifting
in the programming commands is illustrated in Figure 29-15.
TDI
TDO
D
A
T
A
=DQ
ClockDR & PROG_ENABLE
Programming Enable
0xA370
389
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Figure 29-14. Programming Command Register
TDI
TDO
S
T
R
O
B
E
S
A
D
D
R
E
S
S
/
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
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Table 29-17. JTAG Programming Instruction
Set
a = address high bits, b = address low bits, c = address e xtended bits, H = 0 - Lo w byte , 1 - High Byte, o = data out,
i = data in, x = don’t care
Instruction TDI Sequence TDO Sequence Notes
1a. Chip Erase
0100011_10000000
0110001_10000000
0110011_10000000
0110011_10000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx (2)
2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx
2b. Load Address Extended High Byte 0001011_cccccccc xxxxxxx_xxxxxxxx (10)
2c. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx
2d. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
2e. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx
2f . Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx
2g. Latch Data 0110111_00000000
1110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx (1)
2h. Write Flash Page
0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
2i. Poll for Page Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2)
3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx
3b. Load Address Extended High Byte 0001011_cccccccc xxxxxxx_xxxxxxxx (10)
3c. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx
3d. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
3e. Read Data Low and High Byte 0110010_00000000
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo Low byte
High byte
4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx
4b. Load Address High Byte 0 000111_aaaaaaaa xxxxxxx_xxxxxxxx (10)
4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx
4e. Latch Data 0110111_00000000
1110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx (1)
4f. Write EEPROM Page
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
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4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2)
5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx
5b. Load Address High Byte 0 000111_aaaaaaaa xxxxxxx_xxxxxxxx (10)
5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
5d. Read Data Byte 0110011_bbbbbbbb
0110010_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
6a. Enter Fuse Write 0100011_01000000 xxxxxxx_xxxxxxxx
6b. Load Data Low Byte(6) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)
6c. Write Fuse Extended Byte
0111011_00000000
0111001_00000000
0111011_00000000
0111011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
6d. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2)
6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)
6f. Write Fuse High Byte
0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
6g. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2)
6h. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)
6i. Write Fuse Low Byte
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
6j. Poll for Fuse Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2)
7a. Enter Lock Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx
7b. Load Data Byte(9) 0010011_11iiiiii xxxxxxx_xxxxxxxx (4)
7c. Write Lock Bits
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
7d. Poll for Lock Bit Write complete 0110 011_00000000 xxxxxox_xxxxxxxx (2)
8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx
8b. Read Extended Fuse Byte(6) 0111010_00000000
0111011_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
8c. Read Fuse High Byte(7) 0111110_00000000
0111111_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
Table 29-17. JTAG Programming Instruction (Continued)
Set (Continue d) a = address high bits, b = address low bits, c = address e xtended bits, H = 0 - Low byte , 1 - High Byte,
o = data out, i = data in, x = don’t care
Instruction TDI Sequence TDO Sequence Notes
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Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is
nor mally the case).
2. Repeat until o = “1”.
3. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse.
4. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged.
5. “0” = programmed, “1” = unprogrammed.
6. The bit mapping for Fuses Extended byte is listed in Table 29-3 on page 367
7. The bit mapping for Fuses High byte is listed in Table 29-4 on page 368
8. The bit mapping for Fuses Low byte is listed in Table 29 - 5 on page 368
9. The bit mapping for Lock bits byte is listed in Table 29-1 on page 366
10.Address bits exceeding PCMSB and EEAMSB (Table 29-11 and Table 29-12) are don’t care
11.All TDI and TDO sequences are represented by binary digits (0b...).
8d. Read Fuse Low Byte(8) 0110010_00000000
0110011_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
8e. Read Lock Bits(9) 0110110_00000000
0110111_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_xxoooooo (5)
8f . Read Fuses and Lock Bits
0111010_00000000
0111110_00000000
0110010_00000000
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo
(5)
Fuse Ext. byte
Fuse High byte
Fuse Low byte
Lock bits
9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx
9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
9c. Read Signature Byte 0110010_00000000
0110011_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
10a. Enter Calibration Byte Read 0100011_0000100 0 xxxxxxx_xxxxxxxx
10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx
10c. Read Calibration Byte 0110110_00000000
0110111_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
11a. Load No Operation Command 0100011_00000000
0110011_00000000 xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
Table 29-17. JTAG Programming Instruction (Continued)
Set (Continue d) a = address high bits, b = address low bits, c = address e xtended bits, H = 0 - Low byte , 1 - High Byte,
o = data out, i = data in, x = don’t care
Instruction TDI Sequence TDO Sequence Notes
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Figure 29-15. State Machine Sequence for Changing/Readin g the Data Word
29.9.11 Flash Data Byte Register
The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer
before executing Page Write, or to read out/verify the content of the Flash. A state machine sets
up the control signals to the Flash and senses the strobe signals from the Flash, thus only the
data words need to be shifted in/out.
The Flash Data Byt e Regist er actually con sists of the 8-bit scan chain and a 8-bit tempor ary reg-
ister. During page load , the Update-DR state copies the conte nt of the scan chain over to the
temporary register and initiates a write sequence that within 11 TCK cycles loads the content of
the temporary register into the Flash page buffer. The AVR automatically alternates between
writing the low and the high byte for e ach new Update -DR state, startin g with the low b yte f or the
first Update-DR encountered after entering the PROG_PAGELOAD command. The Program
Counter is pre-increment ed before writing the low byte, except for the first writ ten byte. This
ensures that the first data is written to the address set up by PROG_COMMANDS, and loading
the last location in the page buffer does not make the Program Counter increment into the next
page.
During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte
Register during the Capture-DR state. The AVR automatically alternates between reading the
low and the high byte f or each n ew Captur e- DR stat e, sta rt ing with t he low byt e for th e fi rst Ca p-
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
011 1
00
00
11
10
1
1
0
1
0
0
10
1
1
0
1
0
0
00
11
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ATmega32U6/AT90USB64/128
ture-DR encounte red af t er en te rin g the PROG _PAGEREAD co mmand. Th e Progr am Co unt er is
post-incremented after reading each high byte, including the first read byte. This ensures that
the first data is captured from the first address set up by PROG_COMMANDS, and reading the
last location in the page makes the program counter increment into the next page.
Figure 29-16. Flash Data Byte Registe r
The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal
operation in which eight bits are shifted for each Flash byte, the clock cycles needed to naviga te
through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis-
ter with sufficient number of clock pulses to complete its operation transparently for the user.
However, if too few bits are shifted between each Update-DR state during page load, the TAP
controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at
least 11 TCK cycles between each Update-DR state.
29.9.12 Programming Algorithm
All references below of type “1a”, “1b”, and so on, refer to Table 29-17 .
29.9.13 Entering Programming Mode
1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Re gister.
2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program-
ming Enable Register.
29.9.14 Leaving Programming Mode
1. Enter JTAG instruction PROG_COMMANDS .
2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_000 0 in the progr am-
ming Enable Register.
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Re gister.
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
Machine
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29.9.15 Performing Chip Erase
1. Enter JTAG instruction PROG_COMMANDS .
2. Start Chip Erase using programming instruction 1a.
3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE
(refer to Table 29-13 on page 380).
29.9.16 Programming the Flash
Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase”
on page 395.
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable Flash write using prog ramming instruction 2a.
3. Load address Extended High byte using programming instruction 2b.
4. Load address High byte using programming instruction 2c.
5. Load address Low byte using programmin g instruction 2d.
6. Load data using programming instructions 2e, 2f and 2g.
7. Repeat steps 5 and 6 for all instruction words in the page.
8. Write the page using programming instruction 2h.
9. Poll f or F lash write complete using prog ramming instruction 2i, or wait f or tWLRH (refer to
Table 29-13 on page 380).
10. Repeat steps 3 to 9 until all data have been programmed.
A more efficient data tra nsfer can be achieved using the PROG_PAGELOAD instruction:
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable Flash write using prog ramming instruction 2a.
3. Load the page address using prog ra mming instructions 2b, 2c a nd 2d. PCW ORD (ref er
to Tab le 29-11 on pag e 372) is used to address within on e page and must be written as
0.
4. Enter JTAG instruction PROG_PAGELOAD.
5. Load the entire page by shifting in all instruction words in the page byte-by-byte, start-
ing with the LSB of the first instruction in the page and ending with the MSB of the last
instruction in the page. Use Update-DR to copy the contents of the Flash Data Byte
Register into the Flash page location and to auto-increment the Program Counter
before each new word.
6. Enter JTAG instruction PROG_COMMANDS .
7. Write the page using programming instruction 2h.
8. Poll f or F lash write complete using prog ramming instruction 2i, or wait f or tWLRH (refer to
Table 29-13 on page 380).
9. Repeat steps 3 to 8 until all data ha ve been programmed.
29.9.17 Reading the Flash
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable Flash read using programming instruction 3a.
3. Load address using programming instructions 3b, 3c and 3d.
4. Read data using programming instruction 3e.
5. Repeat steps 3 and 4 until all data have been read.
A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction:
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1. Enter JTAG instruction PROG_COMMANDS .
2. Enable Flash read using programming instruction 3a.
3. Load the page address using prog ra mming instructions 3b, 3c a nd 3d. PCW ORD (ref er
to Tab le 29-11 on pag e 372) is used to address within on e page and must be written as
0.
4. Enter JTAG instruction PROG_PAGEREAD.
5. Read the entire page (or Flash) by shif ting out all instruction words in the page (or
Flash), starting with the LSB of the first instruction in the page (Flash) and ending with
the MSB of the last instruction in the page (Flash). The Capture-DR state both captures
the data f rom the Flash, and also auto-incremen ts the prog ram counter after each wor d
is read. Note that Capt ur e- DR co me s be fore the shift-DR state. Hence, the first byte
which is shifted out contains valid data.
6. Enter JTAG instruction PROG_COMMANDS .
7. Repeat steps 3 to 6 until all data have been read.
29.9.18 Programming the EEPROM
Before programming the EEPROM a Chip Erase must be performed, see “Performing Chip
Erase” on page 395.
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable EEPROM write using programming instruction 4a.
3. Load address High byte using programming instruction 4b.
4. Load address Low byte using programming instruction 4c.
5. Load data usin g pr ogramming ins tructions 4d and 4e.
6. Repeat steps 4 and 5 f or all data bytes in the page.
7. Write the data using prog ramming instruction 4f.
8. Poll for EEPROM write complete using programming instruction 4g, or w ait for t WLRH
(refer to Table 29-13 on page 380).
9. Repeat steps 3 to 8 until all data ha ve been programmed.
Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM.
29.9.19 Reading the EEPROM
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable EEPROM read using programming instru ction 5a.
3. Load address using programming instructions 5b and 5c.
4. Read data using programming instruction 5d.
5. Repeat steps 3 and 4 until all data have been read.
Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM.
29.9.20 Programming the Fuses
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable Fuse write using programming instruction 6a.
3. Load data high byte using prog ramming instructions 6b. A bit value of “0” will program
the corresponding fuse, a “1” will unprogram the fuse.
4. Write Fuse High byte using programming instruction 6c.
5. P oll f or Fuse write complete using programming instruction 6d, or wait f or tWLRH (ref er to
Table 29-13 on page 380).
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6. Load data low b yte using prog ramming instructions 6e. A “0” will program the fuse, a “1”
will unprogram the fuse.
7. Write Fuse low b yte using programming instruction 6f.
8. P oll f or Fuse write complete using programming instruction 6g, or wait f or tWLRH (ref er to
Table 29-13 on page 380).
29.9.21 Programming the Lock Bits
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable Lock bit write using programming instructio n 7a .
3. Load data using programming instr u ctions 7b. A bit value of “0” will program the corre-
sponding lock bit, a “1” will leave the lock bit unchanged.
4. Write Lock bits using programming instruction 7c.
5. P oll f or Loc k bit write complete using pro gramming instruction 7d, or wait f or tWLRH (ref er
to Table 29-13 on page 380).
29.9.22 Reading the Fuses and Lock Bits
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable Fuse/Lock bit read using programming instruction 8a.
3. To read all Fuses and Lock bits, use programming instruction 8e.
To only read Fuse High byte, use programming instruction 8b.
To only read Fuse Low byte, use programming instructio n 8c.
To only read Lock bits, use programming instruction 8d.
29.9.23 Reading the Signature Bytes
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable Signature byte read using programming instruction 9a.
3. Load add re ss 0x 00 usin g pr ogrammin g ins truction 9b.
4. Read first signature byte using programming instruction 9c.
5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third
signature bytes, respectively.
29.9.24 Reading the Calibration Byte
1. Enter JTAG instruction PROG_COMMANDS .
2. Enable Calibration byte read using programming instruction 10a.
3. Load add re ss 0x 00 usin g pr ogrammin g ins truction 10 b.
4. Read the calibration byt e using programming instruction 10c.
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30. Electrical Characteristics for AT90USB64/128
30.1 Absolute Maximum Ratings*
30.2 DC Characteristics
Operating Te mperature......................................-40⋅C to +85⋅C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on any Pin except RESET and VBUS
with respect to Ground(7) ................. ... ... ......-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Voltage on VBUS with respect to Ground..........-0.5V to +6.0V
Maximum Operating Voltage ..........................................+6.0V
DC Current per I/O Pin............................................... 40.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
TA = -40⋅C to 85⋅C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter Condition Min.(5) Typ. Max.(5) Units
VIL Input Lo w Voltage ,Ex cept
XTAL1 and Reset pin VCC = 2.7V - 5.5V -0.5 0.2VCC(1) V
VIL1 Input Low Voltage,
XTAL1 pin VCC = 2.7V - 5.5V -0.5 0.1VCC(1) V
VIL2 Input Low Voltage,
RESET pin VCC = 2.7V - 5.5V -0.5 0.1VCC(1) V
VIH
Input High Voltage,
Except XTAL1 and
RESET pins VCC = 2.7V - 5.5V 0.6VCC(2) VCC + 0.5 V
VIH1 Input High Voltage,
XTAL1 pin VCC = 2.7V - 5.5V 0.7VCC(2) VCC + 0.5 V
VIH2 Input High Voltage,
RESET pin VCC = 2.7V - 5.5V 0.9VCC(2) VCC + 0.5 V
VOL Output Low Voltage(3), IOL = 10mA, VCC = 5V
IOL = 5mA, VCC = 3V 0.3
0.2 0.7
0.5 V
VOH Output High Voltage(4), IOH = -20mA, VCC = 5V
IOH = -10mA, VCC = 3V 4.2
2.3 4.5
2.6 V
IIL Input Leakage
Current I/O Pin VCC = 5.5V, pin low
(absolute value) 1µA
IIH Input Leakage
Current I/O Pin VCC = 5.5V, pin high
(absolute value) 1µA
RRST Reset Pull-up Resistor 30 60 kΩ
RPU I/O Pin Pull-up Resistor 20 50 kΩ
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Note: 1. "Max" means the highest value where the pin is guaranteed to be read as low
2. "Min" means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state
conditions (non-transient), the following must be obser ved:
ATmega32U6/AT90USB64/128:
1.)The sum of all IOL, f o r ports A0-A7, G2, C4-C7 should not exceed 100 mA.
2.)The sum of all IOL, for ports C0-C3, G0-G1, D0-D7 should not exceed 100 mA.
3.)The sum of all IOL, for ports G3-G5, B0-B7, E0-E7 shoul d not exceed 100 mA.
4.)The sum of all IOL, f o r ports F0-F7 should not exceed 100 mA.
If IOL e xceeds the test condition, V OL may e x ceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady
state conditions (non-transient), the following must be observed:
ATmega32U6/AT90USB64/128:
1)The sum of all IOH, for ports A0-A7, G2, C4-C7 should not exceed 100 mA.
2)The sum of all IOH, for ports C0-C3, G0-G1, D0-D7 should not exceed 100 mA.
3)The sum of all IOH, for ports G3-G5, B0-B7, E0-E7 should not exceed 100 mA.
4)The sum of all IOH, for ports F0-F7 should not exceed 100 mA.
ICC Power Supply Current(6)
Active 4MHz, VCC = 3V
(ATmega32U6/AT90USB
64/128) 2.5 5 mA
Active 8MHz, VCC = 3V
(ATmega32U6/AT90USB
64/128) 510mA
Active 8MHz, VCC = 5V
(ATmega32U6/AT90USB
64/128) 10 18 mA
Active 16MHz, VCC = 5V
(ATmega32U6/AT90USB
64/128) 19 30 mA
Icc Power-d own mode
WDT enabled, BOD
enabled, VCC = 3V, 25°C 30 µA
WDT enabled, BOD
disabled, VCC = 3V, 25°C 10 µA
WDT disabled, BOD
disabled, VCC = 3V, 25°C 2µA
VACIO Analog Comparator
Input Offset Voltage VCC = 5V
Vin = VCC/2 10 40 mV
IACLK Analog Comparator
Input Leakage Current VCC = 5V
Vin = VCC/2 -50 50 nA
tACID Analog Comparator
Propagation Delay VCC = 2.7V
VCC = 4.0V 750
500 ns
Iq USB Regulator Quiescent
Current UVcc > 3.6V, I = 0mA 10 30 µA
Vusb USB Regulator Output
Voltage (Ucap) UVcc > 3.6V, I = 40mA(8) 3.0 3.3 3.5 V
TA = -40⋅C to 85⋅C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Symbol Parameter Condition Min.(5) Typ. Max.(5) Units
400 7593J–AVR–03/09
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5. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcon-
trollers manufa ctured in the same process technology. These values are preliminary values representing design targets, and
will be updated after characterization of actual silicon
6. Values with “Power Reduction Register 1 - PRR1” disabled (0x00).
7. As specified on the USB Electrical chapter of USB Specifications 2.0, the D+/D- pads can withstand voltages down to -1V
applied through a 39 Ohms resistor
8. USB Peripheral consumes up to 50mA from the regulator or UVcc pin when USB is used at full -load
30.3 External Clock Drive Waveforms
Figure 30-1. External Clock Drive Waveforms
30.4 External Clock Drive
Note: All DC Characteristics contained in this datasheet are based on simulation and characterization of
other AVR microcontrollers manuf actured in the same process technology. These values are pre-
liminary values representing design targets, and will be updated after characterization of actual
silicon.
30.5 Maximum speed vs. VCC
Maximum freque ncy is depending on V CC. As shown in Figure 30- 2, the Maximum Frequen cy vs.
VCC curve is linear between 2.7V < VCC < 5.5V.
V
IL1
V
IH1
Table 30-1. External Clock Drive
Symbol Parameter
VCC=1.8-5.5V VCC=2.7-5.5V VCC=4.5-5.5V
UnitsMin. Max. Min. Max. Min. Max.
1/tCLCL Oscillator
Frequency 0208016MHz
tCLCL Clock Period 500 125 62.5 ns
tCHCX High Time 200 50 25 ns
tCLCX Low Time 200 50 25 ns
tCLCH Rise Time 2.0 1.6 0.5 μs
tCHCL Fall Time 2.0 1.6 0.5 μs
ΔtCLCL
Change in period
from one clock
cycle to the next 222%
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Figure 30-2. Maximum Frequency vs. VCC, ATmega32U6/AT90USB64/128
30.6 2-wire Serial Interface Characteristics
Table 30-2 describes t he requ irement s for de vices connect ed to the 2 -wire Seri al Bus. T he ATmeg a32U6/A T90USB64/ 128
2-wire Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 30-3.
16 MHz
8 MHz
Table 30-2. 2-wire Serial Bus Requirements
Symbol Parameter Condition Min Max Units
VIL Input Low-voltage -0.5 0.3 VCC V
VIH Input High-voltage 0.7 VCC VCC + 0.5 V
Vhys(1) Hysteresis of Schmitt Tr igger Inputs 0.05 VCC(2) –V
VOL(1) Outpu t Low-voltage 3 mA sink current 0 0.4 V
tr(1) Rise Time for both SDA and SCL 20 + 0.1Cb(3)(2) 300 ns
tof(1) Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF(3) 20 + 0.1Cb(3)(2) 250 ns
tSP(1) Spikes Suppressed by Input Filter 0 50(2) ns
IiInput Current each I/O Pin 0.1VCC < Vi < 0.9VCC -10 10 µA
Ci(1) Capacitance for each I/O Pin – 10 pF
fSCL SCL Clock Frequency fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz
Rp Value of Pull-up resistor
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD;STA Hold Time (repeated) START Condition fSCL ≤ 100 kHz 4.0 – µs
fSCL > 100 kHz 0.6 – µ s
tLOW Low Period of the SCL Clock fSCL ≤ 100 kHz(6) 4.7 – µs
fSCL > 100 kHz(7) 1.3 – µs
VCC 0,4V–
3mA
----------------------------
1000ns
Cb
-------------------
Ω
VCC 0,4V–
3mA
----------------------------
300ns
Cb
----------------
Ω
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Notes: 1. In ATmega32U6/AT90USB64/128, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega32U6/AT90USB64/128 2-wire Serial Interface operation. Other de vices connected to
the 2-wire Seri al Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATmega32U6/AT90USB64/128 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK
must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
7. The actual low period generated by the ATmega32U6/AT90USB64/128 2-wire Serial Interf ace is (1/fSCL - 2/fCK), thus the low
time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega32U6/AT90USB64/128 devices
connected to the bus may communicate at full speed (400 kHz) with other ATmega32U6/AT90USB64/128 de vices, as well
as any other device with a proper tLOW acceptance margin.
Figure 30-3. 2-wire Serial Bus Timing
tHIGH High period of the SCL clock fSCL ≤ 100 kHz 4.0 – µs
fSCL > 100 kHz 0.6 – µ s
tSU;STA Set-up tim e for a repeated START conditio n fSCL ≤ 100 kHz 4.7 – µs
fSCL > 100 kHz 0.6 – µ s
tHD;DAT Data hold time fSCL ≤ 100 kHz 0 3.45 µs
fSCL > 100 kHz 0 0.9 µs
tSU;DAT Data setup time fSCL ≤ 100 kHz 250 – ns
fSCL > 100 kHz 100 – ns
tSU;STO Setup time for STOP condition fSCL ≤ 100 kHz 4.0 – µs
fSCL > 100 kHz 0.6 – µ s
tBUF Bus free time between a STOP and START
condition fSCL ≤ 100 kHz 4.7 – µs
fSCL > 100 kHz 1.3 – µ s
Table 30-2. 2-wire Serial Bus Requirements (Continued)
Symbol Parameter Condition Min Max Units
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r
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ATmega32U6/AT90USB64/128
30.7 SPI Timing Characteristics
See Figure 30-4 and Figure 30-5 for details.
Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK > 12 MHz
Figure 30-4. SPI Interface Timing Requirements (Master Mode)
Table 30-3. SPI Timing Parameters
Description Mode Min Typ Max
1 SCK period Master See Table 17-4
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5HoldMaster 10
6 Out to SCK Master 0.5 • tsck
7 SCK to out Master 10
8 SCK to out high Master 10
9SS
low to out Slave 15
10 SCK period Slave 4 • tck
11 SCK high/low(1) Slave 2 • tck
12 Rise/Fall time Slave 1.6 µs
13 Setup Slave 10
ns
14 Hold Slave tck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 20
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
61
22
345
8
7
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ATmega32U6/AT90USB64/128
Figure 30-5. SPI Interface Timing Requirements (Slave Mode)
30.8 Hardware Boot EntranceTiming Characteristics
Figure 30-6. Hardware Boot Timing Requirements
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16
Table 30-4. Hardware Boot Timings
Symbol Parameter Min Max
tSHRH HWB low Setup before Reset High 0
tHHRH HWB low Hold after Reset High
StartUpTime(
SUT) + Time
Out
Delay(TOUT)
RESET
ALE/HWB
tSHRH tHHRH
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ATmega32U6/AT90USB64/128
30.9 ADC Characteristics
Table 30-5. ADC Characteristics
Symbol Parameter Condition Min Typ Max Units
Resolution
Single Ended Conversion 10 Bits
Differential Conversion
Gain = 1x or 10x 8Bits
Differential Conversion
Gain = 200x 7Bits
Absolute accuracy (Including
INL, DNL, quantization error,
gain and offset error)
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 1.5 LSB
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz LSB
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
Noise Reduction Mode
1.5 LSB
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz
Noise Reduction Mode
LSB
Absolute accuracy Gain = 1x, 10x, 20 0x
Vref = 4V, Vcc = 5V
ADC Clock = 50 - 200 kHz 1LSB
Integral Non-Linearity (INL) Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 0.5 1 LSB
Integral Non-Linearity (INL)
(Accuracy after calibration for
offset and gain error)
Gain = 1x, 10x, 200x
Vref = 4V, Vcc = 5V
ADC Clock = 50 - 200 kHz 0.5 1 LSB
Differential Non-Linearity (DNL) Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 0.3 1 LSB
Gain Error
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz -2 0 +2 LSB
Gain = 1x, 10x, 200x -2 0 +2 LSB
Offset Error
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz -2 1 +2 LSB
Gain = 1x, 10x, 200x
Vref = 4V, Vcc = 5V
ADC Clock = 50 - 200 kHz -1 0 +1 LSB
Conversion Time Free Running Conversion 65 260 µs
Clock Frequency Single Ended Conv ersion 50 1000 kHz
406 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
AV CC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V
VREF Referen ce Voltage Single Ended Conversion 2.0 AVCC V
Differential Conversion 2.0 AVCC - 0.5 V
VIN Input Voltage Single ended channels 0 VREF V
Differential Conversion 0 AVCC V
Input Bandwidth Single Ended Channels 38,5 kHz
Differential Channels 4 kHz
VINT1 Internal Voltage Reference 1.1V 1.0 1.1 1.2 V
VINT2 Internal Voltag e Reference 2.56V 2.4 2.56 2.8 V
RREF Ref erence Input Resistance 32 kΩ
RAIN Analog Input Resistance 100 MΩ
Table 30-5. ADC Characteristics (Continued)
Symbol Parameter Condition Min Typ Max Units
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30.10 External Data Memory Timing
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the exter nal clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 30-6. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state
Symbol Parameter
8 MHz Oscillator Variab l e Oscill ator
UnitMin Max Min Max
01/t
CLCL Oscillator Frequency 0.0 16 MHz
1t
LHLL ALE Pulse Width 115 1.0tCLCL-10 ns
2t
AVLL Address Valid A to ALE Low 57.5 0.5tCLCL-5(1) ns
3a tLLAX_ST Address Hold After ALE Low,
write access 55 ns
3b tLLAX_LD Address Hold after ALE Low,
read access 55 ns
4t
AVLLC Address Valid C to ALE Low 57.5 0.5tCLCL-5(1) ns
5t
AVRL Address Valid to RD Low 115 1.0tCLCL-10 ns
6t
AVWL Address Valid to WR Low 115 1.0tCLCL-10 ns
7t
LLWL ALE Low to WR Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) ns
8t
LLRL ALE Low to RD Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) ns
9t
DVRH Data Setup to RD High 40 40 ns
10 tRLDV Read Low to Data Valid 75 1.0tCLCL-50 ns
11 tRHDX Data Hold After RD High 0 0 ns
12 tRLRH RD Pulse Width 115 1.0tCLCL-10 ns
13 tDVWL Data Setup to WR Low 42.5 0.5tCLCL-20(1) ns
14 tWHDX Data Hold After WR High 115 1.0tCLCL-10 ns
15 tDVWH Data Valid to WR High 125 1.0tCLCL ns
16 tWLWH WR Pulse Wi dt h 115 1.0tCLCL-10 ns
Table 30-7. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state
Symbol Parameter
8 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL Oscillator Frequency 0.0 16 MHz
10 tRLDV Read Low to Data Valid 200 2.0tCLCL-50 ns
12 tRLRH RD Pulse Width 240 2.0tCLCL-10 ns
15 tDVWH Data Valid to WR High 240 2.0tCLCL ns
16 tWLWH WR Pulse Width 240 2.0tCLCL-10 ns
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ATmega32U6/AT90USB64/128
Table 30-8. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL Oscillator Frequency 0.0 16 MHz
10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 ns
12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns
15 tDVWH Data Valid to WR High 375 3.0tCLCL ns
16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns
Table 30-9. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL Oscillator Frequency 0.0 16 MHz
10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 ns
12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns
14 tWHDX Data Hold After WR High 240 2.0tCLCL-10 ns
15 tDVWH Data Valid to WR High 375 3.0tCLCL ns
16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns
Table 30-10. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL Oscillator Frequency 0.0 8 MHz
1t
LHLL ALE Pulse Width 235 tCLCL-15 ns
2t
AVLL Address Valid A to ALE Low 115 0.5tCLCL-10(1) ns
3a tLLAX_ST Address Hold After ALE Low,
write access 55ns
3b tLLAX_LD Address Hold after ALE Low,
read access 55ns
4t
AVLLC Address Valid C to ALE Low 115 0.5tCLCL-10(1) ns
5t
AVRL Ad dress Valid to RD Low 235 1.0t CLCL-15 ns
6t
AVWL Address Val i d to WR Low 235 1.0 tCLCL-15 ns
7t
LLWL ALE Low to WR Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns
8t
LLRL ALE Low to RD Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns
9t
DVRH Data Setup to RD High 45 45 ns
10 tRLDV Read Low to Data Valid 190 1.0tCLCL-60 ns
11 tRHDX Data Hold After RD High 0 0 ns
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ATmega32U6/AT90USB64/128
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the exter nal clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
12 tRLRH RD Pulse Width 235 1.0tCLCL-15 ns
13 tDVWL Data Setup to WR L ow 105 0.5tCLCL-20(1) ns
14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 ns
15 tDVWH Data Valid to WR High 250 1.0tCLCL ns
16 tWLWH WR Pulse Width 235 1.0tCLCL-15 ns
Table 30-10. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued)
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
Table 30-11. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL Oscillator Frequency 0.0 8 MHz
10 tRLDV Read Low to Data Valid 440 2.0tCLCL-60 ns
12 tRLRH RD Pulse Width 485 2.0tCLCL-15 ns
15 tDVWH Data Valid to WR High 500 2.0tCLCL ns
16 tWLWH WR Pulse Width 485 2.0tCLCL-15 ns
Table 30-12. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL Oscillator Frequency 0.0 8 MHz
10 tRLDV Read Low to Data Valid 690 3.0tCLCL-60 ns
12 tRLRH RD Pulse Width 735 3.0tCLCL-15 ns
15 tDVWH Data Valid to WR High 750 3.0tCLCL ns
16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns
Table 30-13. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL Oscillator Frequency 0.0 8 MHz
10 tRLDV Read Low to Data Valid 690 3.0tCLCL-60 ns
12 tRLRH RD Pulse Width 735 3.0tCLCL-15 ns
14 tWHDX Data Hold After WR High 485 2.0tCLCL-15 ns
15 tDVWH Data Valid to WR High 750 3.0tCLCL ns
16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns
410 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
Figure 30-7. External Memory Timing (SRWn1 = 0, SRWn0 = 0
Figure 30-8. External Memory Timing (SRWn1 = 0, SRWn0 = 1)
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataAddress
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8 AddressPrev. addr.
DA7:0 Address Data
Prev. data XX
RD
DA7:0 (XMBK = 0) DataAddress
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4
411
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
Figure 30-9. External Memory Timing (SRWn1 = 1, SRWn0 = 0)
Figure 30-10. External Memory Timing (SRWn1 = 1, SRWn0 = 1)()
The ALE pulse in the last period (T4-T7) is only pres ent if the next instr uction accesses the RAM (internal
or external).
ALE
T1 T2 T3
Write
Read
WR
T6
A15:8
Address
Prev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
Data
Address
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4 T5
ALE
T1 T2 T3
Write
Read
WR
T7
A15:8
Address
Prev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
Data
Address
System Clock (CLKCPU)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4 T5 T6
412 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
31. AT90USB64/128 Typical Characteristics
The following charts show typical behavior. These figures are not tested during m anufacturing.
All current consumption measurements are performed with all I/O pins configured as inputs and
with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock
source.
All Active- and Idle current consumption measurements are done with all bits in the PRR regis-
ters set an d thus, th e corres ponding I/O modules are turn ed off. Als o the Ana log Comp arator is
disabled during these measurements.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating
frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-
ture. The dominating factors are operating voltage and frequency.
The current drawn fr om capacitive loaded pin s may be estimated (for on e pin) as CL*VCC*f where
CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to
function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer
enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-
rent drawn by the Watchdog Timer.
413
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ATmega32U6/AT90USB64/128
31.1 Input Voltage Levels
Figure 31-1. Input Low Voltage vs. Vcc, all I/Os excluding DP/DM, XTAL1 and Reset
Figure 31-2. Input High Voltage vs. Vcc, all I/O s excluding DP/DM, XTAL1 and Reset
0.5
0.75
1
1.25
1.5
1.75
2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
Threshold (V)
85
25
-40
0.5
0.75
1
1.25
1.5
1.75
2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
Threshold (V)
85
25
-40
414 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
31.2 Output Voltage Levels
Figure 31-3. Output Low Voltage vs. Output Current, all I/Os excluding DP/DM, Vcc=3V
Figure 31-4. Output Low Voltage vs. Output Current, all I/Os excluding DP/DM, Vcc=5V
0
0.2
0.4
0.6
0.8
1
1.2
0 5 10 15 20
I
OL
(mA)
V
OL
(V)
85
25
-40
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 5 10 15 20
I
OL
(mA)
V
OL
(V)
85
25
-40
415
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ATmega32U6/AT90USB64/128
Figure 31-5. Output High Voltage vs. Output Current, all I/Os excluding DP/DM, Vcc=3V
Figure 31-6. Output High Voltage vs. Output Current, all I/Os excluding DP/DM, Vcc=5V
1.8
2
2.2
2.4
2.6
2.8
3
0 5 10 15 20
I
OH
(mA)
V
OH
(V)
85
25
-40
4.2
4.4
4.6
4.8
5
0 5 10 15 20
I
OH
(mA)
V
OH
(V)
85
25
-40
416 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
31.3 Power-down Supply Current
Figure 31-7. Power-down Supply Current vs. Vcc, with BOD Disabled, WDT Disabled, T=25°C
Figure 31-8. Power-down Supply Current vs. Vcc, with BOD Disabled, WDT Enabled, T=25°C
0
0.5
1
1.5
2
2.5
3
2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
I
CC
(uA)
0
2
4
6
8
10
12
14
16
2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
I
CC
(µA)
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ATmega32U6/AT90USB64/128
Figure 31-9. Power-down Supply Current vs. Vcc, with BOD Enabled, WDT Enabled, T=25°C
31.4 Power-save Supply Current
Figure 31-10. Power-save Supply Current vs. VCc, with BOD & WDT Disabled, T=25°C
0
10
20
30
40
50
60
2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
I
CC
(µA)
0
1
2
3
4
5
6
7
8
2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
I
CC
(µA)
418 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
31.5 Idle Supply Current
Figure 31-11. Idle Supply Curren t vs Frequency, T=25°C
31.6 Active Supply Current
Figure 31-12. Active Supply Current vs Frequency, T=25°C
0
5
10
15
20
2 4 6 8 10121416
Fre quency (MHz )
I
CC
(mA)
5.5
5
4.5
3.3
2.7
0
5
10
15
20
25
2 4 6 8 10 12 14 16
Fre quency (MHz )
I
CC
(mA)
5.5
5
4.5
3.3
2.7
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ATmega32U6/AT90USB64/128
31.7 Reset Supply Current
Figure 31-13. Reset Supply Current vs Frequency
31.8 I/O Pull-up Current
Figure 31-14. I/O Pull-Up Current vs. Pin Voltage, Vcc=5V
0
2
4
6
8
10
12
4 6 8 10121416
Fre quency (MHz )
I
CC
(mA)
5.5
5
4.5
3.3
2.7
-20
0
20
40
60
80
100
120
140
012345
V
OP
(V)
I
OP
(uA)
85
25
-40
420 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
Figure 31-15. Reset Pull-Up Current vs. Pin Voltage, Vcc=5V
31.9 Bandgap Voltage
Figure 31-16. Bandgap voltage vs. Temperature
0
20
40
60
80
100
120
012345
V
RESET
(V)
I
RESET
(uA)
85
25
-40
1.08
1.085
1.09
1.095
1.1
1.105
1.11
1.115
-40-30-20-100 1020304050607080
Temperature (˚)
Bandgap Voltage (V)
5.5
5
4.5
4
3.6
2.7
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31.10 Internal ARef Voltage
Figure 31-17. Internal ARef Reference Voltage vs. Temperature, Vcc=2.7 -5.5V
31.11 USB Regulator
Figure 31-18. USB Regulator Quiescent Current vs. Input Voltage, No Load
2.54
2.56
2.58
2.6
2.62
2.64
-40-200 20406080
Temperature
Te nsion Vre fInter (V)
0
10
20
30
40
50
60
70
80
90
100
33.544.555.56
Voltage (V)
I
CC
(uA)
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ATmega32U6/AT90USB64/128
Figure 31-19. USB Regulator Output Voltage vs. Input Voltage, Load=75 Ohms
Note: The 75 Ohms load is equivalent to the maximum average consumption of the USB peripheral in
operation (full bus load)
31.12 BOD Levels
Figure 31-20. BOD Voltage (2.4V level) vs. Temperature
Figure 31-21. BOD Voltage (3.4V level) vs. Temperature
2.6
2.8
3
3.2
3.4
3 3.5 4 4.5 5 5.5
Input Voltage (V)
Output Voltage (V)
85
25
-40
2.42
2.44
2.46
2.48
2.5
2.52
2.54
-40-30-20-100 1020304050607080
Temperature (C)
Threshold (V)
Risi ng V cc
Falling V c c
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ATmega32U6/AT90USB64/128
Figure 31-22. BOD Voltage (4.3V level) vs. Temperature
31.13 Watchdog Timer Frequency
Figure 31-23. WDT Oscillator Frequency vs. Vcc
3.42
3.44
3.46
3.48
3.5
3.52
3.54
3.56
-40-30-20-100 1020304050607080
Temperature (C)
Threshold (V)
Risi ng V cc
Falling V c c
4.34
4.36
4.38
4.4
4.42
4.44
4.46
4.48
4.5
-40-30-20-100 1020304050607080
Temperature (C)
Threshold (V)
Risi ng V cc
Falling V c c
424 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
31.14 Internal RC Oscillator Frequency
Figure 31-24. RC Oscillator Frequency vs. OSCCAL, T=25°C
Figure 31-25. RC Oscillator Frequency vs. Vcc
Figure 31-26. RC Oscillator Frequency vs. Temperature
108
110
112
114
116
118
120
122
124
2 2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
F
RC
(kHz)
85
25
-40
2
4
6
8
10
12
14
16
-1 15 31 47 63 79 95 111 127 143 159 175 191 207 223 239 255
O SCCAL ( X1)
F
RC
(MHz )
425
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
31.15 Power-On Reset
Figure 31-27. Power-On Reset Level vs. Temperature
7.8
7.9
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
2.5 3 3.5 4 4.5 5 5.5
V
CC
(V)
F
RC
(MHz )
85
25
-40
7.8
8
8.2
8.4
8.6
8.8
-40-30-20-100 1020304050607080
Temperature
F
RC
(MHz )
5.5
4
3.3
3
2.7
426 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
-40-30-20-100 1020304050607080
Temperature
POR Voltage (V)
427
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
32. AT mega32U6 Typical Characteristics
Typical charac te rist ics fo r ATm e g3 2U 6 ar e no t yet ava ilab l e.
428 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
33. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) Reserved - - - - - - - -
(0xFE) Reserved - - - - - - - -
(0xFD) Reserved - - - - - - - -
(0xFC) Reserved - - - - - - - -
(0xFB) Reserved - - - - - - - -
(0xFA) Reserved - - - - - - - -
(0xF9) OTGTCON PAGE VALUE
(0xF8) UPINT PINT7:0
(0xF7) UPBCHX - - - - - PBYCT10:8
(0xF6) UPBCLX PBYCT7:0
(0xF5) UPERRX - COUNTER1:0 CRC16 TIMEOUT PID DATAPID DATATGL
(0xF4) UEINT EPINT6:0
(0xF3) UEBCHX - - - - -BYCT10:8
(0xF2) UEBCLX BYCT7:0
(0xF1) UEDATX DAT7:0
(0xF0) UEIENX FLERRE NAKINE - NAKOUTE RXSTPE RXOUTE STALLEDE TXINE
(0xEF) UESTA1X - - - - - CTRLDIR CURRBK1:0
(0xEE) UESTA0X CFGOK OVERFI UNDERFI - DTSEQ1:0 NBUSYBK1:0
(0xED) UECFG1X EPSIZE2:0 EPBK1:0 ALLOC
(0xEC) UECFG0X EPTYPE1:0 -- EPDIR
(0xEB) UECONX STALLRQ STALLRQC RSTDT EPEN
(0xEA) UERST EPRST6:0
(0xE9) UENUM EPNUM2:0
(0xE8) UEINTX FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLEDI TXINI
(0xE7) Reserved - - - -
(0xE6) UDMFN FNCERR
(0xE5) UDFNUMH FNUM10:8
(0xE4) UDFNUML FNUM7:0
(0xE3) UDADDR ADDEN UADD6:0
(0xE2) UDIEN UPRSME EORSME WAKEUPE EORSTE SOFE SUSPE
(0xE1) UDINT UPRSMI EORSMI WAKEUPI EORSTI SOFI SUSPI
(0xE0) UDCON LSM RMWKUP DETACH
(0xDF) OTGINT STOI HNPERRI ROLEEXI BCERRI VBERRI SRPI
(0xDE) OTGIEN STOE HNPERRE ROLEEXE BCERRE VBERRE SRPE
(0xDD) OTGCON HNPREQ SRPREQ SRPSEL VBUSHWC VBUSREQ VBUSRQC
(0xDC) Reserved
(0xDB) Reserved
(0xDA) USBINT IDTI VBUSTI
(0xD9) USBSTA SPEED ID VBUS
(0xD8) USBCON USBE HOST FRZCLK OTGPADE IDTE VBUSTE
(0xD7) UHWCON UIMOD UIDE UVCONE UVREGE
(0xD6) Reserved
(0xD5) Reserved
(0xD4) Reserved
(0xD3) Reserved
(0xD2) Reserved - - - - - - - -
(0xD1) Reserved - - - - - - - -
(0xD0) Reserved - - - - - - - -
(0xCF) Reserved - - - - - - - -
(0xCE) UDR1 USART1 I/O Data Register
(0xCD) UBRR1H - - - - USART1 Baud Rate Register High Byte
(0xCC) UBRR1L USART1 Baud Rate Register Low Byte
(0xCB) Reserved - - - - - - - -
(0xCA) UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1
(0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81
(0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 PE1 U2X1 MPCM1
(0xC7) Reserved - - - - - - - -
(0xC6) Reserved - - - - - - - -
(0xC5) Reserved - - - - - - - -
(0xC4) Reserved - - - - - - - -
(0xC3) Reserved - - - - - - - -
(0xC2) Reserved - - - - - - - -
(0xC1) Reserved - - - - - - - -
(0xC0) Reserved - - - - - - - -
(0xBF) Reserved - - - - - - - -
429
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
(0xBE) Reserved - - - - - - - -
(0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 -
(0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN -TWIE
(0xBB) TWDR 2-wire Serial Interface Da ta Register
(0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
(0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0
(0xB8) TWBR 2-wire Serial Interface Bit Rate Register
(0xB7) Reserved - - - - - - - -
(0xB6) ASSR - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB
(0xB5) Reserved - - - - - - - -
(0xB4) OCR2B Timer/Counter2 Output Compare Register B
(0xB3) OCR2A Timer/Counter2 Output Compare Register A
(0xB2) TCNT2 Timer/Counter2 (8 Bit)
(0xB1) TCCR2B FOC2A FOC2B -- WGM22 CS22 CS21 CS20
(0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 --WGM21WGM20
(0xAF) UPDATX PDAT7:0
(0xAE) UPIENX FLERRE NAKEDE - PERRE TXSTPE TXOUTE RXSTALLE RXINE
(0xAD) UPCFG2X INTFRQ7:0
(0xAC) UPSTAX CFGOK OVERFI UNDERFI DTSEQ1:0 NBUSYBK1:0
(0xAB) UPCFG1X PSIZE2:0 PBK1:0 ALLOC
(0xAA) UPCFG0X PTYPE1:0 PTOKEN1:0 PEPNUM3:0
(0xA9) UPCONX PFREEZE INMODE RSTDT PEN
(0xA8) UPRST PRST6:0
(0xA7) UPNUM PNUM2:0
(0xA6) UPINTX FIFOCON NAKEDI RWAL PERRI TXSTPI TXOUTI RXSTALLI RXINI
(0xA5) UPINRQX INRQ7:0
(0xA4) UHFLEN FLEN7:0
(0xA3) UHFNUMH FNUM10:8
(0xA2) UHFNUML FNUM7:0
(0xA1) UHADDR HADD6:0
(0xA0) UHIEN HWUPE HSOFE RXRSME RSMEDE RSTE DDISCE DCONNE
(0x9F) UHINT HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI
(0x9E) UHCON RESUME RESET SOFEN
(0x9D) OCR3CH Timer/Counter3 - Output Compare Register C High Byte
(0x9C) OCR3CL Timer/Counter3 - Output Compare Register C Low Byte
(0x9B) OCR3BH Timer/Counter3 - Output Compare Register B High Byte
(0x9A) OCR3BL Timer/Counter3 - Output Compare Register B Low Byte
(0x99) OCR3AH Timer/Counter3 - Output Compare Register A High Byte
(0x98) OCR3AL Timer/Counter3 - Output Compare Register A Low Byte
(0x97) ICR3H Timer/Counter3 - Input Capture Register High Byte
(0x96) ICR3L Timer/Counter3 - Input Capture Register Low Byte
(0x95) TCNT3H Timer/Counter3 - Counter Register High Byte
(0x94) TCNT3L Timer/Co u nte r3 - Counter Registe r Lo w Byte
(0x93) Reserved - - - - - - - -
(0x92) TCCR3C FOC3A FOC3B FOC3C - - - - -
(0x91) TCCR3B ICNC3 ICES3 - WGM33 WGM32 CS32 CS31 CS30
(0x90) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30
(0x8F) Reserved - - - - - - - -
(0x8E) Reserved - - - - - - - -
(0x8D) OCR1CH Timer/Counter1 - Output Compare Register C High Byte
(0x8C) OCR1CL Timer/Counter1 - Output Compare Register C Low Byte
(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte
(0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte
(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte
(0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte
(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte
(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte
(0x85) TCNT1H Timer/Counter1 - Counter Register High Byte
(0x84) TCNT1L Timer/Co u nte r1 - Counter Registe r Lo w Byte
(0x83) Reserved - - - - - - - -
(0x82) TCCR1C FOC1A FOC1B FOC1C - - - - -
(0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10
(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10
(0x7F) DIDR1 - - - - - -AIN1DAIN0D
(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D
(0x7D) - - - - - - - - -
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
430 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
(0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0
(0x7B) ADCSRB ADHSM ACME - - - ADTS2 ADTS1 ADTS0
(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0
(0x79) ADCH ADC Data Register High byte
(0x78) ADCL ADC Data Register Low byte
(0x77) Reserved - - - - - - - -
(0x76) Reserved - - - - - - - -
(0x75) XMCRB XMBK - - - - XMM2 XMM1 XMM0
(0x74) XMCRA SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00
(0x73) Reserved - - - - - - - -
(0x72) Reserved - - - - - - - -
(0x71) TIMSK3 --ICIE3- OCIE3C OCIE3B OCIE3A TOIE3
(0x70) TIMSK2 - - - - - OCIE2B OCIE2A TOIE2
(0x6F) TIMSK1 --ICIE1- OCIE1C OCIE1B OCIE1A TOIE1
(0x6E) TIMSK0 - - - - - OCIE0B OCIE0A TOIE0
(0x6D) Reserved - - - - - - - -
(0x6C) Reserved - - - - - - - -
(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0
(0x6A) EICRB ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40
(0x69) EICRA ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00
(0x68) PCICR - - - - - - -PCIE0
(0x67) Reserved - - - - - - - -
(0x66) OSCCAL Oscillator Calibration Register
(0x65) PRR1 PRUSB - - -PRTIM3-- PRUSART1
(0x64) PRR0 PRTWI PRTIM2 PRTIM0 -PRTIM1PRSPI - PRADC
(0x63) Reserved - - - - - - - -
(0x62) Reserved - - - - - - - -
(0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0
(0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0
0x3F (0x5F) SREG I T H S V N Z C
0x3E (0x5E) SPH SP15 SP14 SP1 3 SP12 SP11 SP10 SP9 SP8
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0x3C (0x5C) Reserved - - - - - - - -
0x3B (0x5B) RAMPZ - - - - - - RAMPZ1 RAMPZ0
0x3A (0x5A) Reserved - - - - - - - -
0x39 (0x59) Reserved - - - - - - - -
0x38 (0x58) Reserved - - - - - - - -
0x37 (0x57) SPMCSR SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN
0x36 (0x56) Reserved - - - - - - - -
0x35 (0x55) MCUCR JTD --PUD-- IVSEL IVCE
0x34 (0x54) MCUSR - - - JTRF WDRF BORF EXTRF PORF
0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE
0x32 (0x52) Reserved - - - - - - - -
0x31 (0x51) OCDR/
MONDR OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0
Monitor Data Register
0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0
0x2F (0x4F) Reserved - - - - - - - -
0x2E (0x4E) SPDR SPI Data Register
0x2D (0x4D) SPSR SPIF WCOL - - - - - SPI2X
0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0
0x2B (0x4B) GPIOR2 General Purpose I/O Register 2
0x2A (0x4A) GPIOR1 General Purpose I/O Register 1
0x29 (0x49) PLLCSR - - - PLLP2 PLLP1 PLLP0 PLLE PLOCK
0x28 (0x48) OCR0B Timer/Counter0 Out put Compare Reg i ster B
0x27 (0x47) OCR0A Timer/Counter0 Out put Compare Reg i ster A
0x26 (0x46 ) TCNT0 Timer/Counter0 (8 Bit)
0x25 (0x45) TCCR0B FOC0A FOC0B -- WGM02 CS02 CS01 CS00
0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 --WGM01WGM00
0x23 (0x43) GTCCR TSM - - - - - PSRASY PSRSYNC
0x22 (0x42) EEARH - - - - EEPROM Address Register High Byte
0x21 (0x4 1) EEARL EEPROM Address Register Low Byte
0x20 (0x40) EEDR EEPROM Data Register
0x1F (0x3F) EEC R -- EEPM1 EEPM0 EERIE EEMPE EEPE EERE
0x1E (0x3E) GPIOR0 General Purpose I/O Register 0
0x1D (0x3D) EIMSK INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
0x1C (0x3C) EIFR INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 INTF0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
431
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
Note: 1. For comp atibility with future devices, reser ved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly b it-accessible using the SBI and CBI instr uction s. In these reg-
isters, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that th e CBI and SBI instr uctions will o perate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag . The CBI and SBI instruction s
work with regi ste r s 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-
ters as data space using LD and ST instructions, $20 must be added to these addresses. The
ATmega32U6/AT90 USB64/128 is a complex microcontroller with more per ip heral units than can be sup ported w ithin the 64
location reserved in Opcode f or the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
0x1B (0x3B) PCIFR - - - - - - -PCIF0
0x1A (0x3A) Reserved - - - - - - - -
0x19 (0x39) Reserved - - - - - - - -
0x18 (0x38) TIFR3 --ICF3- OCF3C OCF3B OCF3A TOV3
0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2
0x16 (0x36) TIFR1 --ICF1- OCF1C OCF1B OCF1A TOV1
0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0
0x14 (0x34) Reserved - - - - - - - -
0x13 (0x33) Reserved - - - - - - - -
0x12 (0x32) Reserved - - - - - - - -
0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0
0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0
0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0
0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0
0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0
0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0
0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0
0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0
0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0
0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0
0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0
0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0
0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0
0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0
0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0
0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0
0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
432 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
34. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl ,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z , N , V 1
COM Rd One ’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Com plement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 N one 2
IJMP Indirect Jump to (Z) PC ← Z None 2
EIJMP Extended Indirect Jump to (Z) PC ←(EIND:Z) None 2
JMP k Direct Jump PC ← kNone3
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 4
ICALL Indirect Call to (Z) PC ← ZNone4
EICALL Extended Indirect Call to (Z) PC ←(EIND:Z) None 4
CALL k Direct Subroutine Call PC ← kNone5
RET Subroutine Return PC ← STACK None 5
RETI Interrupt Return PC ← STACK I 5
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k B ranch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
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BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 N one 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← TNone1
SEC Set Carry C ← 1C1
CLC Clear Carry C ← 0 C 1
SEN Set Negativ e Flag N ← 1N1
CLN Clear Negative Flag N ← 0 N 1
SEZ Set Zero Flag Z ← 1Z1
CLZ Clear Zero Flag Z ← 0 Z 1
SEI Global Interrupt Enable I ← 1I1
CLI Global Interrupt Disable I ← 0 I 1
SES Set Signed Test Flag S ← 1S1
CLS Clear Signed Test Flag S ← 0 S 1
SEV Set Twos Complement Overflow. V ← 1V1
CLV Clear Twos Complement Overflow V ← 0 V 1
SET Set T in SREG T ← 1T1
CLT Clear T in SREG T ← 0 T 1
SEH Set Half Carry Flag in SREG H ← 1H1
CLH Clear Half Carry Flag in SREG H ← 0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1
LDI Rd, K Load Imme diate Rd ← KNone1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and P ost-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and P ost-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Loa d Indirect and Post-Inc. Rd ← (Z) , Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) Non e 2
LDD R d, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr St ore Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displaceme nt (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Loa d Pr ogr a m Me mo r y R0 ← (Z) None 3
LPM Rd, Z Load Progra m Me mory Rd ← (Z) None 3
LPM Rd, Z+ Load P rogram Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
ELPM Extended Load Program Memory R0 ← (RAMPZ:Z) None 3
ELPM Rd, Z Extended Load Program Memory Rd ← (Z) None 3
ELPM Rd, Z+ Extended Load Program Memory Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1 None 3
Mnemonics Operands Description Operation Flags #Clocks
434 7593J–AVR–03/09
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SPM Store Program Memory (Z) ← R1:R0 None -
IN Rd , P In Port Rd ← PNone1
OUT P, Rr Out Port P ← Rr Non e 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On -chip Debug Only None N/A
Mnemonics Operands Description Operation Flags #Clocks
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35. Ordering Information
35.1 ATmega32U6
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering inf ormation
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See “Maximum speed vs. VCC” on page 400.
Speed(MHz) Power Supply(V) Ordering Code(2) USB Interf a ce Package(1) Op erating Range
20(3) 2.7-5.5 ATmega32U6-AU
ATmega32U6-MU Host (OTG) MD
PS Industrial
(-40° to +85°C)
MD 64 - Lead, 14x1 4 mm Body Size, 1.0mm Body Thickness
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
PS 64 - Lead, 9x9 mm Body Size, 0.50mm Pitch
Quad Flat No Lead Package (QFN)
436 7593J–AVR–03/09
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35.2 AT90USB646
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering inf ormation
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See “Maximum speed vs. VCC” on page 400.
Speed(MHz) Power Supply(V) Ordering Code(2) USB Interf a ce Package(1) Op erating Range
20(3) 2.7-5.5 AT90USB646-AU
AT90USB646-MU Device MD
PS Industrial
(-40° to +85°C)
MD 64 - Lead, 14x1 4 mm Body Size, 1.0mm Body Thickness
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
PS 64 - Lead, 9x9 mm Body Size, 0.50mm Pitch
Quad Flat No Lead Package (QFN)
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35.3 AT90USB647
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering inf ormation
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See “Maximum speed vs. VCC” on page 400.
Speed(MHz) Power Supply(V) Ordering Code(2) USB Interf a ce Package(1) Op erating Range
20(3) 2.7-5.5 AT90USB647-AU
AT90USB647-MU Device MD
PS Industrial
(-40° to +85°C)
MD 64 - Lead, 14x1 4 mm Body Size, 1.0mm Body Thickness
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
PS 64 - Lead, 9x9 mm Body Size, 0.50mm Pitch
Quad Flat No Lead Package (QFN)
438 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
35.4 AT90USB1286
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering inf ormation
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See “Maximum speed vs. VCC” on page 400.
Speed(MHz) Power Supply(V) Ordering Code(2) USB Interf a ce Package(1) Op erating Range
20(3) 2.7-5.5 AT90USB1286-AU
AT90USB1286-MU Host (OTG) MD
PS Industrial
(-40° to +85°C)
MD 64 - Lead, 14x1 4 mm Body Size, 1.0mm Body Thickness
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
PS 64 - Lead, 9x9 mm Body Size, 0.50mm Pitch
Quad Flat No Lead Package (QFN)
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ATmega32U6/AT90USB64/128
35.5 AT90USB1287
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering inf ormation
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See “Maximum speed vs. VCC” on page 400.
Speed(MHz) Power Supply(V) Ordering Code(2) USB Interf a ce Package(1) Op erating Range
20(3) 2.7-5.5 AT90USB1287-AU
AT90USB1287-MU Device MD
PS Industrial
(-40° to +85°C)
MD 64 - Lead, 14x1 4 mm Body Size, 1.0mm Body Thickness
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
PS 64 - Lead, 9x9 mm Body Size, 0.50mm Pitch
Quad Flat No Lead Package (QFN)
440 7593J–AVR–03/09
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35.6 TQFP64
441
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442 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
35.7 QFN64
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444 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
36. Errata
37. AT90USB1287/6 Errata.
37.1 AT90USB1287/6 Errata History
Note ‘*’ means a blank or any alphanum eric string
37.2 AT90USB1287/6 First Release
• Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
• USB Eye Diagram violation in low-speed mode
• Transien t perturbation in USB suspend mode generates over consumption
• VBUS Session valid threshold voltage
• USB signal rate
• VBUS residual level
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
9. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI
interrupt flags.
Problem fix/workaround
Do not enable these interrupts, firmware must process these USB events by polling VBUSTI
and IDTI flags.
8. USB Eye Diagram violation in low-speed mode
The low to hig h transition of D- violates the USB eye diagram specification when tran smitting
with low-speed signaling.
Problem fix/workaround
None.
7. Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle stat e following the p erturbati on does
Silicon
Release 90USB1286-16MU 90USB1287-16AU 90USB1287-16MU
First Release Date Code up to 0648 Date Code up to 0714
and lots 0735 6H2726* Date Code up to 0701
Second Release Date Code from 0709 to 0801
except lots 0801 7H5103* from Date Code 0722 to 0806
except lots 0735 6H2726* Date Code from 0714 to 0810
except lots 0748 7H5103*
Third Release Lots 0801 7H5103* and
Date Code from 0814 Date Code from 0814 Lots 0748 7H5103* and
Date Code from 0814
445
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the
USB differential receiver is still enabled and generates a typical 300µA extra-power con-
sumption. Detection of the suspend state after the transient perturbation should be
performed by softw are (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
6. VBUS Session valid threshold voltage
The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.).
That causes the device to attach to the bus only when Vbus is greater than VBusValid
instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the device is detached.
Problem fix/workaround
According to the USB power drop budget, this may require connecting the device toa root
hub or a self-powered hub.
5. UBS signal rate
The average USB signal ra te may sometime be measured out of the USB specifications
(12MHz ±30kHz) with short frames. When measured on a long period, the average signal
rate value complies with the specifications. This bit rate deviation does not generates com-
munication or functi onal errors.
Problem fix/workaround
None.
4. VBUS residual level
In USB device and host mode, on ce a 5V level has been det ected to the VBUS pad, a resid-
ual level (about 3V) ca n be measured on the VBUS pin.
Problem fix/workaround
None.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable ATmega32U6/AT90USB64/128 TWI first versus the others
nodes of the TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up fr om the selected mode, the current consump-
tion will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the par t from the sleep mode should
be disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
446 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep again it may wake up multiple times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
447
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
37.3 AT90USB1287/6 Second Release
• Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
• USB Eye Diagram violation in low-speed mode
• Transien t perturbation in USB suspend mode generates over consumption
• VBUS Session valid threshold voltage
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
7. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI
interrupt flags.
Problem fix/workaround
Do not enable these interrupts, firmware must process these USB events by polling VBUSTI
and IDTI flags.
6. USB Eye Diagram violation in low-speed mode
The low to hig h transition of D- violates the USB eye diagram specification when tran smitting
with low-speed signaling.
Problem fix/workaround
None.
5. Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle stat e following the p erturbati on does
not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the
USB differential receiver is still enabled and generates a typical 300µA extra-power con-
sumption. Detection of the suspend state after the transient perturbation should be
performed by softw are (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
4. VBUS Session valid threshold voltage
The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.).
That causes the device to attach to the bus only when Vbus is greater than VBusValid
instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the device is detached.
Problem fix/workaround
According to the USB power drop budget, this may require connecting the device toa root
hub or a self-powered hub.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
448 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
Problem Fix/workaround
No known workaround, enable ATmega32U6/AT90USB64/128 TWI first versus the others
nodes of the TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up fr om the selected mode, the current consump-
tion will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the par t from the sleep mode should
be disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep again it may wake up multiple times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
449
7593J–AVR–03/09
ATmega32U6/AT90USB64/128
37.4 AT90USB1287/6 Third Release
• Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
• Transien t perturbation in USB suspend mode generates over consumption
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
5. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI
interrupt flags.
Problem fix/workaround
Do not enable these interrupts, firmware must process these USB events by polling VBUSTI
and IDTI flags.
4. Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle stat e following the p erturbati on does
not set the SUSPI bit. The in ternal USB engine r emains in suspend mod e but the USB dif fer-
ential receiver is still enabled and generates a typical 300µA extra-power consum ption.
Detection of the suspend state after the transient perturbation should be performed by soft-
ware (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workar ound, enable ATmeg a32U6/AT90USB64/128 T WI first, before the others
nodes of the TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up fr om the selected mode, the current consump-
tion will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the part from sleep mode should be
disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep mode and wakes-up from an asynchronous timer interrupt and
then goes back into sleep mode, it may wake up multiple times.
Problem Fix/workaround
450 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
A software workaround is to wait beforeperforming the sleep instruction: until
TCNT2>OCR2+1.
38. AT90USB647/6 Errata.
• Incorrect interrupt routine exection for VBUSTI, IDTI interrupts flags
• USB Eye Diagram violation in low-speed mode
• Transien t perturbation in USB suspend mode generates over consumption
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
6. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI
interrupt flags.
Problem fix/workaround
Do not enable these interrupts, firmware must process these USB events by polling VBUSTI
and IDTI flags.
5. USB Eye Diagram violation in low-speed mode
The low to hig h transition of D- violates the USB eye diagram specification when tran smitting
with low-speed signaling.
Problem fix/workaround
None.
4. Transient perturbation in USB suspend mode generates overconsump tion
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle stat e following the p erturbati on does
not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the
USB differential receiver is still enabled and generates a typical 300µA extra-power con-
sumption. Detection of the suspend state after the transient perturbation should be
performed by softw are (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable ATmega32U6/AT90USB64/128 TWI first versus the others
nodes of the TWI network.
2. High current consumption in sleep mode
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7593J–AVR–03/09
ATmega32U6/AT90USB64/128
If a pending interrupt cannot wake the part up fr om the selected mode, the current consump-
tion will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the par t from the sleep mode should
be disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep mode again it may wake up several times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
452 7593J–AVR–03/09
ATmega32U6/AT90USB64/128
39. Datasheet Revision History for ATmega32U6/AT90USB64/128
Please note that the referring page numbers in this section are referred to this document. The
referring re visio n in th is section are referring to the document revision.
39.1 Changes from 7593A to 7593B
1. Changed default configuration for fuse by tes and security byte.
2. Suppression of timer 4,5 registers which does not exist.
3. Updated typical application schematics in USB section
39.2 Changes from 7593B to 7593C
1. Update to package drawings, MQFP64 and TQFP64.
39.3 Changes from 7593C to 7593D
1. For further product compatibility, changed USB PLL possible prescaler configurations.
Only 8MHz and 16MHz crystal frequencies allows USB operation (See Table 6- 11 on
page 49).
39.4 Changes from 7593D to 7593E
1. Updated PLL Prescaler table: configuration words are different between AT90USB64x
and AT90USB128x to enable the PLL with a 16 MHz source.
2. Cleaned up some bits from USB registe rs, and updated information about OTG timers,
remote wake-up, reset and connection timings.
3. Updated clock distribution tree diagram (USB prescaler source and configuration
register).
4. Cleaned up register summary.
5. Suppressed PCINT23:8 that do not exist from External Interrupts.
6. Updated Electrical Characteristics.
7. Added Typical Characteristics.
8. Update Errata section.
39.5 Changes from 7593E to 7593F
1. Removed ’Preliminary’ from document status.
2. Clarification in Stand by mode regarding USB.
39.6 Changes from 7593F to 7593G
1. Updated Errata section.
39.7 Changes from 7593G to 7593H
1. Added Signature information for 64K devices.
2. Fixed figure for typical bus powered application
3. Added min/max values for BOD levels
4. Added ATmega32U6 product
5. Update Errata section
6. Modified descriptions for HWUPE and WAKEUPE interrupts enable (these interrupts
should be enabled only to wake up the CPU core from power down mode).
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7593J–AVR–03/09
ATmega32U6/AT90USB64/128
7. Added description to access unique serial number located in Signature Row see
“Reading the Signature Row from Software” on page 360.
39.8 Changes from 7593H to 7593I
1. Updated Table 8-2 in “Brown- o ut De te ctio n” on pag e 60 . Unused BOD levels removed.
39.9 Changes from 7593I to 7593J
1. Updated Table 8-2 in “Brown- o ut De te ctio n” on pag e 60 . BOD level 100 removed.
2. Updated “Ordering Information” on page 435.
3. Removed ATmega32U6 errata section.
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ATmega32U6/AT90USB64/128
Features.....................................................................................................1
1 Pin Configurations ...................................................................................3
1.1 Disclaimer ................................................................................................................ 4
2 Overview ...................................................................................................4
2.1 B lo ck Dia gr am ............................................................. .................................... ........5
2.2 Pin Descriptions .......................................................................................................7
3 About Code Examples .............................................................................9
4 AVR CPU Core ........................................................................................10
4.1 Introduction ............................................................................................................ 10
4.2 Architectural Overview ...........................................................................................10
4.3 ALU – Arithmetic Logic Unit ...................................................................................11
4.4 S t atu s Re gist er ..... ... .... ... ... ... .... ................................................... ..........................12
4.5 General Purpose Register File ..............................................................................13
4.6 Stack Pointer .........................................................................................................14
4.7 Instruction Execution Timing .................................................................................15
4.8 R e se t an d In te rru p t Han dlin g ....... ... ... ................ .... ... ... ... .... ...................................16
5 AVR ATmega32U6/AT90USB64/128 Memories ....................................19
5.1 In-System Reprogrammable Flash Program Memory ...........................................19
5.2 S RAM Data Memory .... ... ... ... ................................................................. ... ... .... ... ...20
5.3 EEPROM Data Memory ........................................................................................23
5.4 I/O Memory .................................................................................. .... ... ... ... ... ..........29
5.5 External Memory Interface ....................................................................................30
6 System Clock and Clock Options .........................................................39
6.1 Clock Systems and their Distribution .....................................................................39
6.2 Clock Sources .......................................................................................................40
6.3 Low Power Crystal Oscillator .... ................... ................... .................... ...................41
6.4 Low Frequency Crystal Oscillator ..........................................................................43
6.5 Calibrated Internal RC Oscillator ...........................................................................44
6.6 External Clock .......................................................................................................45
6.7 Clock Output Buffer ...............................................................................................46
6.8 Timer/Counter Oscillator ........................................................................................46
6.9 S y ste m Clo ck Pre sca le r ....... .... ... ... ... .................... ................................................4 7
6.10 PLL ......................................................................................................................48
7 Power Management and Sleep Modes .................................................51
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7.1 Idle Mode ...............................................................................................................52
7.2 ADC Noise Reduction Mode ..................................................................................52
7.3 Power-down Mode .................................................................................................52
7.4 P o we r- sa ve M od e .... ................................................................. ... .... ... ... ... .............52
7.5 S t an db y Mo d e ............. ................ ... ... .... ... ... ................................................ .... ... ...53
7.6 Extended Standby Mode .......................................................................................53
7.7 P o we r Red u ctio n Re gis ter .................................................. ...................................54
7.8 Minimizing Power Consumption ............................................................................55
8 System Control and Reset ....................................................................57
8.1 Resetting the AVR .................................................................................................57
8.2 R e se t Sou rc es ...... ... .... ... ................ ... .... ... ... ... ................................................. ... ...57
8.3 Power-on Reset .....................................................................................................58
8.4 External Reset .......................................................................................................59
8.5 B r ow n- ou t Det ec tio n .... ... ... ... ................. ... ... ... ... .... ................................................6 0
8.6 Watchdog Reset ....................................................................................................61
8.7 Internal Voltage Reference ....................................................................................62
8.8 Watchdog Timer ....................................................................................................63
9 Interrupts ................................................................................................68
9.1 In te rr u pt Vec to rs in ATme g a32U 6/ A T90 USB6 4 /12 8 ...... .................... ... ................6 8
10 I/O-Ports ..................................................................................................72
10.1 Introduction .......................................................................................................... 72
10.2 Ports as General Digital I/O .................................................................................73
10.3 Alternate Port Functions ..... .... ... ... ................ ... .... ... ... ... .......................................77
10.4 Register Description for I/O-Ports ........................................................................90
11 External Interrupts .................................................................................94
12 Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers ... 98
12.1 Internal Clock Source ...... ... .... ................... .................................................... ......98
12.2 Prescaler Reset ............................................ ... .... ... ... ..........................................98
12.3 External Clock Source .........................................................................................98
12.4 General Timer/Counter Control Register – GTCCR ............................................99
13 8-bit Timer/Counter0 with PWM ..........................................................100
13.1 Overview ................ ................. ................ ............. ................ ................ ..............1 00
13.2 Timer/Counter Clock Sources ...........................................................................101
13.3 Counter Unit .......... ................................. ... ... ... .... ... ...........................................101
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13.4 Output Compare Unit .........................................................................................102
13.5 Compare Match Output Unit ..............................................................................104
13.6 Modes of Operation ...........................................................................................105
13.7 Timer/Counter Timing Diagrams .......................................................................109
13.8 8-bit Timer/Counter Register Description ..........................................................110
14 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) ........... 117
14.1 Overview ................ ................. ................ ............. ................ ................ ..............1 17
14.2 Accessing 16-bit Registers ................................................................................119
14.3 Timer/Counter Clock Sources ...........................................................................122
14.4 Counter Unit .......... ................................. ... ... ... .... ... ...........................................122
14.5 Input Capture Unit ..... ... ... ................ .... ... ... ... ... ..................................................1 2 4
14.6 Output Compare Units .......................................................................................126
14.7 Compare Match Output Unit ..............................................................................127
14.8 Modes of Operation ...........................................................................................129
14.9 Timer/Counter Timing Diagrams .......................................................................136
14.10 16-bit Timer/Counter Register Description ......................................................138
15 8-bit Timer/Counter2 with PWM and Asynchronous Operation ......149
15.1 Overview ................ ................. ................ ............. ................ ................ ..............1 49
15.2 Timer/Counter Clock Sources ...........................................................................150
15.3 Counter Unit .......... ................................. ... ... ... .... ... ...........................................150
15.4 Output Compare Unit .........................................................................................151
15.5 Compare Match Output Unit ..............................................................................153
15.6 Modes of Operation ...........................................................................................154
15.7 Timer/Counter Timing Diagrams .......................................................................158
15.8 8-bit Timer/Counter Register Description ..........................................................160
15.9 Asynchronous operation of the Timer/Counter ..................................................165
15.10 Timer/Counter Prescaler .................................................................................168
16 Output Compare Modulator (OCM1C0A) ...........................................170
16.1 Overview ................ ................. ................ ............. ................ ................ ..............1 70
16.2 Description .......... ................ ................. ................ ................ ............. ................ . 17 0
17 Serial Peripheral Interface – SPI .........................................................172
17.1 SS Pin Functionality ..........................................................................................176
17.2 Data Modes .......................................................................................................179
18 USART ...................................................................................................181
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18.1 Overview ................ ................. ................ ............. ................ ................ ..............1 81
18.2 Clock Generation ...............................................................................................182
18.3 Frame Formats ..................................................................................................185
18.4 USART Initialization ............ .... ... ... ... .................... ..............................................18 7
18.5 Data Transmission – The USART Transmitter ..................................................188
18.6 Data Reception – The USART Receiver ...........................................................190
18.7 Asynchronous Data Reception ..........................................................................194
18.8 Multi-processor Communication Mode ..............................................................197
18.9 USART Register Description ........ ... .... ... ... ... ... .... ................... ... .................... ... .1 9 8
18.10 Examples of Baud Rate Setting .......................................................................203
19 USART in SPI Mode .............................................................................206
19.1 Overview ................ ................. ................ ............. ................ ................ ..............2 06
19.2 Clock Generation ...............................................................................................207
19.3 SPI Data Modes and Timing ............ .... ... ... .................................... ....................2 0 7
19.4 Frame Formats ..................................................................................................208
19.5 Data Transfer .....................................................................................................210
19.6 USART MSPIM Register Description ................................................................212
19.7 AVR USART MSPIM vs. AVR SPI ............ ... ... .... ................... ... .... ... ... ..............214
20 2-wire Serial Interface ..........................................................................216
20.1 Features ............................................................................................................216
20.2 2-wire Serial Interface Bus Definition ................................................................216
20.3 Data Transfer and Frame Format ......................................................................217
20.4 Multi-master Bus Systems, Arbitration and Synchronization .............................220
20.5 Overview of the TWI Module .............................................................................221
20.6 TWI Register Description ...................................................................................224
20.7 Using the TWI ....................................................................................................227
20.8 Transmission Modes .........................................................................................231
20.9 Multi-master Systems and Arbitration ................................................................244
21 USB controller ......................................................................................246
21.1 Features ............................................................................................................246
21.2 Block Diagram ...................................................................................................246
21.3 Typical Application Implementatio n . .... ... ... ... ... .................... ................... ...........247
21.4 General Operating Modes ......................... ... ................................................. ... .25 1
21.5 Power modes .....................................................................................................255
21.6 Speed Control .. ... ... .................... .................................................... ....................2 5 6
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21.7 Memory management ...... ... .... ... ................................................................ .... ... .2 5 7
21.8 PAD suspend ....................................... ................................... ...........................258
21.9 OTG timers customizing ....................................................................................259
21.10 Plug-in detection ..............................................................................................259
21.11 ID detection .....................................................................................................260
21.12 Registers description .......................................................................................261
21.13 USB Software Operating mod es .......................... ................................... ........266
22 USB Device Operating modes ............................................................267
22.1 Introduction ........................................................................................................ 267
22.2 Power-on and reset ...........................................................................................267
22.3 Endpoint reset ....... .... ... ... ................................ .... ... ... ... .... .................................2 6 7
22.4 USB reset ..................................................... .................................... .................2 6 8
22.5 Endpoint selection ........ ... ... .... ... ................... .................................................... .2 6 8
22.6 Endpoint activation ....... ... ... .... ................................... .................................... ....268
22.7 Address Setup ...................................................................................................269
22.8 Suspend, Wake-up and Resume ...................................... .................................2 7 0
22.9 Detach ...............................................................................................................270
22.10 Remote Wake-up .............................................................................................271
22.11 STALL request .................................................................................................271
22.12 CONTROL endpoint management ..................................................................272
22.13 OUT endpoint management ............................................................................273
22.14 IN endpoint management ................................................................................275
22.15 Isochronous mode ...........................................................................................276
22.16 Overflow ..........................................................................................................277
22.17 Interrupts .........................................................................................................277
22.18 Registers .........................................................................................................278
23 USB Host Operating Modes ................................................................290
23.1 Pipe description .................................................................................................290
23.2 Detach ...............................................................................................................290
23.3 Power-on and Reset ..........................................................................................290
23.4 Device Detection ...............................................................................................291
23.5 Pipe Selection ....................................................................................................291
23.6 Pipe Configuration .............................................................................................291
23.7 USB Reset .... ... ... ... .... ... ................................... .................................... ..............293
23.8 Address Setup ...................................................................................................293
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23.9 Remote Wake-Up detection ..............................................................................293
23.10 USB Pipe Reset ...............................................................................................293
23.11 Pipe Data Access ............................................................................................293
23.12 Control Pipe managemen t ................. ................................................ ... ... .... ... .2 9 4
23.13 OUT Pipe management ...................................................................................294
23.14 IN Pipe management .......................................................................................295
23.15 Interrupt system ...............................................................................................296
23.16 Registers .........................................................................................................297
24 Analog Comparator ..............................................................................310
24.1 Analog Comparator Multiplexed Input ...............................................................312
25 Analog to Digital Converter - ADC ......................................................313
25.1 Features ............................................................................................................313
25.2 Operation ........................................................................................................... 314
25.3 Starting a Conversion ........................................................................................315
25.4 Prescaling and Conversion Tim in g ............ ... ... .... ... ... ... .................................... .3 1 6
25.5 Changing Channel or Reference Selection .......................................................319
25.6 ADC Noise Canceler ....... ... .................................... ................................... ........320
25.7 ADC Conversion Result ............................................. .................................... ....324
25.8 ADC Register Description .......... ... ... .................... ................... ................... .... ....326
26 JTAG Interface and On-chip Debug System ......................................332
26.1 Overview ................ ................. ................ ............. ................ ................ ..............3 32
26.2 Test Access Port – TAP ....................................................................................332
26.3 TAP Controller ...................................................................................................334
26.4 Using the Boundary-scan Chain ........................................................................335
26.5 Using the On-chip Debug System .....................................................................335
26.6 On-chip Debug Specific JTAG Instructions .......................................................336
26.7 On-chip Debug Related Register in I/O Memory ...............................................337
26.8 Using the JTAG Programming Capabilities .. ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ....337
26.9 Bibliography ....................................................................................................... 337
27 IEEE 1149.1 (JTAG) Boundary-scan ...................................................338
27.1 Features ............................................................................................................338
27.2 System Overview ...............................................................................................338
27.3 Data Registers ...................................................................................................338
27.4 Boundary-scan Specific JTAG Instructions .......................................................340
27.5 Boundary-scan Related Register in I/O Memory ...............................................341
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27.6 Boundary-scan Chain ........................................................................................342
27.7 ATmega32U6/AT90USB64/128 Boundary-scan Order .....................................345
27.8 Boundary-scan Description Language Files ......................................................348
28 Boot Loader Support – Read-While-Write Self-Programming .........349
28.1 Boot Loader Features ................... ... .... ..............................................................34 9
28.2 Application and Boot Loader Flash Sections .....................................................349
28.3 Read-While-Write and No Read-While-Write Flash Sections ............................349
28.4 Boot Loader Lock Bits ..... ... .... ... ... ... .... ................................... ...........................352
28.5 Entering the Boot Loader Program ....................................................................353
28.6 Addressing the Flash During Self-Programming ...............................................357
28.7 Self-Programming the Flash ..............................................................................358
29 Memory Programming .........................................................................366
29.1 Program And Data Memory Lock Bits ...............................................................366
29.2 Fuse Bits ............................................................................................................367
29.3 Signature Bytes .................................................................................................369
29.4 Calibration Byte .................................................................................................369
29.5 Parallel Programming Parameters, Pin Mapping, and Commands ...................369
29.6 Parallel Programming ........................................................................................372
29.7 Serial Downloading ............................................................................................380
29.8 Serial Programming Pin Mapping .............. ... ... .... ... ................... ........................381
29.9 Programming via the JTAG Interface ........................ ... .... ... ................... ...........385
30 Electrical Characteristics for AT90USB64/128 ..................................398
30.1 Absolute Maximum Ratings* .............................................................................398
30.2 DC Characteristics ........... ... .... ... ... ................... ..................................................3 9 8
30.3 External Clock Drive Waveforms .......................................................................400
30.4 External Clock Drive ..........................................................................................400
30.5 Maximum speed vs. VCC ........................................................................................................................... 400
30.6 2-wire Serial Interface Characteristics ...............................................................401
30.7 SPI Timing Characteristics ............................................................ ....................4 0 3
30.8 Hardware Boot EntranceTiming Characteristics ................................................404
30.9 ADC Characteristics ..... ... ... .... ... ... ... .................................... ..............................40 5
30.10 External Data Memory Timin g .................................... .................................... .4 0 7
31 AT90USB64/128 Typical Characteristics ..........................................412
31.1 Input Voltage Levels ........... .... ... ... ................................ .... ... ... ... .... ....................413
31.2 Output Voltage Levels .......................................................................................414
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31.3 Power-down Supply Curre nt ...... ... ... .... ................................ ... ... .... ... ... ..............41 6
31.4 Power-save Supply Current ...............................................................................417
31.5 Idle Supply Current .......................................... ..................................................4 1 8
31.6 Active Supply Current .......................... ................................... ...........................418
31.7 Reset Supply Current ........................................................................................419
31.8 I/O Pull-up Current .............................................................................................419
31.9 Bandgap Voltage ...............................................................................................420
31.10 Internal ARef Voltage ......................................................................................421
31.11 USB Regulator .................................................................................................421
31.12 BOD Levels ......... .... ... ................ ... .... ... ... ... ................................................. ... .42 2
31.13 Watchdog Timer Freq u ency .................... ................ ... .... ... ... ................ ... .... ... .42 3
31.14 Internal RC Oscillator Frequency ....................................................................424
31.15 Power-On Reset ..............................................................................................425
32 ATmega32U6 Typical Characteristics ...............................................427
33 Register Summary ...............................................................................428
34 Instruction Set Summary .....................................................................432
35 Ordering Information ...........................................................................435
35.1 ATmega32U6 ....................................................................................................435
35.2 AT90USB646 ................... ................ ................ ................. ................ ................ .436
35.3 AT90USB647 ................... ................ ................ ................. ................ ................ .437
35.4 AT90USB1286 .............. ............. ............. ............. ............. ............. ............ ........43 8
35.5 AT90USB1287 .............. ............. ............. ............. ............. ............. ............ ........43 9
35.6 TQFP64 .............................................................................................................440
35.7 QFN64 ...............................................................................................................442
36 Errata .....................................................................................................444
37 AT90USB1287/6 Errata. .......................................................................444
37.1 AT90USB1287/6 Errata History .........................................................................444
37.2 AT90USB1287/6 First Release .........................................................................444
37.3 AT90USB1287/6 Second Release ....................................................................447
37.4 AT90USB1287/6 Third Release ........................................................................449
38 AT90USB647/6 Errata. .........................................................................450
39 Datasheet Revision History for ATmega32U6/AT90USB64/128 .......452
39.1 Changes from 7593A to 7593B .........................................................................452
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39.2 Changes from 7593B to 7593C .........................................................................452
39.3 Changes from 7593C to 7593D .........................................................................452
39.4 Changes from 7593D to 7593E .........................................................................452
39.5 Changes from 7593E to 7593F .........................................................................452
39.6 Changes from 7593F to 7593G ..................................................................... ... .45 2
39.7 Changes from 7593G to 7593H . ... ... .... ... ...........................................................452
39.8 Changes from 7593H to 7593I ..........................................................................453
39.9 Changes from 7593I to 7593J ...........................................................................453
7593J–AVR–03/09
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