Data Sheet 1 1999-10-07
built using the Infineon multi-technology process SPT® which allows bipola r and CMOS
control circuitry plus DMOS power devices to exist on the same monolithic structure.
Operation modes forward (cw), reverse (ccw), brake and high impedance are invoked
from just two control pins with TTL/CMOS compatible levels. The combination of an
extremely low RDS ON and the use of a power IC package with low thermal resistance and
high therm al c apa city hel ps to minimize sy st em po we r di ss ipa tio n. A blo cking capa cito r
at the supply voltage is the only external circuitry due to the integrated freewheeling
diodes.
1Overview
1.1 Features
Delivers up to 5 A continuous 6 A peak current
Optimized for DC motor management applications
Operates at supply voltages up to 40 V
•Very low RDS ON; typ. 200 m @25°C per switch
Output full short circuit protected
Overtemperature protection with hysteresis
and diagnosis
Short circuit and open load diagnosis
with open drain error flag
Undervoltage lockout
CMOS/TTL compatible inputs with hysteresis
No crossover current
Internal freewheeling diodes
Wide temperature range; 40 °C < Tj < 150 °C
Description
The TLE 5205-2 is an integrated power H-bridge with
DMOS output stages for driving DC-Motors. The part is
Type Ordering Code Package
TLE 5205-2 Q67000-A9283 P-TO220-7-11
TLE 5205-2GP Q67006-A9237 P-DSO-20-10
TLE 5205-2G Q67006-A9325 P-TO263-7-1
TLE 5205-2S Q67000-A9324 P-TO220-7-12
5-A H-Bridge for DC-Motor Applications TLE 5205-2
P-TO220-7-11
P-DSO-20-10
P-TO263-7-1
P-TO220-7-12
TLE 5205-2
Overview
Data Sheet 2 1999-10-07
1.2 Pin Configuration (top view)
Figure 1
AEP02513
OUT1
EF
IN1
GND
IN2
S
V
OUT2
1234567
OUT2OUT1
7651234
IN2
GND
IN1
EF
S
V
AEP01991
TLE 5205-2G
TLE 5205-2S
AEP01680
IN1 IN212
11
S
V
1
2
3
4
20
5
19
6
18
7
17
8
16
9
15
10
14
13
GND
N.C.
V
S
N.C.
GND
EF
Q1 Q2
GND GND
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
AEP01990
OUT1
EF
IN1
GND
IN2 OUT2
S
V
1234567
TLE 5205-2 TLE 5205-2GP
TLE 5205-2
Overview
Data Sheet 3 1999-10-07
1.3 Pin Definitions and Functions
Pin No.
P-TO220 Pin No.
P-DSO Symbol Function
17OUT1Output of Channel 1; Short-circuit protected;
integrated freewheeling diodes for inductive loads.
28EFError Flag; TTL/CMOS compatible output
for error detection; (open drain)
39IN1Control Input 1;
TTL/CMOS compatible
4 1, 10,
11, 20 GND Ground;
internally connected to tab
512IN2Control Input 2;
TTL/CMOS compatible
66, 15
VSSupply Voltage; block to GND
714OUT2Output of Channel 2; Short-circuit protected;
integrated freewheeling diodes for inductive loads.
2, 3, 4, 5,
16, 17, 18,
19
N.C. Not Connected
TLE 5205-2
Overview
Data Sheet 4 1999-10-07
1.4 Functional Block Diagram
Figure 2 Block Diagram
1
0
0
1
11
0
1
0
2
Z
1
0
0
1
Z
0
1
0
2
IN OUT
Error Flag
1
7
EF
IN1
IN2
2
3
5
4
6
OUT1
OUT2
GND
V
S
AEB02394
Diagnosis and Protection Circuit 1
Diagnosis and Protection Circuit 2
TLE 5205-2
Overview
Data Sheet 5 1999-10-07
1.5 Circuit Description
Input Circuit
The control inputs consist of TTL/CMOS-compatible schmitt-triggers with hysteresis.
Buffer amplifiers are driven by this stages.
Output Stages
The output stages consist of a DMOS H-bridge. Integrated circuits protect the outputs
against sh ort-circui t to ground a nd to the su pply volta ge. Positive and negati ve voltage
spikes, which occur when switching inductive loads, are limited by integrated
freewheeling diodes.
A monitoring circuit for e ach output transistor de tects whe ther the partic ular transito r is
active and in this case prevents the corresponding source transistor (sink transistor)
from conducting in sink operation (source operation). Therefore no crossover currents
can occur.
1.6 Input Logic Truth Table
Functional Truth Table
IN1 IN2 OUT1 OUT2 Comments
L L H L Motor turns clockwise
L H L H Motor turns counterclockwise
H L L L Brake; both low side transistors turned-ON
H H Z Z Open circuit detection
Notes for Output Stage
Symbol Value
L Low side transistor is turned-ON
High side transistor is turned-OFF
H High side t ransistor is turne d-ON
Low side transistor is turned-OFF
Z High side t ransistor is turne d-OFF
Low side transistor is turned-OFF
TLE 5205-2
Overview
Data Sheet 6 1999-10-07
1.7 Monitoring Functions
Undervoltage lockout (UVLO):
When VS reaches t he s witch on voltag e VSON
the I C becomes activ e with a h ysteres is.
All output transistors are switched off if the supply voltage VS drops below the switch off
value VSOFF.
1.8 Protective Function
Various errors like short-circuit to + VS, ground or across the load are detected. All faults
result in turn-OFF of the output stages after a delay of 50 µs and setting of the error flag
EF to ground. Changing the inputs resets the error flag.
a. Output Shorted to Ground Detection
If a high s ide tra nsistor is sw itche d on a nd its output is sh orted to grou nd, the output
current is internally limited. After a delay of 50 µs all outputs will be switched-OFF and
the error flag is set.
b. Output Shorted to + VS Detection
If a low si de transis tor is switc hed on a nd its ou tput is s horted to the supply voltage,
the output current is internally limited. After a delay of 50 µs all outputs will be
switched-OFF and the error flag is set.
c. Overload Detection
An internal circuit detects if the current through the low side transistor exceeds the
trippoint ISDL. In this case all outputs are turned off after 50 µs and the error flag is set.
d. Overtemperature Protection
At a junction temperature higher than 150 °C the thermal shutdown turns-OFF, all four
output stages commonly and the error flag is set with a delay.
e. Open Load Detection
The output Q1 has a 10 k pull-up resistor and the output Q2 has a 10 k pull-down
resistor. If E1 and E2 are high, all output power stages are turned-OFF. In case of no
load between Q1 and Q2 the output voltage Q1 is VS and Q2 is ground. This state will
be detected by two comparators and an error flag will be set after a delay time of
50 µs. Changing the inputs resets the error flip flop.
TLE 5205-2
Overview
Data Sheet 7 1999-10-07
Figure 3 Simplified Schematic for Open Load Detection
=
=
&50 s
µ
RS
FF
EF
AES02395
V
EL
EH
V
Pull UP
10 k
10 k
Down
Pull
TLE 5205-2
Diagnosis
Data Sheet 8 1999-10-07
2 Diagnosis
Various errors as listed in the table “Diagnosis” are detected. Short circuits and overload
result in turning off the output stages after a delay t
dSD and setting the error flag
simultaneously [EF = L]. Changing the inputs to a state where the fault is not detectable
resets the error flag (input toggling) with the exception of short circuit from OUT1 to
OUT2 (load short circuit).
Flag IN1 IN2 OUT1 OUT2 EF Remarks Nr.
Open circuit between OUT1 and OUT2 0
0
1
1
0
1
0
1
H
L
L
Z
L
H
L
Z
1
1
1
0
Not detectable
Not detectable
Not detectable
1
2
3
4
Short circuit from OUT1 to OUT2 0
0
1
1
0
1
0
1
VS/2
VS/2
L
Z
VS/2
VS/2
L
Z
0
0
1
1Not detectable
Not detectable
5
6
7
8
Short circuit from OUT1 to GND 0
0
1
1
0
1
0
1
GND
GND
GND
GND
L
H
L
L
0
1
1
1
Not detectable
Not detectable
Not detectable
9
10
11
12
Short circuit from OUT2 to GND 0
0
1
1
0
1
0
1
H
L
L
L
GND
GND
GND
GND
1
0
1
1
Not detectable
Not detectable
Not detectable
13
14
15
16
Short circuit from OUT1 to VS
0
0
1
1
0
1
0
1
VS
VS
VS
VS
L
H
H
H
1
0
0
1
Not detectable
Not detectable
17
18
19
20
Short circuit from OUT2 to VS
0
0
1
1
0
1
0
1
H
L
H
H
VS
VS
VS
VS
0
1
0
1
Not detectable
Not detectable
21
22
23
24
Overtemperature or undervoltage 0
0
1
1
0
1
0
1
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
25
26
27
28
IN: 0 = Logic LOW
1 = Logic HIGH OUT: Z = Output in tristate condition
= VS /2 due to internal Pull-up/down resistors EF: 1 = No error
0 = Error
L = Output in sink condition
H = Output in source condition
TLE 5205-2
Electrical Characteristics
Data Sheet 9 1999-10-07
3 Electrical Characteristics
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.
3.1 Absolute Maximum Ratings
– 40 °C < Tj < 150 °C
Parameter Symbol Limit Values Unit Remarks
min. max.
Voltages
Supply voltage VS– 0.3 40 V
– 1 40 V t < 0.5 s; IS > – 5 A
Logic input voltage VIN1, 2 – 0.3 7 V 0 V < VS < 40 V
Diagnostics output voltage VEF – 0.3 7 V
Currents of DMOS-Transistors and Freewheeling Diodes
Output current (cont.) IOUT1, 2 – 5 5 A
Output current (peak) IOUT1, 2 – 6 6 A tp < 100 ms; T=1s
Output current (peak) IOUT1, 2 – – A tp < 50 µs; T=1s;
internally limitted;
see overcurrent
Temperatures
Junction temperature Tj– 40 150 °C–
Storage temperature Tstg – 50 150 °C–
Thermal Resistances
Junctio n case RthjC 3 K/W P-TO220-7-11/12,
P-TO263-7-1
Junction ambient RthjA 65 K/W P-TO220-7-11/12
75 K/W P-TO263-7-1
Junctio n case RthjC 5 K/W P-DSO-20-10
Junction ambient RthjA 50 K/W P-DSO-20-10
TLE 5205-2
Electrical Characteristics
Data Sheet 10 1999-10-07
3.2 Operating Range
Parameter Symbol Limit Values Unit Remarks
min. max.
Supply voltage VSVUV ON 40 V After VS rising
above VUV ON
Supply voltage increasing – 0.3 VUV ON V Outputs in tristate
condition
Supply voltage decreasing – 0.3 VUV OFF V
Logic input voltage VIN1, 2 – 0.3 7 V
Junction temperature Tj– 40 150 °C–
3.3 Electrical Characteristics
6 V < VS < 18 V; IN1 = IN2 = HIGH
IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter Symbol Limi t Values Unit Test Condition
min. typ. max.
Current Consumption
Quiescent current IS––10mAIN1 = IN2 = LOW;
VS = 13.2 V
Under Voltage Lockout
UV-Switch-ON voltage VUV ON –5.36VVS increasing
UV-Switch-OFF voltage VUV OFF 3.5 4.7 5.6 V VS decreasing
UV-ON/OFF-Hysteresis VUV HY 0.2 0.6 V VUV ONVUV OFF
TLE 5205-2
Electrical Characteristics
Data Sheet 11 1999-10-07
Outputs OUT1, 2
Static Drain-Source-On Resistance
Source
IOUT = – 3 A RDS ON H 220 350 m6V < VS < 1 8 V
Tj = 25 °C
600 m6V < VS < 18 V
350 500 mVSON
< VS 6V
Tj = 25 °C
800 mVSON
< VS 6V
Sink
IOUT = 3 A RDS ON L 230 350 m6V < VS < 18 V
Tj = 25 °C
600 m6V < VS < 18 V
400 600 mVSON
< VS 6V
Tj = 25 °C
1000 mVSON
< VS 6V
Note: Values of
R
DS ON
for
V
S ON
<
V
S
6 V are guaranteed by design.
Overcurrent
Source shutdown trippoint ISDH ––10ATj = – 40 °C
–8–A
Tj = 25 °C
6––A
Tj = 150 °C
Sink shutdown trippoint ISDL ––10ATj = – 40 °C
–8–A
Tj = 25 °C
6––A
Tj = 150 °C
Shutdown delay time tdSD 25 50 80 µs–
3.3 Electrical Characteristics (cont’d)
6 V < VS < 18 V; IN1 = IN2 = HIGH
IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter Symbol Limi t Values Unit Test Condition
min. typ. max.
TLE 5205-2
Electrical Characteristics
Data Sheet 12 1999-10-07
Short Circuit Current Limitation
Source current ISCH ––20At < tdSD
Sink current ISCL ––15At < tdSD
Open Circuit
Pull up resistor RUP 51020k
Pull down resistor RDOWN 51020k
Switching threshold H VEH 22.53V
Switching threshold L VEH 22.43V
Detection delay time tdSD 25 50 80 µs–
Output Delay Times (Device Active for t > 1 m s )
Source ON tdONH –1020
µsIOUT = – 3 A
resist ive l oad
Sink ON tdONL –1020
µsIOUT = 3 A
resist ive l oad
Source OFF tdOFFH –25µsIOUT = – 3 A
resist ive l oad
Sink OFF tdOFFL –25µsIOUT = 3 A
resist ive l oad
3.3 Electrical Characteristics (cont’d)
6 V < VS < 18 V; IN1 = IN2 = HIGH
IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter Symbol Limi t Values Unit Test Condition
min. typ. max.
TLE 5205-2
Electrical Characteristics
Data Sheet 13 1999-10-07
Output Switching Times (Device Active for t > 1 ms)
Source ON tON H –1530
µsIOUT = – 3 A
resist ive l oad
Sink ON tON L –510
µsIOUT = 3 A
resist ive l oad
Source OFF tOFF H –25µsIOUT = – 3 A
resist ive l oad
Sink OFF tOFF L –25µsIOUT = 3 A
resist ive l oad
Clamp Diodes
Forward Voltage
High-side VFH –11.5VIF = 3 A
Low-side VFL –1.11.5VIF = 3 A
Leakage Current
Source ILKH 100 50 µAOUT1 = VS
Sink ILKL 50 100 µAOUT2 = GND
Logic
Control Inputs IN 1, 2
H-input voltage threshold VINH 2.8 2.5 V
L-input voltage VINL –1.71.2V
Hysteresis of input vol tage VINHY 0.4 0.8 1.2 V
H-input current IINH –2 0 2 µAVIN = 5 V
L-input current IINL –10 –4 0 µAVIN = 0 V
3.3 Electrical Characteristics (cont’d)
6 V < VS < 18 V; IN1 = IN2 = HIGH
IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter Symbol Limi t Values Unit Test Condition
min. typ. max.
TLE 5205-2
Electrical Characteristics
Data Sheet 14 1999-10-07
Error Flag Output EF
Low output voltage VEFL 0.25 0.5 V IEF = 3 mA
Leakage current IEFL ––10
µAVEF = 7 V
Thermal Shutdown
Thermal shutdown junction
temperature TjSD 150 175 200 °C–
Thermal switch-on junction
temperature TjSO 120 170 °C–
Temperature hysteresis T–30–K
Shutdown delay time tdSD 25 50 80 µs–
Note: Values of thermal shutdown are guaranteed by design.
3.3 Electrical Characteristics (cont’d)
6 V < VS < 18 V; IN1 = IN2 = HIGH
IOUT1, 2 = 0 A (No load); – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter Symbol Limi t Values Unit Test Condition
min. typ. max.
TLE 5205-2
Electrical Characteristics
Data Sheet 15 1999-10-07
Figure 4 Test Circuit
Overcurrent Short Circuit Open Circuit
IOUT ISD ISC IOC
EF
IN1
IN2
OUT1
OUT2
TLE 5205-2
2
3
57
1
6
4
4700 F
µ
V
S
GND
AES02396
Ι
EF
IN1
Ι
IN2
Ι
FL
Ι
V
EF
V
IN1 IN2
V V
OUT1 OUT2
V
R
Load
OUT1
Ι
OUT2
Ι
470 nF
FU
Ι
;
S
Ι
V
S
63 V
TLE 5205-2
Electrical Characteristics
Data Sheet 16 1999-10-07
Figure 5 Switching Time Definitions
Figure 6 Application Circuit
AET01994
t
t
Ι
OUT
=
IN
V
Source
0
0
3
t
dONH
50%
t
rf
t
100 ns
t
dOFFH
Ι
OUT
Sink
t
50%
20%
80%
t
ONH
t
OFFL ONL
t
OFFH
t
dOFFL
tt
dONL
5
A
V
A
3
0
80%
20%
50% 50%
20%
80%
80%
20%
50%
_
<
EF
IN1
IN2
M
OUT1
OUT2
TLE 5205-2
2
3
57
1
6
4
100 nF
+ 5 V
P
µ
100 F
µ
V
S
+
V
S
GND
2 k
Ι
N
= 3 A
Ι
BL
= 6 A
AES02397
TLE 5205-2
Electrical Characteristics
Data Sheet 17 1999-10-07
Figure 7 Timing Diagram for Output Shorted to Ground
Figure 8 Timing Diagram for Output Shorted to VS
AED01997
IN1, 2
Ι
OUT1, 2
V
EF
R
Short
x
V
FL
OUT1, 2
SCH
Ι
Ι
SCH
dSD
t
Ι
SDH
AED01998
IN1, 2
Ι
OUT1, 2
V
EF
R
Short
x
V
FU
OUT1, 2
SCL
Ι
Ι
SCL
dSD
t
SDL
Ι
S
V
TLE 5205-2
Electrical Characteristics
Data Sheet 18 1999-10-07
Diagrams
Quiescent Current IS (Active)
versus Junction Temperature Tj
Input Switching Thresholds VINH, L
versus Junction Temperature Tj
Static Drain-Source ON-Resistance
versus Junction Temperature Tj
Clamp Diode Forward Voltage VF
versus Junction Temperature Tj
-50
10 15050
S
AED02398
100 C
2
3
4
5
6
7
= 18 V
S
V
j
T
Ι
mA
V
= 6 V
S
0
AED02400
0.5
1.0
1.5
2.0
2.5
3.0
V
INH
INL
V
INH, L
V
500-50 C
100 150
T
j
0
AED02399
0.1
0.2
0.3
0.4
0.5
0.6
j
T
Low Side Transistor
High Side Transistor
R
ON
500-50 C
100 150
0.7
AED02401
0.8
0.9
1.0
1.1
1.2
1.3
High Side Transistor
Low Side Transistor
V
F
500-50 C
100 150
T
j
TLE 5205-2
Electrical Characteristics
Data Sheet 19 1999-10-07
Overcurrent Shutdown Threshold ISD
versus Junction Temperature Tj
Error-Flag Saturation Output Voltage
VEF versus Junction Temperature Tj
Switching Threshold VEH, VEH
versus Junction Temperature Tj
0
SD
AED02402
2
4
6
8
10
12
Ι
Low Side Transistor
High Side Transistor
50
0-50 C
100 150
T
j
-50
00 15050
AED02403
100 C
0.1
0.2
0.3
0.4
0.5
0.6
j
T
V
EF
-50
1.8 0 15050
AED02404
100 C
2.0
2.2
2.4
2.6
2.8
3.0
j
T
V
EH
V
EL
V
EH
,
V
EL
TLE 5205-2
Package Outlines
Data Sheet 20 1999-10-07
4 Package Outlines
P-TO220-7-11
(Plastic Transistor Single Outline Package)
Typical
±0.1
1.27 4.4
9.25
±0.2
0.05
1)
All metal surfaces tin plated, except area of cut.
2.4 0.5
±0.1
±0.3
8.6
10.2
±0.3
±0.4
3.9
±0.4
8.4
3.7
±0.3
A
A0.25
M
9.8
±0.15
2.8
1)
15.65
±0.3
13.4
0...0.15
1.27 0.6
±0.1
C
±0.2
17
±0.3
8.5
1)
9.9
±0.2
7x
-0.15
3.7
10
±0.2
6x
C
1.6
±0.3
GPT09083
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
TLE 5205-2
Package Outlines
Data Sheet 21 1999-10-07
+0.07
-0.02
-0.3
1.2
2.8
1.3
0.25
1) Does not include plastic or metal protrusion of 0.15 max. per side
20x0.25
M
1)
Heatsink
0.95
14.2
+0.15
Index Marking
15.9
101
0.1
+0.13
0.4
1.27
3.5 max.
0
6.3
11
3.25
20 11
±0.15
±0.1
±0.15
1 x 45˚
±0.3
±3˚
±0.15
15.74
±0.1
A
A
1)
B
0.25
M
B
GPS05791
P-DSO-20-10
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
TLE 5205-2
Package Outlines
Data Sheet 22 1999-10-07
A
8˚ max.
BA0.25
M
0.1
Typical
9.8
±0.15
±0.2
10
8.5
1)
8
1)
(15)
±0.2
9.25
±0.3
1
0...0.15
7x0.6
±0.1
±0.1
1.27 4.4
B
0.5
±0.1
±0.3
2.7
4.7
±0.5
0.05
1)
0.1
All metal surfaces tin plated, except area of cut.
2.4
6x1.27
P-TO263-7-1 Option E3180
(Plastic Transistor Single Outline Package)
GPT09114
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
TLE 5205-2
Package Outlines
Data Sheet 23 1999-10-07
GPT09084
A
BA0.25
M
Typical
9.8
±0.15
2.8
1)
15.65
±0.3
13.4
0...0.15
1.27 0.6
±0.1
±0.1
1.27 4.4
B
9.25
±0.2
0.05
1)
All metal surfaces tin plated, except area of cut.
C
±0.2
17
±0.3
8.5
1)
10
±0.2
3.7
-0.15
C
2.4 0.5
±0.1
13
±0.5
±0.5
11
7x
P-TO220-7-12
(Plastic Transistor Single Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm