DS021 (v2.2) June 25, 2000 www.xilinx.com 1
Product Specification 1-800-255-7778
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Product Features
• Certified to MI L-PRF -38535, appendix A QML
(Qualified Manufacturers Listing)
• Also av ai l abl e under the fol lo wing Standard Microcircuit
Drawings (SMD)
- XC4005E 5962-97522
- XC4010E 5962-97523
- XC4013E 5962-97524
- XC4025E 5962-97525
- XC4028EX 5962-98509
• For more information contact the Defense Suppl y
Center Columb us (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
• System feat ured Field-Programmable Gate Arra ys
- Select-RAMTM memory: on-chip ultra-f ast RAM with
·Synchronous write option
·Dual-port RAM option
- A bundant flip-fl ops
- Flexible function generators
- Dedicat ed high -speed carr y logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- E ight global low-skew clo ck or signal distri bution
networks
•System Performance beyond 60 MHz
•Flexible A rray Arc hit e c tur e
•Lo w P ower Segmented Routing Architecture
•Systems-Oriented F eatures
- IEEE 1 149 .1-co mp a tible boundary scan logic
support
- Individual ly programmable output slew rate
- P rogrammable input pull-up or pull -down resistors
- 12 mA sink current per XQ4000E/EX output
•Configured by Loading Binar y Fi le
- Unlimited reprogrammability
•Readback Capability
- P rogram verification
- I nt ernal node observab ilit y
•Backw ard Compatible wit h XC4000 Devices
•Development System runs on most common computer
platforms
- I nterfaces to popular de sign environments
- F ully autom atic mapping, placement and routi ng
- I nteractive design editor for d esign optim ization
•Availab le Speed Grades:
- XQ4000E -3 for plastic packages only
- -4 for ceramic packages only
- XQ4028EX -4 for all packages
More Information
F or more information refer to Xilinx XC4000E and XC4000X
series Field Programmable Gate Arrays product specifica-
tion. This data sheet contains pinout tables for XQ4010E
only. Refer to Xilinx web site for pinout tables for other
devices. (Pinouts for XQ4000E/EX are identical to
XC4000E/EX.)
(http://www.xilinx.com/partinfo/databook.htm)
0QPRO XQ4000E/EX
QML High-Reliab ility F PGAs
DS021 (v2.2) June 25, 2000 02P rod uc t Sp ec if i c ation
R
QPRO XQ4000E/EX QML High-Reliability FPGAs
2www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4000E Switching Characteristics
XQ4000E Absolute Maximum Ratings(1)
Table 1: XQ4 000E/EX Fiel d Programmabl e Gate A rrays
Device
Max.
Logic
Gates
(No RAM)
Max.
RAM Bits
(No
Logic)
Typical
Gate Range
(Logic and
RAM)(1) CLB
Matrix Total
CLBs
Number
of
Flip-Flops
Max.
Decode
Inputs
per Side
Max.
User
I/O Packages
XQ4 005E 5,000 6,272 3,0 00 - 9,000 14 x 14 196 616 42 112 PG156 ,
CB164
XQ4 010E 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 60 160 PG191 ,
CB196,
HQ208
XQ4013E 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 72 192 PG223,
CB228,
HQ240
XQ4025E 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 96 256 PG299,
CB228
XQ4028EX 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 96 256 PG299,
CB228,
HQ240,
BG352
Notes:
1. Max values of Typ ical Gate Range include 20-30% of CLBs used as RAM.
Symbol Description Units
VCC Supply voltage relative to GND –0 .5 to +7 .0 V
VIN Input voltage relative to GND(2) –0.5 to VCC + 0.5 V
VTS Voltage app lied to High-Z output(2) –0.5 to VCC + 0.5 V
TSTG Storage temperature (ambie nt) –65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
TJJunct ion temperature Ceramic package +150 °C
Plastic package +125 °C
Notes:
1. Stresses beyond those lis ted under Absolute Maxi m um Rati ngs may cause permanent damage to the device. These ar e stress
ratings onl y, and functional operation of the devi ce at these or any other conditions bey ond those list ed under Operating Conditions
is not imp lied. Exposure to Absolute Maxim um Ratings conditions for extended periods of time may affec t device reliab il ity.
2. Maximum DC e xcu rsion a bov e VCC or belo w Ground must be limit ed to ei ther 0.5V or 10 mA, whi chever is eas ier to achie v e. During
transitions, the device pins may undershoot to –2.0V or overshoot to VCC + 2.0V, provided thi s over or undershoot las ts l ess than
10 ns and with t he forci ng current being limite d to 200 mA.
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 3
Product Specification 1-800-255-7778
R
XQ4000E Recommended Operating Conditions(1,2)
XQ4000E DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Max Units
VCC Suppl y voltage relative to GND, TJ = –55°C to +125°CPlastic 4.5 5.5 V
Suppl y voltage relative to GND, TC = –55°C to +125°C Ceramic 4.5 5.5 V
VIH High-Level Input Voltage TTL inputs 2.0 VCC V
CMOS inputs 70% 100% VCC
VIL Low-Level Input Voltage TTL inputs 0 0.8 V
CMOS inputs 0 20% VCC
TIN Input signal transition time - 250 ns
Notes:
1. At junction temperatures above those listed as Ope rating Conditions, all dela y parameters increa se by 0.35% per °C.
2. In put an d output measurement thr eshold are 1.5V for TTL and 2.5V f or CMOS.
Symbol Description Min Max Units
VOH High-le vel output voltage @ IOH = –4.0 mA, VCC min TTL output s 2. 4 - V
High-level output voltage @ IOH = –1.0 mA, VCC min CMOS out puts VCC – 0.5 - V
VOL Low-leve l output voltage @ IOL = 12.0 mA, VCC min(1) TTL output s - 0.4 V
CMOS outputs - 0.4 V
ICCO Quiescent FP GA su pply curren t(2) -50mA
ILInput or outpu t leakage current –10 +10 µA
CIN Input capacitance (sampl e tested) - 16 pF
IRIN Pad pull-up (when selected) at VIN = 0V (sample tested)(3) –0.02 –0.25 mA
IRLL Horizontal longline pull-up (when selected) at log ic Low(3) 0.2 2.5 mA
Notes:
1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2. With no out put curr ent l oads , no a ctiv e input or Long line pul l-up resist ors , a ll pa ckage pi ns at VCC or GN D, and the FPGA co nfigur ed
with t he developmen t system Tie option.
3. Characterized Only.
QPRO XQ4000E/EX QML High-Reliability FPGAs
4www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4000E Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values where one global clock input
drives one vertical clock line in each accessible c olumn, and
where all access ible I OB and CLB fl ip-fl ops are clocked by
the global clock net.
When few er vertical clock lines are connected, the clock dis-
tribution is faster ; when mul tiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Dev elopment System) and bac k-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing paramete rs assum e worst-ca se operating conditions
(supply voltage and jun ction temperature).
Note: -3 Speed Grade only applies to XQ4010E and
XQ4013E Plastic Pac kage options only. -4 Speed Grade
applies to all XQ devices and is only available in
Ceramic Pac kages only.
XQ4000E Global Buffer Switching Characteristics
Symbol Description Device
-3(1) -4(2)
UnitsMax Max
TPG F rom pad through primary buffer, to any cloc k K XQ4005E - 7.0 ns
XQ4010E 6.3 11.0 ns
XQ4013E 6.8 11.5 ns
XQ4025E - 12.5 ns
TSG From pad through seconda ry buffer, to any clock K XQ4005E - 7.5 ns
XQ4010E 6.8 11.5 ns
XQ4013E 7.3 12.0 ns
XQ4025E - 13.0 ns
Notes:
1. For plastic package options only.
2. For ceramic package options only.
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 5
Product Specification 1-800-255-7778
R
XQ4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System ) and back-annotat ed to t he simulation net list.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4 000E devi ces unless otherwise noted.
The following guidelines reflect worst-case values over the
recomm ended operating conditions.
Symbol Description Device
-3 -4
UnitsMax Max
TBUF Driving a Horizontal Longline (LL):
TIO1 I going High or Low to LL going High or Low, whil e T is Low.
Buffer is con stantly active.(1) XQ4005E - 5.0 ns
XQ4010E 6.4 8.0 ns
XQ4013E 7.2 9.0 ns
XQ4025E - 11.0 ns
TIO2 I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain. (1) XQ4005E - 6.0 ns
XQ4010E 6.9 10.5 ns
XQ4013E 7.7 11.0 ns
XQ4025E - 12.0 ns
TON T going Low to LL g oing from resistive pull-up or floating High to
active Low. TBUF configured as open-drain or active buffer with
I=Low.
(1)
XQ4005E - 7.0 ns
XQ4010E 7.3 8.5 ns
XQ4013E 7.5 8.7 ns
XQ4025E - 11.0 ns
TOFF T going High to TBUF going inactive, not driving LL. XQ4005E - 1.8 ns
XQ4010E 1.5 1.8 ns
XQ4013E 1.5 1.8 ns
XQ4025E - 1.8 ns
TPUS T going High to LL going from Low to High, pulled up by a single
resistor.(1) XQ4005E - 23.0 ns
XQ4010E 22.0 29.0 ns
XQ4013E 26.0 32.0 ns
XQ4025E - 42.0 ns
TPUF T going High to LL going from Low to High, pulled up by two
resistors.(1) XQ4005E - 10.0 ns
XQ4010E 11.0 13.5 ns
XQ4013E 13.0 15.0 ns
XQ4025E - 18.0 ns
Notes:
1. These v alues incl ude a minimum load. Use t he static timing a nalyzer t o determi ne the delay for each destinat ion.
QPRO XQ4000E/EX QML High-Reliability FPGAs
6www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System ) and back-annotat ed to t he simulation net list.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4 000E devi ces unless otherwise noted.
The following guidelines reflect worst-case values over the
recomm ended operating conditions.
Symbol Description(1,2) Device
-3 -4
UnitsMax Max
TWAF Full length, both pull-ups , inputs from IOB I-pins XQ4005E - 9.5 ns
XQ4010E 9.0 15.0 ns
XQ4013E 11.0 16.0 ns
XQ4025E - 18.0 ns
TWAFL Full length, both pull-ups , inputs from internal logic XQ4005E - 12.5 ns
XQ4010E 11.0 18.0 ns
XQ4013E 13.0 19.0 ns
XQ4025E - 21.0 ns
TWAO Half length, one pull-up, inputs from IOB I-pins XQ4005E - 10. 5 ns
XQ4010E 10.0 16.0 ns
XQ4013E 12.0 17.0 ns
XQ4025E - 19.0 ns
TWAOL Ha lf length, one pull-up, inputs from inter nal logic XQ4005E - 12. 5 ns
XQ4010E 12.0 18.0 ns
XQ4013E 14.0 19.0 ns
XQ4025E - 21.0 ns
Notes:
1. These delays are specified from the decoder input to the decoder output.
2. Fe wer than the specif ied number of pull-up resist ors can be used, if desired. Using fewer pull-ups reduces power con sumption but
increases delays. Use the static timin g analyzer t o determine delays if f e wer pull -ups are used.
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 7
Product Specification 1-800-255-7778
R
XQ4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System ) and back-annotated to the simulation netlist .
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4 000E devi ces unless otherwise noted.
Symbol Description
-3 -4
UnitsMin Max Min Max
Combinatorial Delays
TILO F/G inp uts to X/Y outputs - 2.01 - 2.7 ns
TIHO F/G inputs via H to X/Y outputs - 4.3 - 4.7 ns
THH0O C inputs via SR through H to X/Y outputs - 3.3 - 4.1 ns
THH1O C inputs via H to X/Y output s - 3.6 - 3.7 ns
THH2O C inputs via DIN through H to X/Y outputs - 3 .6 - 4.5 ns
CLB Fast C a rr y Logic
TOPCY Operand inputs (F1, F2, G1, G4) to COUT -2.6-3.2ns
TASCY Add/Subtract input (F3) to COUT -4.4-5.5ns
TINCY Initialization inputs (F1, F3) to COUT -1.7-1.7ns
TSUM CIN through function generators to X/Y outputs - 3 .3 - 3.8 ns
TBYP CIN to C OUT, bypass function generators - 0.7 - 1.0 ns
Sequential Delays
TCKO Clock K to outputs Q - 2.8 - 3.7 ns
Setup Time before Clock K
TICK F/G inputs 3.0 - 4. 0 - ns
TIHCK F/G i n pu ts via H 4.6 - 6.1 - n s
THH0CK C inputs via H0 through H 3.6 - 4.5 - ns
THH1CK C inputs via H1 through H 4.1 - 5.0 - ns
THH2CK C inputs via H2 through H 3.8 - 4.8 - ns
TDICK C inputs via DIN 2.4 - 3.0 - ns
TECCK C inputs via EC 3.0 - 4.0 - ns
TRCK C inputs via S/R, going Low (inactive) 4.0 - 4.2 - ns
TCCK CIN input via F/G 2.1 - 2. 5 - ns
TCHCK CIN input via F/G and H 3.5 - 4. 2 - ns
QPRO XQ4000E/EX QML High-Reliability FPGAs
8www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4000E CLB Switching Characteristic Guidelines (continued)
Symbol
Description
-3 -4
UnitsMin Max Min Max
Hold Time after Clock K
TCKI F/ G in puts 0 - 0 - ns
TCKIH F/ G inputs via H 0 - 0 - ns
TCKHH0 C inputs via H0 through H 0 - 0 - ns
TCKHH1 C inputs via H1 through H 0 - 0 - ns
TCKHH2 C inputs via H2 through H 0 - 0 - ns
TCKDI C inputs via DIN/H2 0 - 0 - ns
TCKEC C inputs via EC 0 - 0 - ns
TCKR C inputs via SR, going Low (inactive) 0 - 0 - ns
Clock
TCH Clock High time 4.0 - 4 .5 - ns
TCL Clock Low time 4.0 - 4.5 - ns
Set/Reset Direct
TRPW Wi dth (High) 4.0 - 5 .5 - ns
TRIO Delay from C in put s via S/R, go ing High to Q - 4.0 - 6. 5 ns
Master Set/Res et(1)
TMRW Width (High or Low) 11.5 - 13.0 - ns
TMRQ Delay from Glob al Set/Reset net to Q - 18.7 - 23.0 ns
TMRK Global Set/Reset inactive to first active clo ck K ed ge - 18.7 - 23.0 ns
FTOG To ggle Frequenc y(2) - 125 - 111 MHz
Notes:
1. Timing is based on the XC4005E. For other devices see the static timing analyzer.
2. Export Control Ma x. flip-fl op toggle ra te.
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 9
Product Specification 1-800-255-7778
R
XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000E /EX devices unless otherwise noted.
Single-Port RAM Synchronous (Edge-Tr iggered) Write Operation Characteristics
Symbo l Write Op eration Descript ion Siz e -3 -4 UnitsMin Max Min Max
TWCS Address write cycle time (clock K period) 16x2 14.4 - 15.0 - ns
TWCTS 32x1 14.4 - 15.0 - ns
TWPS Clock K pulse width (active edge ) 16x2 7. 2 1 m s 7.5 1 m s ns
TWPTS 32x1 7. 2 1 m s 7.5 1 ms ns
TASS Ad dress setup time before clock K 16x2 2.4 - 2.8 - ns
TASTS 32x1 2.4 - 2.8 - ns
TAHS Address hold time after clock K 16x2 0 - 0 - ns
TAHTS 32x1 0 - 0 - ns
TDSS DIN setup time before clock K 16x2 3. 2 - 3.5 - ns
TDSTS 32x1 1.9 - 2.5 - ns
TDHS DIN ho ld time after clock K 16x2 0 - 0 - ns
TDHTS 32x1 0 - 0 - ns
TWSS WE setup time before clock K 16x2 2. 0 - 2.2 - ns
TWSTS 32x1 2.0 - 2.2 - ns
TWHS WE ho ld time after clock K 16x2 0 - 0 - ns
TWHTS 32x1 0 - 0 - ns
TWOS Data valid after cloc k K 16x2 8.8 - - 10.3 ns
TWOTS 32x1 10.3 - - 11.6 ns
Notes:
1. Timing for the 16x1 RAM option i s ide ntical to 16x2 RAM timing.
2. Applicable Read timing specifica ti ons are identical to Level -Sensitive Read timi ng.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol Write Operation Description Size(1) -3 -4 UnitsMin Max Min Max
TWCDS Address write cycle time (clock K period) 16x1 14.4 15.0 ns
TWPDS Clock K pul se width (active edg e) 16x1 7.2 1 m s 7.5 1 ms ns
TASDS A ddress setup time befo re clock K 16x1 2.5 - 2.8 - ns
TAHDS Address hold time after clock K 16x1 0 - 0 - ns
TDSDS DIN setup time before clock K 16x1 2.5 - 2.2 - ns
TDHDS DIN hold time after clock K 16x1 0 - 0 - ns
TWSDS WE setup time before clock K 16x1 1.8 - 2.2 - ns
TWHDS WE hold time after clock K 16x1 0 - 0.3 - ns
TWODS Data val id after clock K 16x1 - 7.8 - 10.0 ns
Notes:
1. Applicable Read timing specifica ti ons are identical to Level -Sensitive Read timi ng.
QPRO XQ4000E/EX QML High-Reliability FPGAs
10 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4000E CLB RAM Synchronous (Edge-Triggered) W rite Timing Waveform
XQ4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform
DS021_01_060100
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
DS021_02_060100
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD NEW
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSS
T
WPDS
T
WHS
T
WODS
T
ILO
T
ILO
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 11
Product Specification 1-800-255-7778
R
XQ4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ400 0E devices unless othe rw ise noted.
Symb ol Single Port RAM Size
-3 -4
UnitsMin Max Min Max
Write Operation
TWC Address write cycle time 16x2 8.0 - 8 .0 - ns
TWCT 32x1 8.0 - 8.0 - ns
TWP Write Enable pulse width (High) 16x2 4.0 - 4.0 - ns
TWPT 32x1 4.0 - 4.0 - ns
TAS Address setup time before WE 16x2 2. 0 - 2.0 - ns
TAST 32x1 2.0 - 2.0 - ns
TAH Address hold time after end of WE 16x2 2.0 - 2.5 - ns
TAHT 32x1 2.0 - 2.0 - ns
TDS DIN setup time before end of WE 16x2 2. 2 - 4.0 - ns
TDST 32x1 2.2 - 5.0 - ns
TDH DIN hold time after end of WE 16x2 2. 0 - 2.0 - ns
TDHT 32x1 2.0 - 2.0 - ns
Read Operation
TRC Address read cycle time 16x2 3.1 - 4 .5 - ns
TRCT 32x1 5.5 - 6.5 - ns
TILO Data val id after address change (no Write Enable) 16x2 - 1.8 - 2.7 ns
TIHO 32x1 - 3.2 - 4.7 ns
Read Operation, Clocking Data into F lip-Flop
TICK Address setup time before clock K 16x2 3.0 - 4.0 - ns
TIHCK 32x1 4.6 - 6.1 - ns
Read During Writ e
TWO Data valid after WE goes active (DIN stable before WE) 16x2 - 6. 0 - 10.0 ns
TWOT 32x1 - 7.3 - 12.0 ns
TDO Data valid after DIN (DIN c hange s dur ing WE) 16x2 - 6.6 - 9.0 ns
TDOT 32x1 - 7.6 - 11.0 ns
Read During Write, Clocking Data into Flip-Flop
TWCK WE set up time before clo ck K 16x2 6. 0 - 8.0 - ns
TWCKT 32x1 6.8 - 9.6 - ns
TDCK Data setup time before clock K 16x2 5. 2 - 7.0 - ns
TDOCK 32x1 6.2 - 8.0 - ns
Notes:
1. Timing for the 16x1 RAM option i s ide ntical to 16x2 RAM timing.
QPRO XQ4000E/EX QML High-Reliability FPGAs
12 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4000E CLB Level-Sensitive RAM Timing Characteristics
DS021_03_060100
WE
ADDRESS
WRITE
READ WITHOUT WRITE
READ, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE
DATA IN
CLOCK
XQ,YQ OUTPUTS
WRITE ENABLE
DATA IN
(stable during WE)
WRITE ENABLE
DATA IN
CLOCK
DATA IN
(changing during WE)
X,Y OUTPUTS VALID
VALID
OLD NEW
VALID
VALID (NEW)VALID (OLD)
VALID
T
AS
T
ILO
T
AH
T
DS
REQUIRED
T
DH
T
WP
T
WC
T
ICK
T
CH
T
CKO
X,Y OUTPUTS
X,Y OUTPUTS
XQ,YQ OUTPUTS
T
DH
T
WO
T
WO
T
DO
T
WCK
T
DCK
T
CKO
T
WP
T
WP
VALID
(OLD)
VALID
(PREVIOUS)
VALID
(NEW)
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 13
Product Specification 1-800-255-7778
R
XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
struct ure, us e the valu es provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the sim ulation netlist. These path dela ys ,
provided as a guideline, hav e been extracted from the static
timing analyzer report. Values apply to all XQ4000E de vices
unless otherwise noted.
Symbol Description D evice -3 -4 Units
TICKOF
(Max) Glob al clock to outpu t (fast) using OFF XQ40 05E - 14.0 ns
XQ4010E 10.9 16.0 ns
XQ4013E 11.0 16.5 ns
XQ4025E - 17.0 ns
TICKO
(Max) Glob al clock to outpu t (slew-limited) us ing OFF XQ4005E - 18. 0 ns
XQ4010E 14.9 20.0 ns
XQ4013E 15.0 20.5 ns
XQ4025E - 21.0 ns
TPSUF
(Min) Input setup time, u sing IFF (no delay) XQ40 05E - 2.0 ns
XQ4010E 0.2 1.0 ns
XQ4013E 0 0.5 ns
XQ4025E - 0 ns
TPHF
(Min) Input hold time, using IFF (no delay) XQ4005E - 4.6 ns
XQ4010E 5.5 6.0 ns
XQ4013E 6.5 7.0 ns
XQ4025E - 8.0 ns
TPSU
(Min) Input setup time, u sing IFF (with delay) XQ40 05E - 8.5 ns
XQ4010E 7.0 8.5 ns
XQ4013E 7.0 8.5 ns
XQ4025E - 9.5 ns
TPH
(Min) Input hold time, using IFF (with delay) XQ4005E - 0 ns
XQ4010E 0 0 ns
XQ4013E 0 0 ns
XQ4025E - 0 ns
Notes:
1. OFF = Output Flip-Flop
2. IFF = Input Flip-Flop or Latch
OFF
TPG
Global Clock-to-Output Delay
DS021_04_060100
OFF
TPG
Global Clock-to-Output Delay
DS021_04_060100
IFF
TPG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
TPG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
TPG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
TPG
D
Input
Setup
and Hold
Time
DS021_05_060100
QPRO XQ4000E/EX QML High-Reliability FPGAs
14 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
struct ure, us e the valu es provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the sim ulation netlist. These path dela ys ,
provided as a guideline, hav e been extracted from the static
timing analyzer report. Values apply to all XQ4000E de vices
unless otherwise noted.
Symbo l Description Device
-3 -4
UnitsMin Max Min Max
Propagation D e lays (TTL In puts)(1)
TPID Pad to I1, I2 All devices - 2.5 - 3.0 ns
TPLI Pad to I1, I2 via transparent input latch, no delay All devices - 3. 6 - 4.8 ns
TPDLI Pad to I1, I2 via transparent FCL and input latch,
with delay XQ4005E - - - 10.8 ns
XQ4010E - 10.8 - 11.0 ns
XQ4013E - 11.2 - 11.4 ns
XQ4025E - - - 13.8 ns
Propagation D e lays (CMOS Inputs)(1)
TPIDC Pad to I1, I2 All devices - 4.1 - 5.5 ns
TPLIC Pad to I1, I2 via transparent input latch, no delay All devices - 8.8 - 6.8 ns
TPDLIC Pad to I1, I2 via transparent FCL and input latch,
with delay XQ4005E - - - 16.5 ns
XQ4010E - 14.0 - 17.5 ns
XQ4013E - 14.4 - 18.0 ns
XQ4025E - - - 20.8 ns
Propagation D e lays (TTL In puts)
TIKRI Clock (IK) to I1, I2 (flip-fl op) All devices - 2.8 - 5.6 ns
TIKLI Clock (IK) to I1, I2 (latch enable, active Low) A ll devices - 4.0 - 6.2 ns
Hold Times(2)
TIKPI Pad to clock (IK), no delay All devices 0 - 0 - ns
TIKPID Pad to clock (IK), with delay All devices 0 - 0 - ns
TIKEC Clock enab l e (EC) to clock (K), no delay All devices 1.5 - 1.5 - ns
TIKECD Cloc k enable (EC) to clock (K), with delay All devices 0 - 0 - ns
Notes:
1. Input pad set up and h old times ar e speci fie d with respec t t o the internal cloc k (IK). For set up and hold t imes with re spect to the clock
input pin, see the pin-to-pin parameters in the Guaranteed Inpu t and Output Parameters table.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the inter nal pull-up
(default) or pull-down resistor, or co nfigured as a driven output, or can be driv en from an external source.
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 15
Product Specification 1-800-255-7778
R
XQ4000E IOB Input Switching Characteristic Guidelines (continued)
Symbol Description Device
-3 -4
UnitsMinMaxMinMax
Setup Times (TTL Inputs)(1,2)
TPICK Pad to clock (IK), no delay All devices 2.6 - 4.0 - ns
TPICKD Pad to clock (IK), with d elay XQ4 005E - - 10.9 - ns
XQ4010E 9.8 - 11.3 - ns
XQ4013E 10.2 - 11.8 - ns
XQ4025E - - 14.0 - ns
Setup Times (CMOS Inputs)(1,2)
TPICKC Pad to clock (IK), no delay All devices 3.3 - 6.0 - ns
TPICKDC Pad to clock (IK) , with delay X Q4005E - - 12.0 - ns
XQ4010E 10.5 - 13.0 - ns
XQ4013E 10.9 - 13.5 - ns
XQ4025E - - 16.0 - ns
(TTL or CMOS)
TECIK Clock enable (EC) to cloc k (IK), no dela y A ll dev ic es 2.5 - 3.5 - ns
TECIKD Clock enable (EC) to cloc k (IK), with delay XQ4005E - - 10.4 - ns
XQ4010E 9.7 - 10.7 - ns
XQ4013E 10.1 - 11.1 - ns
XQ4025E - - 14.0 - ns
Global Set/Reset(3)
TRRI Dela y from GSR net through Q to I1, I2 All devices - 7.8 - 12.0 ns
TMRW GSR width All devices 11.5 - 13.0 - ns
TMRI GSR inactive to first active clock (IK) edge All devices 11.5 - 13.0 - ns
Notes:
1. Input pad set up and h old times are sp eci fied with r espect to the i nternal cl oc k (I K). F o r set up an d hold tim es wit h respe ct to the cloc k
input pin, see the pin-to-pin parameters in the Guaranteed Inpu t and Output Parameters table.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the inter nal pull-up
(default) or pull-down resistor, or co nfigured as a driven output, or can be driv en from an external source.
3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
QPRO XQ4000E/EX QML High-Reliability FPGAs
16 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ400 0E devices unless othe rw ise noted.
Symbol Description -3 -4 UnitsMin Max Min Max
Propag a tion Delays (TTL Output Levels)
TOKPOF Clock (OK) to pad, fast - 6. 5 - 7.5 ns
TOKPOS Clock (OK) to pad, sl ew-rate limited - 9.5 - 11 .5 ns
TOPF O utp ut (O) to pad, fast - 5.5 - 8.0 ns
TOPS Outp ut (O) to pad, slew-rate limited - 8. 6 - 12.0 ns
TTSHZ 3-state to p ad High-Z, slew-ra te independent - 4.2 - 10 .0 ns
TTSONF 3-st ate to p ad active and valid, fast - 8.1 - 10.0 ns
TTSONS 3-state to pad active and valid, sl ew-ra te limited - 11. 1 - 13.7 ns
Propag a tion Delays (CMO S Output Levels)
TOKPOFC Clock (OK ) to pad, fast - 7.8 - 9.5 ns
TOKPOSC Cl ock (OK) to pad, slew-rate lim ited - 11.6 - 13 .5 ns
TOPFC Outp ut (O) to pad, fast - 9.7 - 10.0 ns
TOPSC Output (O) to pad, slew-rate limited - 13.4 - 14.0 ns
TTSHZC 3-state to pad High-Z, slew-rate independent - 4.3 - 5.2 ns
TTSONFC 3-state to pad active and valid, fast - 7. 6 - 9.1 ns
TTSONSC 3-st ate to pad active and valid, sl ew-ra te limited - 11.4 - 13 .1 ns
Setup and Hold Times
TOOK Output (O) to clock (OK) setup time 4.6 - 5.0 - ns
TOKO Output (O) to clock (OK) hold time 0 - 0 - ns
TECOK Cl ock ena ble (EC) to clock (OK) setup 3.5 - 4.8 - ns
TOKEC Clock ena ble (EC) to clock (OK) h old 1.2 - 1.2 - ns
Clock
TCH Clock High 4.0 - 4.5 - ns
TCL Clock Low 4.0 - 4.5 - ns
Global Set/Reset(3)
TRRO Delay from GSR net to pad - 11.8 - 15.0 ns
TMRW GSR width 11.5 - 13.0 - ns
TMRO GSR inactiv e to first active clock (OK) edge 11.5 - 13.0 - ns
Notes:
1. Output timi ng is meas ured a t pi n threshold, with 50 pF external cap acitiv e loads (inc l. test fixture). Slew-rate li mited output rise/fall
times are appro x imatel y two tim es lon ger than fast o utput rise /f al l tim es. F or t he e ff ect of c apacit iv e l oads on g r ound bounce, se e the
“Additional XC4000 Data” section on the Xilinx w eb site, www.xilinx.com/partinfo/databook.htm.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the inter nal pull-up
(default) or pull-down resistor, or co nfigured as a driven output, or can be driv en from an external source.
3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 17
Product Specification 1-800-255-7778
R
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are not
measured directly. They are deriv ed from benchmark timing
patterns that are taken at device introduction, prior to any
process improvements. For more detailed, more precise,
and more up-to-date information, use the values provided
by the XACT timing calculator and used in the simulator.
These values can be printed in tabular format by running
LCA2XNF-S.
The following guidelines reflect worst-case values over the
recomm ended operating conditions. They are expressed in
units of nanoseconds and apply to all XC4000E devices
unless otherwise noted.
-3 -4
UnitsSymbol Description Min Max Min Max
Setup Times
TTDITCK Input (TDI) to clock (TCK) 30.0 30.0 ns
TTMSTCK Input (TMS) to clock (TCK) 15.0 15.0 ns
Hold Times
TTCKTDI Input (TDI) to clock (TCK) 0 0 ns
TTCKTMS Input (TMS) to clock (TCK) 0 0 ns
Propagation Delay
TTCKPO Clock (TCK) to pad (TDO) 30.0 30.0 ns
Clock
TTCKH Clock (TCK) High 5.0 5.0 ns
TTCKL Clock (TCK) Low 5.0 5.0 ns
FMAX Frequency 15.0 15.0 MHz
Notes:
1. Input setup and hold times and clock-to-pad times are specified with respect to exter nal signal pins.
2. Output timi ng is meas ured a t pi n threshold, with 50pF ext ernal capacitive loads (incl. test fi xture). Slew-rate limited output r is e/ fall
times are appro x imatel y two tim es lon ger than fast o utput rise/f al l ti mes . F or t he e ff ect of c apacit iv e l oads on gr ound bounce, s ee the
“Additional XC4000 Data” section of the Programm able Logic Data Book.
3. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the inter nal pull-up
(default) or pull-down resistor, or co nfigured as a driven output, or can be driv en from an external source.
QPRO XQ4000E/EX QML High-Reliability FPGAs
18 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ40 28 EX Swit chin g Chara cter ist ics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: I nitial estimates bas ed on simulation and/or extrapolation from other spe ed grades, devices, or device families.
Values are subject to change. Use as estimates, no t for production.
Preliminary: Based on preliminary characterization. Further c hanges are not expected.
Unmarked: Specif ications not identified as either Advance or Prel iminary are to be considered Final.
Except for pin-to-pin input and output parameters, the A.C. parameter delay specifications included in this document are
deriv ed from measuring internal test patterns. All specifications are representativ e of worst-case supply voltage and junction
temperature conditions.
All specific ations subject to change without notice.
XQ4028EX Absolute Maximum Ratings(1)
Symbol Description Units
VCC Supply voltage relative to GND –0 .5 to +7 .0 V
VIN Input voltage relative to GND(2) –0.5 to VCC + 0.5 V
VTS Voltage app lied to High-Z output(2) –0.5 to VCC + 0.5 V
VCCt Longest supply voltage rise time from 1V to 4V 50 ms
TSTG Storage temperature (ambie nt) –65 to +150 °C
TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C
TJJunct ion temperature Ceramic package +150 °C
Plastic package +125 °C
Notes:
1. Stresses beyond those lis ted under Absolute Maxi m um Rati ngs may cause permanent damage to the device. These ar e stress
ratings onl y, and functional operation of the devi ce at these or any other conditions bey ond those list ed under Operating Conditions
is not imp lied. Exposure to Absolute Maxim um Ratings conditions for extended periods of time may affec t device reliab il ity.
2. Maximum DC excursion abov e VCC or below Ground must be limit ed to ei ther 0.5V or 10 mA, whichever is easi er to achieve .
Maxim um total combi ned current on al l dedi cated input s and Tri-state output s m ust not exceed 200 mA. During t ransitions, the
device pins may undershoot to –2.0V or ov ersh oot toVCC +2.0V, pr ovided this over or undershoot lasts l ess than 10 ns and with t he
forcing current being lim ited to 200 mA.
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 19
Product Specification 1-800-255-7778
R
XQ4028EX Recommended Operating Conditions(1)
XQ4028EX DC Characteristics Over R ecommended Operating Conditions
Symbol Descriptiont Min Max Units
VCC Suppl y voltage relative to GND, TJ = –55°C to +125°CPlastic 4.5 5.5 V
Suppl y voltage relative to GND, TC = –55°C to +125°C Ceramic 4.5 5.5 V
VIH High-level input voltage(2) TTL inputs 2.0 VCC V
CMOS inputs 70% 100% V CC
VIL Low-level input voltage TTL inputs 0 0.8 V
CMOS inputs 0 20% VCC
TIN Input signal transition time - 250 ns
Notes:
1. At junction temperatures above those listed as Ope rating Conditions, all dela y parameters increa se by 0.35% per °C.
2. In put an d output measurement thr eshold are 1.5V for TTL and 2.5V f or CMOS.
Symbol Description Min Max Units
VOH High-le vel output voltage at IOH = –4 mA, VCC min TTL outputs 2.4 - V
High-level output voltage at IOH = –1 mA CMOS outputs VCC – 0.5 - V
VOL Low-level output voltage at IOL = 12 mA, VCC min(1) TTL outputs - 0.4 V
CMOS outputs - 0.4 V
VDR Data retention supply v oltage (belo w which configuration data ma y be lost) 3.0 - V
ICCO Quiescent FP GA su pply curren t(2) -25mA
ILInput or outpu t leakage current –10 10 µA
CIN Input capacitance (sampl e tested) Plastic packages - 10 V
Ceramic packages - 16 V
IRPU Pad pull-up (when selected) at VIN = 0V (sample tested) 0.02 0.25 m A
IRPD Pad pull-down (when selected) at VIN = 5.5V (sample tested) 0.02 0.25 mA
IRLL Horizontal longline pull-up (when selected) at log ic Low(3) 0.3 2.0 mA
Notes:
1. With up to 64 pins si m ultaneously sinking 12 mA.
2. With no output cur rent loads , no activ e input or Longl ine pull-up resisto rs, all package pins at VCC or GND.
QPRO XQ4000E/EX QML High-Reliability FPGAs
20 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ40 28 EX Swit chin g Chara ct erist ic Gu id elin es
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values where one global clock input
drives one vertical clock line in each accessible c olumn, and
where all access ible I OB and CLB fl ip-fl ops are clocked by
the global clock net.
When few er vertical clock lines are connected, the clock dis-
tribution is faster ; when mul tiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Dev elopment System) and bac k-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing paramete rs assum e worst-ca se operating conditions
(supply voltage and jun ction temperature)
Global Buffer Switching Characteristics.
XQ4028EX Horizontal Longline Switching Characteristic Guidelines
Symbol Description
-4
UnitsMax
TGLS Fro m pad thro ugh Glob al Low Skew buffer, to any clock K 9. 2 ns
TGE From pad through Glob al Early buffer, to any clock K in sam e quadrant 5.7 ns
Symbol Description
-4
UnitsMax
TBUF Driving a Horizontal Longline
TIO1 I going High or Low to horizontal longline going High or Low, wh ile T is L ow. Buffer i s
constantl y acti ve. 13.7 ns
TON T going Lo w to horizontal longline going from resistive pull-up or floating High to activ e Low.
TBUF configu red as open-drain or active bu ffe r with I = Low. 14.7 ns
TBUF Driving Half a Horizontal Longline
THIO1 I going High or Low to half of a horizontal longline going High or Low, while T is Low. Buffer
is constantl y active. 6.3 ns
THON T going Low to half of a horizonta l longline going from resistive pull-up or floating High to
active Low. TBUF configured as open-drain or a ctive buffer with I = L ow. 7.2 ns
Notes:
1. These v alues incl ude a minimum load of one output, spa ced as far as possible from the acti vated pull-up(s). Use the static timing
analyzer to det ermine t he delay for each de sti nation.
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 21
Product Specification 1-800-255-7778
R
XQ4028EX CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) an d back-ann otated to th e s imulation n etl ist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000EX de vices unless otherwise noted.
CLB Switching Characteristics
Symbol
Description
-4
UnitsMin Max
Combinatorial Delays
TILO F/G inp uts to X/Y output s - 2.2 ns
TIHO F/G in puts v ia H ’ to X/Y outp uts - 3. 8 ns
TITO F/G inp uts via transparent latch to Q outputs - 3. 2 ns
THH0O C inputs via SR/H0 via H to X/Y outputs - 3.6 ns
THH1O C inputs via H1 via H to X/Y outputs - 3.0 ns
THH2O C inputs via DIN/H2 via H to X/Y outputs - 3.6 ns
TCBYP C inputs via EC, DIN/H2 to YQ, XQ output (bypass ) - 2.0 ns
CLB Fast C a rr y Logic
TOPCY Op erand input s (F1, F2, G1, G4) to COUT -2.5ns
TASCY Add/Subtract input (F3) to COUT -4.1ns
TINCY I n it ializ a t ion inp uts (F1 , F3 ) to C OUT -1.9ns
TSUM CIN through function generators to X/Y outputs - 3.0 ns
TBYP CIN to C OUT, bypass function generators - 0.60 ns
TNET Carry net selay, COUT to C IN -0.18ns
Sequential Delays
TCKO Clock K to flip-flop outputs Q - 2.2 ns
TCKLO Clock K to latch outputs Q - 2.2 ns
Setup Time before Clock K
TICK F/G inputs 1.3 - ns
TIHCK F/G in puts v i a H 3 .0 - ns
THH0CK C inputs via H0 through H 2.8 - ns
THH1CK C inputs via H1 through H 2.2 - ns
THH2CK C inputs via H2 through H 2.8 - ns
TDICK C inputs via DIN 1.2 - ns
TECCK C inputs via EC 1.2 - ns
TRCK C inputs via S/R, going Low ( inactive) 0.8 - ns
TCCK CIN input via F/G 2.2 - ns
TCHCK CIN input via F/G and H 3.9 - ns
Hold Time after Clock K
TCKI F/ G in puts 0 - ns
QPRO XQ4000E/EX QML High-Reliability FPGAs
22 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
TCKIH F/ G inputs via H 0 - ns
TCKHH0 C inputs via SR/H0 through H 0 - ns
TCKHH1 C inputs via H1 through H 0 - ns
TCKHH2 C inputs via DIN/H2 through H 0 - ns
TCKDI C inputs via DIN/H2 0 - ns
TCKEC C inputs via EC 0 - ns
TCKR C inputs via SR, going Low (inactive) 0 - ns
Clock
TCH Clock High time 3.5 - ns
TCL Clock Low time 3 .5 - ns
Set/Reset Direct
TRPW Wi dth (High) 3.5 - ns
TRIO Delay from C inputs via S/R, going High to Q - 4.5 ns
Global Set/Reset
TMRW Minimum GSR pulse width - 13.0 ns
TMRQ Delay from GSR input to any Q - 22.8
FTOG To ggle frequency (MHz) (for export control) - 143 MHz
CLB Switching Characteristics (Continued)
Symbol
Description
-4
UnitsMin Max
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 23
Product Specification 1-800-255-7778
R
XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000EX de vices unless otherwise noted.
Symbol Single Port RAM Size -4 UnitsMin Max
Write Operation
TWCS Address write cycle time (clock K period ) 16x2 11.0 - ns
TWCTS 32x1 11.0 - ns
TWPS Clock K pulse width (active edge) 16x2 5.5 - ns
TWPTS 32x1 5.5 - ns
TASS Address setup time before clock K 16x2 2.7 - ns
TASTS 32x1 2.6 - ns
TAHS A ddress hold time after clock K 16x2 0 - ns
TAHTS 32x1 0 - ns
TDSS DIN setup time before clock K 16x2 2.4 - ns
TDSTS 32x1 2.9 - ns
TDHS DIN hold time after clock K 16x2 0 - ns
TDHTS 32x1 0 - ns
TWSS WE setup time before clock K 16x2 2.3 - ns
TWSTS 32x1 2.1 - ns
TWHS WE hold time after clock K 16x2 0 - ns
TWHTS 32x1 0 - ns
TWOS Data valid after clock K 16x2 - 8.2 ns
TWOTS 32x1 - 10.1 ns
Notes:
1. Applicable Read timing specifica ti ons are identical to Level -Sensitive Read timi ng.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol Dua l Port RAM Size(1) -4 UnitsMin Max
Write Operation
TWCDS Address write cycle time (clock K period) 16x1 11.0 ns
TWPDS Clock K pulse width (a ctive edge) 16x1 5.5 - ns
TASDS Address setup ti me be fore clo ck K 1 6x1 3.1 - ns
TAHDS Address hold time after clock K 16x1 0 - ns
TDSDS DIN setup time before clock K 16 x1 2.9 - ns
TDHDS DIN hold time after clock K 16x1 0 - ns
TWSDS W E setup time befo re clock K 16x1 2.1 - ns
TWHDS WE hold time after clock K 16x1 0 - ns
TWODS Data valid after clock K 16x1 - 9.4 ns
Notes:
1. Timing for the 16x1 RAM option i s ide ntical to 16x2 RAM timing.
2. Applicable Read timing specifica ti ons are identical to Level -Sensitive Read timi ng.
QPRO XQ4000E/EX QML High-Reliability FPGAs
24 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Timing Waveform
XQ4028EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveform
DS021_01_060100
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
DS021_02_060100
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD NEW
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSS
T
WPDS
T
WHS
T
WODS
T
ILO
T
ILO
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 25
Product Specification 1-800-255-7778
R
XQ4028EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000EX de vices unless otherwise noted.
Symbol Single Port RAM Size
-4
UnitsMin Max
Write Operation
TWC Address write c ycle time 16x2 10. 6 - ns
TWCT 32x1 10.6 - ns
TWP Wr ite Enable pulse width (High) 16x2 5.3 - ns
TWPT 32x1 5.3 - ns
TAS A ddress setup time before WE 16x2 2.8 - ns
TAST 32x1 2.8 - ns
TAH A ddress hold time after end of WE 16x2 1.7 - ns
TAHT 32x1 1.7 - ns
TDS DIN setup time before end of WE 16x2 1.1 - ns
TDST 32x1 1.1 - ns
TDH DIN hold time after end of W E 16x2 6.6 - ns
TDHT 32x1 6.6 - ns
Read Operation
TRC Address read cycle time 16x2 4.5 - ns
TRCT 32x1 6.5 - ns
TILO Dat a valid after address change (no Wri te Enable) 16x2 - 2.2 ns
TIHO 32x1 - 3.8 ns
Read Operation, Clocking Data into F lip-Flop
TICK Address setup time before clock K 16x2 1.5 - ns
TIHCK 32x1 3.2 - ns
Read During Writ e
TWO Data valid after WE goes active (DIN stable before WE) 16x2 - 6.5 ns
TWOT 32x1 - 7.4 ns
TDO Data val i d after DIN (DIN changes during WE) 16x2 - 7. 7 ns
TDOT 32x1 - 8.2 ns
Read During Write, Clocking Data into Flip-Flop
TWCK W E setup time before clock K 16x2 7.1 - ns
TWCKT 32x1 9.2 - ns
TDCK Data setu p time befor e clock K 16x2 5.9 - ns
TDOCK 32x1 8.4 - ns
Notes:
1. Timing for the 16x1 RAM option i s ide ntical to 16x2 RAM timing.
QPRO XQ4000E/EX QML High-Reliability FPGAs
26 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4028EX CLB Level-Sensitive RAM Timing Waveforms
Figure 1:
DS021_03_060100
WE
ADDRESS
WRITE
READ WITHOUT WRITE
READ, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE
DATA IN
CLOCK
XQ,YQ OUTPUTS
WRITE ENABLE
DATA IN
(stable during WE)
WRITE ENABLE
DATA IN
CLOCK
DATA IN
(changing during WE)
X,Y OUTPUTS VALID
VALID
OLD NEW
VALID
VALID (NEW)VALID (OLD)
VALID
T
AS
T
ILO
T
AH
T
DS
REQUIRED
T
DH
T
WP
T
WC
T
ICK
T
CH
T
CKO
X,Y OUTPUTS
X,Y OUTPUTS
XQ,YQ OUTPUTS
T
DH
T
WO
T
WO
T
DO
T
WCK
T
DCK
T
CKO
T
WP
T
WP
VALID
(OLD)
VALID
(PREVIOUS)
VALID
(NEW)
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 27
Product Specification 1-800-255-7778
R
XQ4028EX Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
struct ure, us e the valu es provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the sim ulation netlist. These path dela ys ,
provided as a guideline, hav e been extracted from the static
timing analyzer report. Values apply to all XQ4000EX
devices unle ss otherwise noted.
XQ4028EX Output Flip-Flop, Clock to Out(1,2)
XQ4028EX Output Mux, Clock to Out(1,2)
XQ4028EX Output Level and Slew Rate Adjustments
The following table must be used to adjust output parameters and output switching characteristics.
Symbol
Description
-4
UnitsMax
TICKOF Global low skew clock to output using OFF(3) 16.6 ns
TICKEOF Global early clock to output using OFF(3) 13.1 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are cl ock ed by the global clock net.
2. Output timing is measured at TTL threshold with 50 pF external capacitive load.
3. OFF = Output Flip-Flop
Symbol
Description
-4
UnitsMax
TPFPF Global low skew cloc k to TTL output (f ast) using OMUX3) 15.9 ns
TPEFPF Global early clock to TTL output (fast) using OMUXF(3) 12.4 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are cl ock ed by the global clock net.
2. Output timi ng is meas ured at ~50% VCC threshol d with 50 pF external cap acitiv e load. For different loads, see gr aph below.
3. OMUX = Output MUX
Symbol Description
-4
UnitsMax
TTTLOF For TTL output FAST add 0 ns
TTTLO For TTL output SLOW add 2.9 ns
TCMOSOF For CMOS FAST output add 1.0 ns
TCMOSO F or CMOS SLO W output add 3.6 ns
QPRO XQ4000E/EX QML High-Reliability FPGAs
28 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4028EX Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and inter nal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
struct ure, us e the valu es provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the sim ulation netlist. These path dela ys ,
provided as a guideline, hav e been extracted from the static
timing analyzer report. Values apply to all XQ4000EX
devices unle ss otherwise noted
XQ4028EX Global Low Skew Clock, Setup and Hold
XQ4028EX Global Early Clock, Setup and Hold for IFF
XQ4028EX Global Early Clock, Setup and Hold for FCL
XQ4028EX Input Threshold Adjustments
The following table must be used to adjust input parameters and input switching characterist ics.
Symbol Description
-4
UnitsMin
TPSD Input setup time, using Global Low Skew clock and IFF (full delay) 8.0 n s
TPHD Input hold time, using Global Low S kew clock and IFF (full del ay) 0 ns
Notes:
1. IF F = Fli p-Fl op or Latch
Symbol Description
-4
UnitsMin(2)
TPSEP Input setup time, using Global Early clock a nd IFF (full delay) 6.5 n s
TPHEP Input hold time, using Global Early clock an d IFF (full delay) 0 ns
Notes:
1. IF F = Fli p-Fl op or Latch
2. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6.
Symbol Description
-4
UnitsMin(2)
TPFSEP Input setup time, using Global Early clock a nd FCL (part ial delay) 3.4 ns
TPFHEP Input hold time, using Global Early clock and FCL (par t ial delay) 0 ns
Notes:
1. FCL = Fast Capture Latch
2. For CMOS input levels, see the XQ4028EX Input Threshold Adjustments.
3. Setup time is mea sured with th e f astes t rout e and the light est load. Use the st atic timing ana lyze r to dete rmine the setu p time under
given design conditions .
4. Hold time i s measured us ing the farthest di st ance and a ref er ence load of one cloc k pi n per two IOBs . Use the stat ic ti ming analyzer
to determin e the setup and hold times under given design co nditions .
5. Setup parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1, 2, 5 and 6.
Symbol Description
-4
UnitsMax
TTTLI For TTL input add 0 ns
TCMOSI For CMO S input add 0.3 ns
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 29
Product Specification 1-800-255-7778
R
XQ4028EX IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4 000E X devices unless oth erwise noted.
Symb ol Description
-4
UnitsMin
Clocks
TOKIK Delay from FCL enable (OK) active to IFF clock (IK ) active ed ge 3.2 ns
Propagation Delays
TPID P a d to I1, I2 2.2 ns
TPLI Pad to I1, I2 via transparent input latch, no delay 3.8 ns
TPPLI Pad to I1, I2 via transparent input latch, partial delay 13.3 ns
TPDLI Pad to I1, I2 via transparent input latch, full delay 18.2 ns
TPFLI P ad to I1, I2 via transparent FCL and input latch, no delay 5.3 ns
TPPFLI P ad to I1, I2 via transparent FCL and input latch, partial delay 13.6 ns
Propagation D e lays (TTL In puts)
TIKRI Clock (IK) to I1, I2 (flip-flop) 3.0 ns
TIKLI Clock (IK) to I1, I2 (latch en able, active L ow) 3.2 ns
TOKLI FCL enable (OK) active edge to I1, I2 (via transparent standard input latch) 6.2 ns
Global Set/Reset
TMRW Minimum GSR pulse width 13.0 ns
TRRI Delay from GSR input to any Q 22.8 ns
Notes:
1. FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch
2. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28.
3. For setu p and hold times with res pect to the cloc k inp ut pin, see the Global Low Ske w Cloc k and Global Early Cloc k Setup and Hold
t able s on page 28.
QPRO XQ4000E/EX QML High-Reliability FPGAs
30 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
XQ4028EX IOB Input Switching Characteristic Guidelines (Continued)
Symbol
Description
-4
UnitsMin
Setup Times
TPICK Pad to Clock (IK), no dela y 2.5 ns
TPICKP Pad to Clock (IK), partial dela y 10.8 ns
TPICKD Pad to Clock (IK), full dela y 15.7 ns
TPICKF Pad to Clock (IK), via transparent F ast Capture Latch, no delay 3.9 ns
TPICKFP P ad to Clock (IK), via transparent Fast Capture Latch, partial dela y 12.3 ns
TPOCK P ad to Fast Capture Latch Enable (OK), no dela y 0.8 ns
TPOCKP P ad to Fast Capture Latch Enable (OK), partial delay 9.1 ns
Setup Times (TTL or CMOS Inputs)
TECIK Clock E nable (EC) to Clock (IK) 0.3 n s
Hold Times
TIKPI Pad to Clock (IK), no delay 0 ns
TIKPIP Pad to Clock (IK), partial delay 0 ns
TIKPID Pad to Clock (IK), full delay 0 ns
TIKPIF Pad to Clock (IK) via transparent Fast Capture Latch, no d elay 0 ns
TIKFPIP Pad to Clock (IK) via transparent Fast Capture Latch, part ial delay 0 ns
TIKFPID Pad to Clock (IK) via transparent Fast Capture Latch, full d elay 0 ns
TIKEC Clock Enable (EC) to Clock (IK), no delay 0 ns
TIKECP Clock E nable (EC) to Clock (IK), partial d elay 0 ns
TIKECD Clock Enable (EC) to Clock (IK), ful l delay 0 n s
TOKPI Pad to Fast Capture Latch Enable (OK), n o delay 0 ns
TOKPIP Pad to Fast Capture L atch Enable (OK), p artial delay 0 ns
Notes:
1. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28.
2. For set up and hol d times with respe ct to the clo ck inp ut pin, see the Globa l Low Sk e w Clock an d Globa l Early Cloc k Setup and Hold
t able s on page 28.
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 31
Product Specification 1-800-255-7778
R
FXQ4028EX IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
der ived from m easuring i nter n al tes t patter ns. Listed bel ow
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment S y stem) and back-ann otated to th e simu lation n etlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ4000EX de vices unless otherwise noted.
Symbol Description
-4
UnitsMin Max
Propag a tion Delays (TTL Output Levels)
TOKPOF Clock (OK) to pad, f ast - 7.4 ns
TOPF Output (O) to pad, fast - 6.2 ns
TTSHZ 3-state to pad High-Z, slew-rate independent - 4 .9 ns
TTSONF 3-state to pad ac tive and valid, fast - 6.2 ns
TOKFPF Ou tp u t MUX se lect (OK) to pad - 6. 7 ns
TCEFPF Fast path output MUX input (EC) to pad - 6.2
TOFPF Slowes t path output MUX input (EC) to pad - 7.3
Setup and Hold Times
TOOK Output (O) to clock (OK) setup time 0.6 - ns
TOKO Output (O) to clock (OK) hold time 0 - ns
TECOK Clock enable (EC) to clock (OK) setup 0 - ns
TOKEC Cloc k enable (EC) to clock (OK) hold 0 - ns
Clocks
TCH Cloc k High 3.5 - ns
TCL Cloc k Lo w 3.5 - ns
Global Set/Reset
TMRW Minimum GSR pulse width 13.0 - ns
TRRI Dela y from GSR input to any pad 30.2 - ns
Notes:
1. Output timi ng is meas ured at TTL threshold, with 35 pF external capacitive loads.
2. For CMOS output levels, see the "XQ4028EX Output Level and Slew Rate Adjustments" on page 27.
QPRO XQ4000E/EX QML High-Reliability FPGAs
32 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
CB191/196 Package for XQ4010E
Pin Description PG 191 CB196 Bound
Scan
GND D4 P1 -
PGCK1_(A16*I/0) C3 P2 122
I/O_(A17) C4 P3 125
I/0 B3 P4 128
--P5
(1) -
I/O C5 P6 131
I/O_(TDI) A2 P7 134
I/O_(TCK) B4 P8 137
I/O C6 P9 140
I/O A3 P10 143
I/O B5 P11 146
I/O B6 P12 149
GND C7 P13 -
I/O A4 P14 152
I/O A5 P15 155
I/O_(TMS) B7 P16 158
I/O A6 P17 161
I/O C8 P18 164
I/O A7 P19 167
I/O B8 P20 170
I/O A8 P21 173
I/O B9 P22 176
I/O C9 P23 179
GND D9 P24 -
VCC D10 P25 -
I/O C10 P26 182
I/O B10 P27 185
I/O A9 P28 -
I/O A10 P29 191
I/O A11 P30 194
I/O C11 P31 197
I/O B11 P32 200
I/O A12 P33 203
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
I/O B12 P34 206
I/O A13 P35 209
GND C12 P36 -
I/O B13 P37 212
I/O A14 P38 215
I/O A15 P39 218
I/O C13 P40 221
I/O B14 P41 224
I/O A16 P42 227
I/O B15 P43 230
I/O C14 P44 233
I/O A17 P45 236
SCGK2_(I/O) B16 P46 239
M1 C15 P47 242
GND D15 P48 -
M0 A18 P49 245(2)
VCC D16 P50 -
M2 C16 P51 246(2)
PGCK2_(I/O) B17 P52 247
I/O_(HDC) E16 P53 250
--P54
(1) -
I/O C17 P55 253
I/0 D17 P56 256
I/O B18 P57 259
I/O_(LDC) E17 P58 262
I/O F16 P59 265
I/O C18 P60 268
I/O D18 P61 271
I/O F17 P62 274
GND G16 P63 -
I/O E18 P64 277
I/O F18 P65 280
I/O G17 P66 283
I/O G18 P67 286
Pin Description PG191 CB196 Bound
Scan
Notes:
1. Indicates unconnected package pins .
2. Contributes onl y one bit (.I) to the b oundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 33
Product Specification 1-800-255-7778
R
I/O H16 P68 286
I/O H17 P69 291
I/O H18 P70 295
I/O J18 P71 298
I/O J17 P72 301
I/O_(/ERR_/INIT) J16 P73 304
VCC J15 P74 -
GND K15 P75 -
I/O K16 P76 307
I/O K17 P77 310
I/O K18 P78 313
I/O L18 P79 316
I/O L17 P80 319
I/O L16 P81 322
I/O M18 P82 325
I/O M17 P83 328
I/O N18 P84 331
I/O P18 P85 334
GND M16 P86 -
I/O N17 P87 337
I/O R18 P88 340
I/O T18 P89 343
I/O P17 P90 349
I/O N16 P91 349
I/O T17 P92 352
I/O R17 P93 355
I/O P16 P94 358
I/O U18 P95 361
SGCK3_(I/O) T16 P96 364
GND R16 P97 -
DONE U17 P98 -
VCC R15 P99 -
/PROG V18 P100 -
I/O_(D7) T15 P101 367
Pin Description PG 191 CB196 Bound
Scan
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
PGCK3_(I/O) U16 P102 370
--P103
(1) -
I/O T14 P104 376
I/O U15 P105 376
I/O_(D6) V17 P106 379
I/O V16 P107 382
I/O T13 P108 385
I/O U14 P109 388
I/O V15 P110 391
I/O V14 P111 394
GND T12 P112 -
I/O U13 P113 397
I/O V13 P114 400
I/O_(D5) U12 P115 403
I/O_(/CSO) V12 P116 406
I/O T11 P117 409
I/O U11 P118 412
I/O V11 P119 415
I/O V1 P120 418
I/O_(D4) U10 P121 421
I/O T10 P122 424
VCC R10 P123 -
GND R9 P124 -
I/O_(D3) T9 P125 427
I/O_(/RS) U9 P126 430
I/O V9 P127 433
I/O V8 P128 436
I/O U8 P129 439
I/O T8 P130 442
I/O_(D2) V7 P131 445
I/O U7 P132 448
I/O V6 P133 451
I/O U6 P134 454
GND T7 P135 -
Pin Description PG191 CB196 Bound
Scan
Notes:
1. Indicates unconnected package pins .
2. Contributes onl y one bit (.I) to the b oundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
QPRO XQ4000E/EX QML High-Reliability FPGAs
34 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R
Additional XQ4010E Package Pins
I/O V5 P136 457
I/O V4 P137 460
I/O U5 P138 463
I/O T6 T139 446
I/O_(D1) V3 P140 469
I/O_(RCLK-/BUSY/RDY) V2 P141 472
I/O U4 P142 475
I/O T5 P143 478
I/O_(D0*_DIN) U3 P144 481
SGCK4_(DOUT*_I/O) T4 P145 484
CCLK V1 P146 -
VCC R4 P147 -
TDO U2 P148 -
GND R3 P149 -
I/O_(A0*_WS) T3 P150 2
PGCK4_(I/O*_A1) U1 P151 5
- - P152(1) -
I/O P3 P153 8
I/O R2 P154 11
I/O_(CS1*_A2) T2 P155 14
I/O_(A3) N3 P156 17
I/O P2 P157 20
I/O T1 P158 23
I/O R1 P159 26
I/O N2 P160 29
GND M3 P161 -
I/O P1 P162 32
I/O N1 P163 35
I/O_(A4) M2 P164 38
I/O_(A5) M1 P165 41
I/O L3 P166 44
I/O L2 P167 47
I/O L1 P168 50
Pin Description PG 191 CB196 Bound
Scan
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
I/O K1 P169 53
I/O_(A6) K2 P170 56
I/O_(A7) K3 P171 59
GND K4 P172 -
VCC J4 P173 -
I/O_(A8) J3 P174 62
I/O_(A9) J2 P175 65
I/O J1 P176 68
I/O H1 P177 71
I/O H2 P178 74
I/O H3 P179 77
I/O_(A10) G1 P180 80
I/O_(A11) G2 P181 83
I/O F1 P182 86
I/O E1 P183 89
GND G3 P184 -
I/O F2 P185 92
I/O D1 P186 96
I/O C1 P187 98
I/O E2 P188 101
I/O_(A12) F3 P189 104
I/O_(A13 D2 P190 107
--P192
(1) -
I/O E3 P193 113
I/O_(A14) C2 P194 116
SGCK1(A15*I/O) B2 P195 119
VCC D3 P196 -
CB196
No Connect Pins
P5 P54 P103 P152
P192 - - -
Pin Description PG191 CB196 Bound
Scan
Notes:
1. Indicates unconnected package pins .
2. Contributes onl y one bit (.I) to the b oundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000 www.xilinx.com 35
Product Specification 1-800-255-7778
R
Revisio n Hist ory
The following table shows the revision histor y for this document
Date Version Description
05/19/98 2.1 Updates.
06/25/00 2.2 Updated timing specifications to match with commercial data sheet . Updated for m at .
XQ4005E
XQ4010E
XQ4013E
XQ4025E
XQ4028EX
XQ 4010E -4 PG 191 M
Device Type
Speed Grade
Package Type
Number of Pins
Tem peratu re Range
Ordering Information
M = C eramic (TC = –55°C to +125°C)
N = Plastic (TJ = –55°C to +125 °C)
CB = Top Brazed Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
HQ = Plastic Quad Flat Pack
BG = Plastic Ball Gr id Array
-3
-4
MIL-PRF-38535
(QML) Processing
QPRO XQ4000E/EX QML High-Reliability FPGAs
36 www.xilinx.com DS021 (v2.2 ) June 25, 2000
1-800-255-7778 Product Specification
R