CCM-PFC
ICE3PCS02G
Standalone Power Factor
Correction (PFC) Controller in
Continuous Conduction Mode
(CCM)
Version 2.0, 5 May 2010
Power Management & Supply
Edition 2010-05-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 05/05/10.
All Rights Reserved.
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CCM-PFC
Revision History: Datasheet
CCM-PFC
ICE3PCS02G
Version 2.0 3 5 May 2010
Type Package
ICE3PCS02G PG-DSO-8
Standalone Power Factor Correction
(PFC) Controller in Continuous
Conduction Mode (CCM)
ICE3PCS02G
PG-DSO-8
Product Highlights
• High efficiency over the whole load range
• Lowest count of external components
• Accurate and adjustable switching frequency
• Integrated digital voltage loop compensation
• Fast output dynamic response during load jump
• External synchronization
• Low peak current limitation
Features
• Continuous current operation mode PFC
• Wide input rang e of Vc c up to 25 V
• Enhanced dy namic res ponse without input c urrent
distortion
• External current loop compensation for greater
user flexibility
• Open loop protection
• Second over bulk voltage protection
• Maximum duty cycle of 95% (typical)
Description
The ICE3PCS02G is a 8-pins wide input range controller
IC for active power factor correction converters. It is de-
signed for converters in boost topology, and requires few
external components. Its power supply is recommended to
be provided by an external auxiliary supply which will
switch on and off the IC.
90 ~ 270 Vac
Line
Filter C
E
L
Boost
R
SHUNT
R
GATE
D
BYP
D
B
R
CS
C
B
R
BVS 2
R
BVS 3
R
BVS 1
R
GS
ISENSE GATE
R
FREQ
C
ICOMP
C
VCC
V
CC
GND VCCICOMPFREQ
VSENSE
R
BVS5
R
BVS6
R
BVS4
OVP
CCM-PFC
ICE3PCS02G
Version 2.0 4 5 May 2010
1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4 Frequency Setting and External Synchronization . . . . . . . . . . . . . . . . . . . . .8
3.4.1 Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4.2 External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5 Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5.1 Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5.2 Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.6 Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6.1 Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6.2 Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6.3 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.7 PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.8 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.8.1 Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.8.2 Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.8.3 First Over-Voltage Protection (OVP1) . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.8.4 Second Over Voltage Protection (OVP2) . . . . . . . . . . . . . . . . . . . . . . . .12
3.9 Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.10 Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3.2 Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3.4 External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3.5 System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.6 Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.7 Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.8 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3.9 Gate Drive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Version 2.0 5 5 May 2010
CCM-PFC
Preliminary Datasheet ICE3PCS02G
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration
Figure 1 Pin Configuration (top view)
1.2 Pin Functionality
ISENSE (Current Sense Inpu t)
The ISENSE Pin senses the voltage drop at the
external sense resistor (RSHUNT). This is the input signal
for the average curren t regulation in the current loop. It
is also fed to the peak current limitation block.
During power up time, high inrush currents cause high
negative voltage drop at RSHUNT, driving currents out of
pin 1 which could be beyond the absolute maximum
ratings. Therefore a series resistor (RCS) of around 50
is recommended in order to limit this current into the IC.
GND (IC Ground)
The groun d po te n tia l of the IC.
ICOMP (Current Loop Compensation)
Low pass filter and compensation of the c urrent control
loop. The capacitor which is connected at this pin
integrates the output current of OTA6 and averages the
current sense signal.
FREQ (Frequency Setting)
This pin allows the setting of the operating switching
frequency by connecting a resistor to ground. The
frequency range is from 21kHz to 250kHz.
OVP
A resistive voltage divider from bulk voltage to GND
can set the over voltage protection threshold. This
additional OVP is able to ensure system safety
operation.
VSENSE
VSENSE is connected via a resistive divider to the bulk
voltage. The voltage of VSENSE relative to GND
represents the output voltage. The bulk voltage is
monitored for voltage regulation, over voltage
protection and open loop protection.
VCC
VCC provides the power supply of the ground related
to IC section.
GATE
GATE is the output for driving the PFC MOSFET.Its
gate drive voltage is clamped at 15V (typically).
Pin Symbol Function
1 ISENSE Current Sense Input
2 GND IC Ground
3 ICOMP Current Loop Compensation
4 FREQ Switching Frequency Setting
5 OVP Over Voltage Protection
6 VSENSE Bulk Voltage Sense
7 VCC IC Supply Voltage
8 GATE Gate Drive
VSENSE
ISENSE
OVPFREQ
ICOMP P-DSO-8
GATE
GND VCC
Package PG-DSO-8
CCM-PFC
ICE3PCS02G
Block Diagram
Version 2.0 6 5 May 2010
2 Block Diagram
A functional block diagram is given in Figure 2 . Note that the figure only shows the brief functional b lock and does
not represent the implementation of the IC.
Figure 2 Block Diagram
VCC
Unit
Oscillator/
Synchronization
Current Loop
Compensation/
PCL
S ec ond OVPProtection Unit
V oltage Loop
Compensation
Ramp
Generator
PWM Logic
Driver
Nonlinear Gai n
ICE3PCS02G
C
E
L
Boost
D
BYP
D
B
C
B
R
BVS2
R
BVS3
R
BVS1
R
BVS5
R
BVS6
R
BVS4
Q
B
R
CS
R
Shunt
R
GATE
C
ICOMP
90 ~ 270 Vac Line
Filter
R
FREQ
FREQ
GATE
OVP
VSENSE
ISENSE ICOMP GND
Auxiliary Supply
VCC
C
ISENSE
CCM-PFC
ICE3PCS02G
Block Diagram
Version 2.0 7 5 May 2010
Table 1 Bill Of Material
Component Parameters
Rectifier Bridge GBU8J
CE100nF/X2/275V
LBoost 750uH
QBIPP60R199CP
DBYP MUR360
DBIDT04S60C
CB220µF/450V
Rshunt 60m
Cisense 1nF
RCS 50
RGATE 3.3
RFREQ 67k
CICOMP 4.7nF/25V
RBVS1...2 1.5M
RBVS3 18.85k
RBVS4...5 2M
RBVS6 23k
CCM-PFC
ICE3PCS02G
Functional Description
Version 2.0 8 5 May 2010
3 Functional
Description
3.1 General
The ICE3PCS02G is a 8-pins control IC for power
factor correction converters. It is suitable for wide range
line input applications from 85 to 265 VAC with overall
efficiency above 90%. The IC supports converters in
boost topology and it operates in continuous
conduction mode (CCM) with average current con trol.
The IC operates with a cascaded control; the inner
current loop and the outer voltage loop. The inner
current loop of the IC controls the sinusoidal profile for
the average input current. It uses the dependency of
the PWM duty cycle on the line input voltage to
determine th e corresponding input current. This means
the average input current follows the input voltage as
long as the device operates in CCM. Under light load
condition, depending on the choke inductance, the
system may enter into discontinuous conduction mode
(DCM) resulting in a higher harmonics b ut still meeting
the Class D requirement of IEC 1000-3-2.
The outer voltage loop con trols the output bulk voltage,
integrated digitally with in the IC. Depending on the lo ad
condition, internal PI compensation output is converted
to an appropriate DC voltage which controls the
amplitude of the average input current.
The IC is equipped with various protection features to
ensure safe operating condition for both the system
and device.
3.2 Power Supply
An internal under voltage lockout (UVLO) block
monitors the VCC power supply. As soon as it exceeds
12.0V and voltage at pin 6 (VSENSE) >0.5V, the IC
begins operating its gate dr ive and performs its startup
as shown in Figure 3.
If VCC drops below 11V, the IC is off. The IC will then
be consuming typically 1.4mA, whereas consuming
6.4mA during normal operatio n
The IC can be turn ed off and fo rced into st andby mode
by pulling down the voltage at pin 6 (VSENSE) below
0.5V.
Figure 3 State of Operation respect to VCC
3.3 Start-up
During power up when the Vout is less th an 95% of the
rated level, internal voltage loop output increases from
initial voltage under the soft-start control. This results in
a controlled linear increase of the input current from 0A
thus reducing the stress in the external c omponents.
Once Vout has reached 95% of the rated level, the soft-
start control is released to achieve good regulation and
dynamic response in normal operation.
3.4 Frequency Setting and External
Synchronization
The IC can provide external switching frequency
setting by an external resistor RFREQ and the online
synchronization by external pulse signal at FREQ pin.
3.4.1 Frequency Setting
The switching frequency of the PFC converter can be
set with an external resistor RFREQ at FREQ pin as
shown Figure 2. The pin voltage at VFREQ is typical 1V.
The corresponding capacitor for the oscillator is
integrated in the device and the RFREQ/frequency is
given in Figure 4. The recommended operating
frequency range is from 21kHz to 250kHz. As an
example, a RFREQ of 67k at pin FREQ will set a
switching frequency FSW of 65kHz typically.
UVLO Bulk voltage rises to 95% rated value
within 200ms
VBULK
VCC
IVCC
20%
95%
100%
12V
1.4mA
<6.4mA
with 1nF external cap. at gate drive pin
26V
3.5mA
Normal
operation S tandby mode
(VVSENSE< 0.5V)
CCM-PFC
ICE3PCS02G
Functional Description
Version 2.0 9 5 May 2010
Figure 4 Frequency Versus RFREQ
3.4.2 External Synchronization
The switching frequency can be synchronized to the
external pulse signal a fter 6 external pulses delay once
the voltage at the FREQ pin is higher than 2.5V. The
synchronization means two points. Firstly, the PFC
switching frequency is tracking the external pulse
signal frequency. Second ly, the falling edge of the PFC
signal is triggered by the rising edge of the external
pulse signal. Figure 5 shows the blocks of frequency
setting and synchronization. The external RSYN
combined with RFREQ and the external diode DSYN can
ensure pin voltage to be kept between 1.0V (clamped
externally) and 5V (maximum pin voltage). If the
external pulse signal has disappeared longer than
108s (typical) the switching frequency will be
synchronized to internal clock set by the external
resistor RFREQ.
Figure 5 Frequency Setting and
Synchronization
3.5 Voltage Loop
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage VOUT. This loop is closed by the feedback
sensing voltage at VSENSE wh ich is a resistive divider
tapping from VOUT. The pin VSENSE is the input of
sigma-delta ADC which has an internal reference of
2.5V and sampling rate of 3.55kHz (typical). The
voltage loop compensation is integrated digitally for
better dynamic response and saving design effort.
Figure 6 shows the important blocks of this voltage
loop.
Figure 6 Voltage Loop
3.5.1 Notch Filter
In the PFC converter, an averaged current through the
output diode of rectified sine waveform charges the
output capacitor and results in a ripple voltage at the
output ca pacitor with a frequency two times of the line
frequency. In this digital PFC, a notch filter is used to
remove the ripple of the sensed output voltage while
keeping the rest of the signal almost uninfluenced. In
this way, an accurate and fas t output voltage regulation
without influence of the output voltage ripple is
achieved.
3.5.2 Voltage Loop Co mpensation
The Proportion-Integration (PI) compensation of the
voltage loop is integrated digitally inside the IC. The
digital data out of the PI compensator is converted to
analog voltage for current loop control.
Frequency vs Resist ance
0
20
40
60
80
100
120
140
160
180
200
220
240
260
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250
Resistance/kohm
Frequency/kHz
19.223243100
20.22214990
21.22105580
232006270 251917460
26.21698650 29.515010640
31.514014130 3413021120
3612024917 4011027815
Frequency
Resistance
/kohm
Frequency
Resistance
/kohm
RFREQ
D
SYN
OTA7
C9
RSYN
FREQ
1.0V
2.5V/1.25V
Syn. clock I
OSC
SYN
VSENSE
Gate Driver
GATE
V
IN
Av(I
IN
)
Nonlinear
Gain
C urrent Loop
+
PWM Generation
t
Sigma-
delta
ADC
Notch
Filter
PI Filter
2.5V
Rectified
Input Voltage
D
B
C
B
R
BVS2
R
BVS3
R
BVS1
L
Boost
Q
B
R
GATE
C2a
C1a
C1b
R
S
Q
Q
OVP
OVP
OLP 0.5V
2.5V
2.7V
500 ns
CCM-PFC
ICE3PCS02G
Functional Description
Version 2.0 10 5 May 2010
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
output voltage of integrated PI compensator. This block
has been designed to reduce the voltage loop
dependency on the input voltage in order to support the
wide input voltage range (85VAC-265VAC). Figure 7
gives the relative output power transfer curve versus
the digital word from the integrated PI compensator.
The output power at the input voltage of 85VAC and
maximum digital word of 256 from PI compensator is
set as the normative power and the power curves at
different input voltage present th e relative power to the
normative one.
Figure 7 Power Trans fer Curve
3.6 Average Current Control
The choke current is sensed through the voltage
across the shunt resistor and averaged by the ICOMP
pin capacitor so that the IC can control the choke
current to track the instant variation of the input voltage.
3.6.1 Complete Current Loop
The complete system current loop is shown in F igure 8.
It consists of the cu rrent loop block which averages the
voltage at ISENSE pin resulted from the inductor
current flowing across Rshunt. The averaged waveform
is compared with an internal ramp in the ramp
generator and PWM block. Once the ramp crosses the
average waveform, the comparator C10 turns on the
driver stage through the PWM logic block. The
Nonlinear Gain block defines the amplitude of the
inductor current. The following sections describe the
functionality of each individual blocks.
Figure 8 Complete System Current Loop
3.6.2 Current Loop Compensation
The compensation of the current loop is implemented
at the ICOMP pin. This is OTA6 outpu t and a capacitor
CICOMP has to be installed at this node to ground (see
Figure 8). Under normal mode of the operation, this pin
gives a voltage which is proportional to the averaged
inductor current. This pin is internally shorted to 5V in
the event of standby mode.
3.6.3 Pulse Width Modulation (PWM )
The IC employs an average current control scheme in
continuous mode (CCM) to achieve the power factor
correction. Assuming the loop voltage is working and
output voltage is kept constant, the off duty cycle DOFF
for a CCM PFC system is given as:
DOFF=VIN/VOUT
From the above equation, DOFF is proportio nal to VIN.
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle DOFF, and thus to the input voltage
VIN. Figure 9 shows the scheme to achieve the
objective.
0.00001
0.00010
0.00100
0.01000
0.10000
1.00000
10.00000
0 18 37 55 73 91 110 128 146 165 183 201 219 238 256
PI di gita l o utput
relative output power
power at 85V power at 265V
Rectified
Input Voltage
D
B
C
B
L
Boost
Q
B
R
GATE
R
shunt
R
CS
R
S
Gate
Driver
GATE
OTA6
ICOMP
5V
Current Loop
Compensation
C urrent Loop
Nonlinear
Gain
5.0mS
+/-50uA (linear range)
C
ICOMP
S2
Fault
ISENSE
C10
PWM
Comparator
PWM Logic
Q
Input From
Voltage Loop
voltage
proportional to
averaged
I nduc t or c u rrent
CCM-PFC
ICE3PCS02G
Functional Description
Version 2.0 11 5 May 2010
Figure 9 Average Current Control in CCM
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 3
(ICOMP). The PWM cycles starts with the Gate turn off
for a duration of TOFFMIN (600ns typ.) and the ramp is
kept discharged. The ramp is allowed to rise after the
TOFFMIN expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle DOFF.
Figure 10 shows the timing diagrams of the TOFFMIN and
the gate waveforms.
Figure 10 Ramp and PWM waveforms
3.7 PWM Logic
The PWM logic block prioritizes the control input signal
and generates the final logic signal to turn on the drive r
stage. The speed of the logic gates in this block,
together with the width of the reset pulse TOFFMIN, are
designed to meet a maximum duty cycle DMAX of 95%
at the GATE output under 65kHz of operation.
In case of high input currents which results in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal TOFFMIN resets (highest prio rity,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 11.
Figure 11 PWM LOGIC
3.8 System Protection
The IC provides numerous protection features in order
to ensure the PFC system in safe op eration.
3.8.1 Peak Curren t Limit (PCL)
The IC provides a cycle b y cycle peak current limitation
(PCL). It is active when the voltage at pin 1 (ISENSE)
reaches -0.4 V. This voltage is a mplified by a factor o f -
2.5 and connected to comparator with a reference
voltage of 1.0V as shown in Figure 12. A deglitcher with
200ns after the co mparator improves noise immunity to
the activation of this protection.
Figure 12 Peak Current Limit (PCL)
3.8.2 Open Loop Protection (OLP)
Whenever VSENSE voltage falls below 0.5V, or
equivalently VOUT falls below 20% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage VIN for
normal operation. It is implemented using comparator
Ramp Profile A v e(I
in
) at IC OMP
Gat e
Drive
t
t
PWM Cycle
Ramp
Released
T
off_min
600 ns
Clock
V
C,ref(1)
V
ramp
GATE
(1)
V
c,ref
is a function of V
ICOMP
R
S
Q
Q
Current
limit Latch
R
S
Q
Q
PWM on
Latch
High = turn on Gate
T
off_min
600ns
Peak current limit
Current l oop
PWM on signal
R
shunt
R
CS
Full-wave
rectifier ISENSE
AO2 C5
200ns
SGND
G=-2.5
1V
I
in
PCL
CCM-PFC
ICE3PCS02G
Functional Description
Version 2.0 12 5 May 2010
C2a with a threshold of 0.5V as shown in the IC block
diagram in Figure 6.
3.8.3 First Over-Voltage Protection (OVP1)
Whenever VOUT exceeds the rated value by 8%, the
over-voltage protection OVP1 is active as shown in
Figure 6. This is imp lemented by sensing the voltag e at
VSENSE pin with respect to a reference voltage of
2.7V. A VSENSE voltage higher than 2.7V will
immediately turn off the gate, thereby preventing
damage to bus capac itor. After bulk voltage falls below
the rated value, gate drive resumes switching again.
3.8.4 Second Over Voltage Protection (OVP2)
The second OVP is provided in case that the first one
fails due to the aging or incorrect resistors connected to
the VSENSE pin. This is implemented by sensing the
voltage at pin OVP with respect to a reference voltage
of 2.5V. When voltage at OVP pin is higher than 2.5V,
the IC will immediately turn off the gate, thereby
prevent ing damage to bu s capacitor .
When the bulk voltage drops out of the hysteresis the
IC will begin auto soft-start.
In normal operation the trigger level of second OVP
should be des igned higher than the first O VP. However
in the condition of mains transient overshoot the bulk
voltage may be pulled up to the peak value of mains
that is higher than the threshold of OVP1 and OVP2. In
this case the OVP1 and OVP2 are triggered in the
same time the IC will shut down the gate drive until bulk
voltage falls out of the two protection hysteresis, then
resume the gate drive again.
3.9 Output Gate Driver
The output gate driver is a fast tote m pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 13) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (GATE) is typically
clamped at 15V.
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the gate
drive is internally pull low to maintain the off state.
Figure 13 Gate Driver
External
MOS
GATE
Z1
VCC
Gate Driver
P WM Logi c
HIGH to
turn on
LV
* LV: Level Shift
R eg (17 V)
CCM-PFC
ICE3PCS02G
Functional Description
Version 2.0 13 5 May 2010
3.10 Protection Function
Description of Fault Fault-Type Min. Duration
of Effect Consequence
Voltage at Pin ISENSE <
-400mV PCL 200 ns Gate Driver is tu rn ed off immediatel y du rin g
current switching cycle
Voltage at Pin VSENSE < 0 .5V OLP 1 s Power down. Soft-restart after VSENSE voltage
> 0.5V
Voltage at Pin VSENSE >
108% of rated level OVP1 12s Gate Driver is turned off until VSENSE voltage <
2.5V.
Voltage at Pin OVP > 2.5V and
Voltage at Pin VSENSE >
108% of rated level
OVP1 and
OVP2 12 s Gate Driver is turned off until bulk voltage drops
out of both OVP hy steresis
Voltage at Pin OVP > 2.5V OVP2
(auto-
restart
mode)
12 s Gate Driver is turned off. Soft-restart after OVP
voltage < 2.3V
CCM-PFC
ICE3PCS02G
Electrical Characteristics
Version 2.0 14 5 May 2010
4 Electrical Characteristics
All voltages are measured with respect to ground (pin 2). The voltage levels are valid if other ratings are not
violated.
4.1 Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the
integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is
discharged before ass embling the application circuit.
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
VCC Supply Voltage VVCC -0.3 26 V
GATE Voltage VGATE -0.3 17 V Clamped at 15V if
driven internally.
ISENSE Voltage VISENSE -20 5.3 V 1)
1) Absolute ISENSE current should not be exceeded
ISENSE Current IISENSE -1 1 mA
VSENSE Voltage VVSENSE -0.3 5.3 V
VSENSE Current IVSENSE -1 1 mA
ICOMP Voltage VICOMP -0.3 5.3 V
FREQ Voltage VFREQ -0.3 5.3 V
OVP Voltage VOVP -0.3 5.3 V
Junction Temperature TJ-40 150 °C
Storage Temperature TA,STO -55 150 °C
Thermal Resistance RTHJA 185 K/W Junction to Air
Soldering Temperature TSLD 260 °C Wave Soldering2)
2) According to JESD22A111
ESD Capability VESD 2 kV Human Body Model3)
3) According to EIA/JESD22-A114-B (discharging an 100 pF capacitor through an 1.5k series resistor)
CCM-PFC
ICE3PCS02G
Electrical Characteristics
Version 2.0 15 5 May 2010
4.2 Operating Range
Note: Within the operating range the IC operates as described in the functional desc ription.
4.3 Characteristics
Note: The electrical Characteristics involve the spread of values given within the specified supply voltage and
junction temperature range T J from -25 °C to 125 °C. Typical va lues represe nt the median values, whic h
are related to 25 °C. If not otherwise stated, a su pply voltage of VVCC = 18V, a typical switc hing frequency
of ffreq=65kHz are assumed and the IC operates in activ e mode. Furthermore, all voltages are referring to
GND if not otherwise mentioned.
4.3.1 Supply Section
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
VCC Supply Voltage @ 25°C VVCC VVCC,OFF 25 V TJ=25°C
Junction Temperature TJ-25 125 °C
PFC switching frequency FPFC 21 250 kHz
Parameter Symbol Limit Values Unit Note/Test Condition
Min. Typ. Max.
VCC Turn-On Threshold VCCon 11.5 12 12.9 V
VCC Turn-Off Threshold/
Under Voltage Lock Out VCCUVLO 10.5 11.0 11.9 V
VCC Turn-On/Off Hysteresis VCChy 0.7 1 1.45 V
Start Up Current
Before VCCon ICCstart1 - 380 680 AV
CCon-1.2V
Start Up Current
Before VCCon ICCstart2 -1.42.4mAV
CCon-0.2V
Operating Current with active GATE ICCHG -6.48.5mAC
L= 1nF
Operating Current during Standby ICCStdby -3.54.7mAV
VSENSE= 0.4V
VICOMP= 4V
CCM-PFC
ICE3PCS02G
Electrical Characteristics
Version 2.0 16 5 May 2010
4.3.2 Variable Frequenc y Section
4.3.3 PWM Section
4.3.4 External Synchronization
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Switching Frequency (Typical) FSWnom 62.5 65 67.5 kHz R5 = 67k
Switching Frequency (Min.) FSWmin - 21 - kHz R5 = 212k
Switching Frequency (Max.) FSWmax - 250 - kHz R5 = 17k
Voltage at FREQ pin VFREQ -1-V
Max. Duty Cycle Dmax 93 95 98.5 % fSW=fSWnom
(RFREQ=67k)
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
Min. Duty Cycle DMIN 0%V
VSENSE= 2.5V
VICOMP= 4.3V
Min. Off Time TOFFMIN 310 600 920 ns VVSENSE= 2.5V
VISENSE= 0V
(R5 = 67k)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Detection threshold of external clock Vthr_EXT 2.5 V
Synchronization ra nge fEXT_range 50 150 kHz
Synchronization frequency ratio fEXT:fPFC 1:1
propagation delay from rising edge of
external clock to falling edge of PFC
gate drive
TEXT2GATE 500 ns fEXT=65kHz
Allowable external duty on time TD_on 10 70 %
CCM-PFC
ICE3PCS02G
Electrical Characteristics
Version 2.0 17 5 May 2010
4.3.5 System Protection Section
4.3.6 Current Loop Section
4.3.7 Voltage Loop Section
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Over Voltage Protection (OVP1) Low to
High VOVP1_L2H 2.65 2.7 2.77 V 108%VBULKRated
Over Voltage Protection (O VP1) High to
Low VOVP1_H2L 2.45 2.5 2.55 V
Over Voltage Protection (OVP1)
Hysteresis VOVP1_HYS 150 200 270 mV
Blanking time for OVP1 TOVP1 12 s
Over Voltage Protection (OVP2) Low to
High VOVP2_L2H 2.45 2.5 2.55 V
Over Voltage Protection (OVP2) H igh to
Low IOVP2_H2L 2.25 2.3 2.35 V
Blanking time for OVP2 TOVP2 12 s
OVP2 mode detection threshold VOVP2_mode 0.5 V comparator at VBTHL pin
Current source for OVP2 mode
detection1)
1) The parameter is not subject to production test - verified by design/characterization
IOVP2_mode 456A current source at VBTHL
pin
Peak Current Limitation (PCL) ISENSE
Threshold VPCL -365 -400 -435 mV
Blanking time for PCL turn_on TPCLon 200 ns
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
OTA6 Transconductance Gain GmOTA6 3.5 5.0 6.35 mS At Temp = 25°C
OTA6 Output Linear Range1)
1) The parameter is not subject to production test - verified by design/characterization
IOTA6 ± 50 A
ICOMP Voltage during OLP VICOMPF 4.8 5.0 5.2 V VVSENSE= 0.4V
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Trimmed Reference Voltage VVSREF 2.47 2.5 2.53 V ±1.2%
Open Loop Protection (OLP) VSENSE
Threshold VVS_OLP 0.45 0.5 0.55 V
VSENSE Input Bias Current IVSENSE -1 - 1 AVVSENSE= 2.5V
CCM-PFC
ICE3PCS02G
Electrical Characteristics
Version 2.0 18 5 May 2010
4.3.8 Driver S ec tion
4.3.9 Gate Drive Section
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
GATE Low Voltage VGATEL --1.2VV
CC =10V
IGATE = 5 mA
-0.4-VI
GATE = 0 A
--1.4VIGATE = 20 mA
-0.2 0.8 - V IGATE = -20 mA
GATE High Voltage VGATEH -15-VVCC = 25V
CL = 1nF
- 12.4 - V VCC = 15V
CL = 1nF
8.0 - - V VCC = VVCCoff + 0.2V
CL = 1nF
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
GATE Rise Time tr-30-nsVGate = 20% - 80%
VGATEH CL = 1nF
GATE Fall Time tf-25-nsVGate = 80% - 20%
VGATEH CL = 1nF
CCM-PFC
ICE3PCS02G
Outline Dimension
Version 2.0 19 5 May 2010
5 Outline Dimension
PG-DSO-8 Outline Dimension
Notes:
1. You can find all of our packages, sorts of packing and others in our Infineon
Internet Page “Products”: http://www.infineon.com/products.
2. Dimensions in mm.
Does not include plastic or metal protrusion of 0.15 max. per side
-0.05
-0.2
+0.1
5
0.41
Index Marking (Chamfer)
x8
1
1)
4
8
1.27
5
A
0.1
0.2
M
A
(1.5)
0.1 MIN.
1.75 MAX.
C
C
6±0.2
0.64
0.33 4
-0.2
-0.01
0.2
+0.05
x 45˚
±0.08
1)
±0.25
MAX.8˚
1)
Index
Marking
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