10-Bit, 20MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
●NO MISSING CODES
●INTERNAL REFERENCE
●LOW DIFFERENTIAL LINEARITY ERROR:
0.2LSB
●LOW POWER: 195mW
●HIGH SNR: 60dB
●WIDEBAND TRACK/HOLD: 65MHz
DESCRIPTION
The ADS820 is a low-power, monolithic 10-bit, 20MHz Ana-
log-to-Digital (A/D) converter utilizing a small geometry CMOS
process. This complete converter includes a 10-bit quantizer
with internal track-and-hold, reference, and a power down
feature. It operates from a single +5V power supply and can
be configured to accept either differential or single-ended
input signals.
The ADS820 employs digital error correction to provide excel-
lent Nyquist differential linearity performance for demanding
imaging applications. Its low distortion, high SNR, and high
oversampling capability give it the extra margin needed for
telecommunications and video applications.
This high performance converter is specified for AC and
DC-performance at a 20MHz sampling rate. The ADS820
is available in an SO-28 package.
APPLICATIONS
●SET-TOP BOXES
●CABLE MODEMS
●VIDEO DIGITIZING
●CCD IMAGING
Camcorders
Copiers
Scanners
Security Cameras
●IF AND BASEBAND DIGITIZATION
ADS820
SBAS037B – DECEMBER 1995 – REVISED FEBRUARY 2005
www.ti.com
Copyright © 1995-2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Pipeline
A/D
Timing
Circuitry
Error
Correction
Logic
3-State
Outputs
T&H 10-Bit
Digital
Data
CLK
+1.25V
+3.25V
MSBI OE
IN
IN
REFT
CM
REFB
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
ADS820U
All trademarks are the property of their respective owners.
www.ti.com ADS820
2SBAS037B
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS820 SO-8 DW –40°C to +85°C ADS820U ADS820U Rails, 28
"" " ""ADS820U/1K Tape and Reel, 1000
ADS820U
PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
Resolution 10 Bits
Specified Temperature Range TAMBIENT –40 +85 °C
ANALOG INPUT
Differential Full-Scale Input Range +1.25 +3.25 V
Common-Mode Voltage 2.25 V
Analog Input Bandwidth (–3dB)
Small Signal –20dBFS(1) Input +25°C 400 MHz
Full Power 0dB Input +25°C 65 MHz
Input Impedance 1.25 || 4 MΩ || pF
DIGITAL INPUT
Logic Family TTL/HCT Compatible CMOS
Convert Command Start Conversion Falling Edge
ACCURACY(2) fS = 2.5MHz
Gain Error +25°C±0.6 ±1.5 %
Full ±1.0 ±2.5 %
Gain Tempco ±85 ppm/°C
Power-Supply Rejection of Gain ∆ +VS = ±5% +25°C 0.01 0.1 %FSR/%
Input Offset Error Full ±2.1 ±3.0 %
Power-Supply Rejection of Offset ∆ +VS = ±5% +25°C 0.02 0.1 %FSR/%
CONVERSION CHARACTERISTICS
Sample Rate 10k 20M Sample/s
Data Latency 6.5
Convert Cycle
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz +25°C±0.15 ±1.0 LSB
Full ±0.15 ±1.0 LSB
f = 10MHz +25°C±0.2 ±1.0 LSB
Full ±0.2 ±1.0 LSB
No Missing Codes Full Tested
Integral Linearity Error at f = 500kHz Full ±0.5 ±2.0 LSB
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (–1dBFS input) +25°C 67 77 dBFS
Full 64 74 dBFS
f = 10MHz (–1dBFS input) +25°C 59 63 dBFS
Full 57 62 dBFS
ABSOLUTE MAXIMUM RATINGS(1)
+VS....................................................................................................... +6V
Analog Input ............................................................ 0V to (+VS + 300mV)
Logic Input ............................................................... 0V to (+VS + 300mV)
Case Temperature......................................................................... +100°C
Junction Temperature.................................................................... +150 °C
Storage Temperature .................................................................... +125°C
External Top Reference Voltage (REFT)................................. +3.4V Max
External Bottom Reference Voltage (REFB) ............................+1.1V Min
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION(1)
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
NOTE: (1) dBFS refers to dB below Full Scale. (2) Percentage accuracies are referred to the internal A/D Converter Full-Scale Range of 4Vp-p. (3) IMD is
referred to the larger of the two input signals. If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (4) Based on
(SINAD – 1.76)/6.02. (5) No “rollover” of bits.
www.ti.com
ADS820 3
SBAS037B
ADS820U, E
PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
NOTE: (1) dBFS refers to dB below Full Scale. (2) Percentage accuracies are referred to the internal A/D Converter Full-Scale Range of 4Vp-p. (3) IMD is
referred to the larger of the two input signals. If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (4) Based on
(SINAD – 1.76)/6.02. (5) No “rollover” of bits.
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input) +25°C 58 60.5 dB
Full 56 60 dB
f = 10MHz (–1dBFS input) +25°C58 60 dB
Full 56 60 dB
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input) +25°C 58 60.5 dB
Full 55 60 dB
f = 10MHz (–1dBFS input) +25°C56 58 dB
Full 54 57 dB
Differential Gain Error NTSC or PAL +25°C 0.5 %
Differential Phase Error NTSC or PAL +25°C 0.1 degrees
Effective Bits(4) fIN = 3.58MHz 9.5 Bits
Aperture Delay Time +25°C2 ns
Aperture Jitter +25°C 7 ps rms
Overvoltage Recovery Time(5) 1.5x Full-Scale Input +25°C2 ns
OUTPUTS
Logic Family TTL/HCT Compatible CMOS
Logic Coding Logic Selectable SOB or BTC V
Logic Levels Logic LOW, CL = 15pF Full 0 0.4 V
Logic HIGH, CL = 15pF Full 2.5 +VSV
3-State Enable Time 20 40 ns
3-State Disable Time Full 2 10 ns
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VSOperating Full +4.75 +5 +5.25 V
Supply Current: +ISOperating +25°C3947mA
Operating Full 40 55 mA
Power Consumption Operating +25°C 195 235 mW
Operating Full 200 275 mW
Thermal Resistance,
θ
JA
SO-28 75 °C/W
www.ti.com ADS820
4SBAS037B
PIN DESIGNATOR DESCRIPTION
1 GND Ground
2 B1 Bit 1, Most Significant Bit (MSB)
3 B2 Bit 2
4 B3 Bit 3
5 B4 Bit 4
6 B5 Bit 5
7 B6 Bit 6
8 B7 Bit 7
9 B8 Bit 8
10 B9 Bit 9
11 B10 Bit 10, Least Significant Bit (LSB)
12 DNC Do not connect.
13 DNC Do not connect.
14 GND Ground
15 +VS+5V Power Supply
16 CLK Convert Clock Input, 50% Duty Cycle
17 +VS+5V Power Supply
18 OE HIGH: High Impedance State. LOW or Floating:
Normal Operation. Internal pull-down resistor.
19 MSBI Most Significant Bit Inversion, HIGH: MSB in-
verted for complementary output. LOW or Float-
ing: Straight output. Internal pull-down resistor.
20 +VS+5V Power Supply
21 REFB Bottom Reference Bypass. For external bypass-
ing of internal +1.25V reference.
22 CM Common-Mode Voltage. It is derived by (REFT +
REFB)/2.
23 REFT Top Reference Bypass. For external bypassing
of internal +3.25V reference.
24 +VS+5V Power Supply
25 GND Ground
26 IN Input
27 IN Complementary Input
28 GND Ground
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View SO
GND
Bit 1(MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 (LSB)
DNC
DNC
GND
GND
IN
IN
GND
+VS
REFT
CM
REFB
+VS
MSBI
OE
+VS
CLK
+VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS820
DNC: Do Not Connect
TIMING DIAGRAM
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tCONV Convert Clock Period 50 100µsns
tLClock Pulse LOW 24 25 ns
tHClock Pulse HIGH 24 25 ns
tDAperture Delay 2 ns
t1Data Hold Time, CL = 0pF 3.9 ns
t2New Data Delay Time, CL = 15pF max 12.5 ns
Track Hold
"N" Hold
"N + 1" Hold
"N + 2" Hold
"N + 3"
Hold
"N + 4"
Hold
"N + 5
"
Hold
"N + 6"
Track
Data Valid
N – 7 Data Valid
N – 6
Internal
Track-and-Hold
Convert
Clock
Output
Data
t
D
t
2
t
1
Data Latency
(6.5 Clock Cycles)
t
CONV
t
L
t
H
Track Track Track Track
N – 3N – 5N – 4N – 2N – 1 N
Track Track
Data Valid
N – 8
(1)
Data Invalid
NOTE: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates.
www.ti.com
ADS820 5
SBAS037B
SPECTRAL PERFORMANCE
Frequency (MHz)
Amplitude (dB)
0 1.0 2.0 3.0 4.0 5.0
0
–20
–40
–60
–80
–100
–120
f
IN
= 500kHz
f
S
= 10MHz
SPECTRAL PERFORMANCE
Frequency (MHz)
Amplitude (dB)
0 2.0 4.0 6.0 8.0 10.0
0
–20
–40
–60
–80
–100
–120
f
IN
= 4.8MHz
SPECTRAL PERFORMANCE
Frequency (MHz)
Amplitude (dB)
0 2.0 4.0 6.0 8.0 10.0
0
–20
–40
–60
–80
–100
–120
f
IN
= 9.8MHz
0
–20
–40
–60
–80
–100
–120
TWO-TONE INTERMODULATION
Amplitude (dB)
0.0 2.50 5.00 7.50 10.00
Frequency (MHz)
f1 = 4.5MHz
f2 = 4.4MHz
DIFFERENTIAL LINEARITY ERROR
Code
DLE (LSB)
2.0
1.0
0
–1.0
–2.0
Code
24 224 424 624 824 1024
f
IN
= 500kHz
DIFFERENTIAL LINEARITY ERROR
Code
DLE (LSB)
2.0
1.0
0
–1.0
–2.0 24 224 424 624 824 1024
f
IN
= 10MHz
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
www.ti.com ADS820
6SBAS037B
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
Frequency (Hz)
SFDR, SNR (dB)
85
80
75
70
65
60
55100k 1M 10M 100M
SFDR
SNR
100
80
60
40
20
0
Input Amplitude (dBm)
SFDR (dBFS)
SWEPT POWER SFDR
–50 –40 –30 –20 –10 0 10
f
IN
= 10MHz
60
50
40
30
20
10
0
Input Amplitude (dBm)
SWEPT POWER SNR
–48.125 –40 –30 –20 –10 0 10
SNR (dB)
fIN = 10MHz
4.0
2.0
0
–2.0
–4.0
INTEGRAL LINEARITY ERROR
Code
ILE (LSB)
fIN = 500kHz
24 224 424 624 824 1024
80
75
70
65
60
55
DYNAMIC PERFORMANCE
vs SINGLE-ENDED FULL-SCALE INPUT RANGE
Dynamic Range (dB)
12345
Single-Ended Full-Scale Input Range (Vp-p)
SNR (fIN = 10MHz)
SFDR (fIN = 500kHz)
SNR (fIN = 500kHz)
SFDR (fIN = 10MHz)
NOTE: REFTEXT varied, REFB is fixed at the internal value of +1.25V.
80
75
70
65
60
55
DYNAMIC PERFORMANCE
vs DIFFERENTIAL FULL-SCALE INPUT RANGE
Dynamic Range (dB)
12345
Differential Full-Scale Input Range (Vp-p)
NOTE: REFT
EXT
varied, REFB is fixed at internal value of +1.25V.
SNR (f
IN
= 10MHz)
SFDR (f
IN
= 500kHz)
SNR (f
IN
= 500kHz)
SFDR (f
IN
= 10MHz)
www.ti.com
ADS820 7
SBAS037B
DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE
Temperature (°C)
DLE (LSB)
0.3
0.2
0.1
0–50 –25 0 25 50 75 100
f
IN
= 500kHz
f
IN
= 10MHz
SPURIOUS-FREE DYNAMIC RANGE
vs TEMPERATURE
Temperature (°C)
SFDR (dBFS)
90
80
70
60
50–50 –25 0 25 50 75 100
f
IN
= 500kHz
f
IN
= 10MHz
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
Temperature (°C)
SNR (dB)
70
65
60
55
50–50 –25 0 25 50 75 100
fIN = 500kHz
fIN = 10MHz
SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
Temperature (°C)
SINAD (dB)
62
60
58
56
54–50 –25 0 25 50 75 100
f
IN
= 500kHz
f
IN
= 10MHz
SUPPLY CURRENT vs TEMPERATURE
Temperature (°C)
IQ (mA)
42
40
38
36–50 –25 0 25 50 75 100
POWER DISSIPATION vs TEMPERATURE
Temperature (°C)
Power (mW)
210
200
190
180
170–50 –25 0 25 50 75 100
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
www.ti.com ADS820
8SBAS037B
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
GAIN ERROR vs TEMPERATURE
Temperature (°C)
Gain (% FSR)
–0.05
–0.55
–1.05
–1.55–50 –25 0 25 50 75 100
OFFSET ERROR vs TEMPERATURE
Temperature (°C)
Offset (% FSR)
–1.75
–2.0
–2.25
–2.50–50 –25 0 25 50 75 100
TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH
Frequency (Hz)
Track-Mode Input Response (dB)
10k
1
0
–1
–2
–3
–4
–5100k 1M 10M 100M 1G
OUTPUT NOISE HISTOGRAM (NO SIGNAL)
Counts
1.2M
1M
0.8M
0.6M
0.4M
0.2M
0.0
Code
N – 2N – 1 N N + 1 N + 2
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ADS820 9
SBAS037B
THEORY OF OPERATION
The ADS820 is a high-speed, sampling A/D converter with
pipelining. It uses a fully differential architecture and digital
error correction to ensure 10-bit resolution. The differential
track-and-hold circuit is shown in Figure 1. The switches are
controlled by an internal clock that has a non-overlapping,
two-phase signal, φ1 and φ2. At the sampling time the input
signal is sampled on the bottom plates of the input capaci-
tors. In the next clock phase, φ2, the bottom plates of the
input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time,
the charge redistributes between CI and CH, completing one
track-and-hold cycle. The differential output is a held DC
representation of the analog input at the sample time. The
track-and-hold circuit can also convert a single-ended input
signal into a fully differential signal for the quantizer.
The pipelined quantizer architecture has nine stages with
each stage containing a 2-bit quantizer and a 2-bit Digital-to-
Analog Converter (DAC), as shown in Figure 2. Each 2-bit
quantizer stage converts on the edge of the sub-clock, which
is twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to FIGURE 1. Input Track-and-Hold Configuration with Timing
Signals.
FIGURE 2. Pipeline A/D Converter Architecture.
φ1
φ1φ2φ1
φ1φ1
φ1
φ1
φ2
φ1φ2φ1
φ2
IN
IN
OUT
OUT
Op Amp
Bias V
CM
Op Amp
Bias V
CM
C
H
C
I
C
I
C
H
Input Clock (50%)
Internal Non-overlapping Clock
Σ
+–
B1 (MSB)
B2
B3
B4
B5
B6
B7
B8
B9
B10 (LSB)
2-Bit
DAC
2-Bit
Flash
Input
T&H Digital Delay
x2
x2
2-Bit
DAC
2-Bit
Flash
Digital Delay
2-Bit
Flash Digital Delay
2-Bit
DAC
2-Bit
Flash
Digital Delay
x2
Digital Error Correction
IN
IN
STAGE 1
STAGE 2
STAGE 8
STAGE 9
Σ
+–
Σ
+–
www.ti.com ADS820
10 SBAS037B
time-align it with the data created from the following quan-
tizer stages. This aligned data is fed into a digital error
correction circuit that can adjust the output data based on the
information found on the redundant bits. This technique gives
the ADS820 excellent differential linearity and ensures no
missing codes at the 10-bit level.
There is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two’s Complement
(BTC) format.
THE ANALOG INPUT AND INTERNAL REFERENCE
The analog input of the ADS820 can be configured in various
ways and driven with different circuits, depending on the
nature of the signal and the level of performance desired. The
ADS820 has an internal reference that sets the full-scale
input range of the A/D converter. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full-scale range of +1.25V
to +3.25V. Since each input is 2Vp-p and 180° out-of-phase
with the other, a 4V differential input signal to the quantizer
results. The positive full-scale reference (REFT) and the
negative full-scale reference (REFB) are brought out for
external bypassing, as shown in Figure 3. In addition, the
common-mode (CM) voltage may be used as a reference to
provide the appropriate offset for the driving circuitry. How-
ever, care must be taken not to appreciably load this refer-
ence node. For more information regarding external refer-
ences, single-ended inputs, and ADS820 drive circuits, refer
to the applications section.
DIGITAL OUTPUT DATA
The 10-bit output data is provided at CMOS logic levels. The
standard output coding is Straight Offset Binary where a full-
scale input signal corresponds to all “1’s” at the output. This
condition is met with pin 19 LOW or Floating due to an
internal pull-down resistor. By applying a high voltage to this
pin, a BTC output will be provided where the most significant
bit is inverted. The digital outputs of the ADS820 can be set
to a high impedance state by driving
OE
(pin 18) with a logic
HIGH. Normal operation is achieved with pin 18 LOW or
Floating due to internal pull-down resistors. This function is
provided for testability purposes and is not meant to drive
digital buses directly or be dynamically changed during the
conversion process.
FIGURE 3. Internal Reference Structure.
CLOCK REQUIREMENTS
The CLK pin accepts a CMOS level clock input. The rising
and falling edge of the externally applied convert command
clock controls the various interstage conversions in the
pipeline. Therefore, the duty cycle of the clock should be held
at 50% with low jitter and fast rise and fall times of 2ns or
less. This is especially important when digitizing a high-
frequency input and operating at the maximum sample rate.
Deviation from a 50% duty cycle will effectively shorten some
of the interstage settling times, thus degrading the SNR and
DNL performance.
OUTPUT CODE
SOB BTC
PIN 19 PIN 19
DIFFERENTIAL INPUT(1)
FLOATING or LOW
HIGH
+FS (IN = +3.25V, IN = +1.25V) 1111111111 0111111111
+FS –1LSB 1111111111 0111111111
+FS –2LSB 1111111110 0111111110
+3/4 Full Scale 1110000000 0110000000
+1/2 Full Scale 1100000000 0100000000
+1/4 Full Scale 1010000000 0010000000
+1LSB 1000000001 0000000001
Bipolar Zero (IN = IN = +2.25V) 1000000000 0000000000
–1LSB 0111111111 1111111111
–1/4 Full Scale 0110000000 1110000000
–1/2 Full Scale 0100000000 1100000000
–3/4 Full Scale 0010000000 1010000000
–FS +1LSB 0000000001 1000000001
–FS (IN = +1.25V, IN = +3.25V) 0000000000 1000000000
NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.
TABLE I. Coding Table for the ADS820.
APPLICATIONS
DRIVING THE ADS820
The ADS820 has a differential input with a common mode of
+2.25V. For AC-coupled applications, the simplest way to
create this differential input is to drive the primary winding of
a transformer with a single-ended input. A differential output
is created on the secondary if the center tap is tied to the
(CM) voltage of +2.25V, as per Figure 4. This transformer-
coupled input arrangement provides good high frequency
FIGURE 4. AC-Coupled Single-Ended to Differential Drive
Circuit Using a Transformer.
+1.25V
+3.25V
2kΩ
2kΩ
0.1µF
0.1µF
+2.25V
REFT
REFB
CM
ADS820
To
Internal
Comparators
21
22
23
Mini-Circuits
TT1-6-KK81
or equivalent
22
26
27
CM
IN
IN
ADS820
AC Input
Signal 22pF
22pF
0.1µF
www.ti.com
ADS820 11
SBAS037B
AC performance. It is important to select a transformer that
gives low distortion and does not exhibit core saturation at
full-scale voltage levels. Since the transformer does not
appreciably load the ladder, there is no need to buffer the CM
output in this instance. In general, it is advisable to keep the
current draw from the CM output pin below 0.5µA to avoid
nonlinearity in the internal reference ladder. A FET input
operational amplifier, such as the OPA130, can provide a
buffered reference for driving external circuitry. The analog
IN and
IN
inputs should be bypassed with 22pF capacitors to
minimize track-and-hold glitches and to improve high-input
frequency performance.
Figure 5 illustrates another possible low-cost interface circuit
that utilizes resistors and capacitors in place of a transformer.
Depending on the signal bandwidth, the component values
should be carefully selected in order to maintain the perfor-
mance outlined in the data sheet. The input capacitors, CIN,
and the input resistors, RIN, create a high-pass filter with the
lower corner frequency at fC = 1/(2πRINCIN). The corner
frequency can be reduced by either increasing the value of
RIN or CIN. If the circuit operates with a 50Ω or 75Ω imped-
ance level, the resistors are fixed and only the value of the
capacitor can be increased. Usually AC-coupling capacitors
are electrolytic or tantalum capacitors with values of 1µF or
higher. It should be noted that these large capacitors become
inductive with increased input frequency, which could lead to
signal amplitude errors or oscillation. To maintain a low ac-
coupling impedance throughout the signal band, a small
value (e.g. 1µF) ceramic capacitor could be added in parallel
with the polarized capacitor.
Capacitors CSH1 and CSH2 are used to minimize current
glitches resulting from the switching in the input track and
hold stage and to improve signal-to-noise performance. These
capacitors can also be used to establish a low-pass filter and
effectively reduce the noise bandwidth. In order to create a
real pole, resistors RSER1 and RSER2 were added in series with
each input. The cutoff frequency of the filter is determined by
fC = 1/(2πRSER • (CSH + CADC)) where RSER is the resistor in
series with the input, CSH is the external capacitor from the
input to ground, and CADC is the internal input capacitance of
the A/D converter (typically 4pF).
Resistors R1 and R2 are used to derive the necessary
common-mode voltage from the buffered top and bottom
references. The total load of the resistor string should be
selected so that the current does not exceed 1mA. Although
the circuit in Figure 5 uses two resistors of equal value so that
the common-mode voltage is centered between the top and
bottom reference (+2.25V), it is not necessary to do so. In all
cases the center point, VCM, should be bypassed to ground in
order to provide a low-impedance ac ground.
If the signal needs to be DC-coupled to the input of the
ADS820, an operational amplifier input circuit is required. In
the differential input mode, any single-ended signal must be
modified to create a differential signal. This can be accom-
plished by using two operational amplifiers; one in the
noninverting mode for the input and the other amplifier in the
inverting mode for the complementary input. The low distor-
tion circuit in Figure 6 will provide the necessary input shifting
required for signals centered around ground. It also employs
a diode for output level shifting to ensrue a low distortion
+3.25V output swing. Another DC-coupled circuit is shown in
Figure 7. Other amplifiers can be used in place of the
OPA860s if the lowest distortion is not necessary. If output
level shifting circuits are not used, care must be taken to
select operational amplifiers that give the necessary perfor-
mance when swinging to +3.25V with a ±5V supply opera-
tional amplifier. The OPA620 and OPA621, or the lower
power OPA820 can be used in place of the OPA860s in
Figure 6. In that configuration, the OPA820 will typically
swing to within 100mV of positive full scale.
FIGURE 5. AC-Coupled Differential Input Circuit.
ADS8xx
RSER1(1)
49.9Ω
R3
1kΩ
R2
(6kΩ)
R1
(6kΩ)
C2
0.1µF
CSH1
22pF
CSH2
22pF
C3
0.1µF
C1
0.1µF
CIN
0.1µF
VCM
CIN
0.1µF
RIN1
25Ω
RIN2
25Ω
RSER2(1)
49.9Ω
+3.25V
Top Reference
+1.25V
Bottom Reference
IN
NOTE: (1) indicates optional component.
IN
www.ti.com ADS820
12 SBAS037B
FIGURE 6. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit.
FIGURE 7. A Wideband DC-Coupled, Single-Ended to Differential Input Driver Circuit.
604Ω
301Ω
301Ω
301Ω
604Ω
49.9Ω
301Ω
604Ω
2.49kΩ
2.49kΩ+2.25V
OPA842
OPA130
301Ω
0.1µF
OPA842
OPA842
+5V
–5V
+5V(2)
+5V
–5V
+5V
+5V
+5V
–5V
BAS16(1)
BAS16(1)
301Ω
24.9ΩInput Level
Shift Buffer
Optional
High Impedance
Input Amplifier
DC-Coupled
Input Signal
26 IN
22 CM
27 IN
ADS820
NOTES: (1) A Philips BAS16 diode or equivalent may be used.
(2) Supply bypassing not shown. (3) OPA620 or OPA650 may be
substituted. See “Driving the ADS820” section.
22pF
22pF
604Ω
0.1µF
0.1µF
(3)
(3)
(3)
50Ω
1kΩ
OTA
OPA860
OPA860
+1
+1
OPA130
1nF
OTA
+5V –5V
–5V
+5V
DC-Coupled
Input Signal
27 IN
22 CM
26 IN
ADS820
NOTE: Power supplies and bypassing not shown. The measured SNR performance with 12.5MHz input signal is 57dB with this driver circuit.
1kΩ
500Ω
500Ω
1kΩ
200Ω
243Ω
200Ω3B
2
3
2
85
C6
6
1
85
C
E
E
3
2
74
B
200Ω
C
1
15pF
22pF
22pF
0.1µF
2kΩ
V
OUT
–5V
243Ω
www.ti.com
ADS820 13
SBAS037B
FIGURE 8. Single-Ended Input Connection.
set halfway between the two references. This feature can be
used to adjust the gain error, improve gain drift, or to change
the full-scale input range of the ADS820. Changing the full-
scale range to a lower value has the benefit of easing the
swing requirements of external input amplifiers. The external
references can vary as long as the value of the external top
reference (REFTEXT) is less than or equal to +3.4V, the value
of the external bottom reference (REFBEXT) is greater than or
equal to +1.1V, and the difference between the external
references are greater than or equal to 800mV.
For the differential configuration, the full-scale input range
will be set to the external reference values that are
selected. For the single-ended mode, the input range is
2 • (REFTEXT – REFBEXT), with the common-mode being
centered at (REFTEXT + REFBEXT)/2. Refer to the typical
performance curves for expected performance versus full-
scale input range.
The circuit in Figure 9 works completely on a single +5V
supply. As a reference element, it uses micro-power refer-
ence REF1004-2.5, which is set to a quiescent current of
0.1mA. Amplifier A2 is configured as a follower to buffer the
+1.25V generated from the resistor divider. To provide the
necessary current drive, a pull-down resistor, RP, is added.
Amplifier A1 is configured as an adjustable gain stage, with
a range of approximately 1 to 1.32. The pull-up resistor again
relieves the op amp from providing the full current drive. The
value of the pull-up and pull-down resistors is not critical and
can be varied to optimize power consumption. The need for
pull-up/down resistors depends only on the drive capability of
the selected drive amplifiers and thus can be omitted.
The ADS820 can also be configured with a single-ended input
full-scale range of +0.25V to +4.25V by tying the complemen-
tary input to the common-mode reference voltage, as shown
in Figure 8. This configuration will result in increased even-
order harmonics, especially at higher input frequencies. How-
ever, this trade-off may be quite acceptable for time-domain
applications. The driving amplifier must give adequate perfor-
mance with a +0.25V to +4.25V output swing in this case.
EXTERNAL REFERENCES AND
ADJUSTMENT OF FULL-SCALE RANGE
The internal reference buffers are limited to approximately
1mA of output current. As a result, these internal +1.25V and
+3.25V references may be overridden by external references
that have at least 18mA (at room temperature) of output drive
capability. In this instance, the common-mode voltage will be
22
26
27
CM
IN
IN
ADS820
0.1µF
Single-Ended
Input Signal
Full Scale = +0.25V to +4.25V with internal references.
22pF
FIGURE 9. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp.
2kΩ
+2.5V to +3.25V
+5V
+5V
R
P
220Ω
R
P
220Ω
10kΩ
6.2kΩ
0.1µF+2.5V
10kΩ
1/2
OPA2234
1/2
OPA2234
A
1
A
2
Bottom
Reference
Top
Reference
REF1004
+1.25V
10kΩ
10kΩ
(1)
10kΩ
(1)
NOTE: (1) Use parts alternatively for adjustment capability.
www.ti.com ADS820
14 SBAS037B
PC-BOARD LAYOUT AND BYPASSING
A well-designed, clean PC-board layout will assure proper
operation and clean spectral response. Proper grounding
and bypassing, short lead lengths, and the use of ground
planes are particularly important for high frequency circuits.
Multilayer PC boards are recommended for best perfor-
mance but if carefully designed, a two-sided pc board with
large, heavy ground planes can give excellent results. It is
recommended that the analog and digital ground pins of the
ADS820 be connected directly to the analog ground plane. In
our experience, this gives the most consistent results. The
A/D converter power-supply commons should be tied to-
gether at the analog ground plane. Power supplies should be
bypassed with 0.1µF ceramic capacitors as close to the pin
as possible.
DYNAMIC PERFORMANCE TESTING
The ADS820 is a high-performance converter and careful
attention to test techniques is necessary to achieve accurate
results. Highly accurate phase-locked signal sources allow
high-resolution FFT measurements to be made without using
data windowing functions. A low jitter signal generator such
as the HP8644A for the test signal, phase-locked with a low
jitter HP8022A pulse generator for the A/D converter clock,
gives excellent results. Low-pass filtering (or bandpass filter-
ing) of test signals is absolutely necessary to test the low
distortion of the ADS820. Using a signal amplitude slightly
lower than full scale will allow a small amount of “headroom”
so that noise or DC-offset voltage will not overrange the
A/D converter and cause clipping on signal peaks.
DYNAMIC PERFORMANCE DEFINITIONS
1. Signal-to-Noise-and-Distortion Ratio (SINAD):
10 15
log Sinewave SignalPower
Noise HarmonicPower first harmonics+
(
)
2. Signal-to-Noise Ratio (SNR):
10 log Sinewave SignalPower
NoisePower
3. Intermodulation Distortion (IMD):
10 5
log PrHighest IMD oduct Power to th order
Sinewave SignalPower
(
)
IMD is referenced to the larger of the test signals f1 or f2. Five
“bins” either side of peak are used for calculation of funda-
mental and harmonic power. The “0” frequency bin (DC) is
not included in these calculations, as it is of little importance
in dynamic signal processing applications.
www.ti.com
ADS820 15
SBAS037B
FIGURE 10. ADS820 Interface Schematic with AC-Coupling and External Buffers.
GND
DNC
DNC
LSB
MSB
GND
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
19
+V
S
CLK
+V
S
OE
MSBI
+V
S
REFB
CM
REFT
+V
S
GND
IN
IN
GND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ADS820
0.1µF
0.1µF0.1µF
0.1µF
0.1µF
0.1µF0.1µF
R
1
50Ω
R
2
50Ω
Ext
Clk
AC Input
Signal
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
Dir
G+
1
19 Dir
G+
–541
–541
Mini-Circuits
TT1-6-KK81
or equivalent
22pF
22pF
(1)
NOTE: (1) All capacitors should be located as close to the pins as the manufacturing
process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.
+5V
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS820E OBSOLETE SSOP DB 28 TBD Call TI Call TI
ADS820E/1K OBSOLETE SSOP DB 28 TBD Call TI Call TI
ADS820U ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS820UG4 ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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