8-Bit XC886/888CLM 8-Bit Single Chip Microcontroller Data Sheet V1.2 2009-07 Micr o co n t ro l l e rs Edition 2009-07 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 8-Bit XC886/888CLM 8-Bit Single Chip Microcontroller Data Sheet V1.2 2009-07 Micr o co n t ro l l e rs XC886/888CLM XC886/888 Data Sheet Revision History: V1.2 2009-07 Previous Versions: V1.0, V1.1 Page Subjects (major changes since last revision) Changes from V1.1 2009-01 to V1.2 2009-07 89 Note on LIN baud rate detection is added. 92 RXD slave line in SSC block diagram is updated. 108 Electrical parameters are now valid for all variants, previous note on exclusion of ROM variants is removed. 116 Symbol for ADC error parameters are updated. 120 Power supply current parameters for ROM variants are updated. 128 Test condition for the on-chip oscillator short term deviation is updated. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.2, 2009-07 XC886/888CLM Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2.1 2.2 2.3 2.4 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 7 9 3 3.1 3.2 3.2.1 3.2.1.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.2.3.1 3.2.4 3.2.4.1 3.2.4.2 3.2.4.3 3.2.4.4 3.2.4.5 3.2.4.6 3.2.4.7 3.2.4.8 3.2.4.9 3.2.4.10 3.2.4.11 3.2.4.12 3.2.4.13 3.2.4.14 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 3.4.3 3.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC886/888 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Read Access of P-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Programming Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 21 21 23 23 25 29 30 31 31 32 33 34 36 37 39 43 43 44 48 49 49 50 52 53 54 55 56 56 62 64 65 Data Sheet I-1 V1.2, 2009-07 XC886/888CLM Table of Contents 3.6 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.10 3.11 3.12 3.13 3.13.1 3.13.2 3.14 3.15 3.15.1 3.16 3.17 3.18 3.19 3.20 3.21 3.21.1 3.21.2 3.22 3.22.1 3.23 Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . 68 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . 75 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 UART and UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . . 88 LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 91 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Controller Area Network (MultiCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.3 4.2.3.1 4.2.4 4.3 4.3.1 4.3.2 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet I-2 108 108 108 109 110 111 111 115 116 119 120 124 124 125 V1.2, 2009-07 XC886/888CLM Table of Contents 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 5 5.1 5.2 5.3 Data Sheet Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 128 129 130 132 Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 133 134 136 I-3 V1.2, 2009-07 8-Bit Single Chip Microcontroller 1 XC886/888CLM Summary of Features The XC886/888 has the following features: * High-performance XC800 Core - compatible with standard 8051 processor - two clocks per machine cycle architecture (for memory access without wait state) - two data pointers * On-chip memory - 12 Kbytes of Boot ROM - 256 bytes of RAM - 1.5 Kbytes of XRAM - 24/32 Kbytes of Flash; or 24/32 Kbytes of ROM, with additional 4 Kbytes of Flash (includes memory protection strategy) * I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator) (more features on next page) Flash or ROM1) 24K/32K x 8 On-Chip Debug Support Boot ROM 12K x 8 UART SSC Port 0 8-bit Digital I/O Capture/Compare Unit 16-bit Port 1 8-bit Digital I/O Compare Unit 16-bit Port 2 8-bit Digital/ Analog Input XC800 Core XRAM 1.5K x 8 RAM 256 x 8 Timer 0 16-bit Timer 1 16-bit Timer 2 16-bit Watchdog Timer ADC 10-bit 8-channel Port 3 8-bit Digital I/O MDU CORDIC MultiCAN Timer 21 16-bit UART1 Port 5 Port 4 8-bit Digital I/O 1) All ROM devices come with an additional 4K x 8 Flash Figure 1 Data Sheet . 8-bit Digital I/O XC886/888 Functional Units 1 V1.2, 2009-07 XC886/888CLM Summary of Features Features: (continued) * * * * * * * * * * * * * * * * * * Power-on reset generation Brownout detection for core logic supply On-chip OSC and PLL for clock generation - PLL loss-of-lock detection Power saving modes - slow-down mode - idle mode - power-down mode with wake-up capability via RXD or EXINT0 - clock gating control to each peripheral Programmable 16-bit Watchdog Timer (WDT) Six ports - Up to 48 pins as digital I/O - 8 pins as digital/analog input 8-channel, 10-bit ADC Four 16-bit timers - Timer 0 and Timer 1 (T0 and T1) - Timer 2 and Timer 21 (T2 and T21) Multiplication/Division Unit for arithmetic operations (MDU) Software libraries to support floating point and MDU calculations CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear functions MultiCAN with 2 nodes, 32 message objects Capture/compare unit for PWM signal generation (CCU6) Two full-duplex serial interfaces (UART and UART1) Synchronous serial channel (SSC) On-chip debug support - 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM) - 64 bytes of monitor RAM Packages: - PG-TQFP-48 - PG-TQFP-64 Temperature range TA: - SAF (-40 to 85 C) - SAK (-40 to 125 C) Data Sheet 2 V1.2, 2009-07 XC886/888CLM Summary of Features XC886/888 Variant Devices The XC886/888 product family features devices with different configurations, program memory sizes, package options, power supply voltage, temperature and quality profiles (Automotive or Industrial), to offer cost-effective solutions for different application requirements. The list of XC886/888 device configurations are summarized in Table 1. For each configuration, 2 types of packages are available: * * PG-TQFP-48, which is denoted by XC886 and; PG-TQFP-64, which is denoted by XC888. Table 1 Device Configuration Device Name CAN Module LIN BSL Support MDU Module XC886/888 No No No XC886/888C Yes No No XC886/888CM Yes No Yes XC886/888LM No Yes Yes XC886/888CLM Yes Yes Yes Note: For variants with LIN BSL support, only LIN BSL is available regardless of the availability of the CAN module. From these 10 different combinations of configuration and package type, each are further made available in many sales types, which are grouped according to device type, program memory sizes, power supply voltage, temperature and quality profile (Automotive or Industrial), as shown in Table 2. Table 2 Device Profile Sales Type Device Program Type Memory (Kbytes) Power TempSupply erature (V) (C) Quality Profile SAK-XC886*/888*-8FFA 5V Flash 32 5.0 -40 to 125 Automotive SAK-XC886*/888*-6FFA 5V Flash 24 5.0 -40 to 125 Automotive SAF-XC886*/888*-8FFA 5V Flash 32 5.0 -40 to 85 Automotive SAF-XC886*/888*-6FFA 5V Flash 24 5.0 -40 to 85 Automotive SAF-XC886*/888*-8FFI 5V Flash 32 5.0 -40 to 85 Industrial SAF-XC886*/888*-6FFI 5V Flash 24 5.0 -40 to 85 Industrial Data Sheet 3 V1.2, 2009-07 XC886/888CLM Summary of Features Table 2 Device Profile (cont'd) Sales Type Device Program Type Memory (Kbytes) Power TempSupply erature (V) (C) Quality Profile SAK-XC886*/888*-8FFA 3V3 Flash 32 3.3 -40 to 125 Automotive SAK-XC886*/888*-6FFA 3V3 Flash 24 3.3 -40 to 125 Automotive SAF-XC886*/888*-8FFA 3V3 Flash 32 3.3 -40 to 85 Automotive SAF-XC886*/888*-6FFA 3V3 Flash 24 3.3 -40 to 85 Automotive SAF-XC886*/888*-8FFI 3V3 Flash 32 3.3 -40 to 85 Industrial SAF-XC886*/888*-6FFI 3V3 Flash 24 3.3 -40 to 85 Industrial Note: The asterisk (*) above denotes the device configuration letters from Table 1. Corresponding ROM derivatives will be available on request. Note: For variants with LIN BSL support, only LIN BSL is available regardless of the availability of the CAN module. As this document refers to all the derivatives, some description may not apply to a specific product. For simplicity, all versions are referred to by the term XC886/888 throughout this document. Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies: * * The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery For the available ordering codes for the XC886/888, please refer to your responsible sales representative or your local distributor. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Data Sheet 4 V1.2, 2009-07 XC886/888CLM General Device Information 2 General Device Information Chapter 2 contains the block diagram, pin configurations, definitions and functions of the XC886/888. 2.1 Block Diagram The block diagram of the XC886/888 is shown in Figure 2. XC800 Core TMS MBC RESET VDDP VSSP VDDC VSSC 256-byte RAM + 64-byte monitor RAM T0 & T1 UART CORDIC UART1 MDU SSC WDT Timer 2 1.5-Kbyte XRAM 24/32-Kbyte Flash or ROM 2) Port 0 Internal Bus P0.0 - P0.7 Port 1 12-Kbyte Boot ROM1) P1.0 - P1.7 Port 2 XC886/888 P2.0 - P2.7 ADC OCDS Timer 21 CCU6 PLL Port 3 9.6 MHz On-chip OSC P3.0 - P3.7 Port 4 Clock Generator P4.0 - P4.7 Port 5 XTAL1 XTAL2 VAREF VAGND P5.0 - P5.7 MultiCAN 1) Includes 1-Kbyte monitor ROM 2) The 24/32-Kbyte ROM has an additional 4-Kbyte Flash Figure 2 Data Sheet XC886/888 Block Diagram 5 V1.2, 2009-07 XC886/888CLM General Device Information 2.2 Logic Symbol The logic symbols of the XC886/888 are shown in Figure 3. VDDP VDDP VSSP VSSP Port 0 8-Bit VAREF VAREF Port 0 7-Bit VAGND Port 1 8-Bit VAGND Port 1 8-Bit RESET XC886 MBC TMS Port 2 8-Bit RESET Port 2 8-Bit Port 4 8-Bit XTAL1 Port 4 3-Bit XTAL2 VDDC Data Sheet Port 3 8-Bit TMS Port 3 8-Bit XTAL1 Figure 3 XC888 MBC XTAL2 VSSC Port 5 8-Bit VDDC VSSC XC886/888 Logic Symbol 6 V1.2, 2009-07 XC886/888CLM General Device Information 2.3 Pin Configuration P2.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P4.3 P3.6 P3.7 P3.0 P3.1 The pin configuration of the XC886, which is based on the PG-TQFP-48 package, is shown in Figure 4, while that of the XC888, which is based on the PG-TQFP-64 package, is shown in Figure 5. 36 35 34 33 32 31 30 29 28 27 26 25 P3.2 37 24 V AREF P3.3 38 23 V AGND P3.4 39 22 P2.6 P3.5 40 21 P2.5 RESET 41 20 P2.4 V SSP 42 19 P2.3 V DDP 43 18 V SSP MBC 44 17 V DDP P4.0 45 16 P2.2 P4.1 46 15 P2.1 P0.7 47 14 P2.0 P0.3 48 13 P0.1 XTAL1 VSSC VDDC 8 9 10 11 12 P0.2 XTAL2 7 P0.0 6 TMS 5 P1.7 4 P1.6 3 VDDP 2 P0.5 Data Sheet 1 P0.4 Figure 4 XC886 XC886 Pin Configuration, PG-TQFP-48 Package (top view) 7 V1.2, 2009-07 XC886/888CLM P2.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P4.3 P3.6 P3.7 P3.0 P3.1 P4.4 P4.5 P4.6 P4.7 General Device Information 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P3.2 49 32 V AREF P3.3 50 31 V AGND P3.4 51 30 P2.6 P3.5 52 29 P2.5 RESET 53 28 P2.4 V SSP 54 27 P2.3 V DDP 55 26 V SSP NC 56 25 V DDP NC 57 24 P2.2 MBC 58 23 P2.1 P4.0 59 22 P2.0 P4.1 60 21 P0.1 P4.2 61 20 P5.7 P0.7 62 19 P5.6 P0.3 63 18 P0.2 P0.4 64 17 P0.0 XC888 P0.5 P0.6 XTAL2 XTAL1 VSSC VDDC VDDP P5.0 9 10 11 12 13 14 15 16 TMS 8 P5.5 7 P5.4 6 P5.3 5 P5.2 4 P1.7 3 P1.6 2 P5.1 1 Note: The pins shaded in blue are not available in the PG-TQFP-48 package. Figure 5 Data Sheet XC888 Pin Configuration, PG-TQFP-64 Package (top view) 8 V1.2, 2009-07 XC886/888CLM General Device Information 2.4 Pin Definitions and Functions The functions and default states of the XC886/888 external pins are provided in Table 3. Table 3 Pin Definitions and Functions Symbol Pin Number Type Reset Function (TQFP-48/64) State P0 I/O Port 0 Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, UART1, Timer 2, Timer 21, MultiCAN and SSC. P0.0 11/17 Hi-Z TCK_0 T12HR_1 JTAG Clock Input CCU6 Timer 12 Hardware Run Input CC61_1 Input/Output of Capture/Compare channel 1 CLKOUT_0 Clock Output RXDO_1 UART Transmit Data Output P0.1 13/21 Hi-Z TDI_0 T13HR_1 RXD_1 RXDC1_0 COUT61_1 EXF2_1 P0.2 12/18 PU CTRAP_2 TDO_0 TXD_1 TXDC1_0 P0.3 48/63 Hi-Z SCK_1 COUT63_1 RXDO1_0 Data Sheet 9 JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input UART Receive Data Input MultiCAN Node 1 Receiver Input Output of Capture/Compare channel 1 Timer 2 External Flag Output CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/Clock Output MultiCAN Node 1 Transmitter Output SSC Clock Input/Output Output of Capture/Compare channel 3 UART1 Transmit Data Output V1.2, 2009-07 XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64) State P0.4 1/64 Hi-Z MTSR_1 CC62_1 TXD1_0 P0.5 2/1 Hi-Z MRST_1 EXINT0_0 T2EX1_1 RXD1_0 COUT62_1 SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/Compare channel 2 UART1 Transmit Data Output/Clock Output SSC Master Receive Input/Slave Transmit Output External Interrupt Input 0 Timer 21 External Trigger Input UART1 Receive Data Input Output of Capture/Compare channel 2 P0.6 -/2 PU GPIO P0.7 47/62 PU CLKOUT_1 Clock Output Data Sheet 10 V1.2, 2009-07 XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64) State P1 I/O Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 1, Timer 2, Timer 21, MultiCAN and SSC. P1.0 26/34 PU RXD_0 T2EX RXDC0_0 UART Receive Data Input Timer 2 External Trigger Input MultiCAN Node 0 Receiver Input P1.1 27/35 PU EXINT3 T0_1 TDO_1 TXD_0 External Interrupt Input 3 Timer 0 Input JTAG Serial Data Output UART Transmit Data Output/Clock Output MultiCAN Node 0 Transmitter Output TXDC0_0 P1.2 28/36 PU SCK_0 SSC Clock Input/Output P1.3 29/37 PU MTSR_0 SSC Master Transmit Output/Slave Receive Input MultiCAN Node 1 Transmitter Output TXDC1_3 P1.4 P1.5 30/38 31/39 Data Sheet PU PU MRST_0 EXINT0_1 RXDC1_3 SSC Master Receive Input/ Slave Transmit Output External Interrupt Input 0 MultiCAN Node 1 Receiver Input CCPOS0_1 EXINT5 T1_1 EXF2_0 RXDO_0 CCU6 Hall Input 0 External Interrupt Input 5 Timer 1 Input Timer 2 External Flag Output UART Transmit Data Output 11 V1.2, 2009-07 XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64) State P1.6 8/10 PU CCPOS1_1 CCU6 Hall Input 1 T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6_0 External Interrupt Input 6 RXDC0_2 MultiCAN Node 0 Receiver Input T21_1 Timer 21 Input P1.7 9/11 PU CCPOS2_1 CCU6 Hall Input 2 T13HR_0 CCU6 Timer 13 Hardware Run Input T2_1 Timer 2 Input TXDC0_2 MultiCAN Node 0 Transmitter Output P1.5 and P1.6 can be used as a software chip select output for the SSC. Data Sheet 12 V1.2, 2009-07 XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64) State P2 I Port 2 Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC. P2.0 14/22 Hi-Z CCPOS0_0 CCU6 Hall Input 0 EXINT1_0 External Interrupt Input 1 T12HR_2 CCU6 Timer 12 Hardware Run Input TCK_1 JTAG Clock Input CC61_3 Input of Capture/Compare channel 1 AN0 Analog Input 0 P2.1 15/23 Hi-Z CCPOS1_0 CCU6 Hall Input 1 EXINT2_0 External Interrupt Input 2 T13HR_2 CCU6 Timer 13 Hardware Run Input TDI_1 JTAG Serial Data Input CC62_3 Input of Capture/Compare channel 2 AN1 Analog Input 1 P2.2 16/24 Hi-Z CCPOS2_0 CCU6 Hall Input 2 CTRAP_1 CCU6 Trap Input CC60_3 Input of Capture/Compare channel 0 AN2 Analog Input 2 P2.3 19/27 Hi-Z AN3 Analog Input 3 P2.4 20/28 Hi-Z AN4 Analog Input 4 P2.5 21/29 Hi-Z AN5 Analog Input 5 P2.6 22/30 Hi-Z AN6 Analog Input 6 P2.7 25/33 Hi-Z AN7 Analog Input 7 Data Sheet 13 V1.2, 2009-07 XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64) State P3 I/O Port 3 Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, UART1, Timer 21 and MultiCAN. P3.0 35/43 Hi-Z CCPOS1_2 CCU6 Hall Input 1 CC60_0 Input/Output of Capture/Compare channel 0 RXDO1_1 UART1 Transmit Data Output P3.1 36/44 Hi-Z CCPOS0_2 CCU6 Hall Input 0 CC61_2 Input/Output of Capture/Compare channel 1 COUT60_0 Output of Capture/Compare channel 0 TXD1_1 UART1 Transmit Data Output/Clock Output P3.2 37/49 Hi-Z CCPOS2_2 RXDC1_1 RXD1_1 CC61_0 CCU6 Hall Input 2 MultiCAN Node 1 Receiver Input UART1 Receive Data Input Input/Output of Capture/Compare channel 1 P3.3 38/50 Hi-Z COUT61_0 Output of Capture/Compare channel 1 MultiCAN Node 1 Transmitter Output TXDC1_1 P3.4 39/51 Hi-Z CC62_0 RXDC0_1 T2EX1_0 P3.5 40/52 Hi-Z COUT62_0 EXF21_0 TXDC0_1 P3.6 33/41 Data Sheet PD CTRAP_0 14 Input/Output of Capture/Compare channel 2 MultiCAN Node 0 Receiver Input Timer 21 External Trigger Input Output of Capture/Compare channel 2 Timer 21 External Flag Output MultiCAN Node 0 Transmitter Output CCU6 Trap Input V1.2, 2009-07 XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64) State P3.7 34/42 Data Sheet Hi-Z EXINT4 COUT63_0 15 External Interrupt Input 4 Output of Capture/Compare channel 3 V1.2, 2009-07 XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64) State P4 I/O Port 4 Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, Timer 0, Timer 1, Timer 21 and MultiCAN. P4.0 45/59 Hi-Z RXDC0_3 CC60_1 MultiCAN Node 0 Receiver Input Output of Capture/Compare channel 0 P4.1 46/60 Hi-Z TXDC0_3 MultiCAN Node 0 Transmitter Output Output of Capture/Compare channel 0 COUT60_1 P4.2 -/61 PU EXINT6_1 T21_0 External Interrupt Input 6 Timer 21 Input P4.3 32/40 Hi-Z EXF21_1 COUT63_2 Timer 21 External Flag Output Output of Capture/Compare channel 3 P4.4 -/45 Hi-Z CCPOS0_3 CCU6 Hall Input 0 T0_0 Timer 0 Input CC61_4 Output of Capture/Compare channel 1 P4.5 -/46 Hi-Z CCPOS1_3 CCU6 Hall Input 1 T1_0 Timer 1 Input COUT61_2 Output of Capture/Compare channel 1 P4.6 -/47 Hi-Z CCPOS2_3 CCU6 Hall Input 2 T2_0 Timer 2 Input CC62_2 Output of Capture/Compare channel 2 P4.7 -/48 Hi-Z CTRAP_3 COUT62_2 Data Sheet 16 CCU6 Trap Input Output of Capture/Compare channel 2 V1.2, 2009-07 XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64) State P5 I/O Port 5 Port 5 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART, UART1 and JTAG. P5.0 -/8 PU EXINT1_1 External Interrupt Input 1 P5.1 -/9 PU EXINT2_1 External Interrupt Input 2 P5.2 -/12 PU RXD_2 UART Receive Data Input P5.3 -/13 PU TXD_2 UART Transmit Data Output/Clock Output P5.4 -/14 PU RXDO_2 UART Transmit Data Output P5.5 -/15 PU TDO_2 TXD1_2 JTAG Serial Data Output UART1 Transmit Data Output/ Clock Output P5.6 -/19 PU TCK_2 RXDO1_2 JTAG Clock Input UART1 Transmit Data Output P5.7 -/20 PU TDI_2 RXD1_2 JTAG Serial Data Input UART1 Receive Data Input Data Sheet 17 V1.2, 2009-07 XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64) State VDDP 7, 17, 43/ 7, 25, 55 - - I/O Port Supply (3.3 or 5.0 V) Also used by EVR and analog modules. All pins must be connected. VSSP 18, 42/26, 54 - - I/O Port Ground All pins must be connected. VDDC VSSC VAREF VAGND 6/6 - - Core Supply Monitor (2.5 V) 5/5 - - Core Supply Ground 24/32 - - ADC Reference Voltage 23/31 - - ADC Reference Ground XTAL1 4/4 I Hi-Z External Oscillator Input (backup for on-chip OSC, normally NC) XTAL2 3/3 O Hi-Z External Oscillator Output (backup for on-chip OSC, normally NC) TMS 10/16 I PD Test Mode Select RESET 41/53 I PU Reset Input MBC1) 44/58 I PU Monitor & BootStrap Loader Control NC -/56, 57 - - No Connection 1) An external pull-up device in the range of 4.7 k to 100 k. is required to enter user mode. Alternatively MBC can be tied to high if alternate functions (for debugging) of the pin are not utilized. Data Sheet 18 V1.2, 2009-07 XC886/888CLM Functional Description 3 Functional Description Chapter 3 provides an overview of the XC886/888 functional description. 3.1 Processor Architecture The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The XC886/888 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and Special Function Registers (SFRs). Figure 6 shows the CPU functional blocks. Internal Data Memory Core SFRs Register Interface External Data Memory Program Memory fCCLK Memory Wait Reset Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt Figure 6 Data Sheet External SFRs 16-bit Registers & Memory Interface ALU Opcode & Immediate Registers Multiplier / Divider Opcode Decoder Timer 0 / Timer 1 State Machine & Power Saving UART Interrupt Controller CPU Block Diagram 19 V1.2, 2009-07 XC886/888CLM Functional Description 3.2 Memory Organization The XC886/888 CPU operates in the following five address spaces: * * * * * 12 Kbytes of Boot ROM program memory 256 bytes of internal RAM data memory 1.5 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory) A 128-byte Special Function Register area 24/32 Kbytes of Flash program memory (Flash devices); or 24/32 Kbytes of ROM program memory, with additional 4 Kbytes of Flash (ROM devices) Figure 7 illustrates the memory address spaces of the 32-Kbyte Flash devices. For the 24-Kbyte Flash devices, the shaded banks are not available. FFFFH FFFF H F600H F600H 1) XRAM 1.5 Kbytes F000H XRAM 1.5 Kbytes In 24-Kbyte Flash devices, the upper 2Kbyte of Banks 4 and 5 are not available. F000H Boot ROM 12 Kbytes C000H D-Flash Bank 1 4 Kbytes B000H D-Flash Bank 0 4 Kbytes A000H 8000H D-Flash Bank 0 4 Kbytes 7000H D-Flash Bank 1 4 Kbytes 6000H P-Flash Banks 4 and 5 2 x 4 Kbytes 1) 5000H 4000H P-Flash Banks 2 and 3 2 x 4 Kbytes Indirect Address Direct Address Internal RAM Special Function Registers FF H 80H 2000H 7FH P-Flash Banks 0 and 1 2 x 4 Kbytes Internal RAM 0000H Program Space Figure 7 0000H 00H External Data Space Internal Data Space Memory Map of XC886/888 Flash Device For both 24-Kbyte and 32-Kbyte ROM devices, the last four bytes of the ROM from 7FFCH to 7FFFH are reserved for the ROM signature and cannot be used to store user Data Sheet 20 V1.2, 2009-07 XC886/888CLM Functional Description code or data. Therefore, even though the ROM device contains either a 24-Kbyte or 32Kbyte ROM, the maximum size of code that can be placed in the ROM is the given size less four bytes. 3.2.1 Memory Protection Strategy The XC886/888 memory protection strategy includes: * * Read-out protection: The user is able to protect the contents in the Flash (for Flash devices) and ROM (for ROM devices) memory from being read - Flash protection is enabled by programming a valid password (8-bit non-zero value) via BSL mode 6. - ROM protection is fixed with the ROM mask and is always enabled. Flash program and erase protection: This feature is available only for Flash devices. 3.2.1.1 Flash Memory Protection As long as a valid password is available, all external access to the device, including the Flash, will be blocked. For additional security, the Flash hardware protection can be enabled to implement a second layer of read-out protection, as well as to enable program and erase protection. Flash hardware protection is available only for Flash devices and comes in two modes: * * Mode 0: Only the P-Flash is protected; the D-Flash is unprotected Mode 1: Both the P-Flash and D-Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 4. Table 4 Flash Protection Modes Flash Protection Without hardware protection With hardware protection Hardware Protection Mode 0 1 Activation Program a valid password via BSL mode 6 Selection Bit 4 of password = 0 Bit 4 of password = 1 Bit 4 of password = 1 MSB of password = 0 MSB of password = 1 P-Flash Read instructions in Read instructions in contents can be any program memory the P-Flash read by Read instructions in the P-Flash or DFlash External access to P-Flash Not possible Data Sheet Not possible Not possible 21 V1.2, 2009-07 XC886/888CLM Functional Description Table 4 Flash Protection Modes (cont'd) Flash Protection Without hardware protection With hardware protection P-Flash program Possible and erase Not possible Not possible D-Flash Read instructions in Read instructions in Read instructions in contents can be any program memory any program memory the P-Flash or Dread by Flash External access to D-Flash Not possible Not possible Not possible D-Flash program Possible Possible Not possible D-Flash erase Possible Possible, on Not possible condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. A password match triggers an automatic erase of the protected P-Flash and D-Flash contents, including the programmed password. The Flash protection is then disabled upon the next reset. For the ROM device, the ROM is protected at all times and BSL mode 6 is used only to block external access to the device. However, unlike the Flash device, it is not possible to disable the memory protection of the ROM device. Here, entering BSL mode 6 will result in a protection error. Note: If ROM read-out protection is enabled, only read instructions in the ROM memory can target the ROM contents. Although no protection scheme can be considered infallible, the XC886/888 memory protection strategy provides a very high level of protection for a general purpose microcontroller. Data Sheet 22 V1.2, 2009-07 XC886/888CLM Functional Description 3.2.2 Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include: * * Mapping Paging 3.2.2.1 Address Extension by Mapping Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 8. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software. Data Sheet 23 V1.2, 2009-07 XC886/888CLM Functional Description Standard Area (RMAP = 0) FF H Module 1 SFRs SYSCON0.RMAP Module 2 SFRs rw ...... Module n SFRs 80 H SFR Data (to/from CPU) Mapped Area (RMAP = 1) FF H Module (n+1) SFRs Module (n+2) SFRs ...... Module m SFRs 80 H Direct Internal Data Memory Address Figure 8 Data Sheet Address Extension by Mapping 24 V1.2, 2009-07 XC886/888CLM Functional Description SYSCON0 System Control Register 0 7 6 5 Reset Value: 04H 4 3 2 1 0 0 IMODE 0 1 0 RMAP r rw r r r rw Field Bits Type Description RMAP 0 rw Interrupt Node XINTR0 Enable 0 The access to the standard SFR area is enabled 1 The access to the mapped SFR area is enabled 1 2 r Reserved Returns 1 if read; should be written with 1. 0 [7:5], 3,1 r Reserved Returns 0 if read; should be written with 0. Note: The RMAP bit should be cleared/set by ANL or ORL instructions. 3.2.2.2 Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the XC886/888 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 9. Data Sheet 25 V1.2, 2009-07 XC886/888CLM Functional Description SFR Address (from CPU) PAGE 0 MOD_PAGE.PAGE SFR0 rw SFR1 ...... SFRx PAGE 1 SFR0 SFR Data (to/from CPU) SFR1 ...... SFRy ...... PAGE q SFR0 SFR1 ...... SFRz Module Figure 9 Address Extension by Paging In order to access a register located in a page different from the actual one, the current page must be exited. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can: * Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or Data Sheet 26 V1.2, 2009-07 XC886/888CLM Functional Description * Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred) ST3 ST2 ST1 ST0 STNR PAGE value update from CPU Figure 10 Storage Elements for Paging With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The XC886/888 supports local address extension for: * * * * Parallel Ports Analog-to-Digital Converter (ADC) Capture/Compare Unit 6 (CCU6) System Control Registers Data Sheet 27 V1.2, 2009-07 XC886/888CLM Functional Description The page register has the following definition: MOD_PAGE Page Register for module MOD 7 6 Reset Value: 00H 5 4 3 2 1 OP STNR 0 PAGE w w r rw 0 Field Bits Type Description PAGE [2:0] rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 Data Sheet ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected. 28 V1.2, 2009-07 XC886/888CLM Functional Description Field Bits Type Description OP [7:6] w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. 0 3 r Reserved Returns 0 if read; should be written with 0. 3.2.3 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. In both cases, the value of the bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can only be changed when bit field PASS is written with 11000B, for example, writing D0H to PASSWD register disables the bit protection scheme. Note that access is opened for maximum 32 CCLKs if the "close access" password is not written. If "open access" password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include the N- and KDivider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the powerdown and slow-down enable bits, PD and SD. Data Sheet 29 V1.2, 2009-07 XC886/888CLM Functional Description 3.2.3.1 Password Register PASSWD Password Register 7 6 Reset Value: 07H 5 4 3 2 1 0 PASS PROTECT _S MODE wh rh rw Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control Bits 00 Scheme disabled - direct access to the protected bits is allowed. 11 Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to protected bits. (default) Others:Scheme Enabled. These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B; only then, will the MODE[1:0] be registered. PROTECT_S 2 rh Bit Protection Signal Status Bit This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected bits. PASS [7:3] wh Password Bits The Bit Protection Scheme only recognizes three patterns. 11000B Enables writing of the bit field MODE. 10011B Opens access to writing of all protected bits. 10101B Closes access to writing of all protected bits Data Sheet 30 V1.2, 2009-07 XC886/888CLM Functional Description 3.2.4 XC886/888 Register Overview The SFRs of the XC886/888 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.14. Note: The addresses of the bitaddressable SFRs appear in bold typeface. 3.2.4.1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1). Table 5 CPU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 or 1 81H SP Reset: 07H Stack Pointer Register Bit Field 82H DPL Reset: 00H Data Pointer Register Low Bit Field DPH Reset: 00H Data Pointer Register High Bit Field PCON Reset: 00H Power Control Register Bit Field TCON Reset: 00H Timer Control Register Bit Field TF1 TR1 TF0 Type rwh rw rwh TMOD Reset: 00H Timer Mode Register Bit Field GATE 1 T1S rw rw 83H 87H 88H 89H Type Type Type Type Type 8AH 8BH 8CH 8DH 98H 99H A2H SP rw DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 rw rw rw rw rw rw rw rw DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 rw rw rw rw rw rw rw rw SMOD 0 GF1 GF0 0 IDLE rw r rw rw r rw TR0 IE1 IT1 IE0 IT0 rw rwh rw rwh rw T1M GATE 0 T0S T0M rw rw rw rw TL0 Reset: 00H Timer 0 Register Low Bit Field VAL Type rwh TL1 Reset: 00H Timer 1 Register Low Bit Field VAL Type rwh TH0 Reset: 00H Timer 0 Register High Bit Field VAL Type rwh TH1 Reset: 00H Timer 1 Register High Bit Field VAL Type rwh SCON Reset: 00H Serial Channel Control Register Bit Field SBUF Reset: 00H Serial Data Buffer Register Bit Field VAL Type rwh EO Reset: 00H Extended Operation Register Bit Field 0 TRAP_ EN 0 DPSE L0 Type r rw r rw Data Sheet Type SM0 SM1 SM2 REN TB8 RB8 TI RI rw rw rw rw rw rwh rwh rwh 31 V1.2, 2009-07 XC886/888CLM Functional Description Table 5 CPU Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 0 A8H IEN0 Reset: 00H Interrupt Enable Register 0 Bit Field EA 0 ET2 ES ET1 EX1 ET0 EX0 Type rw r rw rw rw rw rw rw IP Reset: 00H Interrupt Priority Register Bit Field 0 PT2 PS PT1 PX1 PT0 PX0 Type r rw rw rw rw rw rw IPH Reset: 00H Interrupt Priority High Register Bit Field 0 PT2H PSH PT1H PX1H PT0H PX0H Type r rw rw rw rw rw rw B8H B9H D0H E0H E8H F0H F8H PSW Reset: 00H Program Status Word Register Bit Field CY AC F0 RS1 RS0 OV F1 P Type rwh rwh rw rw rw rwh rw rh ACC Reset: 00H Accumulator Register Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 rw rw rw rw rw rw rw rw IEN1 Reset: 00H Interrupt Enable Register 1 Bit Field ECCIP 3 ECCIP 2 ECCIP 1 ECCIP 0 EXM EX2 ESSC EADC Type rw rw rw rw rw rw rw rw Bit Field B7 B6 B5 B4 B3 B2 B1 B0 Type rw rw rw rw rw rw rw rw PCCIP 3 PCCIP 2 PCCIP 1 PCCIP 0 PXM PX2 PSSC PADC rw rw rw rw rw rw rw rw PCCIP 3H PCCIP 2H PCCIP 1H PCCIP 0H PXMH PX2H PSSC H PADC H rw rw rw rw rw rw rw rw 2 1 0 B B Register Reset: 00H IP1 Reset: 00H Interrupt Priority 1 Register Type Bit Field Type F9H IPH1 Reset: 00H Bit Field Interrupt Priority 1 High Register Type 3.2.4.2 MDU Registers The MDU SFRs can be accessed in the mapped memory area (RMAP = 1). Table 6 MDU Register Overview Addr Register Name Bit 7 6 5 4 3 RMAP = 1 B0H B1H B2H B2H B3H MDUSTAT Reset: 00H MDU Status Register Bit Field 0 BSY IERR IRDY Type r rh rwh rwh MDUCON Reset: 00H MDU Control Register Bit Field IE IR RSEL STAR T OPCODE Type rw rw rw rwh rw MD0 Reset: 00H MDU Operand Register 0 Bit Field MR0 Reset: 00H MDU Result Register 0 Bit Field MD1 Reset: 00H MDU Operand Register 1 Bit Field Data Sheet DATA Type rw DATA Type rh DATA Type rw 32 V1.2, 2009-07 XC886/888CLM Functional Description Table 6 MDU Register Overview (cont'd) Addr Register Name Bit B3H MR1 Reset: 00H MDU Result Register 1 Bit Field MD2 Reset: 00H MDU Operand Register 2 Bit Field MR2 Reset: 00H MDU Result Register 2 Bit Field MD3 Reset: 00H MDU Operand Register 3 Bit Field MR3 Reset: 00H MDU Result Register 3 Bit Field MD4 Reset: 00H MDU Operand Register 4 Bit Field MR4 Reset: 00H MDU Result Register 4 Bit Field MD5 Reset: 00H MDU Operand Register 5 Bit Field MR5 Reset: 00H MDU Result Register 5 Bit Field B4H B4H B5H B5H B6H B6H B7H B7H 3.2.4.3 7 6 5 4 3 2 1 0 DATA Type rh DATA Type rw DATA Type rh DATA Type rw DATA Type rh DATA Type rw DATA Type rh DATA Type rw DATA Type rh CORDIC Registers The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1). Table 7 CORDIC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 9AH 9BH 9CH 9DH 9EH 9FH CD_CORDXL Reset: 00H CORDIC X Data Low Byte Bit Field CD_CORDXH Reset: 00H CORDIC X Data High Byte Bit Field CD_CORDYL Reset: 00H CORDIC Y Data Low Byte Bit Field CD_CORDYH Reset: 00H CORDIC Y Data High Byte Bit Field CD_CORDZL Reset: 00H CORDIC Z Data Low Byte Bit Field CD_CORDZH Reset: 00H CORDIC Z Data High Byte Bit Field Data Sheet DATAL Type rw DATAH Type rw DATAL Type rw DATAH Type rw DATAL Type rw DATAH Type rw 33 V1.2, 2009-07 XC886/888CLM Functional Description Table 7 CORDIC Register Overview (cont'd) Addr Register Name Bit A0H CD_STATC Reset: 00H CORDIC Status and Data Control Register Bit Field CD_CON Reset: 00H CORDIC Control Register Bit Field A1H Type 7 6 5 4 3 2 1 0 KEEP Z KEEP Y KEEP X DMAP INT_E N EOC ERRO R BSY rw rw rw rw rw rwh rh rh MPS X_USI GN ST_M ODE ROTV EC MODE ST rw rw rw rw rw rwh Type 3.2.4.4 System Control Registers The system control SFRs can be accessed in the mapped memory area (RMAP = 0). Table 8 SCU Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 or 1 8FH SYSCON0 Reset: 04H System Control Register 0 Bit Field 0 IMOD E 0 1 0 RMAP Type r rw r r r rw RMAP = 0 BFH SCU_PAGE Page Register Reset: 00H Bit Field Type OP STNR 0 PAGE w w r rw RMAP = 0, PAGE 0 B3H B4H B5H B6H B7H BAH BBH MODPISEL Reset: 00H Peripheral Input Select Register IRCON0 Reset: 00H Interrupt Request Register 0 IRCON1 Reset: 00H Interrupt Request Register 1 IRCON2 Reset: 00H Interrupt Request Register 2 Bit Field 0 URRIS H JTAGT DIS JTAGT CKS EXINT 2IS EXINT 1IS EXINT 0IS URRIS Type r rw rw rw rw rw rw rw Bit Field 0 EXINT 6 EXINT 5 EXINT 4 EXINT 3 EXINT 2 EXINT 1 EXINT 0 Type r rwh rwh rwh rwh rwh rwh rwh Bit Field 0 CANS RC2 CANS RC1 ADCS R1 ADCS R0 RIR TIR EIR Type r rwh rwh rwh rwh rwh rwh rwh Bit Field 0 CANS RC3 0 CANS RC0 Type r rwh r rwh EXICON0 Reset: F0H External Interrupt Control Register 0 Bit Field EXINT3 EXINT2 EXINT1 EXINT0 Type rw rw rw rw EXICON1 Reset: 3FH External Interrupt Control Register 1 Bit Field 0 EXINT6 EXINT5 EXINT4 Type r rw rw rw NMICON Reset: 00H NMI Control Register Bit Field 0 NMI ECC NMI VDDP NMI VDD NMI OCDS NMI FLASH NMI PLL NMI WDT Type r rw rw rw rw rw rw rw Data Sheet 34 V1.2, 2009-07 XC886/888CLM Functional Description Table 8 SCU Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 0 BCH Bit Field 0 FNMI ECC FNMI VDDP FNMI VDD FNMI OCDS FNMI FLASH FNMI PLL FNMI WDT Type r rwh rwh rwh rwh rwh rwh rwh BGSEL 0 BRDIS BRPRE R rw r rw rw rw NMISR Reset: 00H NMI Status Register BCON Reset: 00H Baud Rate Control Register Bit Field BG Reset: 00H Baud Rate Timer/Reload Register Bit Field E9H FDCON Reset: 00H Fractional Divider Control Register Bit Field EAH FDSTEP Reset: 00H Fractional Divider Reload Register Bit Field FDRES Reset: 00H Fractional Divider Result Register Bit Field BDH BEH EBH Type BR_VALUE Type Type rwh BGS SYNE N ERRS YN EOFS YN BRK NDOV FDM FDEN rw rw rwh rwh rwh rwh rw rw STEP Type rw RESULT Type rh RMAP = 0, PAGE 1 B3H B4H B5H B6H B7H ID Identity Register Reset: UUH PMCON0 Reset: 00H Power Mode Control Register 0 PMCON1 Reset: 00H Power Mode Control Register 1 OSC_CON Reset: 08H OSC Control Register PLL_CON Reset: 90H PLL Control Register Bit Field CMCON Reset: 10H Clock Control Register PASSWD Reset: 07H Password Register BDH WDT RST WKRS WK SEL SD PD WS Type r rwh rwh rw rw rwh rw Bit Field 0 CDC_ DIS CAN_ DIS MDU_ DIS T2_ DIS CCU_ DIS SSC_ DIS ADC_ DIS Type r rw rw rw rw rw rw rw Bit Field 0 OSC PD XPD OSC SS ORD RES OSCR Type r rw rw rw rwh rh NDIV VCO BYP OSC DISC RESL D LOCK rw rw rw rwh rh Bit Field Bit Field VCO SEL KDIV 0 FCCF G CLKREL rw rw r rw rw Bit Field FEAL Reset: 00H Flash Error Address Register Low Bit Field FEAH Reset: 00H Flash Error Address Register High Bit Field Data Sheet r 0 Type BCH r Bit Field Type BBH VERID Type Type BAH PRODID PASS PROT ECT_S MODE wh rh rw ECCERRADDR Type rh ECCERRADDR Type rh 35 V1.2, 2009-07 XC886/888CLM Functional Description Table 8 SCU Register Overview (cont'd) Addr Register Name Bit BEH Bit Field Type E9H COCON Reset: 00H Clock Output Control Register MISC_CON Reset: 00H Miscellaneous Control Register 7 6 5 4 3 2 1 0 TLEN COUT S COREL r rw rw rw 0 Bit Field 0 DFLAS HEN Type r rwh RMAP = 0, PAGE 3 B3H B4H B5H B7H BAH BBH BDH XADDRH Reset: F0H On-chip XRAM Address Higher Order Bit Field IRCON3 Reset: 00H Interrupt Request Register 3 Bit Field 0 CANS RC5 CCU6 SR1 0 CANS RC4 CCU6 SR0 Type r rwh rwh r rwh rwh Bit Field 0 CANS RC7 CCU6 SR3 0 CANS RC6 CCU6 SR2 Type r rwh rwh r rwh rwh IRCON4 Reset: 00H Interrupt Request Register 4 MODPISEL1 Reset: 00H Peripheral Input Select Register 1 MODPISEL2 Reset: 00H Peripheral Input Select Register 2 PMCON2 Reset: 00H Power Mode Control Register 2 MODSUSP Reset: 01H Module Suspend Control Register 3.2.4.5 ADDRH Type Bit Field Type rw EXINT 6IS 0 UR1RIS T21EX IS JTAGT DIS1 JTAGT CKS1 rw r rw rw rw rw Bit Field 0 T21IS T2IS T1IS T0IS Type r rw rw rw rw Bit Field 0 UART 1_DIS T21_D IS Type r rw rw Bit Field 0 T21SU SP T2SUS P T13SU SP T12SU SP WDTS USP Type r rw rw rw rw rw WDT Registers The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). Table 9 WDT Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 1 BBH BCH BDH WDTCON Reset: 00H Watchdog Timer Control Register Bit Field 0 WINB EN WDTP R 0 WDTE N WDTR S WDTI N Type r rw rh r rw rwh rw WDTREL Reset: 00H Watchdog Timer Reload Register Bit Field WDTWINB Reset: 00H Watchdog Window-Boundary Count Register Bit Field Data Sheet WDTREL Type rw WDTWINB Type rw 36 V1.2, 2009-07 XC886/888CLM Functional Description Table 9 WDT Register Overview (cont'd) Addr Register Name Bit BEH WDTL Reset: 00H Watchdog Timer Register Low Bit Field WDTH Reset: 00H Watchdog Timer Register High Bit Field BFH 3.2.4.6 7 6 5 4 3 2 1 0 1 0 WDT Type rh WDT Type rh Port Registers The Port SFRs can be accessed in the standard memory area (RMAP = 0). Table 10 Port Register Overview Addr Register Name Bit 7 6 5 4 3 2 RMAP = 0 B2H PORT_PAGE Page Register Reset: 00H Bit Field Type OP STNR 0 PAGE w w r rw RMAP = 0, PAGE 0 P0_DATA Reset: 00H P0 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_DIR Reset: 00H P0 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_DATA Reset: 00H P1 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_DIR Reset: 00H P1 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_DATA Reset: 00H P5 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_DIR Reset: 00H P5 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P2_DATA Reset: 00H P2 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw A1H P2_DIR Reset: 00H P2 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_DATA Reset: 00H P3 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_DIR Reset: 00H P3 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_DATA Reset: 00H P4 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_DIR Reset: 00H P4 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 80H 86H 90H 91H 92H 93H A0H B1H C8H C9H Data Sheet 37 V1.2, 2009-07 XC886/888CLM Functional Description Table 10 Port Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 0 P0_PUDSEL Reset: FFH P0 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_PUDEN Reset: C4H P0 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_PUDSEL Reset: FFH P1 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_PUDEN Reset: FFH P1 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_PUDSEL Reset: FFH P5 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_PUDEN Reset: FFH P5 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P2_PUDSEL Reset: FFH P2 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P2_PUDEN Reset: 00H P2 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_PUDSEL Reset: BFH P3 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_PUDEN Reset: 40H P3 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_PUDSEL Reset: FFH P4 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_PUDEN Reset: 04H P4 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_ALTSEL0 Reset: 00H P0 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P0_ALTSEL1 Reset: 00H P0 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_ALTSEL0 Reset: 00H P1 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P1_ALTSEL1 Reset: 00H P1 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_ALTSEL0 Reset: 00H P5 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw RMAP = 0, PAGE 1 80H 86H 90H 91H 92H 93H A0H A1H B0H B1H C8H C9H RMAP = 0, PAGE 2 80H 86H 90H 91H 92H Data Sheet 38 V1.2, 2009-07 XC886/888CLM Functional Description Table 10 Port Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 0 93H P5_ALTSEL1 Reset: 00H P5 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_ALTSEL0 Reset: 00H P3 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_ALTSEL1 Reset: 00H P3 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_ALTSEL0 Reset: 00H P4 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_ALTSEL1 Reset: 00H P4 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P7 P6 P5 P4 P3 P2 P1 P0 B0H B1H C8H C9H RMAP = 0, PAGE 3 80H P0_OD Reset: 00H P0 Open Drain Control Register Bit Field Type rw rw rw rw rw rw rw rw 90H P1_OD Reset: 00H P1 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P5_OD Reset: 00H P5 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P3_OD Reset: 00H P3 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw P4_OD Reset: 00H P4 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 1 0 92H B0H C8H 3.2.4.7 ADC Registers The ADC SFRs can be accessed in the standard memory area (RMAP = 0). Table 11 ADC Register Overview Addr Register Name Bit 7 6 5 4 3 2 RMAP = 0 D1H ADC_PAGE Page Register Reset: 00H Bit Field OP STNR 0 PAGE w w r rw Type RMAP = 0, PAGE 0 CAH CBH CCH ADC_GLOBCTR Reset: 30H Global Control Register Bit Field ADC_GLOBSTR Reset: 00H Global Status Register Bit Field 0 CHNR 0 SAMP LE BUSY Type r rh r rh rh ADC_PRAR Reset: 00H Priority and Arbitration Register Type Bit Field Type Data Sheet ANON DW CTC 0 rw rw rw r ASEN 1 ASEN 0 0 ARBM CSM1 PRIO1 CSM0 PRIO0 rw rw r rw rw rw rw rw 39 V1.2, 2009-07 XC886/888CLM Functional Description Table 11 ADC Register Overview (cont'd) Addr Register Name CDH CEH ADC_LCBR Reset: B7H Limit Check Boundary Register Bit 7 6 Bit Field Bit Field ADC_ETRCR Reset: 00H External Trigger Control Register Bit Field 4 3 2 1 BOUND1 BOUND0 rw rw Type ADC_INPCR0 Reset: 00H Input Class 0 Register 5 0 STC Type rw SYNE N1 SYNE N0 ETRSEL1 ETRSEL0 Type rw rw rw rw ADC_CHCTR0 Reset: 00H Channel Control Register 0 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR1 Reset: 00H Channel Control Register 1 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR2 Reset: 00H Channel Control Register 2 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR3 Reset: 00H Channel Control Register 3 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CEH ADC_CHCTR4 Reset: 00H Channel Control Register 4 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CFH ADC_CHCTR5 Reset: 00H Channel Control Register 5 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR6 Reset: 00H Channel Control Register 6 Bit Field 0 LCC 0 RESRSEL Type r rw r rw ADC_CHCTR7 Reset: 00H Channel Control Register 7 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CFH RMAP = 0, PAGE 1 CAH CBH CCH CDH D2H D3H RMAP = 0, PAGE 2 CAH ADC_RESR0L Reset: 00H Result Register 0 Low Bit Field CBH ADC_RESR0H Reset: 00H Result Register 0 High Bit Field CCH ADC_RESR1L Reset: 00H Result Register 1 Low Bit Field ADC_RESR1H Reset: 00H Result Register 1 High Bit Field ADC_RESR2L Reset: 00H Result Register 2 Low Bit Field ADC_RESR2H Reset: 00H Result Register 2 High Bit Field ADC_RESR3L Reset: 00H Result Register 3 Low Bit Field CDH CEH CFH D2H Data Sheet Type RESULT 0 VF DRC CHNR rh r rh rh rh RESULT Type Type rh RESULT 0 VF DRC CHNR rh r rh rh rh RESULT Type Type rh RESULT 0 VF DRC CHNR rh r rh rh rh RESULT Type Type rh RESULT 0 VF DRC CHNR rh r rh rh rh 40 V1.2, 2009-07 XC886/888CLM Functional Description Table 11 ADC Register Overview (cont'd) Addr Register Name Bit D3H Bit Field ADC_RESR3H Reset: 00H Result Register 3 High 7 6 5 4 3 2 1 0 RESULT Type rh RMAP = 0, PAGE 3 ADC_RESRA0L Reset: 00H Result Register 0, View A Low Bit Field ADC_RESRA0H Reset: 00H Result Register 0, View A High Bit Field ADC_RESRA1L Reset: 00H Result Register 1, View A Low Bit Field ADC_RESRA1H Reset: 00H Result Register 1, View A High Bit Field CEH ADC_RESRA2L Reset: 00H Result Register 2, View A Low Bit Field CFH ADC_RESRA2H Reset: 00H Result Register 2, View A High Bit Field ADC_RESRA3L Reset: 00H Result Register 3, View A Low Bit Field ADC_RESRA3H Reset: 00H Result Register 3, View A High Bit Field CAH CBH CCH CDH D2H D3H RESULT VF DRC CHNR rh rh rh rh Type RESULT Type rh RESULT VF DRC CHNR rh rh rh rh Type RESULT Type rh RESULT VF DRC CHNR rh rh rh rh Type RESULT Type rh RESULT VF DRC CHNR rh rh rh rh Type RESULT Type rh RMAP = 0, PAGE 4 CAH ADC_RCR0 Reset: 00H Result Control Register 0 Bit Field Type CBH ADC_RCR1 Reset: 00H Result Control Register 1 Bit Field Type CCH ADC_RCR2 Reset: 00H Result Control Register 2 Bit Field Type CDH ADC_RCR3 Reset: 00H Result Control Register 3 Bit Field Type CEH ADC_VFCR Reset: 00H Valid Flag Clear Register VFCT R WFR 0 IEN 0 DRCT R rw rw r rw r rw VFCT R WFR 0 IEN 0 DRCT R rw rw r rw r rw VFCT R WFR 0 IEN 0 DRCT R rw rw r rw r rw VFCT R WFR 0 IEN 0 DRCT R rw rw r rw r rw Bit Field 0 VFC3 VFC2 VFC1 VFC0 Type r w w w w RMAP = 0, PAGE 5 CAH ADC_CHINFR Reset: 00H Channel Interrupt Flag Register Bit Field Type CBH ADC_CHINCR Reset: 00H Channel Interrupt Clear Register Bit Field Type Data Sheet CHINF 7 CHINF 6 CHINF 5 CHINF 4 CHINF 3 CHINF 2 CHINF 1 CHINF 0 rh rh rh rh rh rh rh rh CHINC 7 CHINC 6 CHINC 5 CHINC 4 CHINC 3 CHINC 2 CHINC 1 CHINC 0 w w w w w w w w 41 V1.2, 2009-07 XC886/888CLM Functional Description Table 11 ADC Register Overview (cont'd) Addr Register Name Bit CCH Bit Field ADC_CHINSR Reset: 00H Channel Interrupt Set Register Type CDH CEH ADC_CHINPR Reset: 00H Channel Interrupt Node Pointer Register Bit Field ADC_EVINFR Reset: 00H Event Interrupt Flag Register Bit Field Type Type CFH D2H ADC_EVINCR Reset: 00H Event Interrupt Clear Flag Register Bit Field Type Bit Field ADC_EVINSR Reset: 00H Event Interrupt Set Flag Register Type D3H ADC_EVINPR Reset: 00H Event Interrupt Node Pointer Register Bit Field Type 7 6 5 4 3 2 1 0 CHINS 7 CHINS 6 CHINS 5 CHINS 4 CHINS 3 CHINS 2 CHINS 1 CHINS 0 w w w w w w w w CHINP 7 CHINP 6 CHINP 5 CHINP 4 CHINP 3 CHINP 2 CHINP 1 CHINP 0 rw rw rw rw rw rw rw rw EVINF 7 EVINF 6 EVINF 5 EVINF 4 0 EVINF 1 EVINF 0 rh rh rh rh r rh rh EVINC 7 EVINC 6 EVINC 5 EVINC 4 0 EVINC 1 EVINC 0 w w w w r w w EVINS 7 EVINS 6 EVINS 5 EVINS 4 0 EVINS 1 EVINS 0 w w w w r w w EVINP 7 EVINP 6 EVINP 5 EVINP 4 0 EVINP 1 EVINP 0 rw rw rw rw r rw rw RMAP = 0, PAGE 6 ADC_CRCR1 Reset: 00H Conversion Request Control Register 1 Bit Field CH7 CH6 CH5 CH4 0 Type rwh rwh rwh rwh r ADC_CRPR1 Reset: 00H Conversion Request Pending Register 1 Bit Field CHP7 CHP6 CHP5 CHP4 0 Type rwh rwh rwh rwh r ADC_CRMR1 Reset: 00H Conversion Request Mode Register 1 Bit Field Rsv LDEV CLRP ND SCAN ENSI ENTR 0 ENGT r w w rw rw rw r rw CDH ADC_QMR0 Reset: 00H Queue Mode Register 0 Bit Field CEV TREV FLUS H CLRV 0 ENTR 0 ENGT r rw r CEH ADC_QSR0 Reset: 20H Queue Status Register 0 Bit Field CAH CBH CCH Type Type Type CFH ADC_Q0R0 Reset: 00H Queue 0 Register 0 Bit Field D2H ADC_QBUR0 Reset: 00H Queue Backup Register 0 Bit Field ADC_QINR0 Reset: 00H Queue Input Register 0 Bit Field D2H Data Sheet Type Type Type w w w w Rsv 0 EMPT Y EV 0 FILL r r rh rh r rh EXTR ENSI RF V 0 rw REQCHNR rh rh rh rh r rh EXTR ENSI RF V 0 REQCHNR rh rh rh rh r rh EXTR ENSI RF 0 REQCHNR w w w r w 42 V1.2, 2009-07 XC886/888CLM Functional Description 3.2.4.8 Timer 2 Registers The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). Table 12 T2 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 Bit Field TF2 EXF2 0 EXEN 2 TR2 C/T2 CP/ RL2 Type rwh rwh r rw rwh rw rw T2RE GS T2RH EN EDGE SEL PREN rw rw rw rw RMAP = 0 C0H C1H T2_T2CON Reset: 00H Timer 2 Control Register T2_T2MOD Reset: 00H Timer 2 Mode Register Bit Field Type C2H C3H C4H C5H T2PRE rw T2_RC2L Reset: 00H Timer 2 Reload/Capture Register Low Bit Field RC2 Type rwh T2_RC2H Reset: 00H Timer 2 Reload/Capture Register High Bit Field RC2 Type rwh T2_T2L Reset: 00H Timer 2 Register Low Bit Field T2_T2H Reset: 00H Timer 2 Register High Bit Field 3.2.4.9 rw DCEN rw rw THL2 Type rwh THL2 Type rwh Timer 21 Registers The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 13 T21 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 Bit Field TF2 EXF2 0 EXEN 2 TR2 C/T2 CP/ RL2 Type rwh rwh r rw rwh rw rw T2RE GS T2RH EN EDGE SEL PREN rw rw rw rw RMAP = 1 C0H C1H T21_T2CON Reset: 00H Timer 2 Control Register T21_T2MOD Reset: 00H Timer 2 Mode Register Bit Field Type C2H C3H C4H rw T21_RC2L Reset: 00H Timer 2 Reload/Capture Register Low Bit Field RC2 Type rwh T21_RC2H Reset: 00H Timer 2 Reload/Capture Register High Bit Field RC2 Type rwh T21_T2L Reset: 00H Timer 2 Register Low Bit Field Data Sheet T2PRE rw DCEN rw rw THL2 Type rwh 43 V1.2, 2009-07 XC886/888CLM Functional Description Table 13 T21 Register Overview (cont'd) Addr Register Name Bit C5H Bit Field T21_T2H Reset: 00H Timer 2 Register High 7 6 5 4 3 2 1 0 THL2 Type rwh 3.2.4.10 CCU6 Registers The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 14 CCU6 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 A3H CCU6_PAGE Page Register Reset: 00H Bit Field OP STNR 0 PAGE w w r rw Type RMAP = 0, PAGE 0 9AH 9BH 9CH CCU6_CC63SRL Reset: 00H Capture/Compare Shadow Register for Channel CC63 Low Bit Field CCU6_CC63SRH Reset: 00H Capture/Compare Shadow Register for Channel CC63 High Bit Field CCU6_TCTR4L Reset: 00H Timer Control Register 4 Low Bit Field Type CCU6_TCTR4H Reset: 00H Timer Control Register 4 High Bit Field Type 9EH 9FH A4H A5H A6H A7H rw CC63SH Type Type 9DH CC63SL rw T12 STD T12 STR 0 DT RES T12 RES T12R S T12R R w w r w w w w T13 STD T13 STR 0 T13 RES T13R S T13R R w w r w w w STRM CM 0 MCMPS w r rw STRH P 0 CURHS EXPHS w r rw rw RT12 PM RT12 OM RCC6 2F RCC6 2R RCC6 1F RCC6 1R RCC6 0F RCC6 0R w w w w w w w w RSTR RIDLE RWH E RCHE 0 RTRP F RT13 PM RT13 CM w w r w w w CCU6_MCMOUTSL Reset: 00H Multi-Channel Mode Output Shadow Register Low Bit Field CCU6_MCMOUTSH Reset: 00H Multi-Channel Mode Output Shadow Register High Bit Field CCU6_ISRL Reset: 00H Capture/Compare Interrupt Status Reset Register Low Bit Field CCU6_ISRH Reset: 00H Capture/Compare Interrupt Status Reset Register High Bit Field Type w w CCU6_CMPMODIFL Reset: 00H Compare State Modification Register Low Bit Field 0 MCC6 3S 0 MCC6 2S MCC6 1S MCC6 0S Type r w r w w w CCU6_CMPMODIFH Reset: 00H Compare State Modification Register High Bit Field 0 MCC6 3R 0 MCC6 2R MCC6 1R MCC6 0R Type r w r w w w Data Sheet Type Type Type 44 V1.2, 2009-07 XC886/888CLM Functional Description Table 14 CCU6 Register Overview (cont'd) Addr Register Name Bit FAH CCU6_CC60SRL Reset: 00H Capture/Compare Shadow Register for Channel CC60 Low Bit Field CCU6_CC60SRH Reset: 00H Capture/Compare Shadow Register for Channel CC60 High Bit Field CCU6_CC61SRL Reset: 00H Capture/Compare Shadow Register for Channel CC61 Low Bit Field CCU6_CC61SRH Reset: 00H Capture/Compare Shadow Register for Channel CC61 High Bit Field CCU6_CC62SRL Reset: 00H Capture/Compare Shadow Register for Channel CC62 Low Bit Field CCU6_CC62SRH Reset: 00H Capture/Compare Shadow Register for Channel CC62 High Bit Field FBH FCH FDH FEH FFH 7 6 5 4 3 2 1 0 CC60SL Type rwh CC60SH Type rwh CC61SL Type rwh CC61SH Type rwh CC62SL Type rwh CC62SH Type rwh RMAP = 0, PAGE 1 CCU6_CC63RL Reset: 00H Capture/Compare Register for Channel CC63 Low Bit Field CCU6_CC63RH Reset: 00H Capture/Compare Register for Channel CC63 High Bit Field CCU6_T12PRL Reset: 00H Timer T12 Period Register Low Bit Field 9DH CCU6_T12PRH Reset: 00H Timer T12 Period Register High Bit Field 9EH CCU6_T13PRL Reset: 00H Timer T13 Period Register Low Bit Field CCU6_T13PRH Reset: 00H Timer T13 Period Register High Bit Field Type rwh CCU6_T12DTCL Reset: 00H Dead-Time Control Register for Timer T12 Low Bit Field DTM CCU6_T12DTCH Reset: 00H Dead-Time Control Register for Timer T12 High Bit Field 0 DTR2 DTR1 DTR0 0 DTE2 DTE1 DTE0 Type r rh rh rh r rw rw rw CCU6_TCTR0L Reset: 00H Timer Control Register 0 Low Bit Field CTM CDIR STE1 2 T12R T12 PRE T12CLK rw rh rh rh rw rw 9AH 9BH 9CH 9FH A4H A5H A6H FAH CCU6_TCTR0H Reset: 00H Timer Control Register 0 High CCU6_CC60RL Reset: 00H Capture/Compare Register for Channel CC60 Low Data Sheet rh CC63VH Type rh T12PVL Type rwh T12PVH Type rwh T13PVL Type rwh T13PVH Type Type A7H CC63VL Type rw Bit Field 0 STE1 3 T13R T13 PRE T13CLK Type r rh rh rw rw CC60VL Bit Field Type rh 45 V1.2, 2009-07 XC886/888CLM Functional Description Table 14 CCU6 Register Overview (cont'd) Addr Register Name Bit FBH CCU6_CC60RH Reset: 00H Capture/Compare Register for Channel CC60 High Bit Field CCU6_CC61RL Reset: 00H Capture/Compare Register for Channel CC61 Low Bit Field CCU6_CC61RH Reset: 00H Capture/Compare Register for Channel CC61 High Bit Field CCU6_CC62RL Reset: 00H Capture/Compare Register for Channel CC62 Low Bit Field CCU6_CC62RH Reset: 00H Capture/Compare Register for Channel CC62 High Bit Field FCH FDH FEH FFH 7 6 5 4 3 2 1 0 CC60VH Type rh CC61VL Type rh CC61VH Type rh CC62VL Type rh CC62VH Type rh RMAP = 0, PAGE 2 9AH 9BH 9CH CCU6_T12MSELL Reset: 00H T12 Capture/Compare Mode Select Register Low Bit Field CCU6_T12MSELH Reset: 00H T12 Capture/Compare Mode Select Register High Bit Field CCU6_IENL Reset: 00H Capture/Compare Interrupt Enable Register Low Bit Field 9EH 9FH A4H A5H A6H A7H FAH MSEL60 rw rw Type Type Type 9DH MSEL61 CCU6_IENH Reset: 00H Capture/Compare Interrupt Enable Register High Bit Field CCU6_INPL Reset: 40H Capture/Compare Interrupt Node Pointer Register Low Bit Field Type DBYP HSYNC MSEL62 rw rw rw ENT1 2 PM ENT1 2 OM ENCC 62F ENCC 62R ENCC 61F ENCC 61R ENCC 60F ENCC 60R rw rw rw rw rw rw rw rw EN STR EN IDLE EN WHE EN CHE 0 EN TRPF ENT1 3PM ENT1 3CM rw rw rw rw r rw rw rw INPCHE INPCC62 INPCC61 INPCC60 Type rw rw rw rw CCU6_INPH Reset: 39H Capture/Compare Interrupt Node Pointer Register High Bit Field 0 INPT13 INPT12 INPERR Type r rw rw rw CCU6_ISSL Reset: 00H Capture/Compare Interrupt Status Set Register Low Bit Field CCU6_ISSH Reset: 00H Capture/Compare Interrupt Status Set Register High Bit Field CCU6_PSLR Reset: 00H Passive State Level Register Bit Field Type Type Type ST12 PM ST12 OM SCC6 2F SCC6 2R SCC6 1F SCC6 1R SCC6 0F SCC6 0R w w w w w w w w SSTR SIDLE SWHE SCHE SWH C STRP F ST13 PM ST13 CM w w w w w w w w PSL63 0 PSL rwh r rwh CCU6_MCMCTR Reset: 00H Bit Field Multi-Channel Mode Control Register Type CCU6_TCTR2L Reset: 00H Timer Control Register 2 Low Data Sheet 0 SWSYN 0 SWSEL r rw r rw Bit Field 0 T13TED T13TEC T13 SSC T12 SSC Type r rw rw rw rw 46 V1.2, 2009-07 XC886/888CLM Functional Description Table 14 CCU6 Register Overview (cont'd) Addr Register Name FBH FCH CCU6_TCTR2H Reset: 00H Timer Control Register 2 High CCU6_MODCTRL Reset: 00H Modulation Control Register Low Bit CCU6_MODCTRH Reset: 00H Modulation Control Register High FFH CCU6_TRPCTRL Reset: 00H Trap Control Register Low CCU6_TRPCTRH Reset: 00H Trap Control Register High 5 4 3 2 1 0 Bit Field 0 T13RSEL T12RSEL r rw rw Bit Field Bit Field Type FEH 6 Type Type FDH 7 MCM EN 0 T12MODEN rw r rw ECT1 3O 0 T13MODEN rw r rw Bit Field 0 TRPM 2 TRPM 1 TRPM 0 Type r rw rw rw TRPP EN TRPE N13 TRPEN Type rw rw rw CCU6_MCMOUTL Reset: 00H Multi-Channel Mode Output Register Low Bit Field 0 R MCMP Type r rh rh CCU6_MCMOUTH Reset: 00H Multi-Channel Mode Output Register High Bit Field 0 CURH EXPH Type r rh rh CCU6_ISL Reset: 00H Capture/Compare Interrupt Status Register Low Bit Field CCU6_ISH Reset: 00H Capture/Compare Interrupt Status Register High Bit Field CCU6_PISEL0L Reset: 00H Port Input Select Register 0 Low Bit Field CCU6_PISEL0H Reset: 00H Port Input Select Register 0 High Bit Field CCU6_PISEL2 Reset: 00H Port Input Select Register 2 Bit Field 0 IST13HR Type r rw CCU6_T12L Reset: 00H Timer T12 Counter Register Low Bit Field CCU6_T12H Reset: 00H Timer T12 Counter Register High Bit Field CCU6_T13L Reset: 00H Timer T13 Counter Register Low Bit Field CCU6_T13H Reset: 00H Timer T13 Counter Register High Bit Field Bit Field RMAP = 0, PAGE 3 9AH 9BH 9CH 9DH 9EH 9FH A4H FAH FBH FCH FDH Data Sheet Type Type Type Type T12 PM T12 OM ICC62 F ICC62 R ICC61 F ICC61 R ICC60 F ICC60 R rh rh rh rh rh rh rh rh STR IDLE WHE CHE TRPS TRPF T13 PM T13 CM rh rh rh rh rh rh rh rh ISTRP ISCC62 ISCC61 ISCC60 rw rw rw rw IST12HR ISPOS2 ISPOS1 ISPOS0 rw rw rw rw T12CVL Type rwh T12CVH Type rwh T13CVL Type rwh T13CVH Type rwh 47 V1.2, 2009-07 XC886/888CLM Functional Description Table 14 CCU6 Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 0 FEH Bit Field 0 CC63 ST CC POS2 CC POS1 CC POS0 CC62 ST CC61 ST CC60 ST Type r rh rh rh rh rh rh rh T13IM COUT 63PS COUT 62PS CC62 PS COUT 61PS CC61 PS COUT 60PS CC60 PS rwh rwh rwh rwh rwh rwh rwh rwh FFH CCU6_CMPSTATL Reset: 00H Compare State Register Low CCU6_CMPSTATH Reset: 00H Compare State Register High Bit Field Type 3.2.4.11 UART1 Registers The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 15 UART1 Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI rw rw rw rw rw rwh rwh rwh RMAP = 1 C8H C9H CAH CBH CCH CDH CEH SCON Reset: 00H Serial Channel Control Register Bit Field SBUF Reset: 00H Serial Data Buffer Register Bit Field VAL Type rwh BCON Reset: 00H Baud Rate Control Register Bit Field 0 BRPRE R Type r rw rw BG Reset: 00H Baud Rate Timer/Reload Register Bit Field FDCON Reset: 00H Fractional Divider Control Register Bit Field 0 NDOV FDM FDEN Type r rwh rw rw FDSTEP Reset: 00H Fractional Divider Reload Register Bit Field FDRES Reset: 00H Fractional Divider Result Register Bit Field Data Sheet Type BR_VALUE Type rwh STEP Type rw RESULT Type rh 48 V1.2, 2009-07 XC886/888CLM Functional Description 3.2.4.12 SSC Registers The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 16 SSC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 A9H AAH AAH ABH ABH ACH ADH AEH AFH SSC_PISEL Reset: 00H Port Input Select Register Bit Field 0 CIS SIS MIS Type r rw rw rw SSC_CONL Reset: 00H Control Register Low Programming Mode Bit Field LB PO PH HB BM Type rw rw rw rw rw SSC_CONL Reset: 00H Control Register Low Operating Mode Bit Field 0 BC Type r rh SSC_CONH Reset: 00H Control Register High Programming Mode Bit Field EN MS 0 AREN BEN PEN REN TEN Type rw rw r rw rw rw rw rw SSC_CONH Reset: 00H Control Register High Operating Mode Bit Field EN MS 0 BSY BE PE RE TE Type rw rw r rh rwh rwh rwh rwh SSC_TBL Reset: 00H Transmitter Buffer Register Low Bit Field SSC_RBL Reset: 00H Receiver Buffer Register Low Bit Field SSC_BRL Reset: 00H Baud Rate Timer Reload Register Low Bit Field SSC_BRH Reset: 00H Baud Rate Timer Reload Register High Bit Field TB_VALUE Type rw RB_VALUE Type rh BR_VALUE Type rw BR_VALUE Type rw 3.2.4.13 MultiCAN Registers The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0). Table 17 CAN Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 ADCON Reset: 00H CAN Address/Data Control Register Bit Field V3 V2 V1 V0 AUAD BSY RWEN Type rw rw rw rw rw rh rw ADL Reset: 00H CAN Address Register Low Bit Field CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 Type rwh rwh rwh rwh rwh rwh rwh rwh ADH Reset: 00H CAN Address Register High Bit Field 0 CA13 CA12 CA11 CA10 Type r rwh rwh rwh rwh RMAP = 0 D8H D9H DAH Data Sheet 49 V1.2, 2009-07 XC886/888CLM Functional Description Table 17 CAN Register Overview (cont'd) Addr Register Name Bit DBH DATA0 Reset: 00H CAN Data Register 0 Bit Field CD Type rwh DATA1 Reset: 00H CAN Data Register 1 Bit Field CD Type rwh DATA2 Reset: 00H CAN Data Register 2 Bit Field CD Type rwh DATA3 Reset: 00H CAN Data Register 3 Bit Field CD Type rwh DCH DDH DEH 7 6 5 4 3 2 1 0 3.2.4.14 OCDS Registers The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). Table 18 OCDS Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 STMO DE EXBC DSUS P MBCO N ALTDI MMEP MMOD E JENA rw rw rw rwh rw rwh rh rh MEXIT _P MEXIT 0 MSTE P MRAM S_P MRAM S TRF RRF w rwh r rw w rwh rh rh MBCA M MBCIN EXBF SWBF HWB3 F HWB2 F HWB1 F HWB0 F rw rwh rwh rwh rwh rwh rwh rwh RMAP = 1 E9H F1H MMCR2 Reset: 1UH Monitor Mode Control 2 Register MMCR Reset: 00H Monitor Mode Control Register Bit Field Type Bit Field Type F2H MMSR Reset: 00H Monitor Mode Status Register Bit Field Type F3H MMBPCR Reset: 00H Breakpoints Control Register Bit Field Type F4H F5H F6H F7H EBH SWBC HWB3C HWB2C HWB1 C HWB0C rw rw rw rw rw MMICR Reset: 00H Monitor Mode Interrupt Control Register Bit Field MMDR Reset: 00H Monitor Mode Data Transfer Register Receive Bit Field HWBPSR Reset: 00H Hardware Breakpoints Select Register Bit Field 0 BPSEL _P BPSEL Type r w rw HWBPDR Reset: 00H Hardware Breakpoints Data Register Bit Field MMWR1 Reset: 00H Monitor Work Register 1 Bit Field Data Sheet Type DVEC T DRET R COMR ST MSTS EL MMUI E_P MMUI E RRIE_ P RRIE rwh rwh rwh rh w rw w rw MMRR Type rh HWBPxx Type rw MMWR1 Type rw 50 V1.2, 2009-07 XC886/888CLM Functional Description Table 18 OCDS Register Overview (cont'd) Addr Register Name Bit ECH Bit Field MMWR2 Reset: 00H Monitor Work Register 2 Data Sheet 7 6 5 4 3 2 1 0 MMWR2 Type rw 51 V1.2, 2009-07 XC886/888CLM Functional Description 3.3 Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage. The sectorization of the Flash memory allows each sector to be erased independently. Features * * * * * * * * * * * * * In-System Programming (ISP) via UART In-Application Programming (IAP) Error Correction Code (ECC) for dynamic correction of single-bit errors Background program and erase operations for CPU load minimization Support for aborting erase operation Minimum program width1) of 32-byte for D-Flash and 64-byte for P-Flash 1-sector minimum erase width 1-byte read access Flash is delivered in erased state (read all zeros) Operating supply voltage: 2.5 V 7.5 % Read access time: 3 x tCCLK = 125 ns2) Program time: 248256 / fSYS = 2.6 ms3) Erase time: 9807360 / fSYS = 102 ms3) 1) P-Flash: 64-byte wordline can only be programmed once, i.e., one gate disturb allowed. D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed. 2) Values shown here are typical values. fsys = 96 MHz 7.5% (fCCLK = 24 MHz 7.5 %) is the maximum frequency range for Flash read access. 3) Values shown here are typical values. fsys = 96 MHz 7.5% is the only frequency range for Flash programming and erasing. fsysmin is used for obtaining the worst case timing. Data Sheet 52 V1.2, 2009-07 XC886/888CLM Functional Description Table 19 shows the Flash data retention and endurance targets. Table 19 Flash Data Retention and Endurance (Operating Conditions apply) Endurance1) Size Remarks 20 years 1,000 cycles up to 32 Kbytes2) for 32-Kbyte Variant 20 years 1,000 cycles up to 24 Kbytes2) for 24-Kbyte Variant 20 years 1,000 cycles 4 Kbytes 5 years 10,000 cycles 1 Kbyte 2 years 70,000 cycles 512 bytes 2 years 100,000 cycles 128 bytes Retention Program Flash Data Flash 1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance data specified in Table 19 is valid only if the following conditions are fulfilled: - the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles. - the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles. - the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles. 2) If no Flash is used for data, the Program Flash size can be up to the maximum Flash size available in the device variant. Having more Data Flash will mean less Flash is available for Program Flash. 3.3.1 Flash Bank Sectorization The XC886/888 product family offers Flash devices with either 24 Kbytes or 32 Kbytes of embedded Flash memory. Each Flash device consists of Program Flash (P-Flash) and Data Flash (D-Flash) bank(s) with different sectorization shown in Figure 11. Both types can be used for code and data storage. The label "Data" neither implies that the D-Flash is mapped to the data memory region, nor that it can only be used for data storage. It is used to distinguish the different Flash bank sectorizations. The 32-Kbyte Flash device consists of 6 P-Flash and 2 D-Flash banks, while the 24Kbyte Flash device consists of also of 6 P-Flash banks but with the upper 2 banks only 2 Kbytes each, and only 1 D-Flash bank. The XC886/888 ROM devices offer a single 4Kbyte D-Flash bank. The P-Flash banks are always grouped in pairs. As such, the P-Flash banks are also sometimes referred to as P-Flash bank pair. Each sector in a P-Flash bank is grouped with the corresponding sector from the other bank within a bank pair to form a P-Flash bank pair sector. Data Sheet 53 V1.2, 2009-07 XC886/888CLM Functional Description Sector 2: 128-byte Sector 1: 128-byte Sector Sector Sector Sector 9: 8: 7: 6: 128-byte 128-byte 128-byte 128-byte Sector 5: 256-byte Sector 4: 256-byte Sector 3: 512-byte Sector 0: 3.75-Kbyte Sector 2: 512-byte Sector 1: 1-Kbyte Sector 0: 1-Kbyte P-Flash Figure 11 D-Flash Flash Bank Sectorization The internal structure of each Flash bank represents a sector architecture for flexible erase capability. The minimum erase width is always a complete sector, and sectors can be erased separately or in parallel. Contrary to standard EPROMs, erased Flash memory cells contain 0s. The D-Flash bank is divided into more physical sectors for extended erasing and reprogramming capability; even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements. 3.3.2 Parallel Read Access of P-Flash To enhance system performance, the P-Flash banks are configured for parallel read to allow two bytes of linear code to be read in 4 x CCLK cycles, compared to 6 x CCLK cycles if serial read is performed. This is achieved by reading two bytes in parallel from a P-Flash bank pair within the 3 x CCLK cycles access time and storing them in a cache. Subsequent read from the cache by the CPU does not require a wait state and can be completed within 1 x CCLK cycle. The result is the average instruction fetch time from the P-Flash banks is reduced and thus, the MIPS (Mega Instruction Per Second) of the system is increased. However, if the parallel read feature is not desired due to certain timing constraints, it can be disabled by calling the parallel read disable subroutine. Data Sheet 54 V1.2, 2009-07 XC886/888CLM Functional Description 3.3.3 Flash Programming Width For the P-Flash banks, a programmed wordline (WL) must be erased before it can be reprogrammed as the Flash cells can only withstand one gate disturb. This means that the entire sector containing the WL must be erased since it is impossible to erase a single WL. For the D-Flash bank, the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs. This means if the number of data bytes that needs to be written is smaller than the 32-byte minimum programming width, the user can opt to program this number of data bytes (x; where x can be any integer from 1 to 31) first and program the remaining bytes (32 - x) later. Hence, it is possible to program the same WL, for example, with 16 bytes of data two times (see Figure 12) 32 bytes (1 WL) 16 bytes 16 bytes 0000 ..... 0000 H 0000 ..... 0000 H Program 1 0000 ..... 0000 H 1111 ..... 1111 H 0000 ..... 0000 H 1111 ..... 1111 H Program 2 1111 ..... 0000 H 0000 ..... 0000 H 1111 ..... 0000 H 1111 ..... 1111 H Note: A Flash memory cell can be programmed from 0 to 1, but not from 1 to 0. Flash memory cells Figure 12 32-byte write buffers D-Flash Programming Note: When programming a D-Flash WL the second time, the previously programmed Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain its original contents and to prevent "over-programming". Data Sheet 55 V1.2, 2009-07 XC886/888CLM Functional Description 3.4 Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC886/888 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional status registers for detecting and determining the interrupt source. 3.4.1 Interrupt Source Figure 13 to Figure 17 give a general overview of the interrupt sources and nodes, and their corresponding control and status flags. WDT Overflow FNMIWDT NMIISR.0 NMIWDT NMICON.0 PLL Loss of Lock FNMIPLL NMIISR.1 NMIPLL NMICON.1 Flash Operation Complete FNMIFLASH NMIISR.2 NMIFLASH >=1 VDD Pre-Warning 0073 FNMIVDD NMIISR.4 H Non Maskable Interrupt NMIVDD NMICON.4 VDDP Pre-Warning FNMIVDDP NMIISR.5 NMIVDDP NMICON.5 Flash ECC Error FNMIECC NMIISR.6 NMIECC NMICON.6 Figure 13 Data Sheet Non-Maskable Interrupt Request Sources 56 V1.2, 2009-07 XC886/888CLM Functional Description Highest Timer 0 Overflow TF0 TCON.5 ET0 000B H IEN0.1 Timer 1 Overflow Lowest Priority Level IP.1/ IPH.1 TF1 TCON.7 ET1 001B H IEN0.3 UART Receive IP.3/ IPH.3 RI SCON.0 UART Transmit >=1 TI ES SCON.1 IEN0.4 0023 H IP.4/ IPH.4 IE0 EINT0 P o l l i n g TCON.1 IT0 EX0 0003 H IEN0.0 TCON.0 S e q u e n c e IP.0/ IPH.0 EXINT0 EXICON0.0/1 IE1 EINT1 TCON.3 IT1 EX1 0013 H IEN0.2 TCON.2 EXINT1 IP.2/ IPH.2 EA EXICON0.2/3 IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 14 Data Sheet Interrupt Request Sources (Part 1) 57 V1.2, 2009-07 XC886/888CLM Functional Description Highest Timer 2 Overflow TF2 Lowest Priority Level T2_T2CON.7 >=1 T2EX EXF2 EXEN2 EDGES EL T2_T2MOD.5 T2_T2CON.6 T2_T2CON.3 Normal Divider Overflow NDOV FDCON.2 End of Synch Byte Synch Byte Error >=1 EOFSYN FDCON.4 ET2 >=1 002B H IEN0.5 ERRSYN IP.5/ IPH.5 SYNEN FDCON.5 MultiCAN_0 CANSRC0 IRCON2.0 ADC_0 ADCSR0 IRCON1.3 ADC_1 ADCSR1 IRCON1.4 MultiCAN_1 >=1 CANSRC1 EADC IRCON1.5 MultiCAN_2 0033 H IEN1.0 CANSRC2 IP1.0/ IPH1.0 P o l l i n g S e q u e n c e EA IEN0.7 IRCON1.6 Bit-addressable Request flag is cleared by hardware Figure 15 Data Sheet Interrupt Request Sources (Part 2) 58 V1.2, 2009-07 XC886/888CLM Functional Description Highest SSC_EIR Lowest Priority Level EIR IRCON1.0 SSC_TIR TIR >=1 IRCON1.1 SSC_RIR ESSC RIR 003B H IEN1.1 IP1.1/ IPH1.1 IRCON1.2 P o l l i n g EXINT2 EINT2 IRCON0.2 EXINT2 EXICON0.4/5 RI UART1_SCON.0 UART1 >=1 TI UART1_SCON.1 Timer 21 Overflow TF2 >=1 T21_T2CON.7 T21EX >=1 EX2 0043 H IEN1.2 EXF2 IP1.2/ IPH1.2 S e q u e n c e EXEN2 T21_T2CON.6 EDGES EL T21_T2MOD.5 T21_T2CON.3 Normal Divider Overflow NDOV UART1_FDCON.2 Cordic EOC CDSTATC.2 MDU_0 IRDY MDUSTAT.0 MDU_1 EA IERR MDUSTAT.1 IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 16 Data Sheet Interrupt Request Sources (Part 3) 59 V1.2, 2009-07 XC886/888CLM Functional Description Highest Lowest Priority Level EXINT3 EINT3 IRCON0.3 EXINT3 EXICON0.6/7 EXINT4 EINT4 P o l l i n g IRCON0.4 EXINT3 EXICON1.0/1 >=1 EXINT5 EINT5 IRCON0.5 EXM 004B H IEN1.3 EXINT5 EXICON1.2/3 EXINT6 EINT6 IRCON0.6 IP1.3/ IPH1.3 S e q u e n c e EXINT6 EXICON1.4/5 MultiCAN_3 CANSRC3 EA IEN0.7 IRCON2.4 Bit-addressable Request flag is cleared by hardware Figure 17 Data Sheet Interrupt Request Sources (Part 4) 60 V1.2, 2009-07 XC886/888CLM Functional Description Highest Lowest CCU6 interrupt node 0 IRCON3.0 MultiCAN_4 Priority Level CCU6SR0 >=1 CANSRC4 ECCIP0 IRCON3.1 CCU6 interrupt node 1 IEN1.4 ECCIP1 IRCON3.5 >=1 ECCIP2 0063 H IEN1.6 IRCON4.1 IP1.5/ IPH1.5 IP1.6/ IPH1.6 P o l l i n g S e q u e n c e CCU6SRC3 IRCON4.4 MultiCAN_7 H IEN1.5 CANSRC6 CCU6 interrupt node 3 005B CCU6SR2 IRCON4.0 MutliCAN_6 IP1.4/ IPH1.4 >=1 CANSRC5 CCU6 interrupt node 2 H CCU6SR1 IRCON3.4 MultiCAN_5 0053 >=1 CANSRC7 IRCON4.5 ECCIP3 006B H IEN1.7 IP1.7/ IPH1.7 EA IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 18 Data Sheet Interrupt Request Sources (Part 5) 61 V1.2, 2009-07 XC886/888CLM Functional Description 3.4.2 Interrupt Source and Vector Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the XC886/888 interrupt sources to the interrupt vector address and the corresponding interrupt node enable bits are summarized in Table 20. Table 20 Interrupt Source NMI Interrupt Vector Addresses Vector Address Assignment for XC886/888 Enable Bit SFR 0073H Watchdog Timer NMI NMIWDT NMICON PLL NMI NMIPLL Flash NMI NMIFLASH VDDC Prewarning NMI NMIVDD VDDP Prewarning NMI NMIVDDP Flash ECC NMI NMIECC XINTR0 0003H External Interrupt 0 EX0 XINTR1 000BH Timer 0 ET0 XINTR2 0013H External Interrupt 1 EX1 XINTR3 001BH Timer 1 ET1 XINTR4 0023H UART ES XINTR5 002BH T2 ET2 IEN0 UART Fractional Divider (Normal Divider Overflow) MultiCAN Node 0 LIN Data Sheet 62 V1.2, 2009-07 XC886/888CLM Functional Description Table 20 Interrupt Source XINTR6 Interrupt Vector Addresses (cont'd) Vector Address Assignment for XC886/888 Enable Bit SFR 0033H MultiCAN Nodes 1 and 2 EADC IEN1 ADC[1:0] XINTR7 003BH SSC ESSC XINTR8 0043H External Interrupt 2 EX2 T21 CORDIC UART1 UART1 Fractional Divider (Normal Divider Overflow) MDU[1:0] XINTR9 004BH External Interrupt 3 EXM External Interrupt 4 External Interrupt 5 External Interrupt 6 MultiCAN Node 3 XINTR10 0053H CCU6 INP0 ECCIP0 MultiCAN Node 4 XINTR11 005BH CCU6 INP1 ECCIP1 MultiCAN Node 5 XINTR12 0063H CCU6 INP2 ECCIP2 MultiCAN Node 6 XINTR13 006BH CCU6 INP3 ECCIP3 MultiCAN Node 7 Data Sheet 63 V1.2, 2009-07 XC886/888CLM Functional Description 3.4.3 Interrupt Priority An interrupt that is currently being serviced can only be interrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by any other interrupt request. If two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within each priority level, there is a second priority structure determined by the polling sequence shown in Table 21. Table 21 Priority Structure within Interrupt Level Source Level Non-Maskable Interrupt (NMI) (highest) External Interrupt 0 1 Timer 0 Interrupt 2 External Interrupt 1 3 Timer 1 Interrupt 4 UART Interrupt 5 Timer 2,UART Normal Divider Overflow, MultiCAN, LIN Interrupt 6 ADC, MultiCAN Interrupt 7 SSC Interrupt 8 External Interrupt 2, Timer 21, UART1, UART1 9 Normal Divider Overflow, MDU, CORDIC Interrupt External Interrupt [6:3], MultiCAN Interrupt 10 CCU6 Interrupt Node Pointer 0, MultiCAN interrupt 11 CCU6 Interrupt Node Pointer 1, MultiCAN Interrupt 12 CCU6 Interrupt Node Pointer 2, MultiCAN Interrupt 13 CCU6 Interrupt Node Pointer 3, MultiCAN Interrupt 14 Data Sheet 64 V1.2, 2009-07 XC886/888CLM Functional Description 3.5 Parallel Ports The XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4), while the XC888 has 48 port pins organized into six parallel ports, Port 0 (P0) to Port 5 (P5). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1, P3, P4 and P5 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. Port P2 is an input-only port, providing general purpose input functions, alternate input functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital Converter (ADC). Bidirectional Port Features * * * * * Configurable pin direction Configurable pull-up/pull-down devices Configurable open drain mode Transfer of data through digital inputs and outputs (general purpose I/O) Alternate input/output for on-chip peripherals Input Port Features * * * * * Configurable input driver Configurable pull-up/pull-down devices Receive of data through digital input (general purpose input) Alternate input for on-chip peripherals Analog input for ADC module Data Sheet 65 V1.2, 2009-07 XC886/888CLM Functional Description Figure 19 shows the structure of a bidirectional port pin. Internal Bus Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_OD Open Drain Control Register Px_DIR Direction Register Px_ALTSEL0 Alternate Select Register 0 VDDP Px_ALTSEL1 Alternate Select Register 1 enable AltDataOut 3 AltDataOut 2 AltDataOut1 enable 11 10 Pull Up Device Output Driver Pin 01 00 Px_Data Data Register enable Out In Input Driver Schmitt Trigger AltDataIn enable Pull Down Device Pad Figure 19 Data Sheet General Structure of Bidirectional Port 66 V1.2, 2009-07 XC886/888CLM Functional Description Figure 20 shows the structure of an input-only port pin. Internal Bus Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR Direction Register VDDP enable enable Px_DATA Data Register In Input Driver Pull Up Device Pin Schmitt Trigger AltDataIn AnalogIn enable Pull Down Device Pad Figure 20 Data Sheet General Structure of Input Port 67 V1.2, 2009-07 XC886/888CLM Functional Description 3.6 Power Supply System with Embedded Voltage Regulator The XC886/888 microcontroller requires two different levels of power supply: * * 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports 2.5 V for the core, memory, on-chip oscillator, and peripherals Figure 21 shows the XC886/888 power supply system. A power supply of 3.3 V or 5.0 V must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design. The EVR consists of a main voltage regulator and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage regulator continues to function and provide power supply to the system with low power consumption. CPU & Memory On-chip OSC Peripheral logic ADC V DDC (2.5V) FLASH PLL GPIO Ports (P0-P5) XTAL1& XTAL2 EVR VDDP (3.3V/5.0V) VSSP Figure 21 XC886/888 Power Supply System EVR Features * * * * * Input voltage (VDDP): 3.3 V/5.0 V Output voltage (VDDC): 2.5 V 7.5% Low power voltage regulator provided in power-down mode VDDC and VDDP prewarning detection VDDC brownout detection Data Sheet 68 V1.2, 2009-07 XC886/888CLM Functional Description 3.7 Reset Control The XC886/888 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC886/888 is first powered up, the status of certain pins (see Table 23) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset. This guarantees stable conditions during the normal operation of the device. In order to power up the system properly, the external reset pin RESET must be asserted until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches 0.4 V, but not before VDDC reaches 0.9* VDDC. A typical application example is shown in Figure 22. The VDDP capacitor value is 100 nF while the VDDC capacitor value is 220 nF. The capacitor connected to RESET pin is 100 nF. Typically, the time taken for VDDC to reach 0.9*VDDC is less than 50 s once VDDP reaches 2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less than 500 s, the RESET pin should be held low for 500 s typically. See Figure 23. VIN VR 3.3 / 5V 220nF 100nF V DDP VSSP typ. 100nF VDDC VSSC RESET EVR 30k XC886/888 Figure 22 Data Sheet Reset Circuitry 69 V1.2, 2009-07 XC886/888CLM Functional Description Voltage 5V VDDP 2.5V 2.3V 0.9*VDDC VDDC Time Voltage RESET with capacitor 5V < 0.4V 0V Time typ. < 50s Figure 23 VDDP, VDDC and VRESET during Power-on Reset The second type of reset in XC886/888 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be detected is a reset while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defined after a wake-up reset from power-down mode. Data Sheet 70 V1.2, 2009-07 XC886/888CLM Functional Description 3.7.1 Module Reset Behavior Table 22 lists the functions of the XC886/888 and the various reset types that affect these functions. The symbol "" signifies that the particular function is reset to its default state. Table 22 Effect of Reset on Device Functions Module/ Function Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset CPU Core Peripherals On-Chip Static RAM Not affected, Not affected, Not affected, Affected, un- Affected, unReliable Reliable Reliable reliable reliable Oscillator, PLL Not affected Port Pins EVR The voltage regulator is switched on Not affected FLASH NMI Disabled Disabled 3.7.2 Booting Scheme When the XC886/888 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0.0 collectively select the different boot options. Table 23 shows the available boot options in the XC886/888. Table 23 MBC XC886/888 Boot Selection TMS P0.0 Type of Mode 1 0 X User Mode1); on-chip OSC/PLL non-bypassed 0000H 0 0 X BSL Mode; on-chip OSC/PLL non-bypassed2) 0000H 0 1 0 OCDS Mode; on-chip OSC/PLL nonbypassed 0000H 1 1 0 User (JTAG) Mode3); on-chip OSC/PLL nonbypassed (normal) 0000H Data Sheet PC Start Value 71 V1.2, 2009-07 XC886/888CLM Functional Description 1) BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals zero. 2) OSC is bypassed in MultiCAN BSL mode 3) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose. Note: The boot options are valid only with the default set of UART and JTAG pins. 3.8 Clock Generation Unit The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC886/888. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. During user program execution, the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore the power consumption can be adapted to the actual application state. Features * * * * * Phase-Locked Loop (PLL) for multiplying clock source by different factors PLL Base Mode Prescaler Mode PLL Mode Power-down mode support The CGU consists of an oscillator circuit and a PLL. In the XC886/888, the oscillator can be from either of these two sources: the on-chip oscillator (9.6 MHz) or the external oscillator (4 MHz to 12 MHz). The term "oscillator" is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down. Data Sheet 72 V1.2, 2009-07 XC886/888CLM Functional Description OSC fosc osc fail detect OSCR lock detect LOCK P:1 PLL core fp fn N:1 OSCDISC Figure 24 fsys K:1 fvco PLLBYP VCOBYP NDIV CGU Block Diagram PLL Base Mode When the oscillator is disconnected from the PLL, the system clock is derived from the VCO base (free running) frequency clock (Table 25) divided by the K factor. 1 f SYS = f VCObase x ---K (3.1) Prescaler Mode (VCO Bypass Operation) In VCO bypass operation, the system clock is derived from the oscillator clock, divided by the P and K factors. 1 f SYS = f OSC x ------------PxK (3.2) Data Sheet 73 V1.2, 2009-07 XC886/888CLM Functional Description PLL Mode The system clock is derived from the oscillator clock, multiplied by the N factor, and divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for this PLL mode. The PLL mode is used during normal system operation. N f SYS = f OSC x ------------PxK (3.3) System Frequency Selection For the XC886/888, the value of P is fixed to 1. In order to obtain the required fsys, the value of N and K can be selected by bits NDIV and KDIV respectively for different oscillator inputs. The output frequency must always be configured for 96 MHz. Table 24 provides examples on how fsys = 96 MHz can be obtained for the different oscillator sources. Table 24 System frequency (fsys = 96 MHz) Oscillator Fosc N P K Fsys On-chip 9.6 MHz 20 1 2 96 MHz External 8 MHz 24 1 2 96 MHz 6 MHz 32 1 2 96 MHz 4 MHz 48 1 2 96 MHz Data Sheet 74 V1.2, 2009-07 XC886/888CLM Functional Description Table 25 shows the VCO range for the XC886/888. Table 25 VCO Range fVCOmin fVCOmax fVCOFREEmin fVCOFREEmax Unit 150 200 20 80 MHz 100 150 10 80 MHz 3.8.1 Recommended External Oscillator Circuits The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output. When using a crystal, a proper external oscillator circuitry must be connected to both pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz to 12 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1 and CX2 values shown in Figure 25 can be used as starting points for the negative resistance evaluation and for non-productive systems. The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative resistance method. Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected). The oscillator can also be used in combination with a ceramic resonator. The final circuitry must also be verified by the resonator vendor. Figure 25 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode. Data Sheet 75 V1.2, 2009-07 XC886/888CLM Functional Description f OSC XTAL1 4 - 12 MHz RQ CX1 XC886/888 Oscillator R X2 XTAL2 CX2 V SS VSS Crystal Frequency CX1, CX2 33 18 15 12 1) pF pF pF pF RX2 1) 0 0 0 0 Clock_EXOSC 1) Note that these are evaluation start values! Figure 25 fOSC XTAL1 XC886/888 Oscillator XTAL2 Fundamental Mode Crystal 4 MHz 8 MHz 10 MHz 12 MHz External Clock Signal External Oscillator Circuitry Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. Data Sheet 76 V1.2, 2009-07 XC886/888CLM Functional Description 3.8.2 Clock Management The CGU generates all clock signals required within the microcontroller from a single clock, fsys. During normal system operation, the typical frequencies of the different modules are as follow: * * * * CPU clock: CCLK, SCLK = 24 MHz Fast clock (used by MultiCAN): FCLK = 24 or 48 MHz Peripheral clock: PCLK = 24 MHz Flash Interface clock: CCLK2 = 48 MHz and CCLK = 24 MHz In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The clock output frequency, which is derived from the clock output divider (bit COREL), can further be divided by 2 using toggle latch (bit TLEN is set to 1). The resulting output frequency has a 50% duty cycle. Figure 26 shows the clock distribution of the XC886/888. FCCFG FCLK CLKREL MultiCAN SD PCLK 1 OSC fosc PLL Peripherals SCLK fsys= 96MHz /2 0 CCLK CORE /2 CCLK2 COREL N,P,K FLASH Interface TLEN Toggle Latch CLKOUT COUTS Figure 26 Data Sheet Clock Generation from fsys 77 V1.2, 2009-07 XC886/888CLM Functional Description For power saving purposes, the clocks may be disabled or slowed down according to Table 26. Table 26 System frequency (fsys = 96 MHz) Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the peripherals are divided by a common programmable factor defined by bit field CMCON.CLKREL. Power-down Oscillator and PLL are switched off. Data Sheet 78 V1.2, 2009-07 XC886/888CLM Functional Description 3.9 Power Saving Modes The power saving modes of the XC886/888 provide flexible power consumption through a combination of techniques, including: * * * * Stopping the CPU clock Stopping the clocks of individual system components Reducing clock speed of some peripheral components Power-down of the entire system with fast restart capability After a reset, the active mode (normal operating mode) is selected by default (see Figure 27) and the system runs in the main system clock frequency. From active mode, different power saving modes can be selected by software. They are: * * * Idle mode Slow-down mode Power-down mode ACTIVE any interrupt & SD=0 set PD bit set IDLE bit set SD bit IDLE EXINT0/RXD pin & SD=0 clear SD bit set IDLE bit any interrupt & SD=1 Figure 27 Data Sheet POWER-DOWN set PD bit SLOW-DOWN EXINT0/RXD pin & SD=1 Transition between Power Saving Modes 79 V1.2, 2009-07 XC886/888CLM Functional Description 3.10 Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an XC886/888 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the XC886/888 will be aborted in a user-specified time period. In debug mode, the WDT is default suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging. Features * * * * * 16-bit Watchdog Timer Programmable reload value for upper 8 bits of timer Programmable window boundary Selectable input frequency of fPCLK/2 or fPCLK/128 Time-out detection with NMI generation and reset prewarning activation (after which a system reset will be performed) The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. The lower 8 bits are reset on each service access. Figure 28 shows the block diagram of the WDT unit. WDT Control Clear 1:2 MUX f PCLK WDTREL WDT Low Byte WDT High Byte 1:128 Overflow/Time-out Control & Window-boundary control WDTIN ENWDT FNMIWDT . WDTRST Logic ENWDT_P Figure 28 Data Sheet WDTWINB WDT Block Diagram 80 V1.2, 2009-07 XC886/888CLM Functional Description If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is entered. The prewarning period lasts for 30H count, after which the system is reset (assert WDTRST). The WDT has a "programmable window boundary" which disallows any refresh during the WDT's count-up. A refresh during this window boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000H to the value obtained from the concatenation of WDTWINB and 00H. After being serviced, the WDT continues counting up from the value (<WDTREL> * 28). The time period for an overflow of the WDT is programmable in two ways: * * The input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128 The reload value WDTREL for the high byte of WDT can be programmed in register WDTREL The period, PWDT, between servicing the WDT and the next overflow can be determined by the following formula: 2 ( 1 + WDTIN x 6 ) x ( 2 16 - WDTREL x 2 8 ) P WDT = --------------------------------------------------------------------------------------------------------f PCLK (3.4) If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL, see Figure 29. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be smaller than WDTREL. Data Sheet 81 V1.2, 2009-07 XC886/888CLM Functional Description Count FFFFH WDTWINB WDTREL time No refresh allowed Figure 29 Refresh allowed WDT Timing Diagram Table 27 lists the possible watchdog time ranges that can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. Table 27 Reload value In WDTREL Watchdog Time Ranges Prescaler for fPCLK 2 (WDTIN = 0) 128 (WDTIN = 1) 24 MHz 24 MHz FFH 21.3 s 1.37 ms 7FH 2.75 ms 176 ms 00H 5.46 ms 350 ms Data Sheet 82 V1.2, 2009-07 XC886/888CLM Functional Description 3.11 Multiplication/Division Unit The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the XC886/888 Core in real-time control applications, which require fast mathematical computations. Features * * * * Fast signed/unsigned 16-bit multiplication Fast signed/unsigned 32-bit divide by 16-bit and 16-bit divide by 16-bit operations 32-bit unsigned normalize operation 32-bit arithmetic/logical shift operations Table 28 specifies the number of clock cycles used for calculation in various operations. Table 28 MDU Operation Characteristics Operation Result Remainder Signed 32-bit/16-bit 32-bit 16-bit 33 Signed 16-bit/16bit 16-bit 16-bit 17 Signed 16-bit x 16-bit 32-bit - 16 Unsigned 32-bit/16-bit 32-bit 16-bit 32 Unsigned 16-bit/16-bit 16-bit 16-bit 16 Unsigned 16-bit x 16-bit 32-bit - 16 32-bit normalize - - No. of shifts + 1 (Max. 32) 32-bit shift L/R - - No. of shifts + 1 (Max. 32) Data Sheet 83 No. of Clock Cycles used for calculation V1.2, 2009-07 XC886/888CLM Functional Description 3.12 CORDIC Coprocessor The CORDIC Coprocessor provides CPU with hardware support for the solving of circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions. Features * * * * * * * * * * * * * Modes of operation - Supports all CORDIC operating modes for solving circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions - Integrated look-up tables (LUTs) for all operating modes Circular vectoring mode: Extended support for values of initial X and Y data up to full range of [-215,(215-1)] for solving angle and magnitude Circular rotation mode: Extended support for values of initial Z data up to full range of [-215,(215-1)], representing angles in the range [-,((215-1)/215)] for solving trigonometry Implementation-dependent operational frequency of up to 80 MHz Gated clock input to support disabling of module 16-bit accessible data width - 24-bit kernel data width plus 2 overflow bits for X and Y each - 20-bit kernel data width plus 1 overflow bit for Z - With KEEP bit to retain the last value in the kernel register for a new calculation 16 iterations per calculation: Approximately 41 clock-cycles or less, from set of start (ST) bit to set of end-of-calculation flag, excluding time taken for write and read access of data bytes. Twos complement data processing - Only exception: X result data with user selectable option for unsigned result X and Y data generally accepted as integer or rational number; X and Y must be of the same data form Entries of LUTs are 20-bit signed integers - Entries of atan and atanh LUTs are integer representations (S19) of angles with the scaling such that [-215,(215-1)] represents the range [-,((215-1)/215)] - Accessible Z result data for circular and hyperbolic functions is integer in data form of S15 Emulated LUT for linear function - Data form is 1 integer bit and 15-bit fractional part (1.15) - Accessible Z result data for linear function is rational number with fixed data form of S4.11 (signed 4Q16) Truncation Error - The result of a CORDIC calculation may return an approximation due to truncation of LSBs - Good accuracy of the CORDIC calculated result data, especially in circular mode Interrupt - On completion of a calculation Data Sheet 84 V1.2, 2009-07 XC886/888CLM Functional Description - Interrupt enabling and corresponding flag 3.13 UART and UART1 The XC886/888 provides two Universal Asynchronous Receiver/Transmitter (UART and UART1) modules for full-duplex asynchronous reception/transmission. Both are also receive-buffered, i.e., they can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. Features * * * * Full-duplex asynchronous modes - 8-bit or 9-bit data frames, LSB first - Fixed or variable baud rate Receive buffered Multiprocessor communication Interrupt generation on the completion of a data transmission or reception The UART modules can operate in the four modes shown in Table 29. Table 29 UART Modes Operating Mode Baud Rate Mode 0: 8-bit shift register fPCLK/2 Mode 1: 8-bit shift UART Variable Mode 2: 9-bit shift UART fPCLK/32 or fPCLK/641) Mode 3: 9-bit shift UART Variable 1) For UART1 module, the baud rate is fixed at fPCLK/64. There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock and can be configured to eitherfPCLK/32 or fPCLK/64. For UART1 module, only fPCLK/64 is available. The variable baud rate is set by the underflow rate on the dedicated baud-rate generator. For UART module, the variable baud rate alternatively can be set by the overflow rate on Timer 1. 3.13.1 Baud-Rate Generator Both UART modules have their own dedicated baud-rate generator, which is based on a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and Data Sheet 85 V1.2, 2009-07 XC886/888CLM Functional Description fractional divider) for generating a wide range of baud rates based on its input clock fPCLK, see Figure 30. Fractional Divider 8-Bit Reload Value FDSTEP 1 FDM 1 FDEN&FDM 0 Adder fDIV 00 01 0 FDRES FDEN fMOD (overflow) 0 1 11 8-Bit Baud Rate Timer fBR 10 R fPCLK Prescaler fDIV clk 11 10 NDOV 01 `0' Figure 30 00 Baud-rate Generator Circuitry The baud rate timer is a count-down timer and is clocked by either the output of the fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate generation, the fractional divider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel. Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.14. The baud rate (fBR) value is dependent on the following parameters: * * * * Input clock fPCLK Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON Fractional divider (STEP/256) defined by register FDSTEP (to be considered only if fractional divider is enabled and operating in fractional divider mode) 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG Data Sheet 86 V1.2, 2009-07 XC886/888CLM Functional Description The following formulas calculate the final baud rate without and with the fractional divider respectively: f PCLK BRPRE baud rate = ------------------------------------------------------------------------------------ where 2 x ( BR_VALUE + 1 ) > 1 BRPRE 16 x 2 x ( BR_VALUE + 1 ) (3.5) f PCLK STEP baud rate = ------------------------------------------------------------------------------------ x --------------BRPRE 256 16 x 2 x ( BR_VALUE + 1 ) (3.6) The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud. Standard LIN protocol can support a maximum baud rate of 20 kHz, the baud rate accuracy is not critical and the fractional divider can be disabled. Only the prescaler is used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of 20 kHz to 115.2 kHz, the higher baud rates require the use of the fractional divider for greater accuracy. Table 30 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors. The fractional divider is disabled and a module clock of 24 MHz is used. Table 30 Typical Baud rates for UART with Fractional Divider disabled Baud rate Prescaling Factor (2BRPRE) Reload Value (BR_VALUE + 1) Deviation Error 19.2 kBaud 1 (BRPRE=000B) 78 (4EH) 0.17 % 9600 Baud 1 (BRPRE=000B) 156 (9CH) 0.17 % 4800 Baud 2 (BRPRE=001B) 156 (9CH) 0.17 % 2400 Baud 4 (BRPRE=010B) 156 (9CH) 0.17 % The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 31 lists the resulting deviation errors from generating a baud rate of 115.2 kHz, using different module clock frequencies. The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown. Data Sheet 87 V1.2, 2009-07 XC886/888CLM Functional Description Table 31 fPCLK Deviation Error for UART with Fractional Divider enabled Prescaling Factor Reload Value STEP (2BRPRE) (BR_VALUE + 1) Deviation Error 24 MHz 1 10 (AH) 197 (C5H) +0.20 % 12 MHz 1 6 (6H) 236 (ECH) +0.03 % 8 MHz 1 4 (4H) 236 (ECH) +0.03 % 6 MHz 1 3 (3H) 236 (ECH) +0.03 % 3.13.2 Baud Rate Generation using Timer 1 In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate. The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows: SMOD 2 x f PCLK Mode 1, 3 baud rate = ---------------------------------------------------32 x 2 x ( 256 - TH1 ) (3.7) 3.14 Normal Divider Mode (8-bit Auto-reload Timer) Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 30). Once the fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At each timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP. The output frequency in normal divider mode is derived as follows: 1 f MOD = f DIV x -----------------------------256 - STEP (3.8) Data Sheet 88 V1.2, 2009-07 XC886/888CLM Functional Description 3.15 LIN Protocol The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Byte detection, provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception. Note: The LIN baud rate detection feature is available for use only with UART. To use UART1 for LIN communication, software has to be implemented to detect the Break and Synch Byte. LIN is a holistic communication concept for local interconnected networks in vehicles. The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An attractive feature of LIN is self-synchronization of the slave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame. The structure of a LIN frame is shown in Figure 31. The frame consists of the: * * * * Header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field Response time Data bytes (according to UART protocol) Checksum Frame slot Frame Header Synch Figure 31 3.15.1 Response space Protected identifier Response Data 1 Data 2 Data N Checksum Structure of LIN Frame LIN Header Transmission LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which frame is to be transferred on the bus. It also identifies a slave task to provide the data transported by each frame. The information Data Sheet 89 V1.2, 2009-07 XC886/888CLM Functional Description needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame. The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data. The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier field of frame. For this purpose, every frame starts with a sequence consisting of a break field followed by a synch byte field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field. Upon entering LIN communication, a connection is established and the transfer speed (baud rate) of the serial communication partner (host) is automatically synchronized in the following steps: STEP 1: Initialize interface for reception and timer for baud rate measurement STEP 2: Wait for an incoming LIN frame from host STEP 3: Synchronize the baud rate to the host STEP 4: Enter for Master Request Frame or for Slave Response Frame Note: Re-synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame. Data Sheet 90 V1.2, 2009-07 XC886/888CLM Functional Description 3.16 High-Speed Synchronous Serial Interface The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces. Features * * * * * * Master and slave mode operation - Full-duplex or half-duplex operation Transmit and receive buffered Flexible data format - Programmable number of data bits: 2 to 8 bits - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock Variable baud rate Compatible with Serial Peripheral Interface (SPI) Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error) Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered. Figure 32 shows the block diagram of the SSC. Data Sheet 91 V1.2, 2009-07 XC886/888CLM Functional Description PCLK Baud-rate Generator SS_CLK MS_CLK Clock Control Shift Clock RIR SSC Control Block Register CON Status Receive Int. Request TIR Transmit Int. Request EIR Error Int. Request Control TXD(Master) Pin Control 16-Bit Shift Register RXD(Slave) TXD(Slave) RXD(Master) Transmit Buffer Register TB Receive Buffer Register RB Internal Bus Figure 32 Data Sheet SSC Block Diagram 92 V1.2, 2009-07 XC886/888CLM Functional Description 3.17 Timer 0 and Timer 1 Timer 0 and Timer 1 can function as both timers or counters. When functioning as a timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are incremented in response to a 1-to-0 transition (falling edge) at their respective external input pins, T0 or T1. Timer 0 and 1 are fully compatible and can be configured in four different operating modes for use in a variety of applications, see Table 32. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. Table 32 Timer 0 and Timer 1 Modes Mode Operation 0 13-bit timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices. 1 16-bit timer The timer registers, TLx and THx, are concatenated to form a 16-bit counter. 2 8-bit timer with auto-reload The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow. 3 Timer 0 operates as two 8-bit timers The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled. Data Sheet 93 V1.2, 2009-07 XC886/888CLM Functional Description 3.18 Timer 2 and Timer 21 Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode, see Table 33. As a timer, the timers count with an input clock of PCLK/12 (if prescaler is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is PCLK/24 (if prescaler is disabled). Table 33 Timer 2 Modes Mode Description Auto-reload Up/Down Count Disabled * Count up only * Start counting from 16-bit reload value, overflow at FFFFH * Reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well * Programmble reload value in register RC2 * Interrupt is generated with reload event Up/Down Count Enabled * Count up or down, direction determined by level at input pin T2EX * No interrupt is generated * Count up - Start counting from 16-bit reload value, overflow at FFFFH - Reload event triggered by overflow condition - Programmble reload value in register RC2 * Count down - Start counting from FFFFH, underflow at value defined in register RC2 - Reload event triggered by underflow condition - Reload value fixed at FFFFH Channel capture Data Sheet * * * * * * * Count up only Start counting from 0000H, overflow at FFFFH Reload event triggered by overflow condition Reload value fixed at 0000H Capture event triggered by falling/rising edge at pin T2EX Captured timer value stored in register RC2 Interrupt is generated with reload or capture event 94 V1.2, 2009-07 XC886/888CLM Functional Description 3.19 Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and multi-phase machines. The timer T12 can function in capture and/or compare mode for its three channels. The timer T13 can work in compare mode only. The multi-channel control unit generates output patterns, which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation. Timer T12 Features * * * * * * * * * Three capture/compare channels, each channel can be used either as a capture or as a compare channel Supports generation of a three-phase PWM (six outputs, individual signals for highside and lowside switches) 16-bit resolution, maximum count frequency = peripheral clock frequency Dead-time control for each channel to avoid short-circuits in the power stage Concurrent update of the required T12/13 registers Generation of center-aligned and edge-aligned PWM Supports single-shot mode Supports many interrupt request sources Hysteresis-like control mode Timer T13 Features * * * * * One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock frequency Can be synchronized to T12 Interrupt generation at period-match and compare-match Supports single-shot mode Additional Features * * * * * * * Implements block commutation for Brushless DC-drives Position detection via Hall-sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage The block diagram of the CCU6 module is shown in Figure 33. Data Sheet 95 V1.2, 2009-07 XC886/888CLM Functional Description module kernel compare 1 channel 2 1 multichannel control compare channel 3 compare capture T13 compare start compare interrupt control 1 2 3 2 2 trap control 3 trap input clock control channel 1 deadtime control output select T12 1 Hall input address decoder output select channel 0 1 CTRAP CCPOS2 CCPOS1 CCPOS0 CC62 COUT62 CC61 COUT61 CC60 COUT60 COUT63 T13HR T12HR input / output control port control CCU6_block_diagram Figure 33 Data Sheet CCU6 Block Diagram 96 V1.2, 2009-07 XC886/888CLM Functional Description 3.20 Controller Area Network (MultiCAN) The MultiCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B active. Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share a common set of message objects, where each message object may be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects may be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organized in double chained lists, where each CAN node has it's own list of message objects. A CAN node stores frames only into message objects that are allocated to the list of the CAN node. It only transmits messages from objects of this list. A powerful, command driven list controller performs all list operations. The bit timings for the CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects each CAN node to a bus transceiver. MultiCAN Module Kernel CANSRC[7:0] Interrupt Controller fCAN Clock Control Message Object Buffer 32 Objects Address Decoder & Data control Linked List Control CAN Node 1 CAN Node 0 TXDC1 RXDC1 TXDC0 Port Control RXDC0 A[13: 2] D[31:0] Access Mediator CAN Control MultiCAN_XC8_overview Figure 34 Overview of the MultiCAN Features * Compliant to ISO 11898. Data Sheet 97 V1.2, 2009-07 XC886/888CLM Functional Description * * * * * * * * * * CAN functionality according to CAN specification V2.0 B active. Dedicated control registers are provided for each CAN node. A data transfer rate up to 1 MBaud is supported. Flexible and powerful message transfer control and error handling capabilities are implemented. Advanced CAN bus bit timing analysis and baud rate detection can be performed for each CAN node via the frame counter. Full-CAN functionality: A set of 32 message objects can be individually - allocated (assigned) to any CAN node - configured as transmit or receive object - setup to handle frames with 11-bit or 29-bit identifier - counted or assigned a timestamp via a frame counter - configured to remote monitoring mode Advanced Acceptance Filtering: - Each message object provides an individual acceptance mask to filter incoming frames. - A message object can be configured to accept only standard or only extended frames or to accept both standard and extended frames. - Message objects can be grouped into 4 priority classes. - The selection of the message to be transmitted first can be performed on the basis of frame identifier, IDE bit and RTR bit according to CAN arbitration rules. Advanced Message Object Functionality: - Message Objects can be combined to build FIFO message buffers of arbitrary size, which is only limited by the total number of message objects. - Message objects can be linked to form a gateway to automatically transfer frames between 2 different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways may be defined. Advanced Data Management: - The Message objects are organized in double chained lists. - List reorganizations may be performed any time, even during full operation of the CAN nodes. - A powerful, command driven list controller manages the organization of the list structure and ensures consistency of the list. - Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation. - Static Allocation Commands offer compatibility with TwinCAN applications, which are not list based. Advanced Interrupt Handling: - Up to 8 interrupt output lines are available. Most interrupt requests can be individually routed to one of the 8 interrupt output lines. - Message postprocessing notifications can be flexibly aggregated into a dedicated register field of 64 notification bits. Data Sheet 98 V1.2, 2009-07 XC886/888CLM Functional Description 3.21 Analog-to-Digital Converter The XC886/888 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at Port 2. Features * * * * * * * * * * * * * * * * * * Successive approximation 8-bit or 10-bit resolution (TUE of 1 LSB and 2 LSB, respectively) Eight analog channels Four independent result registers Result data protection for slow CPU access (wait-for-read mode) Single conversion mode Autoscan functionality Limit checking for conversion results Data reduction filter (accumulation of up to 2 conversion results) Two independent conversion request sources with programmable priority Selectable conversion request trigger Flexible interrupt generation with configurable service nodes Programmable sample time Programmable clock divider Cancel/restart feature for running conversions Integrated sample and hold circuitry Compensation of offset errors Low power modes 3.21.1 ADC Clocking Scheme A common module clock fADC generates the various clock signals used by the analog and digital parts of the ADC module: * * * fADCA is input clock for the analog part. fADCI is internal clock for the analog part (defines the time base for conversion length and the sample time). This clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle for the analog components. fADCD is input clock for the digital part. The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz. Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register Data Sheet 99 V1.2, 2009-07 XC886/888CLM Functional Description GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required. f ADC = fPCLK fADCD arbiter registers interrupts digital part fADCA CTC / 32 f ADCI /4 MUX /3 /2 clock prescaler analog components analog part Condition: f ADCI 10 MHz, where t ADCI = Figure 35 1 f ADCI ADC Clocking Scheme For module clock fADC = 24 MHz, the analog clock fADCI frequency can be selected as shown in Table 34. Table 34 fADCI Frequency Selection Module Clock fADC CTC Prescaling Ratio Analog Clock fADCI 24 MHz 00B /2 12 MHz (N.A) 01B /3 8 MHz 10B /4 6 MHz 11B (default) / 32 750 kHz As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00B when fADC is 24 MHz. During slow-down mode where fADC may be reduced to 12 MHz, 6 MHz etc., CTC can be set to 00B as long as the divided analog clock fADCI does not exceed 10 MHz. Data Sheet 100 V1.2, 2009-07 XC886/888CLM Functional Description However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if fADC becomes too low during slow-down mode. 3.21.2 ADC Conversion Sequence The analog-to-digital conversion procedure consists of the following phases: * * * * Synchronization phase (tSYN) Sample phase (tS) Conversion phase Write result phase (tWR) conversion start trigger Source interrupt Sample Phase Channel interrupt Result interrupt Conversion Phase fADCI BUSY Bit SAMPLE Bit tSYN tS Write Result Phase tCONV Figure 36 Data Sheet tWR ADC Conversion Timing 101 V1.2, 2009-07 XC886/888CLM Functional Description 3.22 On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: * * * * Use the built-in debug functionality of the XC800 Core Add a minimum of hardware overhead Provide support for most of the operations by a Monitor Program Use standard interfaces to communicate with the Host (a Debugger) Features * * * * * Set breakpoints on instruction address and on address range within the Program Memory Set breakpoints on internal RAM address range Support unlimited software breakpoints in Flash/RAM code region Process external breaks via JTAG and upon activating a dedicated pin Step through the program code The OCDS functional blocks are shown in Figure 37. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control signals and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-stack). The OCDS system is accessed through the JTAG1), which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application. The dedicated MBC pin is used for external configuration and debugging control. Note: All the debug functionality described here can normally be used only after XC886/888 has been started in OCDS mode. 1) The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports (Ports 1 and 2/Port 5). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system. Data Sheet 102 V1.2, 2009-07 XC886/888CLM Functional Description JTAG Module Debug Interface TMS TCK TDI TDO JTAG Memory Control Unit TCK TDI TDO Control User Program Memory Boot/ Monitor ROM User Internal RAM Monitor RAM Reset Monitor Mode Control MBC Monitor & Bootstrap loader Control line System Control Unit Suspend Control Reset Clock - parts of OCDS Reset Clock Debug PROG PROG Memory Interface & IRAM Data Control Addresses XC800 Core OCDS_XC886C-Block_Diagram-UM-v0.2 Figure 37 3.22.1 OCDS Block Diagram JTAG ID Register This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is also true immediately after reset. The JTAG ID register contents for the XC886/888 Flash devices are given in Table 35. Table 35 JTAG ID Summary Device Type Device Name JTAG ID Flash XC886/888*-8FF 1012 0083H XC886/888*-6FF 1012 5083H XC886/888*-8RF 1013 C083H XC886/888*-6RF 1013 D083H ROM Note: The asterisk (*) above denotes all possible device configurations. Data Sheet 103 V1.2, 2009-07 XC886/888CLM Functional Description 3.23 Chip Identification Number The XC886/888 identity (ID) register is located at Page 1 of address B3H. The value of ID register is 09H for Flash devices and 22H for ROM devices. However, for easy identification of product variants, the Chip Identification Number, which is an unique number assigned to each product variant, is available. The differentiation is based on the product, variant type and device step information. Two methods are provided to read a device's chip identification number: * * In-application subroutine, GET_CHIP_INFO Bootstrap loader (BSL) mode A Table 36 lists the chip identification numbers of available XC886/888 Flash and ROM device variants. Table 36 Chip Identification Number Product Variant Chip Identification Number AA-Step AB-Step AC-Step XC886CLM-8FFA 3V3 - 09500102H 0B500102H XC888CLM-8FFA 3V3 - 09500103H 0B500103H XC886LM-8FFA 3V3 - 09500122H 0B500122H XC888LM-8FFA 3V3 - 09500123H 0B500123H XC886CLM-6FFA 3V3 - 09551502H 0B551502H XC888CLM-6FFA 3V3 - 09551503H 0B551503H XC886LM-6FFA 3V3 - 09551522H 0B551522H XC888LM-6FFA 3V3 - 09551523H 0B551523H XC886CM-8FFA 3V3 - 09580102H 0B580102H XC888CM-8FFA 3V3 - 09580103H 0B580103H XC886C-8FFA 3V3 - 09580142H 0B580142H XC888C-8FFA 3V3 - 09580143H 0B580143H XC886-8FFA 3V3 - 09580162H 0B580162H XC888-8FFA 3V3 - 09580163H 0B580163H XC886CM-6FFA 3V3 - 095D1502H 0B5D1502H XC888CM-6FFA 3V3 - 095D1503H 0B5D1503H XC886C-6FFA 3V3 - 095D1542H 0B5D1542H XC888C-6FFA 3V3 - 095D1543H 0B5D1543H Flash Devices Data Sheet 104 V1.2, 2009-07 XC886/888CLM Functional Description Table 36 Chip Identification Number (cont'd) Product Variant Chip Identification Number AA-Step AB-Step AC-Step XC886-6FFA 3V3 - 095D1562H 0B5D1562H XC888-6FFA 3V3 - 095D1563H 0B5D1563H XC886CLM-8FFA 5V - 09900102H 0B900102H XC888CLM-8FFA 5V - 09900103H 0B900103H XC886LM-8FFA 5V - 09900122H 0B900122H XC888LM-8FFA 5V - 09900123H 0B900123H XC886CLM-6FFA 5V - 09951502H 0B951502H XC888CLM-6FFA 5V - 09951503H 0B951503H XC886LM-6FFA 5V - 09951522H 0B951522H XC888LM-6FFA 5V - 09951523H 0B951523H XC886CM-8FFA 5V - 09980102H 0B980102H XC888CM-8FFA 5V - 09980103H 0B980103H XC886C-8FFA 5V - 09980142H 0B980142H XC888C-8FFA 5V - 09980143H 0B980143H XC886-8FFA 5V - 09980162H 0B980162H XC888-8FFA 5V - 09980163H 0B980163H XC886CM-6FFA 5V - 099D1502H 0B9D1502H XC888CM-6FFA 5V - 099D1503H 0B9D1503H XC886C-6FFA 5V - 099D1542H 0B9D1542H XC888C-6FFA 5V - 099D1543H 0B9D1543H XC886-6FFA 5V - 099D1562H 0B9D1562H XC888-6FFA 5V - 099D1563H 0B9D1563H XC886CLM-8RFA 3V3 22400502H - - XC888CLM-8RFA 3V3 22400503H - - XC886LM-8RFA 3V3 22400522H - - XC888LM-8RFA 3V3 22400523H - - XC886CLM-6RFA 3V3 22411502H - - XC888CLM-6RFA 3V3 22411503H - - ROM Devices Data Sheet 105 V1.2, 2009-07 XC886/888CLM Functional Description Table 36 Chip Identification Number (cont'd) Product Variant Chip Identification Number AA-Step AB-Step AC-Step XC886LM-6RFA 3V3 22411522H - - XC888LM-6RFA 3V3 22411523H - - XC886CM-8RFA 3V3 22480502H - - XC888CM-8RFA 3V3 22480503H - - XC886C-8RFA 3V3 22480542H - - XC888C-8RFA 3V3 22480543H - - XC886-8RFA 3V3 22480562H - - XC888-8RFA 3V3 22480563H - - XC886CM-6RFA 3V3 22491502H - - XC888CM-6RFA 3V3 22491503H - - XC886C-6RFA 3V3 22491542H - - XC888C-6RFA 3V3 22491543H - - XC886-6RFA 3V3 22491562H - - XC888-6RFA 3V3 22491563H - - XC886CLM-8RFA 5V 22800502H - - XC888CLM-8RFA 5V 22800503H - - XC886LM-8RFA 5V 22800522H - - XC888LM-8RFA 5V 22800523H - - XC886CLM-6RFA 5V 22811502H - - XC888CLM-6RFA 5V 22811503H - - XC886LM-6RFA 5V 22811522H - - XC888LM-6RFA 5V 22811523H - - XC886CM-8RFA 5V 22880502H - - XC888CM-8RFA 5V 22880503H - - XC886C-8RFA 5V 22880542H - - XC888C-8RFA 5V 22880543H - - XC886-8RFA 5V 22880562H - - XC888-8RFA 5V 22880563H - - XC886CM-6RFA 5V 22891502H - - Data Sheet 106 V1.2, 2009-07 XC886/888CLM Functional Description Table 36 Chip Identification Number (cont'd) Product Variant Chip Identification Number AA-Step AB-Step AC-Step XC888CM-6RFA 5V 22891503H - - XC886C-6RFA 5V 22891542H - - XC888C-6RFA 5V 22891543H - - XC886-6RFA 5V 22891562H - - XC888-6RFA 5V 22891563H - - Data Sheet 107 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4 Electrical Parameters Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the XC886/888. 4.1 General Parameters The general parameters are described here to aid the users in interpreting the parameters mainly in Section 4.2 and Section 4.3. 4.1.1 Parameter Interpretation The parameters listed in this section represent partly the characteristics of the XC886/888 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the "Symbol" column: * * CC These parameters indicate Controller Characteristics, which are distinctive features of the XC886/888 and must be regarded for a system design. SR These parameters indicate System Requirements, which must be provided by the microcontroller system in which the XC886/888 is designed in. Data Sheet 108 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.1.2 Absolute Maximum Rating Maximum ratings are the extreme limits to which the XC886/888 can be subjected to without permanent damage. Table 4-1 Absolute Maximum Rating Parameters Parameter Symbol TA Storage temperature TST Junction temperature TJ Voltage on power supply pin with VDDP respect to VSS Voltage on any pin with respect VIN to VSS Ambient temperature Input current on any pin during overload condition IIN Absolute sum of all input currents |IIN| during overload condition Limit Values Unit Notes min. max. -40 125 C under bias -65 150 C 1) -40 150 C under bias1) -0.5 6 V 1) -0.5 VDDP + V whichever is lower1) -10 10 mA 1) - 50 mA 1) 0.5 or max. 6 1) Not subjected to production test, verified by design/characterization. Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pin with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 109 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.1.3 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the XC886/888. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 37 Operating Condition Parameters Parameter Digital power supply voltage Digital power supply voltage Digital ground voltage Digital core supply voltage System Clock Frequency1) Ambient temperature Symbol VDDP VDDP VSS VDDC fSYS TA Limit Values min. max. Unit Notes/ Conditions 4.5 5.5 V 5V Device 3.0 3.6 V 3.3V Device 0 V 2.3 2.7 V 88.8 103.2 MHz -40 85 C SAFXC886/888... -40 125 C SAKXC886/888... 1) fSYS is the PLL output clock. During normal operating mode, CPU clock is fSYS / 4. Please refer to Figure 26 for detailed description. Data Sheet 110 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.2 DC Parameters The electrical characteristics of the DC Parameters are detailed in this section. 4.2.1 Input/Output Characteristics Table 38 provides the characteristics of the input/output pins of the XC886/888. Table 38 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol Limit Values min. Unit Test Conditions max. VDDP = 5 V Range Output low voltage VOL CC - 1.0 V - 1.0 V IOL = 15 mA IOL = 5 mA, current into all pins > 60 mA - 0.4 V IOL = 5 mA, current into all pins 60 mA Output high voltage VOH CC VDDP - - 1.0 V IOH = -15 mA VDDP - - V IOH = -5 mA, current VDDP - - V from all pins > 60 mA 1.0 from all pins 60 mA 0.4 Input low voltage on VILP port pins (all except P0.0 & P0.1) 0.3 x SR - VILP0 SR -0.2 Input low voltage on RESET pin VILR SR - Input low voltage on TMS pin VILT SR - Input high voltage on P0.0 & P0.1 Data Sheet VIHP0 V CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode - V CMOS Mode VDDP V CMOS Mode VDDP Input low voltage on P0.0 & P0.1 Input high voltage on VIHP port pins (all except P0.0 & P0.1) IOH = -5 mA, current 0.3 x VDDP 0.3 x VDDP 0.3 x VDDP SR 0.7 x VDDP SR 0.7 x VDDP 111 V1.2, 2009-07 XC886/888CLM Electrical Parameters Table 38 Input/Output Characteristics (Operating Conditions apply) (cont'd) Parameter Symbol Limit Values min. Unit Test Conditions max. Input high voltage on RESET pin VIHR SR 0.7 x - V CMOS Mode Input high voltage on TMS pin VIHT SR 0.75 x - V CMOS Mode V CMOS Mode1) V 1) VDDP VDDP Input Hysteresis on port HYSP CC 0.07 x - pins VDDP Input Hysteresis on XTAL1 Input low voltage at XTAL1 Input high voltage at XTAL1 Pull-up current HYSX CC 0.07 x - VDDC VILX SR VSS 0.3 x VDDC 0.5 VIHX SR 0.7 x VDDC + VDDC 0.5 IPU SR - -10 IPD IOZ1 IILX Overload current on any IOV Input current at XTAL1 A A 10 A - A CC -1 1 A CC -10 10 A SR -5 5 mA SR - 150 Input leakage current V - -150 Pull-down current V VIHP,min VILP,max VILP,max VIHP,min 0 < VIN < VDDP, TA 125C2) pin Absolute sum of overload currents |IOV| SR - 25 mA 3) Voltage on any pin during VDDP power off VPO SR - 0.3 V 4) Maximum current per IM SR SR - pin (excluding VDDP and VSS) 15 mA Maximum current for all |IM| pins (excluding VDDP and VSS) 90 mA 120 mA Maximum current into VDDP Data Sheet SR - IMVDDP SR - 112 3) V1.2, 2009-07 XC886/888CLM Electrical Parameters Table 38 Input/Output Characteristics (Operating Conditions apply) (cont'd) Parameter Symbol Limit Values min. Maximum current out of IMVSS Unit Test Conditions max. SR - 120 mA 3) CC - 1.0 V - 0.4 V VSS VDDP = 3.3 V Range Output low voltage Output high voltage VOL VOH CC VDDP - - 1.0 V IOL = 8 mA IOL = 2.5 mA IOH = -8 mA VDDP - - V IOH = -2.5 mA V CMOS Mode V CMOS Mode V CMOS Mode V CMOS Mode - V CMOS Mode VDDP V CMOS Mode 0.4 Input low voltage on VILP port pins (all except P0.0 & P0.1) 0.3 x SR - VDDP Input low voltage on P0.0 & P0.1 VILP0 SR -0.2 Input low voltage on RESET pin VILR SR - Input low voltage on TMS pin VILT SR - Input high voltage on VIHP port pins (all except P0.0 & P0.1) 0.3 x VDDP 0.3 x VDDP 0.3 x VDDP SR 0.7 x VDDP Input high voltage on P0.0 & P0.1 VIHP0 SR 0.7 x Input high voltage on RESET pin VIHR SR 0.7 x - V CMOS Mode Input high voltage on TMS pin VIHT SR 0.75 x - V CMOS Mode Input Hysteresis HYS CC 0.03 x - V CMOS Mode1) V 1) VDDP VDDP VDDP VDDP Input Hysteresis on XTAL1 Input low voltage at XTAL1 Data Sheet HYSX CC 0.07 x - VDDC VILX SR VSS 0.3 x VDDC 0.5 113 V V1.2, 2009-07 XC886/888CLM Electrical Parameters Table 38 Input/Output Characteristics (Operating Conditions apply) (cont'd) Parameter Symbol Limit Values min. Input high voltage at XTAL1 VIHX SR 0.7 x Pull-up current IPU SR - VDDC Input leakage current IPD IOZ1 IILX Overload current on any IOV Input current at XTAL1 max. VDDC + V 0.5 -5 A - A 5 A 50 - A CC -1 1 A CC - 10 10 A SR -5 5 mA -50 Pull-down current Unit Test Conditions SR - VIHP,min VILP,max VILP,max VIHP,min 0 < VIN < VDDP, TA 125C2) pin Absolute sum of overload currents |IOV| SR - 25 mA 3) Voltage on any pin during VDDP power off VPO SR - 0.3 V 4) Maximum current per IM SR SR - pin (excluding VDDP and VSS) 15 mA Maximum current for all |IM| pins (excluding VDDP and VSS) 90 mA 120 mA 3) 120 mA 3) Maximum current into VDDP SR - IMVDDP SR - Maximum current out of IMVSS SR - VSS 1) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 2) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and RESET pin have internal pull devices and are not included in the input leakage current characteristic. 3) Not subjected to production test, verified by design/characterization. 4) Not subjected to production test, verified by design/characterization. However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. Data Sheet 114 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.2.2 Supply Threshold Characteristics Table 39 provides the characteristics of the supply threshold in the XC886/888. 5.0V VDDPPW VDDP 2.5V VDDCPW VDDCBO VDDC VDDCRDR VDDCBOPD VDDCPOR Figure 38 Supply Threshold Parameters Table 39 Supply Threshold Parameters (Operating Conditions apply) Parameters Symbol 1) Limit Values Unit min. typ. max. CC 2.2 2.3 2.4 V VDDC prewarning voltage VDDC brownout voltage in VDDCPW VDDCBO CC 2.0 2.1 2.2 V RAM data retention voltage VDDCRDR CC VDDCBOPD CC 0.9 1.0 1.1 V 1.3 1.5 1.7 V VDDPPW VDDCPOR CC 3.4 4.0 4.6 V CC 1.3 1.5 1.7 V 1) active mode VDDC brownout voltage in 2) power-down mode VDDP prewarning voltage3) 2)4) Power-on reset voltage 1) Detection is disabled in power-down mode. 2) Detection is enabled in both active and power-down mode. 3) Detection is enabled for external power supply of 5.0V. Detection must be disabled for external power supply of 3.3V. 4) The reset of EVR is extended by 300 s typically after the VDDC reaches the power-on reset voltage. Data Sheet 115 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.2.3 ADC Characteristics The values in the table below are given for an analog power supply between 4.5 V to 5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case, the analog parameters may show a reduced performance. All ground pins (VSS) must be externally connected to one single star point in the system. The voltage difference between the ground pins must not exceed 200mV. Table 40 ADC Characteristics (Operating Conditions apply; VDDP = 5V Range) Parameter Symbol Limit Values min. typ . max. Unit Test Conditions/ Remarks Analog reference voltage VAREF SR VAGND VDDP +1 VDDP V 1) Analog reference ground VAGND SR VSS 0.05 VAREF V 1) Analog input voltage range VAIN SR VAGND - ADC clocks fADC fADCI VSS + 0.05 -1 VAREF V - 24 25.8 MHz module clock1) - - 10 MHz internal analog clock1) See Figure 35 1) tS CC (2 + INPCR0.STC) x s Conversion time tC CC See Section 4.2.3.1 s Total unadjusted error |TUE| CC - - 1 LSB 8-bit conversion2) - - 2 LSB 10-bit conversion2) Differential Nonlinearity |EADNL| CC - 1 - LSB 10-bit conversion1) Integral Nonlinearity |EAINL| CC - 1 - LSB 10-bit conversion1) Offset |EAOFF| CC - 1 - LSB 10-bit conversion1) Gain |EAGAIN| CC - 1 - LSB 10-bit conversion1) Overload current coupling factor for analog inputs KOVA CC - - 1.0 x 10-4 - IOV > 01)3) - - 1.5 x 10-3 - IOV < 01)3) Sample time Data Sheet tADCI 116 1) V1.2, 2009-07 XC886/888CLM Electrical Parameters Table 40 ADC Characteristics (Operating Conditions apply; VDDP = 5V Range) Parameter Symbol Limit Values min. Unit Test Conditions/ Remarks typ . max. CC - - 5.0 x 10-3 - IOV > 01)3) - - 1.0 x 10-2 - IOV < 01)3) Overload current coupling factor for digital I/O pins KOVD Switched capacitance at the reference voltage input CAREFSW CC - 10 20 pF 1)4) Switched capacitance at the analog voltage inputs CAINSW CC - 5 7 pF 1)5) Input resistance of RAREF the reference input CC - 1 2 k 1) Input resistance of RAIN the selected analog channel CC - 1 1.5 k 1) 1) Not subjected to production test, verified by design/characterization 2) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDDP = 5.0 V. 3) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error current adds to the respective pin's leakage current (IOZ). The amount of error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ1| + (|IOV| x KOV). The additional error current may distort the input voltage on analog inputs. 4) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this, smaller capacitances are successively switched to the reference voltage. 5) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2. Data Sheet 117 V1.2, 2009-07 XC886/888CLM Electrical Parameters Analog Input Circuitry REXT VAIN RAIN, On ANx CEXT C AINSW VAGNDx Reference Voltage Input Circuitry R AREF, On VAREFx VAREF C AREFSW VAGNDx Figure 39 Data Sheet ADC Input Circuits 118 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.2.3.1 ADC Conversion Timing Conversion time, tC = tADC x ( 1 + r x (3 + n + STC) ) , where r = CTC + 2 for CTC = 00B, 01B or 10B, r = 32 for CTC = 11B, CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC), n = 8 or 10 (for 8-bit and 10-bit conversion respectively), tADC = 1 / fADC Data Sheet 119 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.2.4 Power Supply Current Table 41, Table 42, Table 43 and Table 44 provide the characteristics of the power supply current in the XC886/888. Table 41 Power Supply Current Parameters (Operating Conditions apply; VDDP = 5V range) Parameter Symbol Limit Values typ.1) Unit Test Condition max.2) VDDP = 5V Range Active Mode Idle Mode IDDP IDDP Active Mode with slow-down enabled IDDP Idle Mode with slow-down enabled IDDP 27.2 32.8 mA Flash Device3) 24.3 29.8 mA ROM Device3) 21.1 25.3 mA Flash Device4) 18.2 21.6 mA ROM Device4) 14.1 17.0 mA Flash Device5) 11.9 14.3 mA ROM Device5) 11.7 15.0 mA Flash Device6) 9.7 11.9 mA ROM Device6) 1) The typical IDDP values are periodically measured at TA = + 25 C and VDDP = 5.0 V. 2) The maximum IDDP values are measured under worst case conditions (TA = + 125 C and VDDP = 5.5 V). 3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001B), RESET = VDDP, no load on ports. 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 MHz, RESET = VDDP, no load on ports. 5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP, no load on ports. 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP, no load on ports. Data Sheet 120 V1.2, 2009-07 XC886/888CLM Electrical Parameters Table 42 Power Down Current (Operating Conditions apply; VDDP = 5V range) Parameter Symbol Limit Values typ.1) Unit Test Condition max.2) VDDP = 5V Range Power-Down Mode IPDP 1 10 A - 30 A TA = + 25 C3)4) TA = + 85 C4)5) 1) The typical IPDP values are measured at VDDP = 5.0 V. 2) The maximum IPDP values are measured at VDDP = 5.5 V. 3) IPDP has a maximum value of 200 A at TA = + 125 C. 4) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. 5) Not subjected to production test, verified by design/characterization. Data Sheet 121 V1.2, 2009-07 XC886/888CLM Electrical Parameters Table 43 Power Supply Current Parameters (Operating Conditions apply; VDDP = 3.3V range) Parameter Symbol Limit Values typ.1) Unit Test Condition max.2) VDDP = 3.3V Range Active Mode Idle Mode IDDP IDDP Active Mode with slow-down enabled IDDP Idle Mode with slow-down enabled IDDP 25.6 31.0 mA Flash Device3) 23.4 28.6 mA ROM Device3) 19.9 24.7 mA Flash Device4) 17.5 20.7 mA ROM Device4) 13.3 16.2 mA Flash Device5) 11.5 13.7 mA ROM Device5) 11.1 14.4 mA Flash Device6) 9.3 11.4 mA ROM Device6) 1) The typical IDDP values are periodically measured at TA = + 25 C and VDDP = 3.3 V. 2) The maximum IDDP values are measured under worst case conditions (TA = + 125 C and VDDP = 3.6 V). 3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001B), RESET = VDDP, no load on ports. 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 MHz, RESET = VDDP, no load on ports. 5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP, no load on ports. 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110B,, RESET = VDDP, no load on ports. Data Sheet 122 V1.2, 2009-07 XC886/888CLM Electrical Parameters Table 44 Power Down Current (Operating Conditions apply; VDDP = 3.3V range) Parameter Symbol Limit Values typ.1) Unit Test Condition max.2) VDDP = 3.3V Range Power-Down Mode IPDP 1 10 A - 30 A TA = + 25 C3)4) TA = + 85 C4)5) 1) The typical IPDP values are measured at VDDP = 3.3 V. 2) The maximum IPDP values are measured at VDDP = 3.6 V. 3) IPDP has a maximum value of 200 A at TA = + 125 C. 4) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. 5) Not subjected to production test, verified by design/characterization. Data Sheet 123 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.3 AC Parameters The electrical characteristics of the AC Parameters are detailed in this section. 4.3.1 Testing Waveforms The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 40, Figure 41 and Figure 42. VDDP 90% 10% 10% VSS Figure 40 90% tF tR Rise/Fall Time Parameters VDDP VDDE / 2 Test Points VDDE / 2 VSS Figure 41 Testing Waveform, Output Delay VLoad + 0.1 V VLoad - 0.1 V Figure 42 Data Sheet Timing Reference Points VOH - 0.1 V VOL - 0.1 V Testing Waveform, Output High Impedance 124 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.3.2 Output Rise/Fall Times Table 45 provides the characteristics of the output rise/fall times in the XC886/888. Table 45 Output Rise/Fall Times Parameters (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. VDDP = 5V Range Rise/fall times t R , tF - 10 ns 20 pF.1)2)3) t R , tF - 10 ns 20 pF.1)2)4) VDDP = 3.3V Range Rise/fall times 1) Rise/Fall time measurements are taken with 10% - 90% of pad supply. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF. 4) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.225 ns/pF. VDDP 90% 90% VSS 10% 10% tF tR Figure 43 Data Sheet Rise/Fall Times Parameters 125 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.3.3 Power-on Reset and PLL Timing Table 49 provides the characteristics of the power-on reset and PLL timing in the XC886/888. Table 46 Power-On Reset and PLL Timing (Operating Conditions apply) Parameter Symbol Limit Values min. typ. Pad operating voltage On-Chip Oscillator start-up time Flash initialization time RESET hold time PLL lock-in in time PLL accumulated jitter Unit Test Conditions max. VPAD tOSCST CC 2.3 - - V 1) CC - - 500 ns 1) tFINIT tRST CC - 160 - s 1) SR - 500 - s VDDP rise time tLOCK DP CC - - 200 s 1) - - 0.7 ns 1)3) (10% - 90%) 500s1)2) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 2) RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5 V). 3) PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1. Data Sheet 126 V1.2, 2009-07 XC886/888CLM Electrical Parameters VDDP VPAD VDDC tOSCST OSC PLL unlock PLL PLL lock tLOCK Flash State Reset Initialization tFINIT tRST Ready to Read RESET Pads 1) 3) 2) 1)Pad state undefined I)until EVR is stable Figure 44 Data Sheet 2)ENPS control 3)As Programmed II)until PLL is locked III) until Flash go IV) CPU reset is released; Boot to Ready-to-Read ROM software begin execution Power-on Reset Timing 127 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.3.4 On-Chip Oscillator Characteristics Table 47 provides the characteristics of the on-chip oscillator in the XC886/888. Table 47 On-chip Oscillator Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Nominal frequency fNOM CC Long term frequency fLT deviation CC Short term frequency fST CC deviation 9.36 9.6 9.84 MHz under nominal conditions1) -5.0 - 5.0 % with respect to fNOM, over lifetime and temperature (-10C to 125C), for one given device after trimming -6.0 - 0 % with respect to fNOM, over lifetime and temperature (-40C to -10C), for one given device after trimming -1.0 - 1.0 % within one LIN message (<10 ms .... 100 ms) 1) Nominal condition: VDDC = 2.5 V, TA = + 25C. Data Sheet 128 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.3.5 External Clock Drive XTAL1 Table 48 shows the parameters that define the external clock supply for XC886/888. These timing parameters are based on the direct XTAL1 drive of clock input signals. They are not applicable if an external crystal or ceramic resonator is considered. Table 48 External Clock Drive Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. tosc t1 t2 t3 t4 Oscillator period High time Low time Rise time Fall time Unit Test Conditions Max. SR 83.3 250 ns 1)2) SR 25 - ns 2)3) SR 25 - ns 2)3) SR - 20 ns 2)3) SR - 20 ns 2)3) 1) The clock input signals with 45-55% duty cycle are used. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 3) The clock input signal must reach the defined levels VILX and VIHX. t1 t3 t4 VIHX 0.5 V DDC VILX t2 tOSC Figure 45 Data Sheet External Clock Drive XTAL1 129 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.3.6 JTAG Timing Table 49 provides the characteristics of the JTAG timing in the XC886/888. Table 49 TCK Clock Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits min TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time tTCK t1 t2 t3 t4 Unit Test Conditions max SR 50 - ns 1) SR 20 - ns 1) SR 20 - ns 1) SR - 4 ns 1) SR - 4 ns 1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 0.9 V DDP 0.5 V DDP TCK 0.1 V DDP t1 t TCK t2 t4 t3 Figure 46 TCK Clock Timing Table 50 JTAG Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits min Unit Test Conditions max TMS setup to TCK t1 SR 8 - ns 1) TMS hold to TCK t2 SR 24 - ns 1) TDI setup to TCK t1 SR 11 - ns 1) TDI hold to TCK t2 SR 24 - ns 1) TDO valid output from TCK t3 CC - 21 ns 5V Device1) - 28 ns 3.3V Device1) Data Sheet 130 V1.2, 2009-07 XC886/888CLM Electrical Parameters Table 50 JTAG Timing (Operating Conditions apply; CL = 50 pF) (cont'd) Parameter Symbol Limits min TDO high impedance to valid output from TCK t4 TDO valid output to high impedance from TCK t5 CC CC Unit Test Conditions max - 27 ns 5V Device1) - 36 ns 3.3V Device1) - 22 ns 5V Device1) - 28 ns 3.3V Device1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. TCK t1 t2 t1 t2 TMS TDI t4 t3 t5 TDO Figure 47 Data Sheet JTAG Timing 131 V1.2, 2009-07 XC886/888CLM Electrical Parameters 4.3.7 SSC Master Mode Timing Table 51 provides the characteristics of the SSC timing in the XC886/888. Table 51 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limit Values min. max. Unit Test Conditions CC 2*TSSC - ns 1)2) MTSR delay from SCLK t0 t1 CC 0 8 ns 2) MRST setup to SCLK t2 SR 24 - ns 2) MRST hold from SCLK t3 SR 0 - ns 2) SCLK clock period 1) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 83.3ns. TCPU is the CPU clock period. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. t0 SCLK1) t1 t1 MTSR1) t2 t3 Data valid MRST1) t1 1) This timing is based on the following setup: CON.PH = CON.PO = 0. SSC_Tmg1 Figure 52 Data Sheet SSC Master Mode Timing 132 V1.2, 2009-07 XC886/888CLM Package and Quality Declaration 5 Package and Quality Declaration Chapter 5 provides the information of the XC886/888 package and reliability section. 5.1 Package Parameters Table 1 provides the thermal characteristics of the package used in XC886 and XC888. Table 1 Thermal Characteristics of the Packages Parameter Symbol Limit Values Min. Unit Notes Max. PG-TQFP-48 (XC886) Thermal resistance junction RTJC case CC - 13 K/W 1)2) Thermal resistance junction RTJL lead CC - 32.5 K/W 1)2) Thermal resistance junction RTJC case CC - 12.6 K/W 1)2) Thermal resistance junction RTJL lead CC - 33.4 K/W 1)2) - PG-TQFP-64 (XC888) 1) The thermal resistances between the case and the ambient (RTCA) , the lead and the ambient (RTLA) are to be combined with the thermal resistances between the junction and the case (RTJC), the junction and the lead (RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCA), the lead and the ambient (RTLA) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ=TA+RTJA x PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances, by a) simply adding only the two thermal resistances (junction lead and lead ambient), or b) by taking all four resistances into account, depending on the precision needed. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Data Sheet 133 V1.2, 2009-07 XC886/888CLM Package and Quality Declaration 5.2 Package Outline H 0.5 7 MAX. 0.125 +0.075 -0.035 0.1 0.05 1 0.05 1.2 MAX. Figure 48 shows the package outlines of the XC886. 0.6 0.15 C 5.5 0.22 0.05 0.08 2) 0.08 M A-B D C 48x 9 7 1) 0.2 A-B D 48x 0.2 A-B D H 4x D 9 B 7 1) A 48 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. per side GPP09237 Figure 48 Data Sheet PG-TQFP-48 Package Outline 134 V1.2, 2009-07 XC886/888CLM Package and Quality Declaration Figure 49 shows the package outlines of the XC888. Figure 49 Data Sheet PG-TQFP-64 Package Outline 135 V1.2, 2009-07 XC886/888CLM Package and Quality Declaration 5.3 Quality Declaration Table 2 shows the characteristics of the quality parameters in the XC886/888. Table 2 Quality Parameters Parameter Symbol Limit Values Min. Unit Notes Max. ESD susceptibility VHBM according to Human Body Model (HBM) - 2000 V Conforming to EIA/JESD22A114-B1) VCDM - 500 V Conforming to JESD22-C101-C1) ESD susceptibility according to Charged Device Model (CDM) pins 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Data Sheet 136 V1.2, 2009-07 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG