74VHC74MX - Fairchild Semiconductor

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

74VHC74 Rev. 1.3.0

February 2008

74VHC74

Dual D-Type Flip-Flop with Preset and Clear

Features

■

High Speed: f

MAX

170MHz (typ.) at T

25°C

■

High noise immunity: V

NIH

NIL

28% V

(min.)

■

Power down protection is provided on all inputs

■

Low power dissipation: I

2µA (max.) at T

25°C

■

Pin and function compatible with 74HC74

General Description

The VHC74 is an advanced high speed CMOS Dual

D-Type Flip-Flop fabricated with silicon gate CMOS

technology. It achieves the high speed operation similar

to equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation. The signal level applied to

the D input is transferred to the Q output during the posi-

tive going transition of the CK pulse. CLR and PR are

independent of the CK and are accomplished by setting

the appropriate input LOW.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74VHC74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74VHC74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74VHC74 Rev. 1.3.0 2

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

Connection Diagram

Pin Description

Logic Symbol

IEEE/IEC

Truth Table

Note:

1. This configuration is nonstable; that is, it will not persist

when preset and clear inputs return to their inactive

(HIGH) state.

Pin Names Description

, D

Data Inputs

, CK

Clock Pulse Inputs

CLR

, CLR

Direct Clear Inputs

, PR

Direct Preset Inputs

, Q

Output

Inputs Outputs

FunctionCLR PR DCK Q Q

LHXX LHClear

HLXX HLPreset

LLXXH

(1)

HHL L H

HHH H L

HHX Q

No Change

74VHC74 Rev. 1.3.0 3

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions

(2)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Note:

2. Unused inputs must be held HIGH or LOW. They may not float.

Symbol Parameter Rating

Supply Voltage –0.5V to +7.0V

DC Input Voltage –0.5V to +7.0V

OUT

DC Output Voltage –0.5V to V

+ 0.5V

Input Diode Current –20mA

Output Diode Current ±20mA

OUT

DC Output Current ±25mA

DC V

/ GND Current ±50mA

STG

Storage Temperature –65°C to +150°C

Lead Temperature (Soldering, 10 seconds) 260°C

Symbol Parameter Rating

Supply Voltage 2.0V to +5.5V

Input Voltage 0V to +5.5V

OUT

Output Voltage 0V to V

OPR

Operating Temperature –40°C to +85°C

, t

Input Rise and Fall Time,

3.3V ± 0.3V

5.0V ± 0.5V

0ns/V

∼

100ns/V

0ns/V

∼

20ns/V

74VHC74 Rev. 1.3.0 4

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

DC Electrical Characteristics

Symbol Parameter V

(V) Conditions

25°C

–40°C to

+85°C

UnitsMin. Typ. Max. Min. Max.

HIGH Level Input

Voltage

2.0 1.50 1.50 V

3.0–5.5 0.7 x V

0.7 x V

LOW Level Input

Voltage

2.0 0.50 0.50 V

3.0–5.5 0.3 x V

0.3 x V

HIGH Level

Output Voltage

2.0 V

or V

–50µA 1.9 2.0 1.9 V

3.0 2.9 3.0 2.9

4.5 4.4 4.5 4.4

3.0 I

–4mA 2.58 2.48

4.5 I

–8mA 3.94 3.80

LOW Level

Output Voltage

2.0 V

or V

50µA 0.0 0.1 0.1 V

3.0 0.0 0.1 0.1

4.5 0.0 0.1 0.1

3.0 I

4mA 0.36 0.44

4.5 I

8mA 0.36 0.44

Input Leakage

Current

0–5.5 V

5.5V or GND ±0.1 ±1.0 µA

Quiescent

Supply Current

5.5 V

or GND 2.0 20.0 µA

74VHC74 Rev. 1.3.0 5

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

AC Electrical Characteristics

Note:

3. C

is defined as the value of the internal equivalent capacitance which is calculated from the operating

current consumption without load. Average operating current can be obtained from the equation:

(opr.)

• V

• f

+ I

/ 2 (per F/F).

AC Operating Requirements

Note:

4. V

is 3.3 ± 0.3V or 5.0 ± 0.5V

Symbol Parameter V

(V) Conditions

25°C

–40°C

to +85°C

UnitsMin. Typ. Max. Min. Max.

MAX Maximum Clock

Frequency

3.3 ± 0.3 CL = 15pF 80 125 70 MHz

CL = 50pF 50 75 45

5.0 ± 0.5 CL = 15pF 130 170 110

CL = 50pF 90 115 75

tPLH, tPHL Propagation Delay

Time (CK-Q, Q)

3.3 ± 0.3 CL = 15pF 6.7 11.9 1.0 14.0 ns

CL = 50pF 9.2 15.4 1.0 17.5

5.0 ± 0.5 CL = 15pF 4.6 7.3 1.0 8.5

CL = 50pF 6.1 9.3 1.0 10.5

tPLH, tPHL Propagation Delay

Time (CLR, PR -Q, Q)

3.3 ± 0.3 CL = 15pF 7.6 12.3 1.0 14.5 ns

CL = 50pF 10.1 15.8 1.0 18.0

5.0 ± 0.5 CL = 15pF 4.8 7.7 1.0 9.0

CL = 50pF 6.3 9.7 1.0 11.0

CIN Input Capacitance VCC = Open 4 10 10 pF

CPD Power Dissipation

Capacitance

(3) 25 pF

Symbol Parameter VCC (V)(4)

TA = 25°C

TA = –40°C

to +85°C

UnitsTyp.

Guaranteed

Minimum

tW(L), tW(H) Minimum Pulse Width (CK) 3.3 6.0 7.0 ns

5.0 5.0 5.0

tW(L) Minimum Pulse Width (CLR, PR) 3.3 6.0 7.0 ns

5.0 5.0 5.0

tSMinimum Setup Time 3.3 6.0 7.0 ns

5.0 5.0 5.0

tHMinimum Hold Time 3.3 0.5 0.5 ns

5.0 0.5 0.5

tREC Minimum Recovery Time (CLR, PR) 3.3 5.0 5.0 ns

5.0 3.0 3.0

74VHC74 Rev. 1.3.0 6

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

Physical Dimensions

Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

LAND PATTERN RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD:

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

PIN ONE

INDICATOR

8°

0°

SEATING PLANE

DETAIL A

SCALE: 20:1

GAGE PLANE

0.25

X45°

0.10

BC A

14 B

SEE DETAIL A

5.60

0.65

1.70 1.27

8.75

8.50

7.62

6.00 4.00

3.80

(0.33)

1.27 0.51

0.35

1.75 MAX

1.50

1.25 0.25

0.10 0.25

0.19

(1.04)

0.90

0.50

0.36

R0.10

0.50

0.25

74VHC74 Rev. 1.3.0 7

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

Physical Dimensions (Continued)

Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74VHC74 Rev. 1.3.0 8

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

Physical Dimensions (Continued)

Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

F. DRAWING FILE NAME: MTC14REV6

R0.09 min

12.00°TOP & BOTTO

0.43 TYP

1.00

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

R0.09min

E. LANDPATTERN STANDARD: SOP65P640X110-14M

0.65

6.10

1.65

0.45

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

B. DIMENSIONS ARE IN MILLIMETERS

74VHC74 Rev. 1.3.0 9

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear

Physical Dimensions (Continued)

Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

14 8

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANCES PER

ASME Y14.5-1994

E) DRAWING FILE NAME: MKT-N14AREV7

6.60

6.09

8.12

7.62

0.35

0.20

19.56

18.80

3.56

3.30 5.33 MAX

0.38 MIN

1.77

1.14

0.58

0.35 2.54

3.81

3.17 8.82

(1.74)

74VHC74 Rev. 1.3.0 10

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Advance Information Form

First Production

ative or In Design This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

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This datasheet contains preliminary data; supplementary data will be

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Rev. I32

74VHC74 — Dual D-Type Flip-Flop with Preset and Clear