IRFP250N N-Channel Power MOSFET 200V, 30A, 0.075 Features * Peak Current vs Pulse Width Curve * Ultra Low On-Resistance - rDS(ON) = 0.052 (Typ), VGS = 10V * UIS Rating Curve * Simulation Models - Temperature Compensated PSPICE(R) and SABER(c) Electrical Models - Spice and SABER(c) Thermal Impedance Models SOURCE DRAIN GATE D DRAIN (TAB) G S TO-247 MOSFET Maximum Ratings TA = 25C unless otherwise noted Ratings Units VDSS Symbol Drain to Source Voltage Parameter 200 V VGS Gate to Source Voltage 20 V 30 A 21 A Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 10V) Figure 4 A EAS Single Pulse Avalanche Energy (Note 1) Pulsed 315 mJ PD Power dissipation Derate above 25oC 214 1.4 W W/oC TJ, TSTG Operating and Storage Temperature -55 to 175 oC 0.70 oC/W 40 oC/W Thermal Characteristics RJC Thermal Resistance Junction to Case TO-247 RJA Thermal Resistance Junction to Ambient TO-247 Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity IRFP250N IRFP250N TO-247 Tube N/A 30 (c)2002 Fairchild Semiconductor Corporation Rev .B, January 2002 IRFP250N January 2002 Symbol Parameter Test Conditions Min Typ Max Units V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250A, VGS = 0V 200 - - VDS = 200V VGS = 0V - - 25 VDS = 160V TC = 150o - - 250 VGS = 20V - - 100 A nA On Characteristics VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250A 2 - 4 V rDS(ON) Drain to Source On Resistance ID = 18A, VGS = 10V - 0.052 0.075 gfs Forward Transconductance VDS = 50V, ID = 18A (Note 2) 17 - - S Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance VDS = 25V, VGS = 0V, f = 1MHz - 4023 - pF - 880 - pF - 240 - pF 215 280 nC - 114 140 nC - 8 10 nC Qg(TOT) Total Gate Charge at 20V VGS = 0V to 20V Qg(10) Total Gate Charge at 10V VGS = 0V to 10V Qg(TH) Threshold Gate Charge Qgs Gate to Source Gate Charge - 14 - nC Qgd Gate to Drain "Miller" Charge - 44 - nC Switching Characteristics VDD = 160V ID = 18A VGS = 0V to 2V Ig = 2.0mA (VGS = 10V) tON Turn-On Time - - 69 ns td(ON) Turn-On Delay Time - 16 - ns tr Rise Time - 30 - ns td(OFF) Turn-Off Delay Time - 78 - ns tf Fall Time - 40 - ns tOFF Turn-Off Time - - 177 ns - - 1.3 V VDD = 100V, ID = 18A VGS = 10V, RGS = 3.9 Drain-Source Diode Characteristics VSD Source to Drain Diode Voltage ISD = 18A trr Reverse Recovery Time ISD = 18A, dISD/dt = 100A/s - - 279 ns QRR Reverse Recovered Charge ISD = 18A, dISD/dt = 100A/s - - 2000 nC Notes: 1: Starting TJ = 25C, L = 1.9mH, IAS = 18A. 2: Pulse width 300s; duty cycle 2%. (c)2002 Fairchild Semiconductor Corporation Rev. B, January 2002 IRFP250N Electrical Characteristics TA = 25C unless otherwise noted IRFP250N Typical Characteristic 1.2 40 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 30 VGS = 10V 20 10 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZJC, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance IDM, PEAK CURRENT (A) 1000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 100 VGS = 10V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability (c)2002 Fairchild Semiconductor Corporation Rev. B, January 2002 IRFP250N Typical Characteristic (Continued) 500 200 100 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) SINGLE PULSE TJ = MAX RATED TC = 25oC 100 100s 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 10ms 10 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 1 1 10 0.001 500 100 0.01 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.1 Figure 6. Unclamped Inductive Switching Capability 75 75 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) VGS = 10V VGS = 5V 50 25 TJ = -55oC TJ = 175oC 50 VGS =4.5V 25 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC TJ = 25oC 0 0 2 3 0 5 4 1 VGS, GATE TO SOURCE VOLTAGE (V) 3 4 5 6 Figure 8. Saturation Characteristics 1.2 3.5 3.0 2 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics VGS = VDS, ID = 250A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.0 2.5 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 10 1 tAV, TIME IN AVALANCHE (ms) Figure 5. Forward Bias Safe Operating Area ID, DRAIN CURRENT (A) STARTING TJ = 25oC STARTING TJ = 150oC 2.0 1.5 1.0 0.8 0.6 0.5 VGS = 10V, ID = 30A 0.4 0 -80 -40 0 40 80 TJ, JUNCTION TEMPERATURE 120 160 (oC) Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature (c)2002 Fairchild Semiconductor Corporation 200 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE 160 200 (oC) Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature Rev. B, January 2002 IRFP250N Typical Characteristic (Continued) 10000 1.3 VGS = 0V, f = 1MHz CISS = CGS + CGD 1.2 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.1 1.0 1000 COSS CDS + CGD 100 CRSS = CGD 30 0.9 -80 -40 0 40 80 120 160 0.1 200 TJ , JUNCTION TEMPERATURE (oC) 1.0 10 100 200 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature Figure 12. Capacitance vs Drain to Source Voltage 10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 160V 8 6 4 WAVEFORMS IN DESCENDING ORDER: 2 ID = 18A ID = 10A 0 0 20 40 60 80 100 120 Qg, GATE CHARGE (nC) Figure 13. Gate Charge Waveforms for Constant Gate Currents Test Circuits and Waveforms BVDSS VDS tP VDS L IAS VDD VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDD - VGS DUT tP 0V IAS 0 0.01 tAV Figure 14. Unclamped Energy Test Circuit (c)2002 Fairchild Semiconductor Corporation Figure 15. Unclamped Energy Waveforms Rev. B, January 2002 IRFP250N Test Circuits and Waveforms (Continued) VDS VDD Qg(TOT) RL VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS - VGS = 2V DUT 0 Ig(REF) Qg(TH) Qgs Qgd Ig(REF) 0 Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 0 Figure 18. Switching Time Test Circuit (c)2002 Fairchild Semiconductor Corporation 10% Figure 19. Switching Time Waveforms Rev. B, January 2002 IRFP250N PSPICE Electrical Model .SUBCKT IRFP250N 2 1 3 ; rev May 2001 CA 12 8 6.6e-9 CB 15 14 6.5e-9 CIN 6 8 3.80e-9 LDRAIN DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DPLCAP 10 RLDRAIN RSLC1 51 RSLC2 5 51 - IT 8 17 1 LGATE 11 + 50 17 EBREAK 18 - EVTHRES 16 21 + 19 8 + GATE 1 ESLC RDRAIN 6 8 ESG DBREAK + EBREAK 11 7 17 18 221 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 8.05e-9 LSOURCE 3 7 5.8e-9 DRAIN 2 5 EVTEMP RGATE + 18 22 9 20 6 DBODY MWEAK MMED MSTRO RLGATE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD LSOURCE CIN 8 SOURCE 3 7 RSOURCE RLSOURCE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5.0e-2 RGATE 9 20 0.77 RLDRAIN 2 5 10 RLGATE 1 9 80.5 RLSOURCE 3 7 58 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.8e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B S1A 12 13 S2A S1B CA 15 14 13 8 RBREAK 17 18 RVTEMP S2B 13 CB 6 8 VBAT 5 8 EDS - IT 14 + + EGS 19 - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),2.5))} .MODEL DBODYMOD D (IS = 2.8e-12 RS = 3.0e-3 XTI = 5.5 TRS1 = 3.5e-3 TRS2 = 1e-5 CJO = 2.55e-9 TT = 1.52e-7 M = 0.42) .MODEL DBREAKMOD D (RS = 1.2e-0 TRS1 = 1e-3 TRS2 = 1e-6) .MODEL DPLCAPMOD D (CJO = 4.6e-9 IS = 1e-30 N = 10 M = 0.9) .MODEL MMEDMOD NMOS (VTO = 3.05 KP = 2.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.77) .MODEL MSTROMOD NMOS (VTO = 3.55 KP = 100 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.69 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7.70 ) .MODEL RBREAKMOD RES (TC1 =1.27e-3 TC2 = 1.0e-6) .MODEL RDRAINMOD RES (TC1 = 9.90e-3 TC2 = 3.60e-5) .MODEL RSLCMOD RES (TC1 = 3.0e-3 TC2 = 1.0e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.90e-3 TC2 = -1.10e-5) .MODEL RVTEMPMOD RES (TC1 = -2.80e-3 TC2 = 1.70e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.5 VOFF= -4.5) VON = -4.5 VOFF= -5.5) VON = -0.3 VOFF= 0.4) VON = 0.4 VOFF= -0.3) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2002 Fairchild Semiconductor Corporation Rev. B, January 2002 REV May 2001 template IRFP250N n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.8e-12, rs = 3.0e-3, xti = 5.5, trs1 = 3.5e-3, trs2 = 1.0e-5, cjo = 2.55e-9, tt = 1.52e-7, m = 0.42) dp..model dbreakmod = (rs = 1.2, trs1 = 1.0e-3, trs2 = 1.0e-6) dp..model dplcapmod = (cjo = 4.6e-9, isl = 10e-30, nl=10, m = 0.9) m..model mmedmod = (type=_n, vto = 3.05, kp = 2.5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.55, kp = 100, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.69, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -4.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -4.5, voff = -5.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.4) LDRAIN DRAIN sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.4, voff = -0.3) DPLCAP 5 RLDRAIN RSLC1 51 RSLC2 ISCL dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod RDRAIN 6 8 ESG LGATE 11 DBODY EVTHRES 16 21 + 19 8 + GATE 1 DBREAK 50 - i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9 l.lgate n1 n9 = 8.05e-9 l.lsource n3 n7 = 5.80e-9 2 10 c.ca n12 n8 = 6.6e-9 c.cb n15 n14 = 6.5e-9 c.cin n6 n8 = 3.8e-9 EVTEMP RGATE + 18 22 9 20 6 MWEAK EBREAK + MMED MSTRO RLGATE m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u CIN 17 18 - 8 LSOURCE SOURCE 3 7 RSOURCE RLSOURCE res.rbreak n17 n18 = 1, tc1 = 1.27e-3, tc2 = 1.00e-6 res.rdrain n50 n16 = 5.0e-2, tc1 = 9.9e-3, tc2 =3.6e-5 res.rgate n9 n20 = 0.77 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 80.5 res.rlsource n3 n7 = 58 res.rslc1 n5 n51= 1e-6, tc1 = 3e-3, tc2 = -1.0e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.8e-3, tc1 = 1.0e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.8e-3, tc2 = 1.70e-6 res.rvthres n22 n8 = 1, tc1 = -2.9e-3, tc2 = 1.1e-5 S1A 12 13 S2A S1B CA RBREAK 15 14 13 8 17 18 RVTEMP S2B 13 CB 6 8 EGS - 19 IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 221 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6*100))** 2.5)) } } (c)2002 Fairchild Semiconductor Corporation Rev. B, January 2002 IRFP250N SABER Electrical Model th IRFP250N SPICE Thermal Model JUNCTION REV May 2001 IRFP250N CTHERM1 th 6 6.45e-3 CTHERM2 6 5 3.00e-2 CTHERM3 5 4 1.40e-2 CTHERM4 4 3 1.65e-2 CTHERM5 3 2 4.85e-2 CTHERM6 2 tl 1.00e-1 RTHERM1 th 6 3.24e-3 RTHERM2 6 5 8.08e-3 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 1.00e-1 RTHERM5 3 2 1.10e-1 RTHERM6 2 tl 1.40e-1 RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model IRFP250N template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.45e-3 ctherm.ctherm2 6 5 = 3.00e-2 ctherm.ctherm3 5 4 = 1.40e-2 ctherm.ctherm4 4 3 = 1.65e-2 ctherm.ctherm5 3 2 = 4.85e-2 ctherm.ctherm6 2 tl = 1.00e-1 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 rtherm.rtherm1 th 6 = 3.24e-3 rtherm.rtherm2 6 5 = 8.08e-3 rtherm.rtherm3 5 4 = 2.28e-2 rtherm.rtherm4 4 3 = 1.00e-1 rtherm.rtherm5 3 2 = 1.10e-1 rtherm.rtherm6 2 tl = 1.40e-1 } RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl (c)2002 Fairchild Semiconductor Corporation CASE Rev. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4