MAX98356
PDM Input Class D Audio Power Amplifier
19-6311; Rev 1; 7/13
General Description
The MAX98356 is a digital pulse-density modulated
(PDM) input Class D power amplifier that provides Class
AB audio performance with Class D efficiency. This IC
offers five selectable gain settings (3dB, 6dB, 9dB, 12dB,
and 15dB) set by a single gain-select input (GAIN).
The MAX98356 takes a stereo pulse density modulated
(SPDM) input signal directly into the DAC. Data on the
rising edge of PDM_CLK is considered left-channel data
while data on the falling PDM_CLK edge is right channel.
The IC can be configured to produce a left channel, right
channel, or left/2 + right/2 output from the stereo input
data. The IC also features an extremely robust digital
audio interface with very high wideband jitter tolerance
(12ns typ) on PDM_CLK.
Active emissions-limiting, edge-rate limiting, and over-
shoot control circuitry greatly reduce EMI. A filterless
spread-spectrum modulation scheme eliminates the need
for output filtering found in traditional Class D devices and
reduces the component count of the solution.
The IC is available in a 9-pin WLP package (1.345mm x
1.435mm x 0.64mm) and is specified over the -40NC to
+85NC temperature range.
Applications
Cellular Phones
Tablets
Portable Media Players
Notebook Computers
Ultrasonic Devices
Features
S Single-Supply Operation (2.5V to 5.5V)
S 3.2W Output Power into 4I at 5V
S 1.8mA Quiescent Current
S 92% Efficiency (RL = 8I, POUT = 900mW,
VDD = 3.7V)
S 29µVRMS Output Noise (AV = 6dB)
S Low 0.013% THD+N at 1kHz
S Exceptionally High Jitter Tolerance
S Supported PDM_CLK Rates of 1.84MHz–4.32MHz
and 5.28MHz–8.64MHz
S Supports Left, Right, or Left/2 + Right/2 Outputs
S Sophisticated Edge Rate Control Enables
Filterless Class D Outputs
S 77dB PSRR at 217Hz
S Low RF Susceptibility Rejects TDMA
Noise from GSM Radios
S Extensive Click-and-Pop Reduction Circuitry
S Robust Short-Circuit and Thermal Protection
S Available in Space-Saving Package:
1.345mm x 1.435mm WLP (0.4mm Pitch)
Ordering Information and Functional Diagram appears at
end of data sheet.
Simplified Block Diagram
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX98356.related
EVALUATION KIT AVAILABLE
DAC
CLASS D
OUTPUT
STAGE
DIGITAL
AUDIO
INTERFACE
PDM
INPUT
GAIN
CONTROL
SHUTDOWN
AND
CHANNEL
SELECT
MAX98356
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAX98356
PDM Input Class D Audio Power Amplifier
2Maxim Integrated
VDD, PDM_CLK and PDM_DATA to GND ..............-0.3V to +6V
All Other Pins to GND .............................. -0.3V to (VDD + 0.3V)
Continuous Current In/Out of VDD/GND/OUT_ ................. Q1.6A
Continuous Input Current (all other pins) ........................ Q20mA
Duration of OUT_ Short Circuit to GND or VDD….. ...Continuous
Duration of OUTP Short to OUTN .............................Continuous
Continuous Power Dissipation (TA = +70NC)
WLP (derate 13.7mW/NC above +70NC)....................1096mW
Junction Temperature .....................................................+150NC
Operating Temperature Range .......................... -40NC to +85NC
Storage Temperature Range ............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+230NC
WLP
Junction-to-Ambient Thermal Resistance (qJA) ..........73°C/W
Junction-to-Case Thermal Resistance (qJC) ...............50°C/W
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
ELECTRICAL CHARACTERISTICS
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage Range VDD Guaranteed by PSSR test 2.5 5.5 V
Undervoltage Lockout UVLO 1.4 1.8 2.3 V
Quiescent Current IDD
TA = +25NC2.2 2.7 mA
TA = +25NC, VDD = 3.7V 1.8 2.2
Shutdown Current ISHDN SD_MODE = 0V, TA = +25NC0.6 2 FA
Standby Current ISTNDBY SD_MODE = 1.8V, no PDM_CLK, TA =
+25NC300 400 FA
Turn-On Time tON Time from receipt of first clock cycle to
full operation 0.6 0.7 ms
Output Offset Voltage VOS TA = +25NC, gain = 15dB Q0.3 Q1.5 mV
Click-and-Pop Level KCP
Peak voltage, TA =
+25NC, A-weighted,
32 samples per
second (Note 3)
Into shutdown -66
dBV
Out of shutdown -72
Power-Supply Rejection Ratio PSRR
VDD = 2.5V to 5.5V, TA = +25NC60 75
dB
TA = +25NC
(Notes 3, 4)
f = 217Hz,
200mVP-P ripple 77
f = 10kHz,
200mVP-P ripple 60
MAX98356
PDM Input Class D Audio Power Amplifier
3Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Power (Note 3) POUT
THD+N 10%,
gain = 12dB
ZSPK = 4I + 33FH3.2
W
ZSPK = 8I + 68FH1.8
ZSPK = 8I + 68FH,
VDD = 3.7V 0.93
THD+N = 1%,
gain = 12dB
ZSPK = 4I + 33FH2.5
ZSPK = 8I + 68FH1.4
ZSPK = 8I + 68FH,
VDD = 3.7V 0.77
Total Harmonic Distortion +
Noise THD+N
f = 1kHz, POUT = 1W, TA = +25NC,
ZSPK = 4I + 33FH0.02 0.06
%
f = 1kHz, POUT = 0.5W, TA = +25NC,
ZSPK = 8I + 68FH0.013
Dynamic Range DR A-weighted, PDM_CLK = 6.144MHz,
VRMS = 2.54V 99 dB
Output Noise VNA-weighted (Note 4) 29 FVRMS
Gain (Relative to a 2.1dBV
Reference Level) AV
GAIN = GND through 100kI14.4 15 15.6
dB
GAIN = GND 11.4 12 12.6
GAIN = unconnected 8.4 9 9.6
GAIN = VDD 5.4 6 6.6
GAIN = VDD through 100kI2.4 3 3.6
Current Limit ILIM 2.8 A
Efficiency h ZSPK = 8I + 68FH, THD+N = 10%,
f = 1kHz, gain = 12dB 92 %
DAC Gain Error 1 %
Frequency Response Q0.05 dB
DIGITAL AUDIO INTERFACE
PDM_CLK High Frequency
Range fCLKH 5.28 8.64 MHz
PDM_CLK Low Frequency
Range fCLKL 1.84 4.32 MHz
PDM_CLK High Time tPDM_CLKH 40 ns
PDM_CLK Low Time tPDM_CLKL 40 ns
Maximum Low Frequency
PDM_CLK Jitter RMS jitter below 40kHz 0.5
ns
Maximum High Frequency
PDM_CLK Jitter RMS jitter above 40kHz 12
MAX98356
PDM Input Class D Audio Power Amplifier
4Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
Note 2: 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
Note 3: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For
RL = 8I, LL = 68FH. For RL = 4I, LL = 33FH.
Note 4: Digital silence used for input signal.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH Digital audio inputs 1.3 V
Input Low Voltage VIL Digital audio inputs 0.6 V
Input Leakage Current IIH, IIL VIN = 0V, VDD = 5.5V, TA = +25NC-1 +1 FA
Input Capacitance CIN 3 pF
PDM Ones Density Maximum 75 %
Minimum 25
PDM_DATA to PDM_CLK
Setup Time tSETUP 10
ns
PDM_DATA to PDM_CLK
Hold Time tHOLD 10
SD_MODE COMPARATOR TRIP POINTS
B0
See SD_MODE and shutdown operation
for details
0.08 0.16 0.355
VB1 0.65 0.77 0.825
B2 1.245 1.4 1.5
SD_MODE Pulldown Resistor RPD 92 100 108 kI
GAIN COMPARATOR TRIP POINTS
VGAIN
AV = 3dB gain 0.65 x
VDD
0.85 x
VDD
V
AV = 6dB gain 0.9 x
VDD VDD
AV = 9dB gain 0.4 x
VDD
0.6 x
VDD
AV = 12dB gain 00.1 x
VDD
AV = 15dB gain 0.15 x
VDD
0.35 x
VDD
MAX98356
PDM Input Class D Audio Power Amplifier
5Maxim Integrated
Figure 1. PDM Audio Interface Timing Diagram
Typical Operating Characteristics
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
General
tPDM_CLK
PDM_CLK
PDM_DATA
tPDM_CLKH
tSETUP tSETUP
tHOLD tHOLD
tPDM_CLKL
LEFT RIGHT LEFT RIGHT
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX98356 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.04.53.0 3.5 4.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
2.5 5.5
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX98356 toc02
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (µA)
5.04.53.0 3.5 4.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
2.5 5.5
MAX98356
PDM Input Class D Audio Power Amplifier
6Maxim Integrated
Speaker Amplifier
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98356 toc03
OUTPUT POWER (W)
THD+N RATIO (dB)
10.10.01
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0.001 10
VDD = 3.7V
GAIN = 12dB
ZSPK = 8I + 68µH
f = 100Hz
f = 6kHz
f = 1kHz
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98356 toc04
OUTPUT POWER (W)
THD+N RATIO (dB)
10.10.01
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0.001 10
VDD = 4.2V
GAIN = 12dB
ZSPK = 8I + 68µH
f = 100Hz
f = 6kHz
f = 1kHz
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98356 toc05
OUTPUT POWER (W)
THD+N RATIO (dB)
10.10.01
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0.001 10
VDD = 5V
GAIN = 12dB
ZSPK = 8I + 68µH
f = 100Hz
f = 6kHz
f = 1kHz
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98356 toc06
OUTPUT POWER (W)
THD+N RATIO (dB)
10.10.01
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0.001 10
VDD = 3.7V
GAIN = 12dB
ZSPK = 4I + 33µH
f = 100Hz
f = 6kHz
f = 1kHz
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98356 toc07
OUTPUT POWER (W)
THD+N RATIO (dB)
10.10.01
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0.001 10
VDD = 4.2V
GAIN = 12dB
ZSPK = 4I + 33µH
f = 100Hz
f = 6kHz
f = 1kHz
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98356 toc08
OUTPUT POWER (W)
THD+N RATIO (dB)
10.10.01
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0.001 10
VDD = 5V
GAIN = 12dB
ZSPK = 4I + 33µH
f = 100Hz
f = 6kHz
f = 1kHz
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
MAX98356
PDM Input Class D Audio Power Amplifier
7Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98356 toc09
FREQUENCY (Hz)
THD+N RATIO (dB)
10k1k100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100k
VDD = 3.7V
GAIN = 12dB
ZSPK = 8I + 68µH
POUT = 75mW
POUT = 350mW
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98356 toc10
FREQUENCY (Hz)
THD+N RATIO (dB)
10k1k100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100k
VDD = 4.2V
GAIN = 12dB
ZSPK = 8I + 68µH
POUT = 100mW
POUT = 500mW
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98356 toc11
FREQUENCY (Hz)
THD+N RATIO (dB)
10k1k100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100k
VDD = 5V
GAIN = 12dB
ZSPK = 8I + 68µH
POUT = 150mW
POUT = 850mW
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98356 toc12
FREQUENCY (Hz)
THD+N RATIO (dB)
10k1k100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100k
VDD = 3.7V
GAIN = 12dB
ZSPK = 4I + 33µH
POUT = 150mW
POUT = 600mW
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98356 toc13
FREQUENCY (Hz)
THD+N RATIO (dB)
10k1k100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100k
VDD = 4.2V
GAIN = 12dB
ZSPK = 4I + 33µH
POUT = 250mW
POUT = 850mW
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98356 toc14
FREQUENCY (Hz)
THD+N RATIO (dB)
10k1k100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10 100k
VDD = 5V
GAIN = 12dB
ZSPK = 4I + 33µH
POUT = 350mW
POUT = 1.5W
MAX98356
PDM Input Class D Audio Power Amplifier
8Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
OUTPUT POWER vs. LOAD RESISTANCE
MAX98356 toc15
LOAD (I)
OUTPUT POWER (W)
10
0.5
1.0
1.5
2.0
2.5
0
1 100
VDD = 3.7V
GAIN = 12dB
ZSPK = RLOADI + 68µH
THD+N = 10%
THD+N = 1%
OUTPUT POWER vs. LOAD RESISTANCE
MAX98356 toc16
10
0.5
1.0
1.5
2.0
2.5
3.0
0
1 100
LOAD (I)
OUTPUT POWER (W)
VDD = 4.2V
GAIN = 12dB
ZSPK = RLOADI + 68µH
THD+N = 10%
THD+N = 1%
OUTPUT POWER vs. LOAD RESISTANCE
MAX98356 toc17
10
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
1 100
LOAD (I)
OUTPUT POWER (W)
VDD = 5V
GAIN = 12dB
ZSPK = RLOADI + 68µH
THD+N = 10%
THD+N = 1%
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX98356 toc18
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
5.04.54.03.53.0
0.5
1.0
1.5
2.0
2.5
0
2.5 5.5
GAIN = 12dB
ZSPK = 8I + 68µH
THD+N = 10%
THD+N = 1%
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX98356 toc19
SUPPLY VOLTAGE (V)
OUTPUT POWER PER CHANNEL (W)
5.04.54.03.53.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
2.5 5.5
GAIN = 12dB
ZSPK = 4I + 33µH
THD+N = 10%
THD+N = 1%
NORMALIZED GAIN vs. FREQUENCY
MAX98356 toc20
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
10k1k100
-0.4
-0.3
-0.2
0
0.2
-0.1
0.1
0.3
0.4
0.5
-0.5
10 100k
ZSPK = 8I + 68µH
MAX98356
PDM Input Class D Audio Power Amplifier
9Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
EFFICIENCY vs. OUTPUT POWER
MAX98356 toc21
OUTPUT POWER PER CHANNEL (mW)
EFFICIENCY (%)
900800600 700200 300 400 500100
10
20
30
40
50
60
70
80
90
100
0
0 1000
VDD = 3.7V
GAIN = 12dB
ZSPK = 8I + 68µH
EFFICIENCY vs. OUTPUT POWER
MAX98356 toc22
OUTPUT POWER PER CHANNEL (mW)
EFFICIENCY (%)
12001000600 800400200
10
20
30
40
50
60
70
80
90
100
0
0 1400
VDD = 4.2V
GAIN = 12dB
ZSPK = 8I + 68µH
EFFICIENCY vs. OUTPUT POWER
MAX98356 toc23
OUTPUT POWER PER CHANNEL (W)
EFFICIENCY (%)
1.2 1.4 1.6 1.81.00.6 0.80.40.2
10
20
30
40
50
60
70
80
90
100
0
0 2.0
VDD = 5V
GAIN = 12dB
ZSPK = 8I + 68µH
EFFICIENCY vs. OUTPUT POWER
MAX98356 toc24
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
VDD = 3.7V
GAIN = 12dB
ZSPK = 4I + 33µH
OUTPUT POWER PER CHANNEL (mW)
1.2 1.4 1.6 1.81.00.6 0.80.40.20
EFFICIENCY vs. OUTPUT POWER
MAX98356 toc25
OUTPUT POWER PER CHANNEL (mW)
2000
150010005000 2500
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
VDD = 4.2V
GAIN = 12dB
ZSPK = 4I + 33µH
EFFICIENCY vs. OUTPUT POWER
MAX98356 toc26
OUTPUT POWER PER CHANNEL (mW)
EFFICIENCY (%)
300025001500 20001000500
10
20
30
40
50
60
70
80
90
100
0
0 3500
VDD = 5V
GAIN = 12dB
ZSPK = 4I + 33µH
MAX98356
PDM Input Class D Audio Power Amplifier
10Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
INBAND OUTPUT SPECTRUM
MAX98356 toc30
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 6.144MHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98356 toc31
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 5.6448MHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98356 toc32
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 5.6448MHz
ZSPK = 8I + 68µH
POWER-SUPPLY REJECTION
RATIO vs. SUPPLY VOLTAGE
MAX98356 toc27
SUPPLY VOLTAGE (V)
PSRR (dB)
5.04.54.03.53.0
10
20
30
40
50
60
70
80
90
100
0
2.5 5.5
f = 1kHz
ZSPK = 8I + 68µH
POWER-SUPPLY REJECTION
RATIO vs. FREQUENCY
MAX98356 toc28
FREQUENCY (Hz)
PSRR (dB)
10k1k100
10
20
30
40
50
60
70
80
90
100
0
10 100k
VDD = 5V
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98356 toc29
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 6.144MHz
ZSPK = 8I + 68µH
MAX98356
PDM Input Class D Audio Power Amplifier
11Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
INBAND OUTPUT SPECTRUM
MAX98356 toc33
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 3.072MHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98356 toc34
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 3.072MHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98356 toc35
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 2.8224MHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98356 toc36
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 2.8224MHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98356 toc37
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 2.048MHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98356 toc38
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
PDM_CLK = 2.048MHz
ZSPK = 8I + 68µH
MAX98356
PDM Input Class D Audio Power Amplifier
12Maxim Integrated
Pin Description
Pin Configuration
PIN NAME FUNCTION
A1 SD_MODE Shutdown and Channel Select. Determines left, right, or left/2 + right/2 mix and also used for shutdown.
See Table 5.
A2 VDD Power-Supply Input
A3 OUTP Positive Speaker Amplifier Output
B1 PDM_DATA PDM Digital Input Signal
B2 GAIN
Amplifier Gain
Gain Connections Gain (dB)
GND through 100kI resistor 15
GND 12
Unconnected 9
VDD 6
VDD through 100kI resistor 3
B3 OUTN Negative Speaker Amplifier Output
C1 PDM_CLK PDM Bit Clock Input Signal. Supports frequency ranges: 1.84MHz–4.32MHz and 5.28 MHz–8.64MHz.
C2, C3 GND Ground
WLP
TOP VIEW
BUMP SIDE DOWN
GNDPDM_CLK GND
GAINPDM_DATA OUTN
VDD
SD_MODE OUTP
MAX98356
+
A1
B1
C1 C2 C3
B2 B3
A3A2
MAX98356
PDM Input Class D Audio Power Amplifier
13Maxim Integrated
Detailed Description
The MAX98356 is a digital PDM input Class D power
amplifier. The PDM modulation scheme uses the relative
density of digital pulses to represent the amplitude of an
analog signal. The IC accepts stereo PDM data through
PDM_DATA and PDM_CLK.
SD_MODE selects which audio channel is output by the
amplifier and is used to put the IC into shutdown. The
GAIN pin offers five gain settings and allows the output of
the amplifier to be tuned to the appropriate level.
The output stage features low-quiescent current, com-
prehensive click-and-pop suppression, and excellent RF
immunity. The IC offers Class AB audio performance with
Class D efficiency in a minimal board-space solution.
The Class D amplifier features spread-spectrum modula-
tion with edge-rate and overshoot control circuitry that
offers significant improvements in switch-mode amplifier
radiated emissions. The amplifier features click-and-pop
suppression that reduces audible transients on startup
and shutdown. The amplifier includes thermal-overload
and short-circuit protection.
Digital Audio Interface
The IC takes a stereo PDM input signal directly into the
DAC. Data read on the rising edge of PDM_CLK is left-
channel data while data read on the falling PDM_CLK
edge is right channel (Table 1).
Supported PDM_CLK Rates
Table 2 indicates the range of PDM_CLK rates that are
supported by the IC. Table 3 indicates the specific clock
rates to use based on the baseband rate and the over-
sample rate of the incoming PDM signal.
PDM_CLK Jitter Tolerance
The IC features a very high PDM_CLK jitter tolerance of
0.5ns for RMS jitter below 40kHz and 12ns for wideband
RMS jitter while maintaining a dynamic range greater than
98dB (Table 4).
Table 1. PDM_CLK Polarity
Table 2. PDM_CLK Rates
Table 3. Calculated PDM_CLK Rates
*The mono left/2 + right/2 feature is not supported at PDM_CLK rates of 5.28MHz and above.
Table 4. RMS Jitter Tolerance
SUPPORTED CLOCK RATES (MHz)
1.84–4.32
5.28–8.64
BASEBAND SAMPLE
RATE (kHz)
INPUT CLOCK RATES (MHz)
32x OVERSAMPLED
PDM
64x OVERSAMPLED
PDM
128x OVERSAMPLED
PDM
256x OVERSAMPLED
PDM
8 — — — 2.048
16 — — 2.048 4.096
32 — 2.048 4.096 —
44.1 — 2.8224 5.6448* —
48 — 3.072 6.144* —
88.2 2.8224 5.6448* — —
96 3.072 6.144* — —
PDM_CLK EDGE
DIRECTION CHANNEL
Rising edge Left
Falling edge Right
FREQUENCY RMS JITTER TOLERANCE (ns)
< 40kHz 0.5
40kHz–BCLK 12
MAX98356
PDM Input Class D Audio Power Amplifier
14Maxim Integrated
Figure 2. PDM Digital Audio Interface Timing
PDM Timing Characteristics
Figure 2 shows the PDM operation of the IC. The bit-
depth is one bit and each bit alternates between left-
channel and right-channel data.
If the PDM generator produces data that is stuck at logic-
high or logic-low, then the output of the IC is railed, forc-
ing DC at the load. Therefore, it is recommended that the
PDM generator includes protection to detect this invalid
condition. If such a condition is detected, then the IC
should either be put into shutdown or PDM_CLK should
be stopped.
Standby Mode
If PDM_CLK stops toggling, the IC automatically enters
standby mode. In standby mode, the Class D speaker
amplifier is turned off and the outputs go into a high-
impedance state, ensuring that the unwanted current is not
transferred to the load during this condition. Standby mode
should not be used in place of the shutdown mode because
the shutdown mode provides the lowest power consump-
tion and the best power-on/off click-and-pop performance.
SD_MODE Pin and Shutdown Operation
The IC features a low-power shutdown mode, drawing
less than 0.6FA (typ) of supply current. During shutdown,
all internal blocks are turned off, including setting the
output stage to a high-impedance state. Drive SD_MODE
low to put the IC into shutdown.
The state of SD_MODE determines the audio channel
that is sent to the amplifier output (Table 5).
Drive SD_MODE high to select the left channel of the
stereo input data. Drive SD_MODE high through a suf-
ficiently small resistor to select the right channel of
the stereo input data. Drive SD_MODE high through a
sufficiently large resistor to select both the left and right
channels of the stereo input data (left/2 + right/2). The left/2
+ right/2 mode is not supported for PDM_CLK rates above
5.28MHz. RLARGE and RSMALL are determined by the
Table 5. SD_MODE Control
SD_MODE STATUS SELECTED CHANNEL
High VSD_MODE > B2 trip point (1.4V typ) Left
Pullup through RSMALL B2 trip point (1.4V typ) > VSD_MODE >
B1 trip point (0.77V typ) Right
Pullup through RLARGE B1 trip point (0.77V typ) > VSD_MODE >
B0 trip point (0.16V typ) Left/2 + right/2
Low B0 trip point (0.16V typ) > VSD_MODE Shutdown
LRLRLRLRLRLR
RIGHT CHANNEL IGNORED
LRLRLRLRLRLRLRLRLRLRLR
SD_MODE = LOGIC-HIGH
PDM_CLK
PDM_DATA
LRLRLRLRLRLR
LEFT CHANNEL IGNORED
LRLRLRLRLRLRLRLRLRLRLR
SD_MODE = PULLUP THROUGH RSMALL
PDM_CLK
PDM_DATA
LRLRLRLRLRLR
LEFT AND RIGHT CHANNELS AVERAGED
LRLRLRLRLRLRLRLRLRLRLR
SD_MODE = PULLUP THROUGH RLARGE
PDM_CLK
PDM_DATA
MAX98356
PDM Input Class D Audio Power Amplifier
15Maxim Integrated
VDDIO voltage (logic voltage from control interface) that is
driving SD_MODE according to the following two equations:
RSMALL (kI) = 98.5 x VDDIO - 100
RLARGE (kI) = 222.2 x VDDIO - 100
Figure 3 and Figure 4 show how to connect an external
resistor to SD_MODE when using an open-drain driver or
a pullup/down driver.
When the device is configured in left channel mode
(SD_MODE is directly driven to logic-high by the con-
trol interface) care must be taken to avoid violating
the Absolute Maximum Ratings limits for SD_MODE.
Ensuring that VDD is always greater than VDDIO is one
way to prevent SD_MODE from violating the Absolute
Maximum Ratings limits. If this is not possible in the
application (e.g., if VDD < 3.0V and VDDIO = 3.3V), then
it is necessary to add a small resistance (~2kI) in series
with SD_MODE to limit the current into the SD_MODE
pin. This is not a concern when using the right channel or
(left + right)/2 modes.
Class D Speaker Amplifier
The filterless Class D amplifier offers much higher efficiency
than Class AB amplifiers. The high efficiency of a Class
D amplifier is due to the switching operation of the output
stage transistors. Any power loss associated with the
Class D output stage is mostly due to the I2R loss of the
MOSFET on-resistance and quiescent current overhead.
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters, or shielding, to meet EN55022B electromag-
netic-interference (EMI) regulation standards. Maxim’s
active emissions-limiting edge-rate control circuitry and
spread-spectrum modulation reduces EMI emissions
while maintaining up to 92% efficiency.
Maxim’s spread-spectrum modulation mode flattens
wideband spectral components while proprietary tech-
niques ensure that the cycle-to-cycle variation of the
switching period does not degrade audio reproduction or
efficiency. The ICs’ spread-spectrum modulator random-
ly varies the switching frequency by Q10kHz around the
center frequency (300kHz). Above 10MHz, the wideband
spectrum looks like noise for EMI purposes (Figure 5).
Speaker Current Limit
If the output current of the speaker amplifier exceeds the
current limit (2.8A typ), the IC disables the outputs for
approximately 100Fs. At the end of the 100Fs, the out-
puts are re-enabled. If the fault condition still exists, the
IC continues to disable and re-enable the outputs until
the fault condition is removed.
Gain Selection
The IC offers five programmable gain selections through
a singel gain input (GAIN). Gain is referenced to the
full-scale output of the DAC, which is 2.1dBV (Table 7).
Assuming that the desired output swing is not limited by
the supply voltage rail, the IC’s output level can be calcu-
lated based on the PDM input ones’s density and select-
ed amplifier gain according to the following equation:
Output signal level (dBV) = 20 x log[abs(PDM one’s
density(%) - 50) /25] (dBFS) + 2.1dB + selected
speaker amplifier gain (dB)
where the one’s density of the PDM input ranges from
75% (maximum positive magnitude) to 25% (maximum
negative magnitude). 0dFBS is referenced to 0dBV.
Click-and-Pop Suppression
The IC speaker amplifier features Maxim’s comprehensive
click-and-pop suppression. During startup, the click-
and-pop suppression circuitry reduces audible transient
sources internal to the device. To achieve optimal click-
and-pop reduction at startup, it is recommended that idle
data be sent to the digital audio interface for the first 0.5ms
of turn-on time. When entering shutdown, the differential
speaker outputs immediately go to a high-impedance
state without creating an audible click-and-pop noise.
Table 6. Examples of SD_MODE Pullup
Resistor Values
Table 7. Gain Selection
LOGIC VOLTAGE
LEVEL (VDDIO) (V)
RSMALL
(kI, 1% tolerance)
RLARGE
(kI, 1% tolerance)
1.8 76.8 300
3.3 226 634
GAIN GAIN (dB)
Connect to GND through
100kI Q5% resistor 15
Connect to GND 12
Unconnected 9
Connect to VDD 6
Connect to VDD through
100kI Q5% resistor 3
MAX98356
PDM Input Class D Audio Power Amplifier
16Maxim Integrated
Figure 4. SD_MODE Resistor Connection Using Pullup/Down Driver
Figure 3. SD_MODE Resistor Connection Using Open-Drain Driver
Figure 5. EMI with 12in of Speaker Cable and No Output Filtering
GPIO
PROCESSOR
VDDIO
R
100kI
±8%
LEFT MODE
RIGHT MODE
LEFT/2 + RIGHT/2 MODE
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
VSD_MODE
MAX98356
GPIO
PROCESSOR VDDIO
R
100kI
±8%
LEFT MODE
RIGHT MODE
LEFT/2 + RIGHT/2 MODE
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
VSD_MODE
MAX98356
FREQUENCY (MHz)
EMISSION LEVEL (dBµV/m)
900800600 700200 300 400 500100
10
30
50
70
90
-10
0 1000
MAX98356
PDM Input Class D Audio Power Amplifier
17Maxim Integrated
Figure 6. Left-Channel Operation with 6dB Gain
Figure 8. Right-Channel Operation with 6dB Gain
Figure 7. Left-Channel Operation with 12dB Gain
Applications Information
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
SD_MODE
PDM_CLK
PDM_DATA
GND
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98356
B2 A2
A1
C1
B1 C2, C3
B3
A3 OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
SD_MODE
PDM_CLK
PDM_DATA
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98356
GND
B2 A2
A1
C1
B1 C2, C3
B3
A3
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
PDM_CLK
RSMALL
(76.8kI)**
PDM_DATA
GND
*RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
**76.8kI ASSUMES VGPIO = 1.8V.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98356
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
B2 A2
A1
C1
B1 C2, C3
B3
A3
MAX98356
PDM Input Class D Audio Power Amplifier
18Maxim Integrated
Figure 9. Stereo Operation Using Two ICs
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
SD_MODE
PDM_CLK
RSMALL
(76.8kI)**
PDM_DATA
GND
*RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
**76.8kI ASSUMES VGPIO = 1.8V.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98356
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
PDM_CLK
PDM_DATA
GND
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98356
B2 A2
A1
C1
B1 C2, C3
B3
A3
B2 A2
A1
C1
B1 C2, C3
B3
A3
MAX98356
PDM Input Class D Audio Power Amplifier
19Maxim Integrated
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filter adds cost, size, and decreases efficiency
and THD+N performance. The IC’s filterless modulation
scheme does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear to
recover the audio component of the square-wave output.
Because the switching frequency of the IC is well beyond
the bandwidth of most speakers, voice coil movement
due to the switching frequency is very small. Use a
speaker with a series inductance > 10FH. Typical 8I
speakers exhibit series inductances in the 20FH to
100FH range.
Power-Supply Input
VDD, which ranges from 2.5V to 5.5V, powers the IC,
including the speaker amplifier. Bypass VDD with a 0.1FF
and 10FF capacitor to GND. Some applications might
require only the 10FF bypass capacitor, making it pos-
sible to operate with a single external component. Apply
additional bulk capacitance at the IC if long input traces
between VDD and the power source are used.
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Good grounding improves audio perfor-
mance and prevents switching noise from coupling into
the audio signal.
Use wide, low-resistance output traces. As load imped-
ance decreases, the current drawn from the device
outputs increases. At higher current, the resistance of
the output traces decreases the power delivered to the
load. For example, if 2W is delivered from the speaker
output to a 4I load through 100mI of total speaker
trace, 1.904W is being delivered to the speaker. If power
is delivered through 10mI of total speaker trace, 1.951W
is being delivered to the speaker. Wide output, supply,
and ground traces also improve the power dissipation of
the IC.
The IC is inherently designed for excellent RF immunity.
For best performance, add ground fills around all signal
traces on top or bottom PCB planes.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability testing
results, refer to the Application Note 1891: Wafer-Level
Packaging (WLP) and Its Applications. Figure 11 shows
the dimensions of the WLP balls used on the IC.
Figure 10. Left/2 + Right/2 Operation with 6dB Gain
Figure 11. MAX98356 WLP Ball Dimensions
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
PDM_CLK
RLARGE
(300kI)**
PDM_DATA
GND
*LEFT AND RIGHT CHANNELS SUMMED WHEN GPIO IS HIGH.
**300kI ASSUMES VGPIO = 1.8V.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
MAX98356
GPIO*
CODEC
PDM CLOCK
PDM DATA OUT
B2 A2
A1
C1
B1 C2, C3
B3
A3
0.21mm
0.24mm
MAX98356
PDM Input Class D Audio Power Amplifier
20Maxim Integrated
Functional Diagram
Ordering Information
+Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
MAX98356EWL+ -40NC to +85NC9 WLP
2.5V TO 5.5V
0.1µF10µF
PDM_CLK
PDM_DATA
SD_MODE
DAC
CLASS D
OUTPUT
STAGE
OUTP
GAIN
VDD
OUTN
DIGITAL
AUDIO
INTERFACE
MAX98356
GND
B1
C1
A1
C2, C3
A2 B2
A3
B3
MAX98356
PDM Input Class D Audio Power Amplifier
21Maxim Integrated
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
9 WLP W91F1+1 21-0459 Refer to Application Note 1891
E
D
AAAA
PIN 1
INDICATOR
MARKING
A3
A2
A1
A
See Note 7
0.05
S
S
e
D1
E1
b
SE
SD
0.05
M S
AB
A
B
SIDE VIEW
A
TOP VIEW
BOTTOM VIEW
A
1
1
PACKAGE OUTLINE
9 BUMPS, WLP PKG. 0.4mm PITCH
21-0459
G
0.64
0.19
0.45
0.025
0.27
0.80
0.80
0.40
0.00
0.00
W91F1+1
32
B
C
W91B1+7
W91C1+1
1.260
0.040
W91G1+1
1.260
0.040
1.595
0.035
1.465
0.015
1.415
0.035
1.435
0.015
1.345
0.015
1.455
0.015
1.238
0.015
1.238
0.015
W91J1+1
TITLE
DOCUMENT CONTROL NO.
REV.
1
1
APPROVAL
COMMON DIMENSIONS
A
A2
A1
A3
b
E1
D1
e
SD
SE
0.05
0.03
0.03
BASIC
REF
BASIC
E
D
PKG. CODE
DEPOPULATED
BUMPS
NONE
NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
BASIC
BASIC
- DRAWING NOT TO SCALE -
NONE
NONE
NONE
NONE
BASIC
BASIC
TM
integrated
maxim
MAX98356
PDM Input Class D Audio Power Amplifier
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 22
© 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/12 Initial release —
1 7/13 New lower tolerances in the Electrical Characteristics table and throughout; updates
to the Typical Operating Characteristics global conditions 1–11
