SGLS131B − JULY 2002 − REVISED DECEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of
−55°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product Change Notification
DQualification Pedigree†
DOutput Swing Includes Both Supply Rails
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DLow Noise ...9 nV/√Hz Typ at f = 1 kHz
DLow Input Bias Current ...1 pA Typ
DFully Specified for Both Single-Supply and
Split-Supply Operation
DCommon-Mode Input Voltage Range
Includes Negative Rail
DHigh-Gain Bandwidth . . . 2.2 MHz Typ
DHigh Slew Rate . . . 3.6 V/µs Typ
DLow Input Offset Voltage
950 µV Max at TA = 25°C
DMacromodel Included
DPerformance Upgrades for the TS272,
TS274, TLC272, and TLC274
description
The TLC2272A and TLC2274A are dual and
quadruple operational amplifiers from Texas
Instruments. Both devices exhibit rail-to-rail
output performance for increased dynamic range
in single- or split-supply applications. The
TLC227xA family offers 2 MHz of bandwidth and
3 V/µs of slew rate for higher speed applications.
These devices offer comparable ac performance
while having better noise, input offset voltage, and
power dissipation than existing CMOS
operational amplifiers. The TLC227xA has a noise
voltage of 9 nV/√Hz, two times lower than
competitive solutions.
The TLC227xA, exhibiting high input impedance
and low noise, is excellent for small-signal
conditioning for high-impedance sources, such as
piezoelectric transducers. Because of the micro-
power dissipation levels, these devices work well
in hand-held monitoring and remote-sensing
applications. In addition, the rail-to-rail output
feature, with single- or split-supplies, makes this
family a great choice when interfacing with analog-to-digital converters (ADCs). For precision applications, the
TLC227xA family has a maximum input offset voltage of 950 µV. This family is fully characterized at 5 V and
±5 V.
The TLC2272/4 also makes great upgrades to the TLC272/4 or TS272/4 in standard designs. They offer
increased output dynamic range, lower noise voltage, and lower input of fset voltage. This enhanced feature set
allows them to be used in a wider range of applications.
Copyright 2003 Texas Instruments Incorporated
!" # $" # %$&'" "(
$"# ! " #%"# % ") "!# # #"$!"#
#" *"+( $" %##, # " ##'+ '$
"#", '' %!"#(
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
|VDD±| − Supply Voltage − V
10
8
6
446 8
12
14
16
10 12 14 16
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
TA = 25°C
IO = ±50 µA
IO = ±500 µA
V(OPP) − Maximum Peak-to-Peak Output Voltage − VVO(PP)
Copyright 2002 − 2003, Texas Instruments Incorporated
!" # $" # %$&'" "(
$"# ! " #%"# % ") "!# # #"$!"#
#" *"+( $" %##, # " ##'+ '$
"#", '' %!"#(
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TAVIOmax At
25°CSMALL
OUTLINE
(D)
TSSOP
(PW)
−55°C to 125°C
950 µV
TLC2272AMDREP
TLC2272AMPWREP
−55°C to 125°C
950 µV
2.5 mV
TLC2272AMDREP
TLC2272MDREP
TLC2272AMPWREP
TLC2272MPWREP
−55°C to 125°C
950 µV
TLC2274AMDREP
TLC2274AMPWREP
−55°C to 125°C
950 µV
2.5 mV
TLC2274AMDREP
TLC2274MDREP
TLC2274AMPWREP
TLC2274MPWREP
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
VDD−/GND
VDD+
2OUT
2IN−
2IN+
TLC2272
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD+
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
VDD−
3IN+
3IN−
3OUT
TLC2274
D OR PW PACKAGE
(TOP VIEW)
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
equivalent schematic (each amplifier)
Q3 Q6 Q9 Q12 Q14 Q16
Q2 Q5 Q7 Q8 Q10 Q11
D1
Q17Q15Q13
Q4Q1
R5
C1
VDD+
IN+
IN−
R3 R4 R1 R2
OUT
VDD−
ACTUAL DEVICE COMPONENT COUNT†
COMPONENT TLC2272 TLC2274
Transistors 38 76
Resistors 26 52
Diodes 9 18
Capacitors 3 6
†Includes both amplifiers and all ESD, bias, and trim circuitry
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD+ (see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, VDD− (see Note 1) −8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input, see Note 1) VDD− − 0.3 V to VDD+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (any input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VDD+ ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of VDD− ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range (see Note 4) −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or PW package 260°C. . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD −.
2. Differential voltages are at IN+ with respect to IN−. Excessive current will flow if input is brought below VDD− − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
4. Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
DISSIPATION RATING TABLE
PACKAGE
TA
≤
25
°
C
DERATING FACTOR
TA = 70
°
C
TA = 85
°
C
TA = 125
°
C
PACKAGE
TA ≤ 25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70 C
POWER RATING
TA = 85 C
POWER RATING
TA = 125 C
POWER RATING
D-8 725 mW 5.8 mW/°C464 mW 337 mW 145 mW
D-14 950 mW 7.6 mW/°C 608 mW 494 mW 190 mW
PW-8 525 mW 4.2 mW/°C 336 mW 273 mW 105 mW
PW-14 700 mW 5.6 mW/°C448 mW 364 mW —
recommended operating conditions
MIN
MAX
UNIT
MIN
MAX
UNIT
Supply voltage, VDD±±2.2 ±8 V
Input voltage, VIVDD− VDD+ −1.5 V
Common-mode input voltage, VIC VDD− VDD+ −1.5 V
Operating free-air temperature, TA−55 125 °C
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2272-EP electrical characteristics at specified free-air temperature, VDD = 5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC2272-EP TLC2272A-EP
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient
of input offset voltage
25 C
to 125°C
2
2
µ
V/
°
C
Input offset voltage long-
term drift (see Note 5) VIC = 0 V,
V
O
= 0 V, VDD± = ±2.5 V
,
R
S
= 50 Ω25°C0.002 0.002 µV/mo
IIO
Input offset current
VO = 0 V,
RS = 50 Ω
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
Full range 800 800
pA
IIB
Input bias current
25°C 1 60 1 60
pA
I
IB
Input bias current
Full range 800 800
pA
VICR
Common-mode input
RS = 50 Ω
|VIO |≤ 5 mV
25°C0
to 4 −0.3
to 4.2 0
to 4 −0.3
to 4.2
V
V
ICR
Common-mode input
voltage
R
S
= 50
Ω, |
V
IO
| ≤
5 mV
Full range 0
to 3.5 0
to 3.5
V
IOH = −20 µA 25°C 4.99 4.99
High-level output
IOH = −200 µA
25°C 4.85 4.93 4.85 4.93
V
OH
High-level output
voltage
I
OH
= −200
µ
A
Full range 4.85 4.85 V
VOH
voltage
IOH = −1 mA
25°C 4.25 4.65 4.25 4.65
V
I
OH
= −1 mA
Full range 4.25 4.25
VIC = 2.5 V, IOL = 50 µA 25°C 0.01 0.01
VIC = 2.5 V,
IOL = 500 µA
25°C 0.09 0.15 0.09 0.15
V
OL
Low-level output voltage
V
IC
= 2.5 V,
I
OL
= 500
µ
A
Full range 0.15 0.15 V
VOL
Low-level output voltage
VIC = 2.5 V,
IOL = 5 mA
25°C 0.9 1.5 0.9 1.5
V
V
IC
= 2.5 V,
I
OL
= 5
m
A
Full range 1.5 1.5
Large-signal
VIC = 2.5 V,
RL = 10 kه
25°C 10 35 10 35
A
VD
Large-signal
differential voltage VIC = 2.5 V,
VO = 1 V to 4 V
RL = 10 kΩ
‡
Full range 10 10 V/mV
AVD
differential voltage
amplification
V
O
= 1 V to 4 V
RL = 1 mΩ‡25°C 175 175
V/mV
rid Differential input
resistance 25°C 1012 1012 Ω
riCommon-mode input
resistance 25°C 1012 1012 Ω
ciCommon-mode input
capacitance f = 10 kHz, P package 25°C 8 8 pF
zoClosed-loop output
impedance f = 1 MHz, AV = 10 25°C 140 140 Ω
CMRR
Common-mode rejection
VIC = 0 V to 2.7 V,
25°C 70 75 70 75
dB
CMRR
Common-mode rejection
ratio
VIC = 0 V to 2.7 V,
VO = 2.5 V, RS = 50 ΩFull range 70 70
dB
kSVR
Supply-voltage rejection
VDD = 4.4 V to 16 V,
25°C 80 95 80 95
dB
k
SVR
Supply-voltage rejection
ratio (∆VDD/∆VIO)
VDD = 4.4 V to 16 V,
VIC = VDD/2, No load Full range 80 80
dB
IDD
Supply current
VO = 2.5 V,
No load
25°C 2.2 3 2.2 3
mA
IDD Supply current VO = 2.5 V, No load Full range 3 3 mA
†Full range is −55°C to 125°C for M level part.
‡Referenced to 2.5 V
NOTE 5: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2272-EP operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA†
TLC2272-EP TLC2272A-EP
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
Slew rate at
VO = 1.25 V to 2.75 V,
25°C 2.3 3.6 2.3 3.6
SR Slew rate at
unity gain
VO = 1.25 V to 2.75 V,
RL = 10 kΩ‡, CL = 100 pF‡
Full
1.7
1.7
V/µs
SR
unity gain
RL = 10 kΩ‡, CL = 100 pF‡
Full
range 1.7 1.7
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 50 50
nV/√Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 9 9
nV/√Hz
VNPP
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 1 1
V
VNPP
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1.4 1.4 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/√Hz
Total harmonic
VO = 0.5 V to 2.5 V,
AV = 1 0.0013% 0.0013%
THD + N
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
R = 10 k ‡,
AV = 10 25°C0.004% 0.004%
THD + N
distortion plus
noise
f = 20 kHz,
RL = 10 kه,AV = 100
25 C
0.03% 0.03%
Gain-bandwidth
f = 10 kHz,
RL = 10 k
Ω‡
,
25°C
2.18
2.18
MHz
Gain-bandwidth
product
f = 10 kHz,
C
L
= 100 pF‡
RL = 10 kه,
25°C 2.18 2.18 MHz
BOM
Maximum output-
VO(PP) = 2 V,
‡
AV = 1, ‡
25°C
1
1
MHz
BOM
Maximum output-
swing bandwidth
VO(PP) = 2 V,
RL = 10 kه,
AV = 1,
CL = 100 pF‡25°C1 1 MHz
AV = −1,
To 0.1%
1.5
1.5
ts
Settling time
AV = −1,
Step = 0.5 V to 2.5 V,
‡
To 0.1%
25°C
1.5 1.5
s
tsSettling time
Step = 0.5 V to 2.5 V,
R
L
= 10 kه,
‡
To 0.01%
25°C
2.6
2.6
µs
s
RL = 10 kه,
C
L
= 100 pF‡To 0.01% 2.6 2.6
φmPhase margin at
unity gain R
L
= 10 kه, C
L
= 100 pF‡25°C50°50°
Gain margin
RL = 10 kه,
CL = 100 pF‡
25°C 10 10 dB
†Full range is −55°C to 125°C for M level part.
‡Referenced to 2.5 V
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2272-EP electrical characteristics at specified free-air temperature, VDD± = ±5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC2272-EP TLC2272A-EP
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient of
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient of
input offset voltage
25 C
to 125°C
2
2
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 5) VIC = 0 V,
RS = 50 ΩVO = 0 V, 25°C0.002 0.002 µV/mo
IIO
Input offset current
S
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
Full range 800 800
pA
IIB
Input bias current
25°C 1 60 1 60
pA
I
IB
Input bias current
Full range 800 800
pA
25 C
−5
−5.3
−5
−5.3
Common-mode input
25
°
C
−5
to 4
−5.3
to 4.2
−5
to 4
−5.3
to 4.2
VICR
Common-mode input
RS = 50 Ω
|VIO |≤5 mV
25 C
to 4 to 4.2 to 4 to 4.2
V
V
ICR
Common-mode input
voltage
R
S
= 50
Ω, |
V
IO
| ≤
5 mV
Full range
−5
−5
V
VICR
voltage
RS = 50 ,
|VIO |5 mV
Full range
−5
to 3.5
−5
to 3.5
V
Full range
to 3.5 to 3.5
IO = −20 µA 25°C 4.99 4.99
Maximum positive peak
IO = −200 µA
25°C 4.85 4.93 4.85 4.93
V
OM+
Maximum positive peak
output voltage
I
O
= −200
µ
A
Full range 4.85 4.85 V
VOM+
output voltage
IO = −1 mA
25°C 4.25 4.65 4.25 4.65
V
I
O
= −1 mA
Full range 4.25 4.25
VIC = 0 V, IO = 50 µA 25°C −4.99 −4.99
Maximum negative peak
VIC = 0 V,
IO = 500 µA
25°C −4.85 −4.91 −4.85 −4.91
V
OM−
Maximum negative peak
output voltage
V
IC
= 0 V,
I
O
= 500
µ
A
Full range −4.85 −4.85 V
VOM−
output voltage
VIC = 0 V,
IO = 5 mA
25°C −3.5 −4.1 −3.5 −4.1
V
V
IC
= 0 V,
I
O
= 5
m
A
Full range −3.5 −3.5
Large-signal differential
RL = 10 kΩ
25°C 20 50 20 50
A
VD
Large-signal differential
voltage amplification
V
O
= ±4 V
R
L
= 10 k
ΩFull range 20 20 V/mV
AVD
voltage amplification
VO = ±4 V
RL = 1 mΩ25°C 300 300
V/mV
rid Differential input resistance 25°C 1012 1012 Ω
riCommon-mode input
resistance 25°C 1012 1012 Ω
ciCommon-mode input
capacitance f = 10 kHz, P package 25°C 8 8 pF
zoClosed-loop output
impedance f = 1 MHz, AV = 10 25°C 130 130 Ω
CMRR
Common-mode rejection
VIC = −5 V to 2.7 V,
25°C 75 80 75 80
dB
CMRR
Common-mode rejection
ratio
VIC = −5 V to 2.7 V,
VO = 0 V, RS = 50 ΩFull range 75 75
dB
kSVR
Supply-voltage rejection
VDD =
±
2.2 V to
±
8 V,
25°C 80 95 80 95
dB
k
SVR
Supply-voltage rejection
ratio (∆VDD±/∆VIO)
VDD = ±2.2 V to ±8 V,
VIC = 0 V, No load Full range 80 80
dB
IDD
Supply current
VO = 2.5 V,
No load
25°C 2.4 3 2.4 3
mA
IDD Supply current VO = 2.5 V, No load Full range 3 3 mA
†Full range is −55°C to 125°C for M level part.
NOTE 5: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2272-EP operating characteristics at specified free-air temperature, VDD± = ±5 V
PARAMETER
TEST CONDITIONS
TA†
TLC2272-EP TLC2272A-EP
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
Slew rate at
VO = ±1 V, RL = 10 kΩ,
25°C 2.3 3.6 2.3 3.6
SR Slew rate at
unity gain
VO = ±1 V, RL = 10 kΩ,
CL = 100 pF
Full
1.7
1.7
V/µs
SR
unity gain
CL = 100 pF
Full
range 1.7 1.7
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 50 50
nV/√Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 9 9
nV/√Hz
VNPP
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 1 1
V
VNPP
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1.4 1.4 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/√Hz
Total harmonic
VO = ±2.3 V
AV = 1 0.0011% 0.0011%
THD + N
Total harmonic
distortion plus
noise
VO = ±2.3 V
R
L
= 10 kΩ,
f = 20 kHz
AV = 10 25°C0.004% 0.004%
THD + N
distortion plus
noise
RL = 10 kΩ,
f = 20 kHz AV = 100
25 C
0.03% 0.03%
Gain-bandwidth
f = 10 kHz,
RL = 10 k
Ω
,
25°C
2.25
2.25
MHz
Gain-bandwidth
product
f = 10 kHz,
CL = 100 pF
RL = 10 kΩ,
25°C 2.25 2.25 MHz
BOM
Maximum
output-swing
VO(PP) = 4.6 V,
AV = 1,
25°C
0.54
0.54
MHz
BOM
output-swing
bandwidth
VO(PP) = 4.6 V,
RL = 10 kΩ,
AV = 1,
CL = 100 pF 25°C 0.54 0.54 MHz
AV = −1,
To 0.1%
1.5
1.5
ts
Settling time
AV = −1,
Step = −2.3 V to 2.3 V,
To 0.1%
25°C
1.5 1.5
s
tsSettling time
Step = −2.3 V to 2.3 V,
R
L
= 10 kΩ,
To 0.01%
25°C
3.2
3.2
µs
s
RL = 10 kΩ,
C
L
= 100 pF To 0.01% 3.2 3.2
φmPhase margin at
unity gain
RL = 10 k
Ω
,
CL = 100 pF
25°C52°52°
Gain margin
RL = 10 kΩ,
CL = 100 pF
25°C 10 10 dB
†Full range is −55°C to 125°C for M level part.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2274-EP electrical characteristics at specified free-air temperature, VDD = 5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC2274-EP TLC2274A-EP
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
µV
V
IO
Input offset voltage
Full range 3000 1500 µ
V
αVIO
Temperature coefficient
25
°
C
2
2
µV/°C
αVIO
Temperature coefficient
of input offset voltage
25 C
to 125°C
2
2
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 5) VDD± = ±2.5 V
,
VO = 0 V, VIC = 0 V,
RS = 50 Ω25°C0.002 0.002 µV/mo
IIO
Input offset current
O
S
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
Full range 800 800
pA
IIB
Input bias current
25°C 1 60 1 60
pA
I
IB
Input bias current
Full range 800 800
pA
25 C
0
−0.3
0
−0.3
Common-mode input
25
°
C
0
to 4
−0.3
to 4.2
0
to 4
−0.3
to 4.2
VICR
Common-mode input
RS = 50 Ω
|VIO |≤ 5 mV
25 C
to 4 to 4.2 to 4 to 4.2
V
V
ICR
Common-mode input
voltage
R
S
= 50
Ω, |
V
IO
| ≤
5 mV
Full range
0 to
0 to
V
VICR
voltage
RS = 50 ,
|VIO | 5 mV
Full range
0 to
3.5
0 to
3.5
V
Full range
3.5 3.5
IOH = −20 µA 25°C 4.99 4.99
High-level output
IOH = −200 µA
25°C 4.85 4.93 4.85 4.93
V
OH
High-level output
voltage
I
OH
= −200
µ
A
Full range 4.85 4.85 V
VOH
voltage
IOH = −1 mA
25°C 4.25 4.65 4.25 4.65
V
I
OH
= −1 mA
Full range 4.25 4.25
VIC = 2.5 V, IOL = 50 µA 25°C 0.01 0.01
Low-level output
VIC = 2.5 V,
25°C 0.09 0.15 0.09 0.15
V
OL
Low-level output
voltage
VIC = 2.5 V,
IOL = 500 µAFull range 0.15 0.15 V
VOL
voltage
VIC = 2.5 V,
IOL = 5 mA
25°C 0.9 1.5 0.9 1.5
V
V
IC
= 2.5 V,
I
OL
= 5
m
A
Full range 1.5 1.5
Large-signal differential
VIC = 2.5 V,
RL = 10 kه
25°C 10 35 10 35
A
VD
Large-signal differential
voltage amplification
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 10 kΩ
‡
Full range 10 10 V/mV
AVD
voltage amplification
V
O
= 1 V to 4 V
RL = 1 MΩ‡25°C 175 175
V/mV
rid Differential input
resistance 25°C 1012 1012 Ω
riCommon-mode input
resistance 25°C 1012 1012 Ω
ciCommon-mode input
capacitance f = 10 kHz, N package 25°C 8 8 pF
zoClosed-loop output
impedance f = 1 MHz, AV = 10 25°C 140 140 Ω
CMRR
Common-mode
VIC = 0 V to 2.7 V,
25°C 70 75 70 75
dB
CMRR
Common-mode
rejection ratio
VIC = 0 V to 2.7 V,
VO = 2.5 V, RS = 50 ΩFull range 70 70
dB
kSVR
Supply-voltage rejection
VDD = 4.4 V to 16 V,
25°C 80 95 80 95
dB
k
SVR
Supply-voltage rejection
ratio (∆VDD/∆VIO)
VDD = 4.4 V to 16 V,
VIC = VDD/2, No load Full range 80 80
dB
IDD
Supply current
VO = 2.5 V,
No load
25°C 4.4 6 4.4 6
mA
IDD Supply current VO = 2.5 V, No load Full range 6 6 mA
†Full range is −55°C to 125°C for M level part.
‡Referenced to 2.5 V
NOTE 5: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2274-EP operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA†
TLC2274-EP TLC2274A-EP
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
Slew rate at unity
VO = 0.5 V to 2.5 V,
CL = 100 pF‡
25°C2.3 3.6 2.3 3.6
SR Slew rate at unity
gain
VO = 0.5 V to 2.5 V,
RL = 10 kه,
CL = 100 pF
‡
Full
1.7
1.7
V/µs
SR
gain
RL = 10 kه,
Full
range 1.7 1.7
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 50 50
nV/√Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 9 9 nV/√Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 1 1
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1.4 1.4 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/√Hz
Total harmonic
VO = 0.5 V to 2.5 V,
AV = 1 0.0013% 0.0013%
THD + N
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
R = 10 k ‡
AV = 10 25°C0.004% 0.004%
THD + N
distortion plus
noise
f = 20 kHz,
RL = 10 kهAV = 100
25 C
0.03% 0.03%
Gain-bandwidth
f = 10 kHz,
RL = 10 k
Ω‡
,
25°C
2.18
2.18
MHz
Gain-bandwidth
product
f = 10 kHz,
C
L
= 100 pF‡
RL = 10 kه,
25°C 2.18 2.18 MHz
BOM
Maximum out-
put-swing band-
VO(PP) = 2 V,
‡
AV = 1, ‡
25°C
1
1
MHz
BOM
put-swing band-
width
VO(PP) = 2 V,
RL = 10 kه,
AV = 1,
CL = 100 pF‡25°C 1 1 MHz
AV = −1,
To 0.1%
1.5
1.5
ts
Settling time
AV = −1,
Step = 0.5 V to 2.5 V,
‡
To 0.1%
25°C
1.5 1.5
s
tsSettling time
Step = 0.5 V to 2.5 V,
R
L
= 10 kه,
‡
To 0.01%
25°C
2.6
2.6
µs
s
RL = 10 kه,
C
L
= 100 pF‡To 0.01% 2.6 2.6
φmPhase margin at
unity gain
RL = 10 k
Ω‡
,
CL = 100 pF
‡25°C50°50°
Gain margin
RL = 10 kه,
CL = 100 pF‡
25°C 10 10 dB
†Full range is −55°C to 125°C for M level part.
‡Referenced to 2.5 V
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2274-EP electrical characteristics at specified free-air temperature, VDD± = ±5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC2274-EP TLC2274A-EP
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
25°C 300 2500 300 950
V
VIO Input offset voltage Full range 3000 1500 µV
VIO
Temperature coefficient of
25
°
C
2
2
V/°C
αVIO
Temperature coefficient of
input offset voltage
25 C
to 125°C2 2 µV/°C
Input offset voltage long-
term drift (see Note 5) VIC = 0 V,
R
S
= 50 ΩVO = 0 V, 25°C 0.002 0.002 µV/mo
IIO
Input offset current
RS = 50 Ω
25°C 0.5 60 0.5 60
pA
IIO Input offset current Full range 800 800 pA
IIB
Input bias current
25°C 1 60 1 60
pA
IIB Input bias current Full range 800 800 pA
−5
−5.3
−5
−5.3
Common-mode input
25
°
C
−5
to 4
−5.3
to 4.2
−5
to 4
−5.3
to 4.2
VICR
Common-mode input
RS = 50 Ω
|VIO |≤ 5 mV
25°C
to 4 to 4.2 to 4 to 4.2
V
V
ICR
Common-mode input
voltage
R
S
= 50 Ω, |V
IO
| ≤ 5 mV
−5
−5
V
VICR
voltage
RS = 50 ,
|VIO | 5 mV
Full range
−5
to 3.5
−5
to 3.5
V
Full range
to 3.5 to 3.5
IO = −20 µA 25°C 4.99 4.99
Maximum positive peak
IO = −200 A
25°C 4.85 4.93 4.85 4.93
V
OM+
Maximum positive peak
output voltage
IO = −200 µAFull range 4.85 4.85 V
VOM+
output voltage
IO = −1 mA
25°C 4.25 4.65 4.25 4.65
V
IO = −1 mA Full range 4.25 4.25
VIC = 0 V, IO = 50 µA 25°C −4.99 −4.99
Maximum negative peak
VIC = 0 V,
IO = 500 A
25°C −4.85 −4.91 −4.85 −4.91
V
OM−
Maximum negative peak
output voltage
VIC = 0 V, IO = 500 µAFull range −4.85 −4.85 V
VOM−
output voltage
VIC = 0 V,
IO = 5 mA
25°C −3.5 −4.1 −3.5 −4.1
V
VIC = 0 V, IO = 5 mAFull range −3.5 −3.5
Large-signal differential
RL = 10 kΩ
25°C 20 50 20 50
A
VD
Large-signal differential
voltage amplification
V
O
= ±4 V RL = 10 kΩFull range 20 20 V/mV
AVD
voltage amplification
VO = ±4 V
RL = 1 MΩ25°C 300 300
V/mV
rid Differential input resistance 25°C 1012 1012 Ω
riCommon-mode input
resistance 25°C 1012 1012 Ω
ciCommon-mode input
capacitance f = 10 kHz, N package 25°C 8 8 pF
zoClosed-loop output
impedance f = 1 MHz, AV = 10 25°C 130 130 Ω
CMRR
Common-mode rejection
VIC = −5 V to 2.7 V
25°C 75 80 75 80
dB
CMRR
Common-mode rejection
ratio
VIC = −5 V to 2.7 V
VO = 0 V, RS = 50 ΩFull range 75 75 dB
kSVR
Supply-voltage rejection
VDD± =
±
2.2 V to
±
8 V,
25°C 80 95 80 95
dB
kSVR
Supply-voltage rejection
ratio (∆VDD±/∆VIO)
VDD± = ± 2.2 V to ±8 V,
VIC = 0 V, No load Full range 80 80 dB
IDD
Supply current
VO = 0 V,
No load
25°C 4.8 6 4.8 6
mA
I
DD
Supply current
V
O
= 0 V,
No load
Full range 6 6
mA
†Full range is −55°C to 125°C for M level part.
NOTE 5: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2274-EP operating characteristics at specified free-air temperature, VDD± = ±5 V
PARAMETER
TEST CONDITIONS
TA†
TLC2274-EP TLC2274A-EP
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
Slew rate at unity
VO = ±2.3 V,
RL = 10 kΩ,
25°C 2.3 3.6 2.3 3.6
SR Slew rate at unity
gain
VO = ±2.3 V,
CL = 100 pF
RL = 10 kΩ,
Full
1.7
1.7
V/µs
SR
gain
CL = 100 pF
Full
range 1.7 1.7
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 50 50
nV/√Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 9 9 nV/√Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 1 1
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1.4 1.4 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/√Hz
Total harmonic
VO = ±2.3 V,
AV = 1 0.0011% 0.0011%
THD + N
Total harmonic
distortion plus
noise
VO = ±2.3 V,
R
L
= 10 kΩ,
f = 20 kHz
AV = 10 25°C0.004% 0.004%
THD + N
distortion plus
noise
RL = 10 kΩ,
f = 20 kHz AV = 100
25 C
0.03% 0.03%
Gain-bandwidth
f = 10 kHz,
RL = 10 k
Ω
,
25°C
2.25
2.25
MHz
Gain-bandwidth
product
f = 10 kHz,
CL = 100 pF
RL = 10 kΩ,
25°C 2.25 2.25 MHz
BOM
Maximum
output-swing
VO(PP) = 4.6 V,
AV = 1,
25°C
0.54
0.54
MHz
BOM
output-swing
bandwidth
VO(PP) = 4.6 V,
RL = 10 kΩ,
AV = 1,
CL = 100 pF 25°C 0.54 0.54 MHz
AV = −1,
To 0.1%
1.5
1.5
ts
Settling time
AV = −1,
Step = −2.3 V to 2.3 V,
To 0.1%
25°C
1.5 1.5
s
tsSettling time
Step = −2.3 V to 2.3 V,
R
L
= 10 kΩ,
To 0.01%
25°C
3.2
3.2
µs
s
RL = 10 kΩ,
C
L
= 100 pF To 0.01% 3.2 3.2
φmPhase margin at
unit gain
RL = 10 k
Ω
,
CL = 100 pF
25°C 52°52°
Gain margin
RL = 10 kΩ,
CL = 100 pF
25°C 10 10 dB
†Full range is −55°C to 125°C for M level part.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
1 − 4
VIO Input offset voltage
Distribution
vs Common-mode voltage
1 − 4
5, 6
αVIO Input offset voltage temperature coefficient Distribution 7 − 10
IIB/IIO Input bias and input offset current vs Free-air temperature 11
VI
Input voltage
vs Supply voltage
12
VIInput voltage
vs Supply voltage
vs Free-air temperature
12
13
VOH High-level output voltage vs High-level output current 14
VOL Low-level output voltage vs Low-level output current 15, 16
VOM+ Maximum positive peak output voltage vs Output current 17
VOM− Maximum negative peak output voltage vs Output current 18
VO(PP) Maximum peak-to-peak output voltage vs Frequency 19
IOS
Short-circuit output current
vs Supply voltage
20
IOS Short-circuit output current
vs Supply voltage
vs Free-air temperature
20
21
VOOutput voltage vs Differential input voltage 22, 23
Large-signal differential voltage amplification vs Load resistance 24
AVD Large-signal differential voltage amplification
and phase margin vs Frequency 25, 26
Large-signal differential voltage amplification vs Free-air temperature 27, 28
zoOutput impedance vs Frequency 29, 30
CMRR
Common-mode rejection ratio
vs Frequency
31
CMRR Common-mode rejection ratio
vs Frequency
vs Free-air temperature
31
32
kSVR
Supply-voltage rejection ratio
vs Frequency
33, 34
kSVR Supply-voltage rejection ratio
vs Frequency
vs Free-air temperature
33, 34
35
IDD
Supply current
vs Supply voltage
36, 37
IDD Supply current
vs Supply voltage
vs Free-air temperature
36, 37
38, 39
SR
Slew rate
vs Load capacitance
40
SR Slew rate
vs Load capacitance
vs Free-air temperature
40
41
Inverting large-signal pulse response 42, 43
VO
Voltage-follower large-signal pulse response 44, 45
VOInverting small-signal pulse response 46, 47
Voltage-follower small-signal pulse response 48, 49
VnEquivalent input noise voltage vs Frequency 50, 51
Noise voltage over a 10-second period 52
Integrated noise voltage vs Frequency 53
THD + N Total harmonic distortion plus noise vs Frequency 54
Gain-bandwidth product
vs Supply voltage
55
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
55
56
φmPhase margin vs Load capacitance 57
Gain margin vs Load capacitance 58
NOTE: For all graphs where VDD = 5 V, all loads are referenced to 2.5 V.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VIO − Input Offset Voltage − mV
Percentage of Amplifiers − %
DISTRIBUTION OF TLC2272
INPUT OFFSET VOLTAGE
10
5
0
20
15
−1.6 −1.2 0 0.4 0.8 1.2 1.6
891 Amplifiers From
−0.8 −0.4
2 Wafer Lots
VDD = ±2.5 V
TA = 25°C
Figure 1
VIO − Input Offset Voltage − mV
Percentage of Amplifiers − %
DISTRIBUTION OF TLC2272
INPUT OFFSET VOLTAGE
10
5
0
20
15
−1.6 −1.2 0 0.4 0.8 1.2 1.6
−0.8 −0.4
891 Amplifiers From
2 Wafer Lots
VDD = ±5 V
TA = 25°C
Figure 2
Figure 3
VIO − Input Offset Voltage − mV
Percentage of Amplifiers − %
DISTRIBUTION OF TLC2274
INPUT OFFSET VOLTAGE
10
5
0
20
15
0 0.4 0.8 1.2 1.6
992 Amplifiers From
−1.6 −1.2 −0.8 −0.4
2 Wafer Lots
VDD = ±2.5 V
Figure 4
VIO − Input Offset Voltage − mV
Percentage of Amplifiers − %
DISTRIBUTION OF TLC2274
INPUT OFFSET VOLTAGE
10
5
0
20
15
0 0.4 0.8 1.2 1.6
992 Amplifiers From
−1.6 −1.2 −0.8 −0.4
2 Wafer Lots
VDD = ±5 V
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
0.5
0
−1−1 0 1
VIO − Input Offset Voltage − mV
1
2345
VIO
VIC − Common-Mode Voltage − V
VDD = 5 V
TA = 25°C
RS = 50 Ω
−0.5
INPUT OFFSET VOLTAGE
vs
COMMON-MODE VOLTAGE
Figure 5
0.5
0
−1 −1 0 1
VIO − Input Offset Voltage − mV
1
2345
INPUT OFFSET VOLTAGE
vs
COMMON-MODE VOLTAGE
VIC − Common-Mode Voltage − V
VIO
−0.5
VDD = ±5 V
TA = 25°C
RS = 50 Ω
−6 −5 −4 −3 −2
Figure 6
15
10
5
0−1 0 1
Percentage of Amplifiers − %
20
25
2345
DISTRIBUTION OF TLC2272
vs
INPUT OFFSET VOLTAGE TEMPERATURE
COEFFICIENT†
αVIO − Temperature Coefficient − µV/°C
128 Amplifiers From
2 Wafer Lots
VDD = ±2.5 V
P Package
25°C to 125°C
−5 −4 −3 −2
Figure 7
−5 −4 −3 −2
15
10
5
0−1 0 1
Percentage of Amplifiers − %
20
25
2345
DISTRIBUTION OF TLC2272
vs
INPUT OFFSET VOLTAGE TEMPERATURE
COEFFICIENT†
αVIO − Temperature Coefficient − µV/°C
128 Amplifiers From
2 Wafer Lots
VDD = ±5 V
P Package
25°C to 125°C
Figure 8
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
15
10
5
001
Percentage of Amplifiers − %
20
25
2345
DISTRIBUTION OF TLC2274
vs
INPUT OFFSET VOLTAGE TEMPERATURE
COEFFICIENT†
αVIO − Temperature Coefficient − µV/°C
−5 −4 −3 −2 −1
128 Amplifiers From
2 Wafer Lots
VDD = ±2.5 V
N Package
TA = 25°C to 125°C
Figure 9
15
10
5
0
Percentage of Amplifiers − %
20
25
DISTRIBUTION OF TLC2274
vs
INPUT OFFSET VOLTAGE TEMPERATURE
COEFFICIENT†
αVIO − Temperature Coefficient − µV/°C
012345
−5 −4 −3 −2 −1
128 Amplifiers From
2 Wafer Lots
VDD = ±2.5 V
N Package
TA = 25°C to 125°C
Figure 10
15
10
5
025 45 65 85
20
25
30
105 125
INPUT BIAS AND INPUT OFFSET CURRENT†
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
35 VDD = ±2.5 V
VIC = 0 V
VO = 0 V
RS = 50 Ω
IIB
IIO
IIB and IIO − Input Bias and Input Offset Currents − pA
IB
IIIO
Figure 11
0
− 2
− 6
− 8
− 10
8
− 4
2345678
− Input Voltage − V
4
2
6
10
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
|VDD±| − Supply Voltage − V
VI
TA = 25°C
RS = 50 Ω
|VIO| ≤ 5mV
12
Figure 12
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
−75 − 25 0 25 50 75 100 125
2
1
0
−1
3
4
5
− Input Voltage − V
VI
INPUT VOLTAGE†
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
|VIO| ≤ 5mV
VDD = 5 V
−50
Figure 13
V0H − High-Level Output Voltage − V
VOH
IOH − High-Level Output Current − mA
4
2
1
0
6
3
01234
5
HIGH-LEVEL OUTPUT VOLTAGE†
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 5 V
TA = 125°C
TA = −55°C
TA = 25°C
Figure 14
VOL − Low-Level Output Voltage − V
0.6
0.4
0.2
00123
0.8
45
VDD = 5 V
TA = 25°C
IOL − Low-Level Output Current − mA
VOL
VIC = 1.25 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1
1.2
VIC = 2.5 V
Figure 15
VIC = 0 V
LOW-LEVEL OUTPUT VOLTAGE †
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Low-Level Output Voltage − V
IOL − Low-Level Output Current − mA
VOL
0.6
0.4
0.2
00123
0.8
4
1
1.2
56
1.4 VDD = 5 V
VIC = 2.5 V
TA = 125°C
TA = 25°C
TA = −55°C
Figure 16
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
3
2
1012 3 45
− Maximum Positive Peak Output Voltage − V
4
5
MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE†
vs
OUTPUT CURRENT
|IO| − Output Current − mA
TA = −55°C
TA = 25°C
TA = 125°C
VDD± = ±5 V
VOM +
Figure 17
0123456
IO − Output Current − mA
MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE†
vs
OUTPUT CURRENT
VDD = ±5 V
VIC = 0 V
TA = 125°C
TA = 25°C
TA = −55°C
−3.8
−4
−4.2
−4.4
−4.6
−4.8
−5
− Maximum Negative Peak Output Voltage − V
VOM −
Figure 18
Figure 19
2
1
0
10 k 100 k 1 M
3
f − Frequency − Hz
4
10 M
6
5
7
8
9
10
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
V(OPP) − Maximum Peak-to-Peak Output Voltage − VVO(PP)
VDD = 5 V
VDD = ±5 V
RL = 10 kΩ
TA = 25°C
Figure 20
4
0
23 4
8
12
16
5678
IOS − Short-Circuit Output Current − mA
OS
I
|VDD±| − Supply Voltage − V
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
VID = 100 mV
VO = 0 V
TA = 25°C
−8
VID = −100 mV
−4
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
−5
SHORT-CIRCUIT OUTPUT CURRENT†
vs
FREE-AIR TEMPERATURE
−75 −50 −25 0 25 50 75 100 125
−1
−3
7
11
15
IOS − Short-Circuit Output Current − mA
OS
I
TA − Free-Air Temperature − °C
VID = 100 mV
VID = −100 mV
VO = 0 V
VDD = ±5 V
Figure 21
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
3
2
1
0800
4
5
1200
VID − Differential Input Voltage − µV
− Output Voltage − V
VO
−800 −400 4000
VDD = 5 V
TA = 25°C
RL = 10 kΩ
VIC = 2.5 V
Figure 22
1
−1
−3
−5 0 250
3
5
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
500 750 1000
VID − Differential Input Voltage − µV
− Output Voltage − V
VO
−1000 −750 −250−500
Figure 23
VDD = ±5 V
TA = 25°C
RL = 10 kΩ
VIC = 0 V
0.1
1
0.1 1 10 100
10
100
1000
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
RL − Load Resistance − kΩ
VO = ±1 V
TA = 25°C
VDD = ±5 V
VDD = 5 V
Figure 24
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
0
20
1 k 10 k 100 k 1 M
40
60
80
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
f − Frequency − Hz
10 M
om − Phase Margin
φm
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
−20
−40 −90°
−45°
0°
45°
90°
135°
180°
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
Figure 25
0
20
1 k 10 k 100 k 1 M
40
60
80
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
f − Frequency − Hz 10 M
VDD = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
om − Phase Margin
φm
−20
−40 −90°
−45°
0°
45°
90°
135°
180°
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
Figure 26
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†
vs
FREE-AIR TEMPERATURE
−75 −50 −25 0 25 50 75 100 125
10
100
1 k
TA − Free-Air Temperature − °C
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
RL = 1 MΩ
RL = 10 kΩ
AVD − Large-Signal Differential
ÁÁ
ÁÁ
AVD
Voltage Amplification − V/mV
Figure 27
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†
vs
FREE-AIR TEMPERATURE
−75 −50 −25 0 25 50 75 100 125
10
100
1 k
TA − Free-Air Temperature − °C
RL = 1 MΩ
RL = 10 kΩ
VDD = ±5 V
VIC = 0 V
VO = ±4 V
AVD − Large-Signal Differential
ÁÁ
ÁÁ
AVD
Voltage Amplification − V/mV
Figure 28
10
1
0.1
1000
100
100 1 k 10 k 100 k 1 M
zo − Output Impedance − O
f − Frequency − Hz
Ωzo
OUTPUT IMPEDANCE
vs
FREQUENCY
VDD = 5 V
TA = 25°C
AV = 100
AV = 10
AV = 1
Figure 29
10
1
0.1
1000
100
100 1 k 10 k 100 k 1 M
zo − Output Impedance − O
f − Frequency − Hz
Ωzo
OUTPUT IMPEDANCE
vs
FREQUENCY
VDD = ±5 V
TA = 25°C
AV = 100
AV = 10
AV = 1
Figure 30
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
60
40
20
010 100 1 k 10 k
CMRR − Common-Mode Rejection Ratio − dB
80
100
100 k 1 M
f − Frequency − Hz
VDD = ±5 V
VDD = 5 V
10 M
TA = 25°C
Figure 31
TA − Free-Air Temperature − °C
CMRR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
82
78
74
70
86
90
−75 −50 −25 0 25 50 75 100 125
VDD = ±5 V
VDD = 5 V
VIC = 0 V to 2.7 V
VIC = −5 V to 2.7 V
Figure 32
40
20
0
10 100 1 k
kSVR − Supply-Voltage Rejection Ratio − dB
60
80
f − Frequency − Hz
100
10 k 100 k 1 M 10 M
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
kSVR
VDD = 5 V
TA = 25°C
kSVR+
kSVR−
−20
Figure 33
40
20
0
10 100 1 k
kSVR − Supply-Voltage Rejection Ratio − dB
60
80
f − Frequency − Hz
100
10 k 100 k 1 M 10 M
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
kSVR
VDD = ±5 V
TA = 25°C
kSVR+
kSVR−
−20
Figure 34
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
kSVR − Supply Voltage Rejection Ratio − dB
SUPPLY VOLTAGE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
kSVR
TA − Free-Air Temperature − °C
−75 −50 −25 0 25 50 75 100 125
100
95
90
85
105
110 VDD± = ±2.2 V to ±8 V
VO = 0 V
Figure 35
012345678
0
0.6
1.2
1.8
2.4
3
IDD − Supply Current − mA
DD
I
|VDD±| − Supply Voltage − V
VO = 0 V
No Load
TA = 25°C
TA = −55°C
TA = 125°C
Figure 36
TLC2272
SUPPLY CURRENT†
vs
SUPPLY VOLTAGE
Figure 37
012345678
0
1.2
2.4
3.6
4.8
6
IDD − Supply Current − mA
DD
I
|VDD±| − Supply Voltage − V
VO = 0 V
No Load
TA = 25°C
TA = −55°C
TA = 125°C
TLC2274
SUPPLY CURRENT†
vs
SUPPLY VOLTAGE
Figure 38
−75 −50 −25 0 25 50 75 100 125
0
0.6
1.2
1.8
2.4
3
TA − Free-Air Temperature − °C
IDD − Supply Current − mA
DD
I
VDD = 5 V
VO = 2.5 V
VDD = ±5 V
VO = 0 V
TLC2272
SUPPLY CURRENT†
vs
FREE-AIR TEMPERATURE
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 39
−75 −50 −25 0 25 50 75 100 125
0
1.2
2.4
3.6
4.8
6
TA − Free-Air Temperature − °C
IDD − Supply Current − mA
DD
I
VDD = 5 V
VO = 2.5 V
VDD = ±5 V
VO = 0 V
TLC2274
SUPPLY CURRENT†
vs
FREE-AIR TEMPERATURE
µs
SR − Slew Rate − V/
0
1
2
3
CL − Load Capacitance − pF
SLEW RATE
vs
LOAD CAPACITANCE
10 k1 k10010
SR +
SR −
4
5VDD = 5 V
AV = −1
TA = 25°C
Figure 40
3
2
1
4
µs
SR − Slew Rate − V/
−75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C
SLEW RATE†
vs
FREE-AIR TEMPERATURE
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
SR +
SR −
0
5
Figure 41
INVERTING LARGE-SIGNAL PULSE RESPONSE
2
1
012345
3
4
5
6789
VO − Output Voltage − mV
VO
t − Time − µs
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = −1
0
Figure 42
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
0
− 1
− 3
− 4
− 5
4
− 2
12345
2
1
3
5
6789
VO − Output Voltage − V
VO
t − Time − µs
VDD = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = −1
INVERTING LARGE-SIGNAL PULSE RESPONSE
0
Figure 43
3
2
1
012345
4
5
6789
VO − Output Voltage − V
VO
t − Time − µs
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
TA = 25°C
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
0
Figure 44
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
0
−1
4
12345
2
1
3
5
6789
VO − Output Voltage − V
VO
t − Time − µs
VDD = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
0
−2
−3
−5
−4
Figure 45
INVERTING SMALL-SIGNAL PULSE RESPONSE
2.5
2.45
2.4 0.5 1 1.5 2 2.5
2.55
2.6
2.65
3.5 4.5 5 5.5
VO − Output Voltage − V
VO
t − Time − µs
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = −1
034
Figure 46
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
0
−100 0 0.5 1 1.5 2
50
100
2.5 3 3.5 4
VO − Output Voltage − mV
VO
t − Time − µs
INVERTING SMALL-SIGNAL PULSE RESPONSE
VDD = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
−50
Figure 47
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
2.5
2.45
2.4
2.55
2.6
0 0.5 1 1.5
VO − Output Voltage − V
VO
t − Time − µs
2.65 VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
Figure 48
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
0
−50
−100
50
100
0 0.5 1 1.5
VO − Output Voltage − mV
VO
t − Time − µs
VDD = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
Figure 49
20
10
0
10 100 1 k
Vn − Equivalent Input Noise Voltage − nV Hz
30
f − Frequency − Hz
40
10 k
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
50
60
VnnV/ Hz
VDD = 5 V
TA = 25°C
RS = 20 Ω
Figure 50
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
20
10
0
10 100 1 k
Vn − Equivalent Input Noise Voltage − nV Hz
30
f − Frequency − Hz
40
10 k
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
50
60
VnnV/ Hz
VDD = ±5 V
TA = 25°C
RS = 20 Ω
Figure 51
−750
−1000 246
0
250
810
Noise Voltage − nV
t − Time − s
NOISE VOLTAGE
OVER A 10 SECOND PERIOD
0
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
500
750
1000
−250
−500
Figure 52
Integrated Noise Voltage − uVRMS
1
0.1
100
1 10 100 1 k
f − Frequency − Hz
INTEGRATED NOISE VOLTAGE
vs
FREQUENCY
10 k 100 k
VRMS
µ
Calculated Using
Ideal Pass-Band Filter
Lower Frequency = 1 Hz
TA= 25°C
10
Figure 53
0.0001
0.001
100 1 k 10 k 100 k
THD + N − Total Harmonic Distortion Plus Noise − %
f − Frequency − Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
0.01
0.1
1VDD = 5 V
TA = 25°C
RL = 10 kΩ
AV = 100
AV = 10
AV = 1
Figure 54
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 55
Gain-Bandwidth Product − MHz
2.1
2012345
2.2
2.3
678
|VDD±| − Supply Voltage − V
2.4
2.5
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
f = 10 kHz
RL = 10 kΩ
CL = 100 pF
TA = 25°C
Figure 56
−75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C
Gain-Bandwidth Product − MHz
GAIN-BANDWIDTH PRODUCT†
vs
FREE-AIR TEMPERATURE
1.8
1.6
1.4
2
2.4
2.2
2.6
2.8
3VDD = 5 V
f = 10 kHz
RL = 10 kΩ
CL = 100 pF
10
om − Phase Margin
10000
CL − Load Capacitance − pF
φm
PHASE MARGIN
vs
LOAD CAPACITANCE
1000100
VDD = ±5 V
TA = 25°C
Rnull = 20 Ω
Rnull = 10 Ω
Rnull = 0
75°
60°
45°
30°
15°
0°
10 kΩ
10 kΩ
VDD−
VDD+ Rnull
CL
VI
Rnull = 100 Ω
Rnull = 50 Ω
Figure 57 Figure 58
3
010
Gain Margin − dB
6
9
10000
CL − Load Capacitance − pF
12
15
GAIN MARGIN
vs
LOAD CAPACITANCE
1000100
VDD = 5 V
AV = 1
RL = 10 kΩ
TA = 25°C
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS131A − JULY 2002 − REVISED NOVEMBER 2003
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 6) and subcircuit in Figure 59 were generated using
the TLC227x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 6: G . R . Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
−
+
−
+
−
+
−
+
−
+
−
+
−+
−
+−
.SUBCKT TLC227x 1 2 3 4 5
C1 11 1214E−12
C2 6 760.00E−12
DC 5 53DX
DE 54 5DX
DLP 90 91DX
DLN 92 90DX
DP 4 3DX
EGND 99 0POLY (2) (3,0) (4,) 0 .5 .5
FB 99 0POLY (5) VB VC VE VLP VLN 0
+ 984.9E3 −1E6 1E6 1E6 −1E6
GA 6 011 12 377.0E−6
GCM 0 6 10 99 134E−9
ISS 3 10DC 216.OE−6
HLIM 90 0VLIM 1K
J1 11 210 JX
J2 12 110 JX
R2 6 9100.OE3
RD1 60 112.653E3
RD2 60 122.653E3
R01 8 550
R02 7 9950
RP 3 44.310E3
RSS 10 99925.9E3
VAD 60 4−.5
VB 9 0DC 0
VC 3 53 DC .78
VE 54 4DC .78
VLIM 7 8DC 0
VLP 91 0DC 1.9
VLN 0 92DC 9.4
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=1.500E−12BETA=1.316E-3
+ VTO=−.270)
.ENDS
VCC+
RP
IN − 2
IN+ 1
VCC−
VAD
RD1
11
J1 J2
10
RSS ISS
3
12
RD2
60
VE
54 DE
DP
VC
DC
4
C1
53
R2 6
9
EGND
VB
FB
C2
GCM GA VLIM
8
5RO1
RO2
HLIM
90 DIP
91
DIN
92
VINVIP
99
7
Figure 59. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
!'# #!$'" !'# ") !'# % &+
"'+ "'+ " *" &+ # $''+ %#", ''
") #%" %", )"#"# ")
#!$" %$" " *)) ") !' '"#(
PACKAGE OPTION ADDENDUM
www.ti.com 17-Dec-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLC2272AMDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2272AE
TLC2272AMDREPG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2272AE
TLC2274AMDREP ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274AME
TLC2274AMPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274AME
TLC2274MDREP ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274ME
V62/03618-01XE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2272AE
V62/03618-02UE ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274AME
V62/03618-02YE ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274AME
V62/03618-04YE ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 2274ME
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 17-Dec-2015
Addendum-Page 2
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2272A-EP, TLC2274-EP, TLC2274A-EP :
•Catalog: TLC2272A, TLC2274, TLC2274A
•Automotive: TLC2272A-Q1, TLC2274-Q1, TLC2274A-Q1
•Military: TLC2272AM, TLC2274M, TLC2274AM
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC2272AMDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC2274AMDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC2274AMPWREP TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLC2274MDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Feb-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC2272AMDREP SOIC D 8 2500 367.0 367.0 38.0
TLC2274AMDREP SOIC D 14 2500 333.2 345.9 28.6
TLC2274AMPWREP TSSOP PW 14 2000 367.0 367.0 35.0
TLC2274MDREP SOIC D 14 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Feb-2016
Pack Materials-Page 2
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