MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
DESCRIPTION
The MH4S64BLG is 4194304 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Clock frequency 100MHz
single 3.3V±0.3V power supply
Fully synchronous operation referenced to clock rising
edge
Burst length- 1/2/4/8/Full Page(programmable)
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
APPLICATION
PC main memory
Auto precharge / All bank precharge controlled by A10
Burst type- sequential / interleave(programmable)
Column access - random
LVTTL Interface
Auto refresh and Self refresh
4096 refresh cycle /64ms
1pin
10pin
11pin
40pin
41pin
84pin
Front side
85pin
94pin
95pin
124pin
125pin
168pin
Back side
1
Utilizes industry standard 4M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
Discrete IC and module design conform to
PC100 specification.
(module Spec. Rev. 1.0 and
SPD 1.2A(-7,-8), SPD1.0(-10))
Frequency CLK Access Time
-8 100MHz 6.0ns(CL=3)
(Component SDRAM)
6.0ns(CL=3)100MHz
-7
-10 8.0ns(CL=3)100MHz
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
NC = No Connection
2
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 NC 86 DQ32 128 CKE0
3 DQ1 45 /S2 87 DQ33 129 NC
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6 VDD 48 NC 90 VDD 132 NC
7 DQ4 49 VDD 91 DQ36 133 VDD
8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC
10 DQ7 52 NC 94 DQ39 136 NC
11 DQ8 53 NC 95 DQ40 137 NC
12 VSS 54 VSS 96 VSS 138 VSS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 VDD 101 DQ45 143 VDD
18 VDD 60 DQ20 102 VDD 144 DQ52
19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 NC 104 DQ47 146 NC
21 NC 63 NC 105 NC 147 NC
22 NC 64 VSS 106 NC 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 VDD 68 VSS 110 VDD 152 VSS
27 /WE0 69 DQ24 111 /CAS 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 /S0 72 DQ27 114 NC 156 DQ59
31 NC 73 VDD 115 /RAS 157 VDD
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 CK2 121 A9 163 CK3
38 A10 80 NC 122 BA0 164 NC
39 BA1 81 WP 123 A11 165 SA0
40 VDD 82 SDA 124 VDD 166 SA1
41 VDD 83 SCL 125 CK1 167 SA2
42 CK0 84 VDD 126 NC 168 VDD
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
3
Block Diagram
CK0
Vcc
Vss
D0 - D3
D0 - D3
CKE0 D0 - D3
/RAS D0 - D3
/CAS D0 - D3
/WE D0 - D3
BA0,BA1,A<11:0> D0 - D3
CK3
CK,DQ=10Ω
2SDRAMs+15pF
10pF
CK1 10pF
CS
D0
DQ1
DQ0
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ32
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ41
DQ40
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ49
DQ48
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ57
DQ56
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ25
DQ24
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ17
DQ16
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ9
DQ8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB4
DQMB1
DQMB5
DQMB2
DQMB6
DQMB3
DQMB7
D4
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7 D2
D3
D2
D1
DQMB0
DQMU
DQMU
DQMU
DQMU
DQ0~DQ7
DQ8~DQ15
DQ0~DQ7
DQ8~DQ15
DQ0~DQ7
DQ8~DQ15
DQ0~DQ7
DQ8~DQ15
/S2
/S0
CS
CS CS
DQML DQML
DQML DQML
CK2 2SDRAMs+15pF
SA0 SA1 SA2
SERIAL PD
SCL SDA
A0 A1 A2
WP
47K
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
PIN FUNCTION
Input Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0 Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S
(/S0-3) Input Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1 Input Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
DQ0-63 Input/Output Data In and Data out are referenced to the rising edge of
CK
DQMB0-7 Input Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Vdd,Vss Power Supply Power Supply for the memory mounted module.
SCL
SDA
SA0-3
Input
Output
Input
Serial clock for serial PD
Serial data for serial PD
Address input for serial PD
4
CK
(CK0 ~ CK3)
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
BASIC FUNCTIONS
/S Chip Select : L=select, H=deselect
/RAS Command
/CAS Command
/WE Command
CKE Refresh Option @refresh command
A10 Precharge Option @precharge or read/write command
CK
define basic commands
The MH4S64BLG provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
Activate(ACT) [/RAS =L, /CAS = /WE =H]
Read(READ) [/RAS =H,/CAS =L, /WE =H]
Write(WRITE) [/RAS =H, /CAS = /WE =L]
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
ACT command activates a row in an idle bank indicated by BA.
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
5
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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COMMAND TRUTH TABLE
COMMAND MNEMONIC CKE
n-1 CKE
n/S /RAS /CAS /WE BA0,1 A10 A0-9
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Adress Entry &
Bank Activate ACT H X L L H H V V V
Single Bank Precharge PRE H X L L H L V L X
Precharge All Bank PREA H X L L H L X H X
Column Address Entry
& Write WRITE H X L H L L V L V
Column Address Entry
& Write with Auto-
Precharge WRITEA H X L H L L V H V
Column Address Entry
& Read READ H X L H L H V L V
Column Address Entry
& Read with Auto
Precharge READA H X L H L H V H V
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
L H L H H H X X X
Burst Terminate TERM H X L H H L X X X
Mode Register Set MRS H X L L L L L L V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
6
A11
X
X
V
X
X
X
X
X
X
X
X
X
X
X
L
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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Current State /S /RAS /CAS /WE Address Command Action
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT Bank Active,Latch RA
L L H L BA,A10 PRE/PREA NOP*4
L L L H X REFA Auto-Refresh*5
LLLLOp-Code,
Mode-Add MRS Mode Register Set*5
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST NOP
L H L H BA,CA,A10 READ/READA Begin Read,Latch CA,
Determine Auto-Precharge
L H L L BA,CA,A10 WRITE/
WRITEA Begin Write,Latch CA,
Determine Auto-Precharge
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10 READ/READA Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
L H L L BA,CA,A10 WRITE/WRITEATerminate Burst,Latch CA,
Begin Write,Determine Auto-
Precharge*3
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
FUNCTION TRUTH TABLE
7
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10 READ/READA Terminate Burst,Latch CA,
Begin Read,Determine Auto-
Precharge*3
L H L L BA,CA,A10 WRITE/
WRITEA
Terminate Burst,Latch CA,
Begin Write,Determine Auto-
Precharge*3
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10 WRITE/
WRITEA ILLEGAL
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10 WRITE/
WRITEA ILLEGAL
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
8
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
9
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP NOP(Idle after tRC)
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
LLLLOp-Code,
Mode-Add MRS ILLEGAL
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
10
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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FUNCTION TRUTH TABLE FOR CKE
Current State CKE
n-1 CKE
n/S /RAS /CAS /WE Add Action
SELF - H X X X X X X INVALID
REFRESH*1 L H H X X X X Exit Self-Refresh(Idle after tRC)
L H L H H H X Exit Self-Refresh(Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
LLXXXXXNOP(Maintain Self-Refresh)
POWER H X X X X X X INVALID
DOWN L H X X X X X Exit Power Down to Idle
LLXXXXXNOP(Maintain Self-Refresh)
ALL BANKS H H X X X X X Refer to Function Truth Table
IDLE*2 H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
LXXXXXXRefer to Current State = Power Down
ANY STATE H H X X X X X Refer to Function Truth Table
other than H L X X X X X Begin CK0 Suspend at Next Cycle*3
listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3
LLXXXXXMaintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
11
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
SIMPLIFIED STATE DIAGRAM
ROW
ACTIVE
IDLE
PRE
CHARGE
AUTO
REFRESH
SELF
REFRESH
MODE
REGISTER
SET
POWER
DOWN
READ
READA
WRITE
WRITEA
READ
SUSPEND
READA
SUSPEND
WRITE
SUSPEND
WRITEA
SUSPEND
POWER
ON
CLK
SUSPEND
CKEL
CKEH
CKEL
CKEH
CKEL
CKEH
CKEL
CKEH
ACT
REFA
REFS
REFSX
CKEL
CKEH
MRS
CKEL
CKEH
WRITE READ
WRITEA
WRITEA READA
WRITE READ
PRE
READA
WRITEA READA
PRE PRE
PRE
POWER
APPLIED
Automatic Sequence
Command Sequence
12
TBST(for Full Page) TBST(for Full Page)
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
R:Reserved for Future Use
/S
/RAS
/CAS
/WE
BA0,1 A11-0
CK
V
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
13
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BURST
LENGTH
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
1
2
4
8
R
R
R
R
0
1
BURST
TYPE SEQUENTIAL
INTERLEAVED
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0 WM 0 0 LTMODE BT BL
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LATENCY
MODE
/CAS LATENCY
2
3
R
R
R
R
R
R
0
1
WRITE
MODE BURST
SINGLE BIT FP: Full Page
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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DQ
Command
Address
CK
ACT
X
Q0 Q1 Q2 Q3
Y
DQ
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the
speed of CLK determines which CL should be used.First output data is available after CL
cycles from READ command.
READ
tRCD
CL=2
Q0 Q1 Q2 Q3
CL=3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
/CAS Latency Timing(BL=4)
Burst Length Timing(CL=2)
DQ
Command
Address
CK
ACT
XY
DQ
READ
tRCD
DQ
DQ
DQ Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7 Q8
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
Q0 Q1 Q2 Q3
Q0 Q1
Q0
Qm Q0 Q1
BL=1
BL=2
BL=4
BL=8
BL=FP
Full Page counter rolls over
and continues to count.
m=511
14
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
Command
Address
CK Read
Y
Q0 Q1 Q2 Q3
Write
Y
D0 D1 D2 D3
/CAS Latency Burst Length Burst Length
DQ
Burst Type
CL= 3
BL= 4
A2 A1 A0
Initial Address BL
Sequential Interleaved
Column Addressing
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
0123456701234567
1234567010325476
2345670123016745
3456701232107654
4567012345670123
5670123454761032
6701234567452301
7 0 1 2
0 1 2 3
1 2 3 0
2 3 0 1
3 0
0 1
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
- - 1
1 2
1 0
3 4 5 6 3 2 1 0
1 0
1 0
8
4
2
15
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
Qa0 Qa1 Qa2 Qa3
ACT
Xb
Xb
01
PRE
tRRD
tRCD 1
ACT
Xb
Xb
01
Precharge all
tRAS tRP
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD.The number of banks which
are active concurrently is not limited.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A8-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start at
BL after READA. The next ACT command can be issued after (BL + tRP) from the previous
READA.
16
A11 Xa Xb Xb
tRCmin
2ACT command/tRCmin
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
Multi Bank Interleaving READ (BL=4, CL=3)
CK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
READ
Y
0
10
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
ACT
Xb
Xb
10
PRE
0
00
tRCD
/CAS latency Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CK
Command
A10
DQ
ACT
Xa
Xa
00
READ
Y
1
00
Qa0 Qa1 Qa2 Qa3
ACT
Xa
Xa
00
Internal precharge begins
tRCD tRP
READ Auto-Precharge Timing (BL=4)
CK
Command ACT READ
Internal Precharge Start Timing
DQ Qa0 Qa1 Qa2 Qa3
DQ Qa0 Qa1 Qa2 Qa3
CL=3
CL=2
17
A0-9
BA0,1
A11 Xa Xb
A11 Xa Xa
BL
BL + tRP
BL
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
Multi Bank Interleaving WRITE (BL=4)
CK
Command
A10
DQ
ACT
Xa
Xa
00
Write
Y
0
00
Write
Y
0
10
Da0 Da1 Da2 Da3
ACT
Xb
Xb
10
PRE
0
00
tRCD
Db0 Db1 Db2 Db3
tRCD
CK
Command
A10
DQ
ACT
Xa
Xa
00
Write
Y
1
00
Da0 Da1 Da2 Da3
ACT
Xa
Xa
00
Internal precharge begins
tRCD tRP
WRITE with Auto-Precharge (BL=4)
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the
Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst
data is defined by the Burst Type. A WRITE command may be applied to any active bank, so
the row precharge time(tRP) can be hidden behind continuous input data by interleaving the
multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at tWR after the last input data
cycle. The next ACT command can be issued after tRP from the internal precharge timing.
The Mode Register can be WRITE command is issued and the remaining burst length is
ignored.The read data burst length os unaffected while in this mode.
18
A0-9
BA0,1
A0-9
BA0,1
A11 Xa Xb 0
PRE
0
10
0
A11 Xa Xa
tWR
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0 at MRS.A burst write stats in
the same cycle as a write command set.(The latency of data input is 0.) The
burst length can be set to 1,2,4,8,and full-page,like burst read operations.
[ SINGLE WRITE ]
A single write operation is enabled by setting A9=1 at MRS.In a single write
operation,data is written only to the column address specified by the write
command set cycle without regard to the burst length setting.(The latency of data
input is 0.)
DQ
Command
Address
CK
ACT
XY
DQ
READ
tRCD
DQ
DQ
DQ Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7 Q8
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
Q0 Q1 Q2 Q3
Q0 Q1
Q0
Qm Q0 Q1
BL=1
BL=2
BL=4
BL=8
BL=FP
Full Page counter rolls over
and continues to count.
m=255
Command
Address
CK
ACT
XY
READ
DQ Q0
tRCD
19
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of any bank. Random column access is
allowed. READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=3)
CK
Command
A10
DQ
READ
Yi
0
00
READ
Yk
0
10
Qai0 Qaj1 Qbk0 Qbk1
READ
Yj
0
00
Qaj0 Qbk2 Qal0
READ
Yl
0
01
Qal1 Qal2 Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 1 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CK
Command
A10
Q
READ
Yi
0
0
Qai0
Write
Yj
0
0
DDaj0 Daj1 Daj2 Daj3
DQMB0-7
DQM control Write control
20
A0-9
BA0,1
A0-9
BA0,1
A11
A11
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same or the other bank. Read
to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to
the /CAS Latency.As a result, READ to PRE interval determines valid data length to be
output.The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CK
Command
DQ
READ PRE
Q0 Q1
Command
DQ
READ PRE
Q0 Q1
Command
DQ
READ PRE
Q0 Q2Q1
Command
DQ
READ PRE
Q0 Q1
Q2
CL=3
CL=2
21
Command
DQ
READ PRE
Q0
Command
DQ
READ PRE
Q0
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command,TBST, can interrupt burst read
operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST is
mainly used to interrupt FP bursts.The figure below show examples, of how the output data
is terminated with TBST.
Read Interrupted by Burst Terminate (BL=4)
CK
Command
DQ
READ TBST
Q0 Q1 Q2 Q3
CL=3
Command
DQ
READ TBST
Q0 Q1 Q2
Command
DQ
READ TBST
Q0
Command
DQ
READ TBST
Q0 Q1 Q2 Q3
CL=2
Command
DQ
READ TBST
Q0 Q1 Q2
22
Command
DQ
READ TBST
Q0
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A10
DQ
Write
Yi
0
00
Write
Yk
0
10
Dai0 Daj0 Daj1 Dbk0
Write
Yj
0
00
Dbk1 Dbk2
Write
Yl
0
00
Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A10
DQ
Write
Yi
0
00
Qaj0
READ
Yj
0
00
Qaj1Dai0 Dbk0 Dbk1
DQMB0-7
Write
Yk
0
10
READ
Yl
0
00
Qbl0
23
A0-9
BA0,1
A0-9,11
BA0,1
A11
A11
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required from the
last data to PRE command.
Write Interrupted by Precharge (BL=4)
CK
Command
A10
DQ
Write
Yi
0
00
PRE
0
00
Dai0 Dai1
DQMB0-7
ACT
Xb
Xb
00
tWR tRP
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can terminate burst write operation. In this case,
the write recovery time is not required and the bank remains active (Please see the
waveforms below).The WRITE to TBST minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
A10
DQ
Write
Yi
0
0
TBST
Dai0 Dai1
DQMB0-7
Dai2
24
A0-9,11
BA0,1
A0-9
BA0,1
A11 Xb
Dai2
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268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
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MIT-DS-0227-0.2
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycles within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on
4bank concurrentry. Before performing an auto-refresh, all banks must be in the idle
state. Auto-refresh to Auto-refresh interval is minimum tRC.Any command must not be
supplied to the device before tRC from the REFA command.
Auto-Refresh
CK
/S
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Auto Refresh on All Banks Auto Refresh on All Banks
minimum tRC
NOP or DESLECT
25
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MIT-DS-0227-0.2
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting
CKE(REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle
state and a new command can be issued after tRC, but DESEL or NOP commands
must be asserted till then.
Self-Refresh
CK
/S
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry Self Refresh Exit
X
00
minimum tRC
+1 CLOCK
for recovery
Stable CK
NOP
new command
26
tSRX
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MIT-DS-0227-0.2
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle, A command at the following cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CK
Command PRE
CKE
Command
CKE
ACT
NOP NOP NOP NOP NOP NOP
NOP NOP NOP NOP NOP NOP
Standby Power Down
Active Power Down
NOP
NOP
DQ Suspend by CKE
CK
Command
DQ
Write
D0 D1 D2 D3
CKE
READ
Q0 Q1 Q2 Q3
27
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DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the output
disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7
to write mask latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
DQ
Write
D0 D2 D3
DQMB0-7
READ
Q0 Q1 Q3
masked by DQM=H disabled by DQM=H
28
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MIT-DS-0227-0.2
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Condition Ratings Unit
Vdd
VI
VO
IO
Pd
Topr
Tstg
Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
with respect to Vss
with respect to Vss
with respect to Vss
Ta=25°C
-0.5 ~ 4.6
-0.5 ~ Vdd+0.5
50
4
0 ~ 70
-40 ~ 100
V
V
V
mA
W
°C
°C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Symbol
Vdd
Vss
VIH
VIL
Parameter
Supply Voltage
High-Level Input Voltage all inputs
Supply Voltage
Low-Level Input Voltage all inputs
Limits Unit
Min. Typ. Max.
3.0
0
2.0
-0.3
3.3
03.6
0
Vdd+0.3
0.8
V
V
V
V
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
Parameter
Input Capacitance, address pin
Input Capacitance, /RAS,/CAS,/WE
Input Capacitance, CK pin
Input Capacitance, I/O pin
Test Condition Limits(max.) Unit
VI = Vss
f=1MHz
Vi=25mVrms
37
37
45
15
pF
pF
pF
pF
29
-0.5 ~ Vdd+0.5
CI(S) Input Capacitance, /CS pin 37 pFCI(E) Input Capacitance, CKE pin 37
pFCI(M) Input Capacitance, DQM pin 15
pF
Note:* VIH (max) = Vdd+2.0V AC for pulse width<=3ns acceptable.
VIL (min) = -2V AC for pulse width< =3ns acceptable.
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MIT-DS-0227-0.2
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
30
Symbol Parameter Test Condition Limits Unit
Min. Max.
VOH(DC) High-Level Output Voltage(DC) IOH=-2mA 2.4 V
VOL(DC) Low-Level Output Voltage(DC) IOL=2mA 0.4 V
VOH(AC
)High-Level Output Voltage(AC) CL=50pF,
IOH=-2mA 2 V
VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V
IOZ Off-stare Output Current Q floating VO=0 ~ Vdd -5 5 uA
Ii Input Current VIH=0 ~ Vdd+0.3V -20 20 uA
Note:Input signals are changed one time during 30ns.
Note:All other pins not under test are 0V.
460
8
4
88
500
600
4
80
8
4
220
160
-7, -8
Test Condition Limits
(max) Unit
tRC=min.tCLK=min, BL=1, IOL=min mA
CKE=VILmax,tCLK=15ns mA
CKE=CLK=VILmax(fixed) mA
mA
tCLK=min, BL=4, CL=3,IOL=0mAall banks active(discerte) mA
tRC=min, tCLK=min mA
CKE <0.2V mA
CKE=/CS=VIHmin,tCLK=15ns(Note)
Symbol
Icc1
Icc2P
Icc2PS
Icc2NS
Icc4
Icc5
Icc6
Icc2N
Parameter
operating current
one bank active (discrete)
precharge stanby current
in power-down mode
burst current
auto-refresh current
self-refresh current
CKE=VIHmin,CLK=VILmax(fixed) mA
precharge stanby current
in non power-down mode mA
Icc3PS
Icc3P mA
active stanby current
in power-down mode
mA
CKE=/CS=VIHmin,tCLK=15ns
Icc3NS
Icc3N CKE=VIHmin,CLK=VILmax(fixed) mA
active stanby current
in non power-down mode
one bank active (discrete)
CKE=VILmax,tCLK=15ns
CKE=CLK=VILmax(fixed)
360
8
4
88
500
460
4
80
8
4
180
160
-10
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MIT-DS-0227-0.2
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
CK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing through
1.4V.
31
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns should
be added to the parameter.
Limits
Symbol Parameter -7 Unit
Min. Max.
tCLK CK cycle time ns
tCH CK High pulse width 3
10
ns
tCL CK Low pilse width 3 ns
tT Transition time of CK 1 10 ns
tIS Input Setup time(all inputs) 2 ns
tIH Input Hold time(all inputs) 1 ns
tRC Row cycle time 70 ns
tRCD Row to Column Delay 20 ns
tRAS Row Active time 50 10000 ns
tRP Row Precharge time 20 ns
tWR Write Recovery time 10 ns
tRRD Act to Act Deley time 20 ns
tRSC Mode Register Set Cycle time 20 ns
tSRX Self Refresh Exit time 10 ns
tREF Refresh Interval time 64 ms
tCCD Col to Col Delay time 10 ns
-8
Min. Max.
3
13
3
1 10
2
1
70
20
50 10000
20
10
20
20
10 64
10
CL=2
CL=3 10 10
-10
Min. Max.
4
15
4
1 10
3
1
90
30
60 10000
30
10
20
20
10 64
10
10
Note
ns 1
1
1
1
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ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
1.4V
1.4VDQ
CK
tAC tOH tOHZ
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Output Load
Condition
VOUT
50pF
50Ω
VTT=1.4V
DQ
CK
Output Timing
Measurement
Reference Point
1.4V
1.4V
32
VREF=1.4V
Note:3 If tr(clock rising time) is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Limits
Symbol Parameter -8 Unit
Min. Max.
tAC Access time from CK 7ns
tOH Output Hold time 3 ns
from CK
tOLZ Delay time, output low
impedance from CK 0 ns
tOHZ Delay time, output high
impedance from CK 3 ns6
-7
Min.
6
3
0
3 6
Max.
66ns
CL=2
CL=3
-10
Min. Max.
8
3
0
38
8
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Burst Write (single bank) @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 0
D0 D0 D0 D0
X
X
X
0
Y
0
D0 D0 D0 D0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
tWR
tRP
tRC
tRCD
CLK
Italic parameter indicates minimum case
tRAS
A0-8
A10
DQM
A9,11
33
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Burst Write (multi bank) @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 1
D0 D0 D0 D0
X
X
0
Y
0
D0 D0 D0 D0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
tRAS
tWR
tRP
tRC
tRCD
D1 D1 D1 D1
X
X
X
1
tRRD
Y
tWR
0
X
1
X
X
X
2
tRRD
ACT#1 WRITE#1 PRE#1
ACT#2
CLK
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
34
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Burst Read (single bank) @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 0
Q0 Q0 Q0 Q0
X
X
X
0
Y
0
Q0 Q0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
tRAS tRP
tRC
tRCD
CL=3
READ to PRE ≥BL allows full data out
DQM read latency =2
CLK
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
35
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Burst Read (multiple bank) @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 0
Q0 Q0 Q0 Q0
X
X
X
0
Y
0
Q0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
tRAS tRP
tRC
tRCD
CL=3
DQM read latency =2
tRRD
X
X
X
1
ACT#1
Y
1
tRRD
Q1 Q1 Q1 Q1
X
X
X
21
CL=3
READ#1 PRE#1 ACT#2
CLK
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
36
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Burst Write (multi bank) with Auto-Precharge @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 1
D0 D0 D0 D0
X
X
0
Y
0
D0 D0 D0 D0
ACT#0 WRITE#0 with
AutoPrecharge ACT#0 WRITE#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
tRC
tRCD
D1 D1 D1 D1
X
X
X
1
tRRD
Y X
1
X
X
X
tRRD
ACT#1 WRITE#1 with
AutoPrecharge
BL-1+ tWR + tRP
Y
1
D1
tRCD
ACT#1 WRITE#1
CLK
BL-1+ tWR + tRP
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
37
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
Q0 Q0 Q0 Q0
X
X
X
0
Y
0
Q0
ACT#0 READ#0 with
Auto-Precharge ACT#0 READ#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
tRC
tRCD
CL=3
DQM read latency =2
tRRD
X
X
X
1
ACT#1
Y
1
tRRD
Q1 Q1 Q1 Q1
CL=3
READ#1 with
Auto-Precharge ACT#1
BL+tRP BL+tRP
X
X
X
1
Y
1
CLK
Q0
CL=3
tRCD
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
38
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Page Mode Burst Write (multi bank) @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 0
D0 D0 D0 D0
ACT#0 WRITE#0 WRITE#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
D1 D1 D1 D1
Y Y
0
WRITE#1
CLK
X
X
X
1
tRRD
1
Y
D0 D0 D0 D0 D0 D0 D0
ACT#1 WRITE#0
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
39
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Page Mode Burst Read (multi bank) @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 0
Q0 Q0 Q0
ACT#0 READ#0 READ#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
Q1 Q1 Q1 Q1
Y Y
0
READ#1
CLK
X
X
X
1
tRRD
1
Y
Q0 Q0 Q0 Q0
ACT#1 READ#0
Q0
CL=3 CL=3 CL=3
DQM read latency=2
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
40
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Write Interrupted by Write / Read @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
D0 D0 D0 D0
ACT#0 WRITE#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
Q0
WRITE#1
CLK
X
X
X
1
tRRD
1
Y
D0 D0 D1 D1 Q0 Q0 Q0
ACT#1 WRITE#0
Y Y
0 0 0
Y
tCCD
CL=3
WRITE#0 READ#0
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
41
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Read Interrupted by Read / Write @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 0
Q0 Q0 Q0
ACT#0 READ#0 WRITE#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
Q0 D0 D0
Y Y
0
READ#1
CLK
X
X
X
1
tRRD
0
Y
Q0 Q0 Q1 Q1
ACT#1 READ#0
Q0
DQM read latency=2
0
Y
1
Y
Burst Read can be interrupted by Read or Write of any active bank.
READ#0 READ#0
blank to prevent bus contention
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
42
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Write Interrupted by Precharge @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
D0 D0 D0 D0
ACT#0 WRITE#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
WRITE#1
CLK
X
X
X
1
tRRD
1
D1 D1 D1 D1 D1
ACT#1
Y
1 1
Y
Burst Write is not interrupted by
Precharge of the other bank.
0
X
X
X
1
PRE#1
PRE#0 ACT#1 WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
43
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Read Interrupted by Precharge @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
Q0 Q0 Q0
ACT#0 READ#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
Y
1
PRE#1
CLK
X
X
X
1
tRRD
Q1 Q1
ACT#1 PRE#0
Q0
DQM read latency=2
1
Y
1
Burst Read is not interrupted
by Precharge of the other bank.
0
X
X
X
1
tRCD
tRP
READ#1 ACT#1 READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
44
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Mode Register Setting
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
Auto-Ref (last of 8 cycles)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Y
0
CLK
tRC
D0
Mode
Register
Setting
M
0
X
X
X
0
tRCD
tRSC
ACT#0 WRITE#0
D0 D0 D0
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
45
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Auto-Refresh @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
Auto-Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
Before Auto-Refresh,
all banks must be idle state.
Y
0
D0
X
X
X
0
tRCD
ACT#0 WRITE#0
D0 D0 D0
After tRC from Auto-Refresh,
all banks are idle state.
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
46
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Self-Refresh
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
Self-Refresh Entry
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
Before Self-Refresh Entry,
all banks must be idle state.
X
X
X
0
Self-Refresh Exit ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
tRC
tSRX
CLK can be stopped
CKE must be low to maintain Self-Refresh
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
47
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
DQM Write Mask @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 0
D0 D0 D0 D0
Y
0
D0 D0 D0
ACT#0 WRITE#0 WRITE#0 WRITE#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
CLK
Y
masked masked
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
48
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
DQM Read Mask @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 0
Q0 Q0 Q0 Q0
Y
0
Q0 Q0 Q0
ACT#0 READ#0 READ#0 READ#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
CLK
Y
masked masked
DQM read latency=2
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
49
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Power Down
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
0
Precharge All ACT#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
X
X
X
Standby Power Down Active Power Down
CKE latency=1
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
50
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
CLK Suspend @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0 0
Q0 Q0 Q0 Q0
ACT#0 WRITE#0 READ#0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRCD
CLK
Y
D0 D0 D0D0
CLK suspendedCLK suspended
CKE latency=1 CKE latency=1
Italic parameter indicates minimum case
A0-8
A10
DQM
A9,11
51
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
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MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
52
OUTLINE
1.27±0.1
133.35±0.13 3.9MAX
34.925±0.13
841
127.35±0.13
17.78±0.13
3±0.13
1±0.13
3±0.13
2±0.13
6.35±0.13
24.495±0.13
8.89±0.13 29x1.27=36.83±0.2
42.18±0.13
9x1.27=11.43±0.2 6.35±0.1 43x1.27=54.61±0.2 1.27±0.1
2-ø3±0.1
17.78±0.13
2-R2±0.13
1±0.13
168 85
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 53 )
MITSUBISHI
ELECTRIC 5. Aug.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.2
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or circuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
diagrams and charts,represent information on products at the time of
publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,
vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
53
