BD9123MUV - ROHM Co., Ltd.

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Single-chip Type with Built-in FET Switching Regulators

Output 1.5A or Less

High-efficiency Step-down Switching Regulator

with Built-in Power MOSFET

BD9123MUV

●Description

ROHM’s high efficiency step-down switching regulator BD9123MUV is a power supply designed to produce a low voltage

including 0.85 to 1.2 volts from 5.5/3.3 volts power supply line. Offers high efficiency with our original pulse skip control

technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden

change in load.

●Features

1) Offers fast transient response with current mode PWM control system.

2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET)

and SLLM (Simple Light Load Mode)

3) Incorporates output voltage inside control function.(3 bit)

4) Incorporates PGOOD function.

5) Incorporates soft-start function.

6) Incorporates thermal protection and ULVO functions.

7) Incorporates short-current protection circuit with time delay function.

8) Incorporates shutdown function Icc=0µA(Typ.)

9) Employs small surface mount package: VQFN016V3030

●Applications

Power supply for LSI including DSP, Micro computer and ASIC

●Absolute maximum ratings (Ta=25℃)

Parameter Symbol Ratings Unit

VCC Voltage Vcc -0.3～+7 *1 V

PVCC Voltage PVcc -0.3～+7 *1 V

EN,SW,ITH Voltage EN, SW, ITH -0.3～+7 V

Logic input voltage VID<2:0> -0.3～+7 V

Power Dissipation 1 Pd1 0.27 *2 W

Power Dissipation 2 Pd2 0.62 *3 W

Power Dissipation 3 Pd3 1.77 *4 W

Power Dissipation 4 Pd4 2.66 *5 W

Operating temperature range Topr -40～+95 ℃

Storage temperature range Tstg -55～+150 ℃

Maximum junction temperature Tj +150 ℃

*1 Pd should not be exceeded.

*2 IC only

*3 1-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2

*4 4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, 1st and 4th copper foil area : 10.29mm2 , 2nd and 3rd copper foil area : 5505mm2

*5 4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers

No.11027EAT38

Technical Note

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BD9123MUV

●Operating Conditions (Ta=-40～+95℃)

Parameter Symbol

Ratings Unit

Min. Typ. Max.

Power Supply Voltage VCC 2.7 3.3 5.5 V

PVCC 2.7 3.3 5.5 V

EN Voltage VEN 0 - Vcc V

Logic input voltage VID<2:0> 0 - 5.5 V

Output voltage Setting Range VOUT 0.85 - 1.2 V

SW average output current ISW - - 1.2*6 A

*6 Pd should not be exceeded.

●Electrical Characteristics (Ta=25℃ V

CC=PVCC=5V, EN=VCC, VID<2>=VID<1>=VID<0>= 0V), unless otherwise specified.)

Parameter Symbol

Limits Unit Conditions

Min. Typ. Max.

Standby current ISTB - 0 10 µA EN=GND

Active current ICC - 300 500 µA

EN Low voltage VENL - GND 0.8 V Standby mode

EN High voltage VENH 2.0 VCC - V Active mode

EN input current IEN - 5 10 µA VEN=5V

VID Low voltage VVIDL - GND 0.8 V

VID High voltage VVIDH 2.0 VCC - V

VID input current IVID - 5 10 µA VVID=5V

Oscillation frequency FOSC 0.8 1 1.2 MHz

Pch FET ON resistance RONP - 0.35 0.60 Ω PVCC=5V

Nch FET ON resistance RONN - 0.25 0.50 Ω PVCC=5V

Output voltage VOUT 0.98 1.0 1.02 V VID<2:0>=(0,0,0)

ITH SInk current ITHSI 25 50 - µA VOUT =1.2V

ITH Source Current ITHSO 25 50 - µA VOUT =0.8V

UVLO threshold voltage VUVLO1 2.4 2.5 2.6 V VCC=5V→0V

UVLO release voltage VUVLO2 2.425 2.55 2.7 V VCC=0V→5V

Power Good Threshold VPGOOD1 70 75 80 % VOUT→0V

Power Good Release VPGOOD2 85 90 95 % 0V→VOUT

Power Good Delay TPG 2.5 5 10 ms

PGOOD ON Resistance RONPG - 140 280 Ω

Soft start time TSS 0.4 0.8 1.6 ms

Timer latch time TLATCH 1 2 4 ms

Output Short circuit threshold Voltage VSCP - VOUT×0.5 VOUT×0.7 V VOUT→0V

Technical Note

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BD9123MUV

●Package outline, SYMBOLS ●Block Diagram, Application Circuit

【BD9123MUV】

VQFN016V3030 (Unit:mm)

Fig.1 BD9123MUV Package outline Fig.2 BD9123MUV Block Diagram

●Pin No. & function table

Pin No. Pin name Function

SW Pch/Nch FET drain output pin

4 PGND Nch FET source pin

6 GND

Ground

7 PGOOD

Power Good pin

8 ITH

Gm Amp output pin/Connected phase

compensation capacitor

9 VOUT Output voltage pin

10 VID<2>

Output voltage control pin<2>

11 VID<1>

Output voltage control pin<1>

12 VID<0>

Output voltage control pin<0>

13 EN Enable pin(High Active）

14 VCC VCC power supply input pin

15 PVCC Pch FET source pin

Fig 3 Top View

13 8

11 10 9

SW SW SW PGND

PGND

GND

VID<0> VID<1> VID<2> VOUT

VCC

PVCC

14 PGOOD

ITH

PVCC

PGND

GND

Output

Gm Amp 4.7µH

VCC

OSC

UVLO

TSD

22µF

Vcc

CLK

SLOPE

Current

Comp 10µF

Soft

Start

Current

Sense/

Protect

Driver

Logic

VREF

ITH

RITH

CITH

SELECTOR

VID<0>

VID<1>

VID<2>

VOUT

PGOOD

VCC

100Ω

0.1µF

Input

Lot No.

D 9 1

2 3

Technical Note

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BD9123MUV

●Characteristics data

100

150

200

250

300

350

400

-40 - 20 0 20 40 60 80 100

TEMPERATURE:Ta[℃]

ON RESISTANCE:RON[O]

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

-40 - 20 0 20 40 60 80 100

TEMPERATURE:Ta[℃]

EN VOLTAGE:VEN[V]

100

125

150

175

200

-40 - 20 0 20 40 60 80 100

TEMPERATURE:Ta[℃]

ON RESISTANCE:RON[O]

200

400

600

800

1000

1200

-40 - 20 0 20 40 60 80 100

TEMPERATURE:Ta[℃]

FREQUENCY:FOSC[kHz]

0.0

0.5

1.0

1.5

2.0

2.7 3.4 4.1 4.8 5.5

INPUT VOLTAGE:VCC[V]

FREQUENCY:FOSC[MHz]

100

1 10 100 1000 10000

Io [A]

EFFICIENCY:?[%]

0.96

0.98

1.00

1.02

1.04

-40 - 20 0 20 40 60 80 100

INPUT VOLTAGE:VCC[V]

OUTPUT VOLTAGE:VOUT[V]

0.0

0.4

0.8

1.2

1.6

2.0

012345

EN VOLTAGE:VEN[V]

OUTPUT VOLTAGE:VOUT[V]

0.0

0.4

0.8

1.2

1.6

2.0

012345

EN VOLTAGE:VEN[V]

OUTPUT VOLTAGE:VOUT[V]

0.0

0.4

0.8

1.2

1.6

2.0

012345

INPUT VOLTAGE:VCC[V]

OUTPUT VOLTAGE:VOUT[V]

Fig. 7 Ta-VOUT

Fig.12 Ta-VEN

Fig.10 Ta-Fosc

Fig.8 Efficiency

Fig.9 Power supply voltage-

Operating frequency

Fig.11 Ta-RONN,RONP

Fig.4 Vcc-VouT Fig.5 VEN - VOUT Fig.6 IOUT-VOUT

Io=1.2A

Ta=2 5 ℃

VCC=5V

Ta=2 5 ℃

Io=0A

【VOUT=1.0V】

VCC=5V

Ta=2 5 ℃

VCC=5V

Io=0A

【VOUT=1.0V】【VOUT=1.0】

【VOUT=1.0V】【VOUT=1.0V】

High side

(PMOS FET)

Low side

(NMOS FET)

VCC=5V

Vcc=5.0V

Ta=2 5 ℃ Ta =25℃

VCC=5V

VCC=5.0V

Fig.14 Soft start waveform Fig.15 SW waveform Io=0mA

VCC=5V

Fig.13 Ta-Icc

【VOUT=1.0V】

VCC=5V

Io=1.2A

Ta=2 5 ℃

VCC=5V

Io=0A Ta=25℃

【SLLM control VOUT=1.0V】

Technical Note

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BD9123MUV

VCC=5V

Io=1.2A

Ta=2 5 ℃

Fig.16 SW waveform Io=1.2A Fig.17 Transient Response

Io=125mA→850mA(2µA)

Fig.18 Transient Response

Io=850mA→125mA(2µA)

Fig.19 BIT CHANCE RESPONSE Fig.21 PGOOD Delay

Fig.20 BIT CHANCE RESPONSE

Ta=2 5 ℃

VID

VID[2:0]=(0,0,1)→(1,1,1)

0.85V

1.2V

VID

1.2V

0.85V

VID[2:0]= (1,1,1)→0,0,1)

PGOOD

VOUT

VCC=5V

Vo=1V

Ta=2 5 ℃

0.9V

0.75V TPG

Ta=2 5 ℃

Technical Note

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BD9123MUV

●Information on advantages

Advantage 1: Offers fast transient response with current mode control system.

Fig.22 Comparison of transient response

Advantage 2: Offers high efficiency for all load range.

・For lighter load:

Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching

dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance

dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.

Achieves efficiency improvement for lighter load.

・For heavier load:

Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor.

ON resistance of Pch side MOS FET : 0.35mΩ(Typ.)

ON resistance of Nch side MOS FET : 0.25mΩ(Typ.)

Achieves efficiency improvement for heavier load.

Offers high efficiency for all load range with the improvements mentioned above.

Advantage 3:

・Supplied in smaller package due to small-sized power MOS FET incorporated.

・Output capacitor Co required for current mode control: 10µF ceramic capacitor

・Inductance L required for the operating frequency of 1 MHz: 4.7µH inductor

Reduces a mounting area required.

Fig.24 Example application

Conventional product (Load response IO=0.1A→0.6A) BD9123MUV (Load response IO=0.6A→0.1A)

DC/DC

Convertor

RITH

VOUT

CITH

VCC

Cin

VCC

R PGOOD

15mm

20mm

CITH

RITH

CIN

RPGOOD

Cf Rf

0.001 0.01 0.1 1

100

①

②

PWM

SLLM

①inprovement by SLLM system

②improvement by synchronous rectifier

Efficiency η[%]

Fig.23 Efficiency

Output current Io[A]

VOUT

27mV

VOUT 37mV

IOUT

Technical Note

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BD9123MUV

●Operation

BD9123MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing

current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load,

while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.

○Synchronous rectifier

It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,

and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power

dissipation of the set is reduced.

○Current mode PWM control

Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.

・PWM (Pulse Width Modulation) control

The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a Pch MOS FET (while a Nch MOS FET

is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a

current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and

issues a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET (while a

lowside MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation.

・SLLM (Simple Light Load Mode) control

When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse

is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without

voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa.

Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current

Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is

tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the

switching dissipation and improves the efficiency.

Fig.25 Diagram of current mode PWM control

Fig.26 PWM switching timing chart Fig.27 SLLM

switching timing chart

Curren

Comp

SET

RESET

VOUT

PVCC

GND

IL(AVE)

VOUT(AVE)

SENSE

Curren

Comp

SET

RESET

VOUT

PVCC

GND

VOUT(AVE)

SENSE

Not switching

OSC

Level

Shift Driver

Logic

ITH

Current

Comp

Gm Amp.

SET

RESET

Load

SENSE

VOUT

Technical Note

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BD9123MUV

●Description of operations

・Soft-start function

EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during

startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.

The inclination of standing up is different and the soft start time is different because of constancy depending on the value

offset output voltage. When 1V settiing it, it is Tss=1msec(Typ.)

Fig.28 Soft start action

・Shutdown function

With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference

voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0µA(Typ.).

・UVLO function

Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of

50mV (Typ.) is provided to prevent output chattering.

Fig.29 Soft start, Shutdown, UVLO timing chart

・PGOOD function

When the output voltage falls below 75% (Typ.) of a set value, the PGOOD pin of Open-Drain is turned off. And the

hysteresis width of 15% (Typ.) is provided to prevent output chattering.

Fig.30 PGOOD timing chart

UVLO

Hysteresis 50mV

Ts s Ts s Ts s

Soft start

Standby mode

Operating mode

Standby

mode Operating mode

Standby

mode Operating mode Standby mode

Vcc

VOUT

VCC,EN

Tss

Tss’

1.2V

0.85V

[ms]

VOUT

90%

The hysteresis width

VOUT

75%

PGOOD

TGP

Technical Note

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BD9123MUV

●About setting the output voltage

Output voltage shifts step by step as often as bit setting to control the overshoot/undershoot that happen when changing the

setting value of output voltage. From the bit switching until output voltage reach to setting value, 8 steps (max) delay will

occur.

ⅰ) Switching 3 bit synchronously ⅲ) Switching the bit during counting

ⅱ) Switching 3 bit with the time lag

It is possible to set output voltage, shown the diagram 1 below, by setting VID<0>～<2> 0 or 1.

VID<2:0> terminal is set to VID<2:0>=(0,0,0) originally by the pull down resistor with high impedance inside IC.

By pulling up/ pulling down about 10kΩ, the original value is changeable optionally.

Table of output voltage setting

VID<2> VID<1> VID<0> VOUT

0 0 0 1.0V

0 0 1 0.85V

0 1 0 0.9V

0 1 1 0.95V

1 0 0 1.05V

1 0 1 1.1V

1 1 0 1.15V

1 1 1 1.2V

*After 10µs(max) from the bit change, VOUT change starts.

*Requiring time for one step (50 mV shift) of VOUT is 5µs(max).

*From the bit switching until output voltage reach to setting value, tVID(max)=0.06ms delay will occur.

VOUT

VID<2:0> (0,0,1) (1,1,1)

1.2

0.85V

tVID (max)=0.06ms

Fig.31 Timing chart of setting the output voltage

About 10µs from bit switching

VOUT

Count STOP

About 10µs from switching the last bit

VID<2>

VID<1>

VID<0>

〈1〉

V2D〈2〉

VOUT

〈0〉

Count STOP

About 10µs from bit switching

VID<2>

VOUT

Count STOP

VID<1>

VID<0>

(

max

)

Technical Note

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BD9123MUV

・Short-current protection circuit with time delay function

Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for

the fixed time (TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking

UVLO.

Fig.32 Short-current protection circuit with time delay timing chart

●Switching regulator efficiency

Efficiency ŋ may be expressed by the equation shown below:

Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:

Dissipation factors:

1) ON resistance dissipation of inductor and FET: PD(I2R)

2) Gate charge/discharge dissipation: PD(Gate)

3) Switching dissipation: PD (SW)

4) ESR dissipation of capacitor: PD (ESR)

5) Operating current dissipation of IC: PD(IC)

1) PD(I2R)=IOUT2×(RCOIL+RON)

(RCOIL[Ω]: DC resistance of inductor, RON[Ω]: ON resistance of FET, IOUT[A]: Output current.)

2) PD(Gate)=Cgs×f×V

(Cgs[F]: Gate capacitance of FET、f[H]: Switching frequency、V[V]: Gate driving voltage of FET)

4) PD(ESR)=IRMS2×ESR

(IRMS[A]: Ripple current of capacitor, ESR[Ω]: Equivalent series resistance.)

5) PD(IC)=Vin×ICC

(ICC[A]: Circuit current.)

η= VOUT×IOUT

Vin×Iin

×100[%]= POUT

POUT+PDα

×100[%]

Output voltage OFF Latch

t2=TLATCH

VCC

VOUT

Output Short circuit

Threshold Voltage

Output voltage

OFF Operated mode Operated mode

UVLO Timer Latch UVLO

Output voltage

OFF

IL Limit

t1<TLATCH

Vin2×CRSS×IOUT×f

IDRIVE

3) PD(SW)=

(CRSS[F]: Reverse transfer capacitance of FET, IDRIVE[A]: Peak current of gate.)

Technical Note

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BD9123MUV

●Consideration on permissible dissipation and heat generation

As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is

needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input

voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation

must be carefully considered.

For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.

Because the conduction losses are considered to play the leading role among other dissipation mentioned above including

gate charge/discharge dissipation and switching dissipation.

If VCC=3.3V, VOUT=1.2V, RONP=0.35mΩ, RONN=0.25mΩ

IOUT=1.2A, for example,

D=VOUT/VCC=1.2/5=0.24

RON=0.24×0.35+(1-0.24)×0.25

=0.084+0.19

=0.274[Ω]

P=1.22×0.247=0.394[W]

As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration

on the dissipation as above, thermal design must be carried out with sufficient margin allowed.

P=IOUT2×RON

RON=D×RONP+(1-D)RONN

D：ON duty (=VOUT/VCC)

RONP：ON resistance of Highside MOS FET

RONN：ON resistance of Lowside MOS FET

IOUT：Output curren

Fig.33 Thermal derating curve

(VQFN016V3030)

Ambient temperature:Ta [℃]

0 25 50 75 100 125 150

2.0

3.0

4.0

②1.77W

①2.66W

Power dissipation:Pd [W]

1.0 ③0.62W

④0.27W

① 4 layers (Copper foil area : 5505mm2)

copper foil in each layers.

θj-a=47.0℃/W

② 4 layers (1st and 4th copper foil area : 6.28m2)

(2nd and 3rd copper foil area: 5505m2)

(copper foil in each layers)

θj-a=70.62℃/W

③ 1 layer (Copper foil area : 6.28m2)

θj-a=201.6℃/W

④ IC only.

θj-a=462.9℃/W

105

Technical Note

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BD9123MUV

●Selection of components externally connected

1. Selection of inductor (L)

The inductance significantly depends on output ripple current. As seen

in the equation (1), the ripple current decreases as the inductor and/or

switching frequency increases.

Appropriate ripple current at output should be 20% more or less of the

maximum output current.

※Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases

efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its

current rating.

If VCC=5.0V, VOUT=1.2V, f=1MHz, ΔIL=0.3×1.2A=0.36A, for example,

※Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for

better efficiency.

2. Selection of output capacitor (CO)

Output capacitor should be selected with the consideration on the

stability region and the equivalent series resistance required to smooth

ripple voltage.

Output ripple voltage is determined by the equation (4):

ΔVOUT=ΔIL×ESR [V]・・・(4)

(ΔIL: Output ripple current, ESR: Equivalent series resistance of

output capacitor)

※Rating of the capacitor should be determined allowing sufficient

margin against output voltage. A 10µF to 100µF ceramic capacitor is

recommended.

Less ESR allows reduction in output ripple voltage.

3. Selection of input capacitor (Cin)

Input capacitor to select must be a low ESR capacitor of the capacitance

sufficient to cope with high ripple current to prevent high transient voltage.

The ripple current IRMS is given by the equation (5):

A low ESR 10µF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.

ΔIL=

(VCC-VOUT)×VOUT

L×VCC×f

[

]

・・・

(

)

ΔIL=0.3×IOUTmax. [A]・・・(2)

(VCC-VOUT)×VOUT

ΔIL×VCC×f

[

]

・・・

(

)

(ΔIL: Output ripple current, and f: Switching frequency)

(

5-1.2

)

×1.2

0.6×5×1M

L= =2.53µ → 4.7 [µH]

Fig.34 Output ripple current

ΔIL

VCC

VOUT

Fig.35 Output capacitor

VCC

VOUT

ESR

IRMS=IOUT×

VOUT

(

VCC-VOUT

)

VCC [A]・・・

(

)

√

When Vcc=2×VOUT, IRMS=

IOUT

< Worst case > IRMS(max.)

If VCC=5V, VOUT=1.2V, and IOUTmax.=1.2A,

IRMS=1.2× 1.2

(

5-1.2

)

5=0.51

[

ARMS

]

√

Fig.36 Input capacitor

VCC

L Co

VOUT

Cin

Technical Note

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BD9123MUV

Fig.39 Typical application

4. Determination of RITH, CITH that works as a phase compensator

As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area

due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high

frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the

power amplifier output with C and R as described below to cancel a pole at the power amplifier.

Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load

resistance with CR zero correction by the error amplifier.

Fig.37 Open loop gain characteristics

Fig.38 Error amp phase compensation characteristics

fp= 2π×RO×CO

fz(ESR)=2π×ESR×CO

Pole at power amplifie

When the output current decreases, the load resistance Ro

increases and the pole frequency lowers.

fp(Min.)=2π×ROMax.×CO

1[Hz]←with lighter load

fp(Max.)=2π×ROMin.×CO

1[Hz]←with heavier load

Zero at power amplifie

Increasing capacitance of the output capacitor lowers the

pole frequency while the zero frequency does not change.

(This is because when the capacitance is doubled, the

capacitor ESR reduces to half.)

fz(Amp.)=2π×RITH.×CITH

Gain

[dB]

Phase

[deg]

-90

fz(Amp.)

fp(Min.)

fp(Max.)

fz(ESR)

IOUTMin. IOUTMax.

Gain

[dB]

Phase

[deg]

fz(Amp.)= fp(Min.)

2π×RITH×CITH

1 = 2π×ROMax.×CO

GND,PGND SW

VCC,PVCC

VOUT

ITH

VCC

VOUT

Cin

RITH

CITH

ESR

VOUT

PGOOD

VCC

RPG

VID<2:0

)

VID<2:0>

Technical Note

14/17

www.rohm.com 2011.01 - Rev.

BD9123MUV

●Cautions on PC Board layout

Fig.40 Layout diagram

① Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the

pin PGND.

② Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.

※VQFN016V3030 has thermal PAD on the reverse of the package.

The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of

PCB.

●Recommended components Lists on above application

Recommended components Lists

Symbol Part Value Manufacturer Series

L Coil 4.7uH TDK VLF5014S-4R7M1R7

CIN Ceramic capacitor 10uF KYOCERA CM316X5R106M10A

CO Ceramic capacitor 22uF KYOCERA CM316B226M06A

CITH Ceramic capacitor 1500pF murata GRM18 Series

RITH Resistance 9.1kΩ ROHM MCR03 Series

Cf Ceramic capacitor 0.1uF murata GRM18 Series

Rf Resistance 100Ω ROHM MCR03 Series

※The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit

characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to

accommodate variations between external devices and this IC when employing the depicted circuit with other circuit

constants modified. Both static and transient characteristics should be considered in establishing these margins. When

switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and

PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins.

Technical Note

15/17

www.rohm.com 2011.01 - Rev.

BD9123MUV

●I/O equivalence circuit

【BD9123MUV】

・EN pin ・SW pin

・VOUT pin ・ITH pin

・PGOOD ・VID〈2:0〉 pin

Fig.41 I/O equivalence circuit

PVCC

PVCC PVCC

ITH

VCC

VOUT VID〈2:0〉

PGOOD

Technical Note

16/17

www.rohm.com 2011.01 - Rev.

BD9123MUV

●Notes for use

1. Absolute Maximum Ratings

While utmost care is taken to quality control of this product, any application that may exceed some of the absolute

maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,

short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the

absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.

2. Electrical potential at GND

GND must be designed to have the lowest electrical potential In any operating conditions.

3. Short-circuiting between terminals, and mismounting

When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may

result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and

power supply or GND may also cause breakdown.

4. Thermal shutdown protection circuit

Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to

protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be

used thereafter for any operation originally intended.

5. Inspection with the IC set to a pc board

If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the

capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper

grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the

inspection process, be sure to turn OFF the power supply before it is connected and removed.

6. Input to IC terminals

This is a monolithic IC with P+ isolation between P-substrate and each element as illustrated below. This P-layer and the

N-layer of each element form a P-N junction, and various parasitic elements are formed.

If a resistor is joined to a transistor terminal as shown in Fig 42.

○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or

GND>Terminal B (at transistor side); and

○if GND>Terminal B (at NPN transistor side),

a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.

The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,

and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such

manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in

activation of parasitic elements.

7. Ground wiring pattern

If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND

pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that

resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the

small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.

8. Selection of inductor

It is recommended to use an inductor with a series resistance element (DCR) 50mΩ or less. Especially, in case output

voltage is set 1.6V or more, note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output

voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit

protection will be activated and output will be latched OFF. When using an inductor over 50mΩ, be careful to ensure

adequate margins for variation between external devices and this IC, including transient as well as static characteristics.

Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within operation range.

Fig.42 Simplified structure of monorisic IC

Resistor Transistor (NPN)

N N P+ P

P substrate

GND

Parasitic element

Pin A

N P+ P+

P substrate

GND

Parasitic element

Pin B

C B

GND

Pin A

aras

iti

element

Pin B

Other adjacent elements

B C

GND

aras

iti

element

Technical Note

17/17

www.rohm.com 2011.01 - Rev.

BD9123MUV

●Ordering part number

B D 9 1 2 3 M U V - E 2

Part No. Part No.

Package

MUV : VQFN016V3030

Packaging and forming specification

E2: Embossed tape and reel

∗

Order quantity needs to be multiple of the minimum quantity.

Embossed carrier tapeTape

Quantity

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

3000pcs

()

Direction of feed

Reel 1pin

(Unit : mm)

VQFN016V3030

12 9

0.5

0.75 0.25 +0.05

−0.04

1.4±0.1

0.4±0.1

C0.2

1.0MAX

0.02 +0.03

−0.02

(0.22)

3.0±0.1

1PIN MARK

0.08 S

R1120

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