CyberPro2010
Data Sheet
“The Internet Multimedia Company!”
Revision 1.A1F
CyberPro2010 DATA SHEET
ii IGS Technologies, Inc.
CyberPro2010
Data Sheet
September, 1997
1997 IGS Technologies, Inc. All rights reserved.
Printed in the United States of America
IGS Technologies, Inc.
4001 Burton Drive
Santa Clara, CA 95054
Phone (408) 982-8588
FAX (408) 982-8591
http://www.igst.com
CyberPro2010 DATA SHEET
IGS Technologies, Inc. iii
Table of Contents
1. FEATURES OVERVIEW..................................................................................................................................................1-1
1.1 WORLD’S FIRST
TV
DIRECT™ OUTPUT .......................................................................................................................1-1
1.2 VL BUS INTERFACE ..................................................................................................................................................1-1
1.3 DUOVISION™ DUAL DISPLAY SUPPORT ......................................................................................................................1-1
1.4 64-BIT GUI, 128/64/32-BIT EDO INTERFACE...............................................................................................................1-1
1.5 FLEXIBLE VIDEO INPUTS............................................................................................................................................1-1
1.6 SUPPORT FOR VIDEO GAMES ON TV...........................................................................................................................1-1
1.7 RGB/COMPOSITE/S-VIDEO/AMD SCART TV .............................................................................................................1-1
1.8 MPEG MOVIE PLAYBACK ON TV................................................................................................................................1-1
1.9 VIDEO EDITING/PHONE/VIDEO CONFERENCING ON TV..................................................................................................1-1
2. FEATURES DESCRIPTION.............................................................................................................................................2-1
2.1 INTEGRATED BRIDGE, GUI & ENCODER......................................................................................................................2-1
2.2 FLICKER-FREE
TV
DIRECT™ OUTPUT.........................................................................................................................2-1
2.3 WORLD’S FIRST FLEXIBUS™ INTERFACE.....................................................................................................................2-1
2.4 DUOVISION™ DUAL DISPLAY SUPPORT ......................................................................................................................2-1
2.5 VIDEO CAPTURE AND PLAYBACK OUTPUT....................................................................................................................2-1
3. VL BUS INFORMATION..................................................................................................................................................3-1
3.1 AMD ELAN4XX CPU INTERFACES.............................................................................................................................3-1
3.2 POWER-UP BUS TYPE CONFIGURATION.......................................................................................................................3-1
3.3 VL PIN DESCRIPTION................................................................................................................................................3-2
3.4 VL PIN DESCRIPTION TABLES ....................................................................................................................................3-3
3.4.1 Host Interface (VL)..................................................................................................................................3-3
3.4.2 Memory Interface (VL).............................................................................................................................3-4
3.4.3 Miscellaneous (VL)..................................................................................................................................3-4
3.4.4 Power (VL)..............................................................................................................................................3-5
3.4.5 Video Port Interface (VL) .........................................................................................................................3-5
3.4.6 CRT & TV Interface (VL)..........................................................................................................................3-5
3.5 VL TIMING DIAGRAMS...............................................................................................................................................3-6
3.5.1 VL Bus LCLK Timing...............................................................................................................................3-6
3.5.2 VL Bus Write and Read Cycle..................................................................................................................3-6
3.5.3 VL Bus Input Setup and Hold Timing........................................................................................................3-7
3.5.4 VL Bus Output Valid Delay Timing...........................................................................................................3-7
3.5.5 VL Bus Output Float Delay Timing...........................................................................................................3-8
4. ADDRESSING MODES...................................................................................................................................................4-1
4.1 LEGEND FOR DECODE TABLES ...................................................................................................................................4-1
4.2 VL LINEAR INFORMATION ..........................................................................................................................................4-1
4.2.1 Address Map...........................................................................................................................................4-1
4.2.2 VL Linear Address Decodes ....................................................................................................................4-1
CyberPro2010 DATA SHEET
iv IGS Technologies, Inc.
Table of Contents
5. FRAME BUFFER MEMORY TIMING...............................................................................................................................5-1
5.1 EDO/FAST PAGE MODE............................................................................................................................................5-1
5.1.1 Read Cycle.............................................................................................................................................5-1
5.1.2 Write Cycle .............................................................................................................................................5-2
5.1.3 Read-to-Write Cycle................................................................................................................................5-2
5.1.4 Write-to-Read Cycle................................................................................................................................5-3
5.1.5 Timing Parameters..................................................................................................................................5-3
5.2 MEMORY TIMING SPECIFICATIONS ..............................................................................................................................5-4
5.2.1 Clock Waveforms....................................................................................................................................5-4
5.2.2 Clock Skew.............................................................................................................................................5-4
5.2.3 Clock Skew Parameters...........................................................................................................................5-4
5.2.4 Output Timing .........................................................................................................................................5-5
5.2.5 Input Timing............................................................................................................................................5-5
6. ELECTRICAL CHARACTERISTICS................................................................................................................................6-1
6.1 ABSOLUTE MAXIMUM RATINGS...................................................................................................................................6-1
6.2 DC SPECIFICATIONS (DIGITAL)...................................................................................................................................6-1
6.3 DAC CHARACTERISTICS............................................................................................................................................6-2
7. PACKAGE DIMENSIONS................................................................................................................................................7-1
CyberPro2010 DATA SHEET
IGS Technologies, Inc. 1-1
1. Features Overview
1.1 World’s First
TV
Direct™ Output
• Integrated TV Encoder for Direct NTSC/PAL
• Only requires a single crystal for NTSC/PAL
• NTSC(640x480,60Hz), PAL(800x600/640x480,50Hz)
• Simultaneous S-video, composite & AMD SCART TV
• Simultaneous VGA & TV
1.2 VL Bus Interface
• Direct Interface to 486 Embedded Processors via VL bus,
including AMD Elan 400/410
1.3 DuoVision™ Dual Display Support
• DuoVision provides simultaneous display of graphics on
VGA while playing MPEG movies on TV
1.4 64-bit GUI, 128/64/32-bit EDO Interface
• 64-bit GUI engine, 200mhz RAMDAC, dual clock
• Supports EDO DRAM from 1MB up to 4MB
1.5 Flexible Video Inputs
• VBI data including Intercast, teletext, CC support
• CCIR656/8-bit video input interface
1.6 Support for Video Games on TV
• Shadow registers provide complete compatibility for
popular DOS, Windows, and other video games on TV
1.7 RGB/Composite/S-video/AMD SCART TV
• Six DAC’s on-chip to support TV RGB, Composite,
S-video and AMD SCART outputs
• Best Text, Video quality for composite underscan TV
output using 3-line buffers, Interpolation, 9-bit DAC for
8/16/24-bit colors
• Flicker control bypass for best video quality on TV
• Higher precision PLL to work with any TV world wide
1.8 MPEG Movie Playback on TV
• MPEG-2 movie playback on TV using H/W MPEG-2
decoders/players
• DirectDraw MPEG-1 playback on TV with S/W
• High quality horizontal and vertical interpolation with
jagged edge smoothing
1.9 Video Editing/Phone/Video Conferencing
on TV
• Three scaleable video windows plus PIP
• Direct input from TV tuner, analog & digital camera via
IGS video port and decoder ASIC
• High quality multitap filtering during video capture
• Mirror/upside down support for video conferencing
RAM/
ROM
CyberPro2010
AMD
Elan400/410
Embedded
CPU
RAM
Cable/
Modem
IR Universal
Remote
Video
Decoder
VGA
TV-Composite
TV-S-video
Cable/Tel. Line
Remote Control
Keyboard
Video Camera
Audio
TV-SCART
(RGB, Composite,
S-video)
Speaker/Mic
MPEG2
Decoder
i
Figure 1-1. System Block Diagram Example
CyberPro2010 DATA SHEET
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CyberPro2010 DATA SHEET
IGS Technologies, Inc. 2-1
2. Features Description
2.1 Integrated Bridge, GUI & Encoder
The CyberPro2010 is the FIRST and ONLY
multimedia accelerator that integrates three
major components of an NC/SetTop/Internet
Appliance/TV design; namely, CPU Bridge, GUI
and video Accelerator, and NTSC/PAL TV
Encoder.
In addition, the CyberPro2010 integrates high
speed 200 MHz RAMDAC and clock.
The CyberPro2010 has a 64-bit GUI multimedia
accelerator which interfaces to true single cycle
SDRAM, SGRAM and EDO DRAM frame buffer
sizes from 1MB to 4MB. It provides VGA output
up to 1600x1200 resolutions for enterprise NC
applications.
2.2 Flicker-Free
TV
Direct™ Output
The TVDirect™ feature incorporates an on-chip
NTSC/PAL TV encoder which has a proprietary
flicker free technology with a 3-line buffer. It
provides the best TV quality for the majority of
TV’s worldwide, where composite input is the
norm with its underscan interpolation
techniques, high precision PLL and 9-bit DAC.
Also, SetTops can be designed with several
glueless connectors directly from the
CyberPro2010 for simultaneous connections,
including VGA, RGB at TV frequency, SCART,
S-video and Composite TV outputs.
2.3 World’s First FlexiBus™ Interface
The flexuous feature incorporates the CPU
bridge functions for most of the embedded
CPU’s which are designed into NC’s, SetTops
and Internet appliances. As indicated in
Table 2-1, the CyberPro2010 has a glueless
CPU bus interface to all PCI, VL bus and RISC
CPU’s, like IBM and Motorola PowerPC, NEC
V83X, Hitachi SHX and ESS ES3208.
In addition, any other RISC CPU can be
interfaced through the non-multiplexed linear VL
bus interfaced on-chip. This lowers the total
BOM for an Internet appliance to a cost lower
than any competitive solution on the market.
2.4 DuoVision™ Dual Display Support
The DuoVision™ feature, unique to the
CyberPro2010, enables simultaneous display on
TV of video (DVD, MPEG, karaoke or video
conferencing) and VGA graphics.
2.5 Video Capture and Playback Output
The CyberPro2010 provides the best quality
video capture and playback output on TV of any
single chip solution, by using its multi-tap filters,
interpolation techniques and multiple hardware
windows capability. These features are very
important for SetTop designs which require DVD
or MPEG output on TV or video conferencing
capability where the CyberPro2010 can interface
directly to DVD decoders (connected to DVD
drives, players or satellite equipment) or video
decoders (connected to analog or digital
cameras, or a VCR).
CPU
Bridge
strongARM
PowerPC
SH
MIPS
Java
x86
64-bit GUI
&
Video
Accelerator
NTSC/PAL
Encoder
RGB
NTSC
PAL
SCART
Composite
S-video
Figure 2-1: Block Diagram
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CyberPro2010 DATA SHEET
IGS Technologies, Inc. 3-1
3. VL Bus Information
• Faster memory means higher performance for the CyberPro2010, allowing use of EDO and FPM
DRAM of 35-60ns.
• For VL bus configuration, the memory bus bandwidth is always 32-bit for 1MB and 2MB.
3.1 AMD Elan4XX CPU Interfaces
ADR[31:2] ADS# W/R# LRDY#
CS#/AUX[1:0] LDEV# RDYTRN# INTR
DAT[31:0] LCLK MIO# RESET#
BE[3:0]#
3.2 Power-up Bus Type Configuration
All memory addresses from RA8 to RA0 have an internal power-down.
RA2 RA1 RA0 Bus Type
100VL Standard
101VL Linear Address
CyberPro2010 DATA SHEET
3-2IGS Technologies, Inc.
3.3 VL Pin Description
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
VSS
VDD
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
BE0#
DAT8
DAT9
DAT10
DAT11
DAT12
DAT13
VSS
DAT14
DAT15
BE1#
MIO#
NC
LDEV#
PVDD
LRDY#
RDYRTN#
ADS#
BE2#
DAT16
DAT17
DAT18
DAT19
DAT20
VSS
DAT21
DAT22
DAT23
W/R#
BE3#
DAT24
DAT25
DAT26
DAT27
DAT28
DAT29
DAT30
DAT31
RESET#
VSS
VDD
VDD
VSS
RCVCK
RCMCK
VSS
VDD
VSS
I2CCK
ADR27
ADR19
ADR28
ADR18
ADR29
ADR17
ADR30
ADR16
ADR31
VSS
OE0#
CAS/WE0#
RAS0#
WE/CAS2#
WE/CAS3#
M0D23
M0D24
MOD22
M0D25
M0D21
M0D26
M0D20
M0D27
VSS
PVDD
M0D19
M0D28
M0D18
M0D29
M0D17
M0D30
M0D16
M0D31
LUMA
CAS/WE1#
RAS1#
WE/CAS4#
WE/CAS5#
IREF
VDD
B
G
R
VDD
COMP
CHROMA
VSS
PVDD
VDD
I2CDA
XTIN
XTOUT
VSS
ADR20
ADR26
ADR21
ADR25
ADR22
ADR24
ADR23
WE/CAS7#
WE/CAS6#
RA8
RA0
VSS
RA7
RA1
RA6
RA2
RA5
RA3
RA4
VSS
VDD
VSS
PVDD
M0D15
M0D0/JA0
M0D14
M0D1/JA1
M0D13
M0D2/JA2
M0D12
M0D3/JA3
M0D11
VSS
M0D4
M0D10
M0D5
M0D9
M0D6
M0D8
M0D7
WE/CAS1#
WE/CAS0#
PVDD
DAT0
DAT1
VSS
VSS
ADR7
ADR8
ADR6
ADR9
NC
ADR5
ADR10
ADR4
ADR11
ADR3
ADR12
VSS
PVDD
ADR2
ADR13
NC
ADR14
NC
ADR15
HSYNC
VSYNC/CSYNC
NC
DDC_CK
ODD
PIXCLK
VSS
QVSYNC
HREF
QHSYNC
DDC_DA
PA2
PA3
PA4
PA5
PA6
LCLK
PA7
PA0
PA1
PORT2
NC
PORT3
OE1#
PORT0/CSYNC
PORT1
INTR
VACE#
NC
NC
PVDD
VSS
CyberPro2010
VL Bus Pinout
CyberPro2010 DATA SHEET
IGS Technologies, Inc. 3-3
3.4 VL Pin Description Tables
3.4.1 Host Interface (VL)
Name Type Pin No. Description
ADR[31:2] I/O 170,168,166,164,
162,149,147,145,
144,146,148,150,
163,165,167,169,
20,18,16,12,10,8,
5,3,2,4,7,9,11,15
The address bus furnishes the physical memory or I/O port
addresses to the VL bus target.
LCLK I37 The system input clock signal.
INTR O47 Used to request an interrupt to the system.
RESET# I58 System reset. During power-up or a hardware reset, this signal
must be at a logic low for at least 1ms. When this signal is low, the
CyberPro2010 is in a reset state, all the pins are inactive, and the
memory data bus is tri-state.
DAT[31:0]I/O 59,60,61,62,63,
64,65,66,69,70,
71,73,74,75,76,
77,87,88,90,91,
92,93,94,95,97,
98,99,100,101,
102,106,107
Data bus. This is a bi-directional data path between VL bus devices
and the CPU.
BE[3:0]#I/O 67,78,86,96 Byte enable. The byte enables indicate which byte lanes of the 32-
bit data bus are involved with the current VL bus transfer.
W/R# I/O 68 Writer or read status. This CPU output indicates the type of access
currently executing on the VL bus.
ADS# I/O 79 Address data strobe. ADS# indicates the start of the VL bus cycle.
RDYRTN# I/O 80 Ready return. RDYRTN# establishes a handshake so the VL bus
target knows when the cycle has ended.
LRDY# I/O 81 Local ready. LRDY# begins the handshake that terminates the
current active bus cycle when the target is not bursting.
LDEV# I/O 83 Device select. LDEV# is an active low output signal that responds
to the current access, which means it is a valid cycle for the
CyberPro2010.
MIO# I/O 85 Memory or I/O status. This CPU output indicates the type of access
currently executing on the VL bus.
CyberPro2010 DATA SHEET
3-4IGS Technologies, Inc.
3.4.2 Memory Interface (VL)
Name Type Pin No. Description
OE1# O44 Output enable.
WE/CAS[7:0]#O143,142,199,198,
176,175,110,109 Used to control different banks of memory.
M0D[31:0]I/O 194,192,190,188,
184,182,180,178,
177,179,181,183,
187,189,191,193,
127,125,123,121,
119,116,114,112,
111,113,115,117,
120,122,124,126
Used to transfer data between DRAM and the CyberPro2010.
RA[8:0]O141,138,136,
134,132,133,
135,137,140,
Output address pins to DRAM.
OE0# O172 Output enable. Used to control output enable to the DRAM.
CAS/WE[1:0]#O196,173 Each of these signals is used to control one bank of DRAM.
RAS[1:0]# O197,174 ROW ADDRESS STROBE[1:0]# is used to control the DRAM
RAS# signal.
3.4.3 Miscellaneous (VL)
Name Type Pin No. Description
NC 6,17,19,23,42,49,50,
84 No connection.
PORT2 I/O 41 Port I/O programmable pin.
PORT3 I/O 43 Port I/O programmable pin.
PORT0/
CSYNC I/O 45 Port I/O programmable pin/composite sync for TV.
PORT1 I/O 46 Port I/O programmable pin.
RCVCK I53 RC filter for internal DOT clock.
XTOUT O152 An output loop back pin for a crystal.
XTIN I153 An input pin for a crystal.
I2CDA I/O 154 I2C bus serial data input/output.
RCMCK I157 RC memory clock. An input from the memory clock RC network to
control the memory frequency.
I2CCK I/O 161 I2C bus serial clock input/output.
IREF O200 DAC reference current.
CyberPro2010 DATA SHEET
IGS Technologies, Inc. 3-5
3.4.4 Power (VL)
Name Type Pin No. Description
VSS I1,13,27,52,54,57,72,
89,104,105,118,
129,131,139,151,
158,160,171,185,
208
0.0V
PVDD I14,51,82,108,128,
156,186 I/O pad power, 3.3/5.0V.
VDD I55,56,103,130,155,
159,201,205 +5.0V.
3.4.5 Video Port Interface (VL)
Name Type Pin No. Description
ODD I/O 25 Odd/even field ID.
PIXCLK I/O 26 Video port clock.
QVSYNC I/O 28 Vertical sync for video port.
QHSYNC I/O 30 Video port horizontal reference or sync.
HREF I/O 29 Horizontal Reference.
PA[7:0] I/O 38,36-32,40,39 Video port data.
VACE# O48 Video port enable.
3.4.6 CRT & TV Interface (VL)
Name Type Pin No. Description
HSYNC O21 HSYNC to CRT/fast switch (SCART).
VSYNC/
CSYNC O22 VSYNC to CRT; composite sync to TV.
DDC_CK I/O 24 DDC2B clock.
DDC_DA I/O 31 DDC2B data.
LUMA O195 Luminance output/TV blue.
BO202 Blue analog output connected to the monitor/TV blue.
G O 203 Green analog output connected to the monitor/TV green.
RO204 Red analog output connected to the monitor/TV red.
COMP O206 Composite video output/TV red.
CHROMA O207 Chrominance output//TV green.
CyberPro2010 DATA SHEET
3-6IGS Technologies, Inc.
3.5 VL Timing Diagrams
3.5.1 VL Bus LCLK Timing
t4
t2 t1
t3 t5
LCLK
3.5.2 VL Bus Write and Read Cycle
LRDY#
LDEV#
A B C/D A B C/D A B
LCLK
ADS#
DAT[31:0]
RDYRTN#
ADR[31:2]#,BE[3:0]#,
MIO#,W/R#,D/C#
W/R#
Valid Valid
2
ReadWrite
1
CyberPro2010 DATA SHEET
IGS Technologies, Inc. 3-7
3.5.3 VL Bus Input Setup and Hold Timing
LCLK
LRDY#
ADS#
DAT31-0
RDYRTN#
ADR[31:2]#,BE[3:0]#,
MIO#,W/R#,D/C#
t43 t42
t44
t21(w) t22
t20(r)
t47 t48
t12 t13
t8 t9
3.5.4 VL Bus Output Valid Delay Timing
LCLK
LRDY#
ADS#
DAT31-0
ADR[31:2]#,BE[3:0]#,
MIO#,W/R#,D/C#
max
(100pf) t41
(100pf) t45
Valid N Valid N+1
min
max
t18
Valid N Valid N+1
min
max
t10
Valid N Valid N+1
min
max
t6
Valid N Valid N+1
min
CyberPro2010 DATA SHEET
3-8IGS Technologies, Inc.
3.5.5 VL Bus Output Float Delay Timing
LCLK
LRDY#
ADS#
DAT31-0
ADR[31:2]#,BE[3:0]#,
MIO#,W/R#,D/C#
t42
t19
Valid N
t11
t7
Valid N
Valid N
CyberPro2010 DATA SHEET
IGS Technologies, Inc. 4-1
4. Addressing Modes
4.1 Legend for Decode Tables
#0 or one range
xDon’t Care
CRISC processor chip select (active low)
$Binary range ($$$ : from 0 to 7)
JJumper setting at power-up (JJJJ : M0D[3:0]
4.2 VL Linear Information
ADR[23:0] ADR[31:24]
1st 1MB Memory 00JJ JJ00
2nd 1MB Memory 00JJ JJ00
Map I/O Write 00JJ JJ00
Map I/O Read BE0 00JJ JJ00
Map I/O Read BE1 00JJ JJ00
Map I/O Read BE2 00JJ JJ00
Map I/O Read BE3 00JJ JJ00
R/W Port [7:0] 00JJ JJ00
R/W TV 2K Byte 00JJ JJ00
COPREG R/W 00JJ JJ00
EPROM Read (R=0) 00JJ JJ00
COP Memory (R=1) 00JJ JJ00
4.2.1 Address Map
1. M0D[3:0] has internal pull-down.
2. At power-up, M0D[3:0] to decode the
linear address.
3. M0D[3:0] is mapped to linear address
A[29:26].
4. Process addresses A[31:30] and
A[25:24] are always zero.
5. Example:
At power-up, M0D[3:0] = 0101; then,
linear address will be 0001,0100 or 14H.
4.2.2 VL Linear Address Decodes
ADR[23:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1st 1MB Memory 0 0 0 0 # # # # # # # # # # # # # # # # # # x x
2nd 1MB Memory 0 0 0 1 # # # # # # # # # # # # # # # # # # x x
Map I/O Write 10000000##xx# # ########x x
Map I/O Read BE0 1 0 0 0 0 0 0 0 # # 0 0 # # # # # # # # # # x x
Map I/O Read BE1 1 0 0 0 0 0 0 0 # # 0 1 # # # # # # # # # # x x
Map I/O Read BE2 1 0 0 0 0 0 0 0 # # 1 0 # # # # # # # # # # x x
Map I/O Read BE3 1 0 0 0 0 0 0 0 # # 1 1 # # # # # # # # # # x x
R/W Port [7:0] 1000101%1 1 0 $ $ $ ########00
R/W TV 2K Byte 1000101%1110x# ########00
COPREG R/W 1000101%1 1 1 1 # # ########00
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CyberPro2010 DATA SHEET
IGS Technologies, Inc. 5-1
5. Frame Buffer Memory Timing
For memory timing parameters, refer to the manufacturer’s data manual.
5.1 EDO/Fast Page Mode
All timing is relative to the memory clock (MCLK).
5.1.1 Read Cycle
Read data latch position relationship (small vertical rectangle in the diagram under T4):
1. Coprocessor read (3CE.7A[7:6]): If the CAS wave form has been used for the memory
read data latch, then 3CE.7A[6:5] controls the edge to latch the memory read data.
2. Other reads (3CE.79[5:4]): If the CAS wave form has been used for the memory read
data latch, then 3CE.79[3:2] controls the edge to latch the memory read data.
Row
T5 T6
T1
T2
T3
T4
RAS#
CAS#
MA[8:0]
WE#
Column
T7 T8
OE#
T15
T9
M0D[31:0]
M1D[31:0] Data
CyberPro2010 DATA SHEET
5-2IGS Technologies, Inc.
5.1.2 Write Cycle
Row
RAS#
CAS#
MA[8:0]
WE#
T10 T11
OE#
M0D[31:0]
M1D[31:0] Data
T12 T13
Column
5.1.3 Read-to-Write Cycle
Row
RAS#
CAS#
MA[8:0]
WE#
T17
T14
OE#
M0D[31:0]
M1D[31:0] Data
Column
T18
Column
Word
CyberPro2010 DATA SHEET
IGS Technologies, Inc. 5-3
5.1.4 Write-to-Read Cycle
Row
RAS#
CAS#
MA[8:0]
WE#
T19
T16
OE#
M0D[31:0]
M1D[31:0] RD
T20
Column
Word
Column
5.1.5 Timing Parameters
Symbol T Periods (T = 1xMCLK) Register[Bits]
T1 2.5-4T 3CE.70[0]; 3CE.70[1]
T2 2.5-4T 3CE.70[0]; 3CE.70[2]
T3 1T Fixed
T4 0,2,4,6 ns 3CE.79[1:0]
T5 2.5-3T 3CE.70[0]
T6 2T Fixed
T7 0.5-1T 3CE.F4[0]
T8 1-1.5T 3CE.F4[0]
T9 2-2.5T 3CE.70[0]
T10 0.5T Fixed
T11 1.5T Fixed
T12 0.5-1T 3CE.73[5]
T13 1-1.5T Fixed
T14 1-3T 3CE.73[1]; 3CE.7A[0]
T15 1T Fixed
T16 1-2T 3CE.7A[1]
T17 0.5-2.5T 3CE.F8[1:0]
T18 1-3T 3CE.F8[3:2]
T19 0.5T Fixed
T20 1T Fixed
CyberPro2010 DATA SHEET
5-4IGS Technologies, Inc.
5.2 Memory Timing Specifications
5.2.1 Clock Waveforms
5.0V Clock
2.0V PP
(MIN)
T_cyc
T_high
2.4V
0.4V
2.0V
1.5V
0.8V
3.3V Clock
0.2Vcc PP
(MIN)
0.6Vcc
0.2Vcc
0.5Vcc
0.4Vcc
0.3Vcc
T_low
5.2.2 Clock Skew
CLK
(@ Device #1
T_skew
V_ih
V_il
CLK
(@ Device #2
V_test
V_il
V_ih
T_skew
V_test
T_skew
5.2.3 Clock Skew Parameters
Symbol 5.0V Signaling 3.3V Signaling Units
V_test 1.5 0.4Vcc V
T_skew 2 (max) 2 (max) ns
CyberPro2010 DATA SHEET
IGS Technologies, Inc. 5-5
5.2.4 Output Timing
V_tl
CLK
V_th
Output
Delay
T_val
V_test
V_test (5V Signal)
V_step (3.3V Signal)
Tri-state
Output
T_on
T_off
5.2.5 Input Timing
V_tl
CLK
V_th
INPUT
T_su
V_test
Inputs Valid
V_th
T_su
V_tl
V_test V_test V_max
CyberPro2010 DATA SHEET
5-6IGS Technologies, Inc.
THIS PAGE INTENTIONALLY LEFT BLANK
CyberPro2010 DATA SHEET
IGS Technologies, Inc. 6-1
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Ambient temperature ......................................... 0°C to 55°C
Storage temperature.......................................... -65°C to 150°C
Voltage on any digital pin................................... -0.5V to Vcc + 0.5V
Power supply voltage......................................... -0.5V to 7.0V
Injection current (latch-up testing)...................... 100mA
Note:
Stresses above those listed may cause permanent damage to the device. These are absolute stress
ratings only. Functional operation at these or any conditions above those indicated in the operational
ratings of this specification is not implied. Exposure to absolute maximum ratings conditions for extended
periods may affect device reliability.
6.2 DC Specifications (Digital)
(Vcc = 5V ± 5%, TA = 0° to 70°C, unless otherwise specified.
Symbol Parameter MIN MAX Units Test Conditions
IVcc Internal Power Supply Voltage 4.75 5.25 V5.0V Operation
BVcc I/O Bus Interface
Power Supply Voltage 4.75
3.0 5.75
3.6 V
V5.0V Bus Interface
3.3V Bus Interface
ICC Power Supply Current 350 mA MCLK = 50 MHz
VCLK = 80MHZ
VIL Input Low Voltage 00.8 V
VIH Input High Voltage 2.0 Vcc + 0.5 V
VOL Output Low Voltage 0.5 VIOL = 16mA
VOH Output High Voltage 2.4 VIOH = -10mA
IOH Output High Current 16 mA VOH = 2.4V
IOL Output Low Current 16 mA VOL = 0.5V
IOZ Input Leakage -10 10 µA0 < VIN < VCC
CIN Input Capacitance 7pF
COUT Output Capacitance 10 pF
CyberPro2010 DATA SHEET
6-2IGS Technologies, Inc.
6.3 DAC Characteristics
(Vcc = 5V ± 5%, TA = 0° to 70° C)
Parameter MAX Units Test Note
Resolution (each DAC) 8Bits
Output Current (White Level) 20 mA VO <1V 1,2
Analog Output Rise/Fall Time 8ns 4
Analog Output Settling Time 15 ns 5
Analog Output Skew TBD ns
DAC-to-DAC Matching 5%
Glitch Impulse Typical TBD pV-Sec
Integral Linearity Error ±1LSB
Differential Linearity Error ±1LSB
Notes:
1. IREF = 8.39mA.
2. Load is 37.5Ω and 10 pF per analog output.
3. TD is measured from the 50% point of VCLK to 50% point of full-scale transition.
4. Rise time is measured from 10% to 90% full-scale; fall time is measured from 90% to 10% full-scale.
5. Settling time is measured from 50% of full-scale transition to output remaining within 2% of final
value.
CyberPro2010 DATA SHEET
IGS Technologies, Inc. 7-1
7. Package Dimensions
0.50 (0.020) 0.20 (0.008)
28.00 (1.102)
30.60 (1.205)
25.50 (1.020)30.60 (1.205)
0.50 (0.020)
1.30 (0.051)
0°-10°
3.32 (0.131)
0.25 (0.010)
0.15 (0.006)
THK
CyberPro2010
Figure 7-1. CyberPro2010 Physical Dimensions
