Understanding Large FIFOs - Cypress Semiconductor

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Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

May 1992 - Revised December 1995

Understanding Large FIFOs

Introduction

This application note explains the internal operation of the

large FIFOs manu factured by Cypress and shows how to use

the devices to accomplish depth and width expansion. Other

topics covered here include FIFO interfacing, the writing and

reading process, failure modes, and typical problem symp-

toms and solutio ns. This informat ion applies to the followi ng

Cypress FIFOs: CY7C419, CY7C420, CY7C421, CY7C424,

CY7C425, CY7C428, CY7C429, CY7C432, CY7C433,

CY7C439, CY7C460, CY7C462, CY7C464, CY7C470,

CY7C472, and CY7C474.

Timing parameters given in this application note are taken

from Cypress Semiconductor’s

High Performance Data Book

Large FIFO Overview

The Cypress product line of large FIFOs include densities

from 256 x 9 up to 32, 768 (32K) x 9,with the depth doubling

(256, 512, 1K, 2K, 4K, 8K, 16K, 32K) between densities.

These monolithic devices are available in a wide variety of

packages with the indust ry standard pinout and wi th access

times a s fast as t en na noseconds and cycle t imes as fast as

twenty nanoseconds. Not all speed grades a re ava ilable in all

densities or a ll pack ages, so cons ult the Cyp ress data book to

determine valid speed, density, package combinations. The

smallest packag e av a i lable is the 32-lead 7mm x 7mm T QFP,

which oc cupies less than one-third the area of a 300-mil-wide

28-pin DIP.

Although the first FIFOs utili zed a shift-register t ype of archi-

tecture, today’s large FIFOs employ an SRAM t ype of inter-

face. Data is written into and read out of the devices, as with

SRAM write and read operations. These operations can occur

independently of one another and are made possible by a

spec ially d esigned six-transistor , dual-ported SRAM cell. This

cell makes use of s eparate read an d write transistors to allow

independent R/W operation.

Operating these FIFOs at their maximum throughput rates

demands the generation of nar row writ e and read pulses. To

facilitate significantly higher throughput rates, Cypress has

developed the CY7C440 and CY7C450 families of clocked, or

self-timed FIFOs.

These FIFOs feature 70-MHz operation and are character-

ized by self-timed interfaces. You generate the read and write

enables, which are combined internally wi th the appropriate

clocks. Thus, you do not need to generate narrow read and

write pulses. These FIFOs also feature totally independent,

asyn chronous, read and wri te oper ations.

Each FIFO is organized su ch that data is read out in the same

sequential order in which it was written. Full, half-full and

empty flags facilitate wri ting and reading. Additio nal pins ar e

provided to facilitate unlimited expansion in width and depth,

with no performance penalty.

Writing to and Reading from the FIFO

Figure 1

shows the la rge F IFOs’ read and write timing. Reads

and writes are asynchronous to each other. The read proce ss

Figure 1. Asynchronous Read and Write Timi ng

tPR

tRR

tRC

tDVR tHZR

tWC

DATAOUT VA LID

tLZR

Q0-Q8

WtPW tWR

DATAIN VALID

tHD

tSD

DATAIN VALID

D0-D8

DATAOUT VALID

Understanding Large FIFOs

begins with R’s falling edge. The output data bus, Q0–Q8,

leaves the high-impedance s tate t LZR ns after R’s falling edge.

The output data becomes valid tA ns after that same falli ng

edge. This tA period is referred t o as the FIFO’s re ad a ccess

time. R’s ri sing edge ends the read process.

The data on the Q0–Q8 bus remains valid for tDVR ns following

the R rising edge. This is the output data hold time at the end

of the read cycle. The internal circuitr y then readies itself for

the next r ead operation. This peri od is ref erred to as the tRR,

or read recovery time, and must be observed between con-

secutive read operations. The read signal’s minimum pulse

width is denoted by tPR and is identical to the read access

time, tA.

You can determine the read cycle time (tRC) by adding the

access time (tA) and the read re covery tim e (tRR), which you

can find in the FIFO data sheet. The maximum read frequen-

cy is the reciprocal of tA + tRR. For example, a Cypress FIFO

with a 20-ns access time and a 10-ns re ad recover y ti me re-

sults in a 30-ns re ad cycle time, or 33.3-MHz maximum read

cycle frequency.

The wr ite process is similar to the rea d process. A write be-

gins with the fal ling edge of th e write line, W, and terminates

with W’s rising edge. For a valid write to occur, the input data

bus , D0–D8 , must be stable for t SD ns prior to W’s rising edge

and for tHD ns after this edge. These specifications are re-

ferred to as the data set-up and hold t imes, respectively. The

write strobe also has a minimum negative pulse width, denot-

ed as tPW. A minimum recovery time, tWR, is required between

write cycles.

The maximum write frequency is the reciprocal of tPW + tWR.

As an example, a device with a 20-ns write strobe width and

a 10-ns write recov ery time yields a 30-ns write cycle time, or

a 33.3-MHz maximum write cycle frequency.

The FIFOs include separate write and read counters (point-

ers). Each write or read o peration increments the ap propriate

counter one position. When the FIFO is empty, both counters

point to the same location. The relative position of these

counters determines the device’s status, which is indicated

externally via empty, half-ful l, and full flags.

Applications

FIFOs are asynchronous devices that are ide al for interfacing

between two asynchronous processes. A FIFO allows two

systems running at different data rates to communicate by

providi ng a temporar y data or control buffer.

Typical FIFO applications include

• Interprocessor communications, in which bidire ctional de-

vices are especially useful

• Communicatio ns systems, including local ar ea networks

• Digital-signal-processing-based systems for buffering

real-time data

• Electronic data processing, CPU, and peripheral equip-

ment, i ncluding high-p erform ance disk controllers

Common FIFO Configurations

All large FIFOs ca n be interconnected , without external log ic,

to create either wider FIFOs, deeper FIFOs, or both. Standa-

lone operation, width expansion, depth expansion, and de-

sign considerations are described next.

Figure 2

illustrates standalone mode, and

Figure 3

shows

width e xpansion mode. In both the se modes, the XI (expan-

sion in) pin is grounded and the FL (first load) pin is tied HIGH.

The OR gates in the wi dth-expansion design generate com-

posite full, half-full, and empty flags (F, HF, E). Composite

flags are necess ary becau se variations in propagation delays

might prevent the individual FIFOs in the design from entering

the F, HF, or E states simultaneously. A composite flag prop-

erly reflects the insta ntaneous stat us of t he entire word.

Figure 4

illustrates depth expans ion. The FL (first load) pin on

one device must be grounded to define that FIFO as the first

FIFO t o be written to. Th e FIFOs are then daisy-chained to-

gether by co nnecting o ne device’ s XO (expans io n o ut) ou tput

pin to the next device’ s XI (expa nsion in) input. The XO of the

last device in the chain is connected to the XI of t he f irst de-

vice, thus forming a token-passing ring.

Figure 2. Stan dalo ne Operatio n

WRITE ENABLE

INPUT DATA W R OUTPUT DATA

READ ENABLE

STATUS FLAGS

FULL, EMPTY, HALF-FULL

D0–D8 Q0–Q8

+5V

MASTER RESET

Understanding Large FIFOs

Figure 3. Wi dth Expansion

FF EF

Vcc

READ

CY7C420

CY7C421

CY7C424

CY7C425

CY7C428

CY7C429

9DATA IN

FULL

CY7C420

CY7C421

CY7C424

CY7C425

CY7C428

CY7C429

CY7C420

CY7C421

CY7C424

CY7C425

CY7C428

CY7C429

DATA IN

RESET

DATA OUT

EMPTY

XIFL

WRITE

Figure 4. Depth Expansion

READCY7C420

CY7C421

CY7C424

CY7C425

CY7C428

CY7C429

DATA IN

WRITE

FULL 9

CY7C420

CY7C421

CY7C424

CY7C425

CY7C428

CY7C429

CY7C420

CY7C421

CY7C424

CY7C425

CY7C428

CY7C429

DATA OUT

EMPTY

RESET

XO EF

VCC

Understanding Large FIFOs

Token passing allows the writing and reading processes to

stay consistent. That is, the passing and holding of a read or

write token tells an individual FIFO whether it is actively being

read from or written to. In the token-passing procedure for

write operations, the first FIFO is written to until it is filled. An

internal write pointer determines the location written to, and

after every write, the p ointer is incremented. When the pointer

reaches th e last physical locati on, no mor e writes c an o ccur

to th at device. At that point, the first FIFO passes the write

token to the next FIFO in the chain via the XO–XI interface.

The second device, now in possession of the write token, re-

ceives all future written data until this device also fills up and

passes the write token onto the next device i n the chain.

If enough wr ites oc cur to fill up the FIFO chain, the las t device

fails in its attempt to pass the write token back to the first

device. This is because the full FIFO cannot accept a write

token. No further writes to the FIFO chain are allowed until a

read operation occurs, which frees up an internal location.

The relati ve positi ons of the internal write and re ad counters

determine a device’s status and whether it can accept data

though a write operatio n.

Figure 5

shows the timing for write

operations.

As with the procedure for writes, the first FIFO in the chain

holds the read t oken. When the FI FO chai n is read from, the

device holding the read token supplies the data from the ad-

dress specified by the device’s read pointer . The read pointer

is then incremented. The incrementing continues until the

FIFO is empty , and the read token is passe d to the next device

in the chain. The passing of the read token is done via the

XO–XI interface.

Figure 6

shows the timing for read opera-

tions.

A depth-expansion design must generate composite status

flags to adequately reflect the instantaneous state of the FIFO

chain, as is done for width expansion.

Figure 5. Write Expansion Timi n g

WRITE TO LAS T PHYSICAL

LOCATION OF DEVICE 1

W RIT E TO FIRST P HY S ICA L

LOCATION OF DEVICE 2

XO1[1] (XI)2

DO - D8 VA LID DATA VA LI D DATA

tXOH

tXOL

tSD tHD

Figure 6. Read Expansion Tim ing

READ FROM LAST PH YSICAL

LOCATION OF DE VICE 1

READ FROM FIRST PHYSICAL

LOCATION OF DE VICE 2

XO1[1] (XI)2

QO - Q8 VALID DATA OUT

tXOH

tXOL

tLZR tDVR tHZR

VALID DATA OUT

Understanding Large FIFOs

Retransmit

The retransmit feature is useful in communications for re-

transmitting packets of data and in disk drives for rewriting

sectors. It is especially useful i n applications where a single

block of data in the FIFO must be sent out multiple times, as

in a word or pattern generator.

Data can be retransmitted any number of times, and with Cy-

press FIFOs, the retransmit fe ature can be used at any time,

no mat ter how mu ch data the FIFO contains. This is in con-

trast to some competing FIFOs, such those from IDT, which

do not allow use of the retr ansmi t fu nctio n wh en the FIFO i s

full .

In the retransmit operation, the read pointer is reset to its

initial locati on and the R pin is pulsed until the read pointer

advances to the same memory location addressed by the

write pointer. The retransmit (RT) pin is available in the sin-

gle-device an d width- expansion modes, but n ot i n depth ex-

pansion because this pin designates the FIFO to be loaded

first.

The retransmit function is initiated by asserting an ac-

tive-LOW pulse to the retransmit input, which resets the inter-

nal read counter to zero. Keep the R inp ut inactive during this

time; otherwise, the conflicting requirements on the read

counter might cause it to become corr upted. T he retransmit

process does not affect the state of the write counter or the

write process, though the retransmit tim ing constraints shown

Figure 7

must not be violated.

Note that the architect ural description in the 19 90 and pre vi-

ous Cypress data books incorrectly stated that the W input

must be inactive dur ing a ret ransmit cycle. No design or us-

age rules are violated if retransmit and write cycles overlap or

occur simultaneously; the device does not lock up, and data

is neither lost nor corrupted.

The reasons for the data book’s retransmit/write restriction

are more historical and application-oriented than functional.

Specifically, the first large FIFOs did not permit writes during

a retransmit cycle. Thi s set a do cumentat ion precedent that

all future devices had to match.

Additionally, keeping track of what data is currently in the

FIFO and what data is being read o ut can b ecome complica t-

ed. For example, if a FIFO is ha lf full and the retransmit func-

tion is activated and writ e s continue, fillin g the FIFO to t hree

quarters full before the read pointer catches up with the write

pointer, the FIFO outputs all of the dat a.

Common Problems and Solutions

To help prevent prob lems and correct them when they occur,

this section describes the causes and solutions to some com-

mon FIFO problems. The first problem to consider is corrupt-

ed or repetitive data in a FIFO.

Corrupt ed or Repet itive Data

The most common caus e of corrupted a nd repetitive data b e-

ing present in a FIFO is a spurious active signa l (glitch) on the

FIFO’ s W input. Because Cypress devices are extremely fast,

a wr it e pul se as sh ort as 3 ns ini tiat es a wr it e. Writ e glit ch es

cause whatever logic levels are present at the data inputs to

be written into the FIFO, which can put false data into the

device . If valid data is present at the data inputs, a wr ite glitch

caus e s this data to b e writte n a second ti me, resulti ng in du-

plicat ed data.

Write g litches are often the resu lt of voltage reflections due to

impedance mismatches, which you can eliminate using im-

pedance-matching termination networks. Termination net-

works are recommended on the W and R traces on printed

circuit boards (PCBs) when the lines exce e d approximately 4

in ches from source to a single load . This line length ass umes

a 2-ns rise/fall time for the read and write strobes. For R and

W signals with sub-2- ns rise/fall tim es, line lengths a s short

as 1 i n ch might requi re termi nat ion.

A termination network matches the load impedance to the

PCB trace’s characteristi c impedance, which is typically 50Ω

or less for microstrip or stripli ne construction on G- 10 glass

epoxy material. To minimize voltage reflections, a slightly

overdamped term inat ion is preferred. Cypress recommends

a 47-pF (max.) series capacitor and a 47-ohm resistor be

connected from the read or write pin to ground (

Figure 8

). This

termination network acts as a high-pass filter to short,

high-frequency pulses and dissipates no DC power. Read or

write lines that drive more than one FIFO require only one

termination network. Put the network at the input that is elec-

trically farthest from the source. For multiple loads, see the

“Systems Design Considerations When Using Cypress

CMOS Circuits” application note for help in determining the

maximum line leng th.

Figure 7. Retransmit Timing

FL,RT

tPRT[2]

tRTR[3]

Understanding Large FIFOs

FIFO data corruption can also be cau sed by violation of mas-

ter-reset t iming constr aints. A s shown in the timing diagram

Figure 9

, the read and write signals must be inactive around

the rising edge of MR (master reset) to satisfy the t RMR, or

master-reset recovery-time specification. This constraint is

necessary because the FIFO goes through an internal i nitial-

ization process during reset and requires a settling period

after the reset terminates.

FIFO Locks Up

Short noise pulses on the FIFO’s master reset pin can cause

the FIFO t o not respond because it is “partiall y reset.” If this

problem occurs, you need to terminate the master reset line.

Missing or Di s appeari ng Data

Gli tches on the R inpu t ca n caus e data t o disappe ar be cause

of an unintended read operation. The read increments the

internal read counter, resulting in the loss of the current data

word. Here again, a termination network eliminates the un-

wante d glitches.

Repetiti ve or Out-of -Sequence Data, Fals e Full or Empty

A misaligned internal read or w rite pointer can caus e a v ariety

of symptoms, including repetitive or out-of-sequence data

and false full and/or empty conditions. Th e two most common

causes of misaligned pointers are master-reset violations and

boundary-condition violati ons.

Bounda ry condition s are define d as the FIFO b eing either full

or empty. When high-density FIFOs are c onnected in parallel

to make a wider word, c ertain conditions c an cause the FIFOs

to choose individually to either ignore or act upon a read or

write request. The system-level sympt om of individual FIFOs

making different decisions is word misalignment. The prob-

lem o ccurs in th e empt y conditi on when a read imme di ately

follows a write and in th e full co ndition wh en a write immedi-

ately foll ows a read.

Operation at t he Empty Boundary

Consider a FIFO that has been reset and is empty. The empty

flag is active (LOW), and internal logic inhibits read opera-

tions. In the general case, the read and write signals are asyn-

chronous . Upon completion of th e wr ite operation the in ternal

state of t he FIFO go es from em pty to empty + 1. During this

interval, a read operation might or might not be reco gnized. A

read preceding the write is ignored; a read following the write

is not. In between the se conditions, the FIFO decides whether

to recognize the read. During this aperture of uncertainty, it

cann ot be de termined whether the read will be ignored or not.

With one FIFO, this uncertainty is acceptable. Howeve r , i f two

or more FIFOs are connected in parallel to make a wider

word, some might ignore the read, and others might not.

Operation at the Full Boundary

A similar condition o ccurs when a single FIFO becomes full.

The full flag is active (LOW), and intern al logic inhibits write

operations. A read operation immediately followed by a write

operation causes the FIFO to go from full to full – 1 and back

to full. During the time the FIFO is going from full to full – 1, a

write operati on might or might not be recognized. The aper-

ture of uncertainty applies here because the FIFO takes a

finite amount of time to change states, and a write command

arriving at this instant might be ignored.

Figure 8. Recom mended Ter minati on Network

CYPRESS

FIFO

SOURCE

47 pF

R, W

47 OHMS

Figure 9. Master Reset Timing

tMRSC

tRPW

tWPW tRMR

R, W

Understanding Large FIFOs

Waiting at the Empty Boundar y

Figure 10

shows the timing th at prevents problems w ith reads

at the empty boundary. Any device reading from the FIFO

must wait an amount of time, tRAE, after the termination of the

write operation before causing a HIGH-to-LOW transition of

the R signal. The W signal ’s rising edge indicates the termi -

nation of the write operation.

One way to satisfy this timing is to gate read operations with

the composite empty f lag (EF) such that the read operation is

prevent ed when the empty flag is active. Note, however, that

the R signal can be LOW either b efore or during the first write

to the empty FIFO and the data still propagates to the outputs

correctly .

Waiting at t he Full Boundar y

Figure 11

shows the ti ming that prevents problems with wri tes

at the full boundary. Any device writing to the FIFO must wait

an amount of time, tWAF, after the termination of the read op-

eration before causing a HIGH-to-LOW transition of the W

signal. The R signal’s rising edge indicates the end of the read

operation.

You can meet t hi s timi ng by ga ting writ e operat ions wi th the

composi te full flag (FF) such that the write operation is pre-

vented when the fu ll f lag is active. However, the W signal can

be LOW either before or during the first read from a full FIFO

and the dat a is sti ll properly written.

Empty Reads an d Full Writes

When Cypress FIFOs are empty, their data outputs go to the

high-impedance state. Therefore, attempt ing to read from an

empty FIFO yields unpredictable data. Internal logic inhibits

the read, and the read pointer is not incremented.

Internal logic also inhibits attempts to write to a full FIFO, and

the write pointer is not incremented.

Figure 10. Read Fall-Through Timing Violation

DATA OUT

tRAE[4]

tWEF

VA LID DATA

Figure 11. Write Bubble-Thro ugh Timing Violatio n

tWAF[5]

tRFF

Understanding Large FIFOs

of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey or im ply any li cense under patent or other rights. Cypress Semicondu ctor does not authori ze

its products for use as critic al components in life-support sy stems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Effective Pulse Width Violat ion

This phenomenon can occur at either the empty or the full

boundary if the flags are not properly used. The empty flag

must be used to prevent reading from an empty FIFO and the

full fl ag m ust be used t o prevent writing into a full FIFO. Oth-

erwise, the ef fective pulse width of the read or the write strobe

will be violated, even though the actual signals meet the data

sheet specif ications.

Consider an empty FIFO that is receiving read pulses. Be-

cause the FIFO is empty, the read pulses are ignored, and

nothing happe ns. Next, a single word is written into the FIFO,

with a signal that is asynchronous to the read pulses, while

the read pulses continue. The internal state machine in the

FIFO goes from empty to empty + 1 shortly after the rising

edge of the write pulse . However, it does th is asynchronou sly

with resp ect to the read pulse, and it does no t loo k at the read

signal until it enters the empty + 1 state. I f the rising e dge of

the write signal occurs slightly before the rising edge of the

read signal an effective minimum LOW read pulse widt h vio-

lati on will oc cur.

In a similar manner, the minimum write pulse width may be

violated by attempting to write into a full FIFO and asynchro-

nously performi ng a r ead. The empt y a nd full f lags must be

used t o avoid these effective pulse width violations.

Intermittent Malfunctions

If all the timing requirements appear to be met and data in the

FIFO is still corrupted, the cause is likely to be noise on the

power supply. Random spikes on either the VCC or ground

pins of th e FIFO are likely culprits when non-repeatable fail-

ures occur.

The cure for this problem is to add a high-pas s f ilter capacitor

between th e device ’s p ower a nd ground pins. This practice is

recommended whenever the read or write frequency ex ceeds

5 MHz. Use a very small (100–500 pF) ceramic or mica ca-

pacitor. Surface-mounted capacitors are recommended be-

cause they have at least an order of magnitude less lead in-

ductance than radial or axial leaded capacitors.

The filter c apacitor is in addition to the 0.1- or 0.01-µF de cou-

pling capacitor that should always be present with any

high-speed digital chip. Although decoupling capacitors are

often referred to as bypass capacitors-implying filtering prop-

erties-their true function is to supply the instantaneous cur-

rent required when man y or a ll device o utputs simultaneou sly

switch from LOW to HIGH. This larger capacitor th u s decou-

ples or isolate s the IC from the power distributio n system.

Notes

1. Expansion out of device 1 (XO1) is connected to expansion in of

device 2 (XI2).

2. tPRT is the minimum retransmit pulse width.

3. tRTR is the retransmit recovery time. It is a timing window that must

not be violated.

4. tRAE is an invalid read window. A read operation should never be

initiated inside this window.

5. tWAF is an invalid write window. A write operation should never be

initiated inside this window.