JFET Transistor
N–Channel
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain–Source Voltage VDS 25 Vdc
Gate–Source Voltage VGS 25 Vdc
Gate Current IG10 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board(1)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 556 °C/W
Junction and Storage Temperature TJ, Tstg –55 to +150 °C
DEVICE MARKING
MMBFU310LT1 = 6C
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Gate–Source Breakdown Voltage (IG = –1.0 µAdc, VDS = 0) V(BR)GSS –25 – Vdc
Gate 1 Leakage Current (VGS = –15 Vdc, VDS = 0) IG1SS – –150 pA
Gate 2 Leakage Current (VGS = –15 Vdc, VDS = 0, TA = 125°C) IG2SS – –150 nAdc
Gate Source Cutoff Voltage (VDS = 10 Vdc, ID = 1.0 nAdc) VGS(off) –2.5 –6.0 Vdc
ON CHARACTERISTICS
Zero–Gate–Voltage Drain Current (VDS = 10 Vdc, VGS = 0) IDSS 24 60 mAdc
Gate–Source Forward Voltage (IG = 10 mAdc, VDS = 0) VGS(f) – 1.0 Vdc
SMALL–SIGNAL CHARACTERISTICS
Forward Transfer Admittance
(VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) |Yfs| 10 18 mmhos
Output Admittance
(VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) |yos| – 250 µmhos
Input Capacitance
(VGS = –10 Vdc, VDS = 0 Vdc, f = 1.0 MHz) Ciss – 5.0 pF
Reverse Transfer Capacitance
(VGS = –10 Vdc, VDS = 0 Vdc, f = 1.0 MHz) Crss – 2.5 pF
1. FR–5 = 1.0 0.75 0.062 in.
Preferred devices are ON Semiconductor recommended choices for future use and best overall value.
ON Semiconductor
Semiconductor Components Industries, LLC, 2001
November, 2001 – Rev. 2 1Publication Order Number:
MMBFU310LT1/D
MMBFU310LT1
ON Semiconductor Preferred Device
12
3
CASE 318–08, STYLE 10
SOT–23 (TO–236AB)
2 SOURCE
3
GATE
1 DRAIN
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70
60
50
40
30
20
-5.0 -4.0 -3.0 -2.0 -1.0 0
ID - VGS, GATE-SOURCE VOLTAGE (VOLTS)
10
0
70
60
50
40
30
20
10
, DRAIN CURRENT (mA)ID
IDSS - VGS, GATE-SOURCE CUTOFF VOLTAGE (VOLTS)
VDS = 10 V
IDSS
+25°C
TA = -55°C
+25°C
+25°C
-55°C
+150°C
+150°C
, SATURATION DRAIN CURRENT (mA)IDSS
Figure 1. Drain Current and Transfer
Characteristics versus Gate–Source Voltage
VGS, GATE-SOURCE VOLTAGE (VOLTS)
5.0 4.0 3.0 2.0 1.0 0
35
30
25
20
15
10
5.0
0
, FORWARD TRANSCONDUCTANCE (mmhos)Y
fs
Figure 2. Forward Transconductance
versus Gate–Source Voltage
VDS = 10 V
f = 1.0 MHz
TA = -55°C
+25°C
+150°C+25°C
-55°C
+150°C
ID, DRAIN CURRENT (mA)
100 k
10 k
1.0 k
100
1.0 k
100
10
1.0
0.01 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100
, FORWARD TRANSCONDUCTANCE ( mhos)Yfs µ
, OUTPUT ADMITTANCE ( mhos)Y
os µ
VGS(off) = -2.3 V =
VGS(off) = -5.7 V =
Figure 3. Common–Source Output
Admittance and Forward Transconductance
versus Drain Current
Yfs Yfs
Yos
VGS, GATE SOURCE VOLTAGE (VOLTS)
5.0 4.0 3.0 2.0 1.0 06.07.08.09.010
CAPACITANCE (pF)
10
7.0
4.0
1.0
0
120
96
72
48
24
0
, ON RESISTANCE (OHMS)RDS
RDS
Cgs
Cgd
Figure 4. On Resistance and Junction
Capacitance versus Gate–Source Voltage
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|Y11|, |Y21|, |Y22 | (mmhos)
Y12 (mmhos)
30
24
18
12
6.0
01000100 200 300 500 700
f, FREQUENCY (MHz)
3.0
2.4
1.8
1.2
0.6
|S21|, |S11|
0.45
0.39
0.33
0.27
0.21
0.15
0.85
0.79
0.73
0.67
0.61
0.55
|S12|, |S22|
0.060
0.048
0.036
0.024
0.012
1.00
0.98
0.96
0.94
0.92
0.90
1000100 200 300 500 700
f, FREQUENCY (MHz)
Figure 5. Common–Gate Y Parameter
Magnitude versus Frequency Figure 6. Common–Gate S Parameter
Magnitude versus Frequency
VDS = 10 V
ID = 10 mA
TA = 25°CY11
Y21
Y22
Y12
S22
S21
S11
S12
VDS = 10 V
ID = 10 mA
TA = 25°C
f, FREQUENCY (MHz)
θ21, θ11
50°
40°
30°
20°
10°
0°
180°
170°
160°
150°
140°
130°
θ12, θ22
-20°
-40°
-80°
-120°
-160°
-200°
-20°
-60°
-100°
-140°
-180°
87°
86°
85°
84°
83°
82°
1000100 200 300 500 700
Figure 7. Common–Gate Y Parameter
Phase–Angle versus Frequency
f, FREQUENCY (MHz)
θ11, θ12
120°
100°
80°
60°
40°
20°
-20°
-40°
-60°
-80°
-100°
-120°
θ21, θ22
0
-40°
-80°
-20°
-60°
-100°
1000100 200 300 500 700
Figure 8. S Parameter Phase–Angle
versus Frequency
θ22
θ21
θ12 θ11 VDS = 10 V
ID = 10 mA
TA = 25°C
θ11
θ21 θ22
θ21
θ11
θ12 VDS = 10 V
ID = 10 mA
TA = 25°C
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The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
PD = TJ(max) – TA
RθJA
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipa-
tion. Power dissipation for a surface mount device is deter-
mined b y T J(max), the maximum rated junction temperature
of the die, RθJA, the thermal resistance from the device
junction to ambient, and the operating temperature, TA.
Using the values provided on the data sheet for the SOT–23
package, PD can be calculated as follows:
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225 milli-
watts. There are other alternatives to achieving higher
power dissipation from the SOT–23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. There-
fore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
•Always preheat the device.
•The delta temperature between the preheat and
soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device.
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PACKAGE DIMENSIONS
CASE 318–08
ISSUE AF
SOT–23 (TO–236AB)
DJ
K
L
A
C
BS
H
GV
3
12
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0140 0.0285 0.35 0.69
L0.0350 0.0401 0.89 1.02
S0.0830 0.1039 2.10 2.64
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
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Notes
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Notes
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MMBFU310LT1/D
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
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