MAX9867ETJ+ - Hytronics

General Description

The MAX9867 is an ultra-low power stereo audio codec

designed for portable consumer devices such as

mobile phones and portable gaming consoles.

The device features stereo differential microphone inputs

that can be connected to either analog or digital micro-

phones. The single-ended line inputs, with configurable

preamplifier, can be sent to the ADC for record or routed

directly to the headphone amplifier for playback. An aux-

iliary ADC path can be used to track any DC voltage.

The stereo headphone amplifiers support differential,

single-ended, and capacitorless output configurations.

Using the capacitorless output configuration, the

device can output 10mW into 32Ωheadphones.

Comprehensive click-and-pop circuitry suppresses

audible clicks and pops during volume changes and

startup or shutdown.

Utilizing Maxim’s proprietary digital circuitry, the device

can accept any available 10MHz to 60MHz system

clock. This architecture eliminates the need for an

external PLL and multiple crystal oscillators. The stereo

ADC and DAC paths provide user-configurable voice-

band or audioband digital filters. Voiceband filters pro-

vide extra attenuation at the GSM packet frequency

and greater than 70dB stopband attenuation at fS/2.

The MAX9867 operates from a single 1.8V supply, and

supports a 1.65V to 3.6V logic level. An I2C 2-wire seri-

al interface provides control for volume levels, signal

mixing, and general operating modes.

The MAX9867 is available in a tiny 2.2mm x 2.7mm,

0.4mm-ball-pitch, WLP package. A 32-pin 5mm x 5mm

TQFN package is also available.

Features

o1.8V Single-Supply Operation

o6.7mW Playback Power Consumption

o90dB Stereo DAC, 8kHz ≤fS≤48kHz

o85dB Stereo ADC, 8kHz ≤fS≤48kHz

oBattery-Measurement Auxiliary ADC

oSupport for Any Master Clock Between 10MHz to

60MHz

oStereo Digital Microphone Input Support

oStereo Analog Differential Microphone Inputs

oStereo Headphone Amplifiers: Differential,

Single-Ended, or Capacitorless

oStereo Line Inputs

oVoiceband Filter with a Stopband Attenuation

Greater than 70dB

o1.65V to 3.6V Digital Interface Supply Voltage

oI2S/TDM-Compatible Digital Audio Bus

o30-Bump, 2.2mm x 2.7mm 0.4mm-Pitch WLP

MAX9867

Ultra-Low Power Stereo Audio Codec

________________________________________________________________

Maxim Integrated Products

19-4573; Rev 2; 6/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX9867EWV+ -40°C to +85°C 30 WLP

MAX9867ETJ+ -40°C to +85°C 32 TQFN-EP*

Denotes lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

Applications

Cell Phones

Portable Gaming Devices

Portable Navigation Devices

Portable Multimedia Players

Wireless Headsets

MAX9867

ADC

AUDIO DIGITAL

FILTERS

DAC

MIX

DIGITAL AUDIO INTERFACE

DIGITAL MICROPHONE

INTERFACE

CONTROL

INTERFACE

HEADPHONE

AMP

RIGHT MIC AMP

LEFT MIC AMP

LEFT PREAMP

RIGHT PREAMP

LINEIN 1

LINEIN 2

HEADPHONE

AMP

I2CI2S/PCM

ADC

Simplified Block Diagram

MAX9867

Ultra-Low Power Stereo Audio Codec

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

(Voltages with respect to AGND.)

DVDD, AVDD, and PVDD .........................................-0.3V to +2V

DVDDIO.................................................................-0.3V to +3.6V

DGND and PGND..................................................-0.1V to +0.1V

PREG, REF, REG, MICBIAS ....................-0.3V to (AVDD + 0.3V)

MCLK, LRCLK, BCLK

SDOUT, SDIN .................................-0.3V to (DVDDIO + 0.3V)

SDA, SCL, IRQ ......................................................-0.3V to +3.6V

LOUTP, LOUTN, ROUTP,

ROUTN .................................(PGND - 0.3V) to (PVDD + 0.3V)

LINL, LINR, JACKSNS/AUX, MICLP/DIGMICDATA,

MICLN/DIGMICCLK, MICRP, MICRN..-0.3V to (AVDD + 0.3V)

Continuous Power Dissipation (TA= +70°C)

30-Bump WLP (derate 12.5mW/°C above +70°C) ....1000mW

32-Pin TQFN-EP (derate 34.5mW/°C above +70°C) .2759mW

Junction-to-Ambient Thermal Resistance (θJA) (Note 1)

30-Bump WLP .............................................................80°C/W

32-Pin TQFN-EP ..........................................................29°C/W

Operating Temp Range.......................................-40°C to +85°C

Storage Temp Range ........................................-65°C to +150°C

Lead Temperature (TQFN only, 10s) ...............................+300°C

Soldering Temperature (reflow) .......................................+260°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PVDD, DVDD, AVDD 1.65 1.8 1.95

Supply Voltage Range DVDDIO 1.65 1.8 3.6 V

Analog (AVDD +

PVDD) 4.65 7

Full-duplex 8kHz

mono (voice mode)

(Note 3) Digital (DVDD +

DVDDIO) 0.96 1.5

Analog (AVDD +

PVDD) 3.28 5

DAC playback 48kHz

stereo (audio mode)

(Note 3) Digital (DVDD +

DVDDIO) 1.40 2

Analog (AVDD +

PVDD) 8.0 12

Full-duplex 48kHz

stereo (audio mode)

(Note 3) Digital (DVDD +

DVDDIO) 2.0 3

Analog (AVDD +

PVDD) 3.8 6

Total Supply Current IVDD

Stereo line-in only

Digital (DVDD +

DVDDIO) 0.004 0.05

Analog (AVDD +

PVDD) 15

Shutdown Supply Current TA = +25°C

Digital (DVDD +

DVDDIO) 15

µA

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

MAX9867

Ultra-Low Power Stereo Audio Codec

_______________________________________________________________________________________ 3

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Shutdown to Full Operation Excludes PLL lock time 10 ms

Soft-Start/-Stop Time 10 ms

DAC (Note 4)

Master or slave

mode 90

Dynamic Range (Note 5) DR fS = 48kHz, AVVOL =

0dB, TA = +25°C

Slave mode 84

Differential mode 1

Full-Scale Output VOLL/VOLR = 0x09 Capacitorless and

single-ended modes 0.56 VRMS

Gain Error DC accuracy, measured with respect to

full-scale output 15%

fS = 8kHz 1.2

Voice Path Phase Delay PDLY

f = 1kH z, 0d BFS , H P

fi l ter d i sab l ed , d i g i tal

i np ut to anal og outp ut fS = 16kHz 0.59

Total Harmonic Distortion THD MCLK = 12.288MHz, fS = 48kHz, 0dBFS,

measured at headphone outputs -80 dB

DAC Attenuation Range AVDAC DACA = 0xF to 0x0 -15 0 dB

DAC Gain Adjust AVGAIN DACG = 00 to 11 0 +18 dB

VAVDD = VPVDD = 1.65V to 1.95V 60 78

f = 217Hz, VRIPPLE = 100mVP-P,

AVVOL = 0dB 78

f = 1kHz, VRIPPLE = 100mVP-P,

AVVOL = 0dB 75

Power-Supply Rejection Ratio PSRR

f = 10kHz, VRIPPLE = 100mVP-P,

AVVOL = 0dB 62

DAC VOICE MODE DIGITAL IIR LOWPASS FILTER

With respect to fS within ripple; fS = 8kHz to

48kHz

0.448 x

Passband Cutoff fPLP

-3dB cutoff 0.451 x

Passband Ripple f < fPLP ±0.1 dB

Stopband Cutoff fSLP With respect to fS; fS = 8kHz to 48kHz 0.476 x

fSHz

Stopband Attenuation f > fSLP, f = 20Hz to 20kHz 75 dB

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

4 _______________________________________________________________________________________

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DAC VOICE MODE DIGITAL 5th ORDER IIR HIGHPASS FILTER

DVFLT = 0x1

(elliptical tuned for 16kHz GSM + 217Hz

notch)

0.0161

x fS

DVFLT = 0x2

(500Hz Butterworth tuned for 16kHz)

0.0312

x fS

DVFLT = 0x3

(elliptical tuned for 8kHz GSM + 217Hz

notch)

0.0321

x fS

DVFLT = 0x4

(500Hz Butterworth tuned for 8kHz)

0.0625

x fS

5th Order Passband Cutoff

(-3dB from Peak, I2C Register

Programmable)

fDHPPB

DVFLT = 0x5

(fS/240 Butterworth)

0.0042

x fS

DVFLT = 0x1

(elliptical tuned for 16kHz GSM + 217Hz

notch)

0.0139

x fS

DVFLT = 0x2

(500Hz Butterworth tuned for 16kHz)

0.0156

x fS

DVFLT = 0x3

(elliptical tuned for 8kHz GSM + 217Hz

notch)

0.0279

x fS

DVFLT = 0x4

(500Hz Butterworth tuned for 8kHz)

0.0312

x fS

5th Order Stopband Cutoff

(-30dB from Peak, I2C Register

Programmable)

fDHPSB

DVFLT = 0x5

(fS/240 Butterworth)

0.0021

x fS

DC Attenuation DCATTEN DVFLT ≠ 000 90 dB

DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER

With respect to fS within ripple;

fS = 8kHz to 48kHz

0.43 x

-3dB cutoff 0.47 x

Passband Cutoff fPLP

-6.02dB cutoff 0.50 x

Passband Ripple f < fPLP ±0.1 dB

Stopband Cutoff fSLP With respect to fS; fS = 8kHz to 48kHz 0.58 x

fSHz

Stopband Attenuation 60 dB

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

_______________________________________________________________________________________ 5

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DAC STEREO AUDIO MODE DIGITAL DC BLOCKING HIGHPASS FILTER

Passband Cutoff

(-3dB from Peak) fDHPPB DVFLT = 0x1 0.000625

x fSHz

DC Attenuation DCATTEN DVFLT = 0x1 90 dB

ADC (Note 6)

fS = 8kHz, MODE = 0 (IIR voice) 75 84

Dynamic Range (Note 5) DR fS = 8kHz to 48kHz, MODE = 1 (FIR audio) 85 dB

Full-Scale Input Differential MIC input or stereo-line inputs,

AVPRE = 0dB, AVPGAM = 0dB 1V

P-P

Gain Error (Note 7) DC accuracy, measured with respect to

80% of full-scale output 15%

fS = 8kHz 1.2

Voice Path Phase Delay PDLY

f = 1kHz, 0dBFS, HP

filter disabled,

analog input to

digital output fS = 16kHz 0.61

Total Harmonic Distortion THD f = 1kHz, fS = 8kHz, TA = +25°C, 0dBFS -81 -70 dB

ADC Level Adjust Range AVADC AVL/AVR = 0xF to 0x0 -12 +3 dB

VAVDD = 1.65V to 1.95V, input referred 60 85

f = 217Hz, VRIPPLE = 100mV, AVADC = 0dB,

input referred 85

f = 1kHz, VRIPPLE = 100mV, AVADC = 0dB,

input referred 80

Power-Supply Rejection Ratio PSRR

f = 10kHz, VRIPPLE = 100mV, AVADC = 0dB,

input referred 80

ADC VOICE MODE DIGITAL IIR LOWPASS FILTER

With respect to fS within ripple;

fS = 8kHz to 48kHz

0.445 x

Passband Cutoff fPLP

-3dB cutoff 0.449 x

Passband Ripple f < fPLP ±0.1 dB

Stopband Cutoff fSLP With respect to fS; fS = 8kHz to 48kHz 0.469 x

fSHz

Stopband Attenuation f > fSLP, f = 20Hz to 20kHz 74 dB

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

6 _______________________________________________________________________________________

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ADC VOICE MODE DIGITAL 5th ORDER IIR HIGHPASS FILTER

AVFLT = 0x1

(elliptical tuned for 16kHz GSM + 217Hz

notch)

0.0161

x fS

AVFLT = 0x2

(500Hz Butterworth tuned for 16kHz)

0.0312

x fS

AVFLT = 0x3

(elliptical tuned for 8kHz GSM + 217Hz

notch)

0.0321

x fS

AVFLT = 0x4

(500Hz Butterworth tuned for 8kHz)

0.0625

x fS

5th Order Passband Cutoff

(-3dB from Peak, I2C Register

Programmable)

fAHPPB

AVFLT = 0x5

(fS/240 Butterworth)

0.0042

x fS

AVFLT = 0x1

(elliptical tuned for 16kHz GSM + 217Hz

notch)

0.0139

x fS

AVFLT = 0x2

(500Hz Butterworth tuned for 16kHz)

0.0156

x fS

AVFLT = 0x3

(elliptical tuned for 8kHz GSM + 217Hz

notch)

0.0279

x fS

AVFLT = 0x4

(500Hz Butterworth tuned for 8kHz)

0.0312

x fS

Stopband Cutoff (-30dB from

Peak) fAHPSB

AVFLT = 0x5

(fS/240 Butterworth)

0.0021

x fS

DC Attenuation DCATTEN AVFLT ≠ 000 90 dB

ADC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER

With respect to fS within ripple;

fS = 8kHz to 48kHz

0.43 x

-3dB cutoff 0.48 x

Passband Cutoff fPLP

-6.02dB cutoff 0.5 x fS

Passband Ripple f < fPLP ±0.1 dB

Stopband Cutoff fSLP With respect to fS; fS = 8kHz to 48kHz 0.58 x

fSHz

Stopband Attenuation f > fSLP, f = 20Hz to 20kHz 60 dB

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

_______________________________________________________________________________________ 7

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ADC STEREO AUDIO MODE DIGITAL DC BLOCKING HIGHPASS FILTER

Passband Cutoff

(-3dB from Peak) fAHPPB AVFLT = 0x1 0.000625

x fSHz

DC Attenuation DCATTEN AVFLT = 0x1 90 dB

OUTPUT VOLUME CONTROL

VOLL/VOLR = 0x00 14.55 14.9 15.15

VOLL/VOLR = 0x01 14.1 14.4 14.6

VOLL/VOLR = 0x02 13.6 13.9 14.1

VOLL/VOLR = 0x04 12.6 12.9 13.1

VOLL/VOLR = 0x08 9.35 9.9 10.35

VOLL/VOLR = 0x10 0.35 0.9 1.35

Line Input to Output Volume

Control AVVOL

VOLL/VOLR = 0x20 -50.15 -49.2 -48.15

VOLL/VOLR = 0x00 to 0x06 (+6dB to +3dB) 0.5

VOLL/VOLR = 0x06 to 0x0F (+3dB to -6dB) 1

VOLL/VOLR = 0x0F to 0x17 (-6dB to -22dB) 2

Output Volume Control Step Size

V O LL/V O LR = 0x17 to 0x3F ( - 22d B to m ute) 4

Output Volume Control Mute

Attenuation f = 1kHz 100 dB

HEADPHONE AMPLIFIER (Note 8)

RL = 16Ω30 52

Output Power per Channel

(Differential Mode) POUT f = 1kHz, THD <

1%, TA = +25°C RL = 32Ω32 mW

RL = 16Ω19

Output Power per Channel

(Capacitorless Mode) POUT f = 1kHz, THD <

1%, TA = +25°C RL = 32Ω810 mW

RL = 16Ω, POUT = 25mW, f = 1kHz -76

MCLK = 13MHz,

fS = 8kHz -77 -70

Total Harmonic Distortion + Noise

(Differential Mode) THD+N RL = 32Ω, POUT =

25mW, f = 1kHz MCLK = 12.288MHz,

fS = 48kHz -80

RL = 16Ω, POUT = 6.25mW, f = 1kHz -72

MCLK = 13MHz,

fS = 8kHz -74 -65

Total Harmonic Distortion + Noise

(Capacitorless Mode) THD+N RL = 32Ω, POUT =

6.25mW, f = 1kHz MCLK = 12.288MHz,

fS = 48kHz -74

RL = 16Ω, POUT = 6.25mW, f = 1kHz -74

MCLK = 13MHz,

fS = 8kHz -74 -65

Total Harmonic Distortion + Noise

(SE Mode) THD+N RL = 32Ω, POUT =

6.25mW, f = 1kHz MCLK = 12.288MHz,

fS = 48kHz -76

Dynamic Range DR AVVOL = +6dB (Notes 5, 7) 76 90 dB

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

8 _______________________________________________________________________________________

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VAVDD = VPVDD = 1.65V to 1.95V 60 78

f = 217Hz, VRIPPLE = 100mVP-P,

AVVOL = 0dB 78

f = 1kHz, VRIPPLE = 100mVP-P,

AVVOL = 0dB 75

Power-Supply Rejection Ratio

(Note 7) PSRR

f = 10kHz, VRIPPLE = 100mVP-P,

AVVOL = 0dB 62

AVVOL = -84dB

differential mode

(LOUTP–LOUTN,

ROUTP–ROUTN),

TA = +25°C

±0.2

Output Offset Voltage VOS

AVVOL = -84dB

capacitorless

mode

(LOUTP–LOUTN,

ROUTP–LOUTN),

TA = +25°C

±0.8

Differential mode, POUT = 5mW, f = 1kHz 87

TQFN 55

Crosstalk XTALK

Capacitorless

mode,

POUT = 5mW,

f = 1kHz WLP 60

RL = 32Ω500

Capacitive Drive No sustained

oscillations RL = ∞100 pF

Into shutdown -80

Click-and-Pop Level

(Differential, Capacitorless

Modes)

Peak voltage,

A-weighted, 32

samples per

second Out of shutdown -69

dBV

Into shutdown -75

Click-and-Pop Level

(SE Mode)

Peak voltage,

A-weighted, 32

samples per

second Out of shutdown -75

dBV

MICROPHONE AMPLIFIER

PALEN/PAREN = 01 -0.5 0 +0.5

PALEN/PAREN = 10 19.5 20 20.5

Preamplifier Gain AVPRE

PALEN/PAREN = 11 29.5 30 30.5

PGAML/PGAMR = 0x1F -0.6 -0.1 +0.4

MIC PGA Gain AVPGAM PGAML/PGAMR = 0x00 19.3 19.75 20.3 dB

Common-Mode Rejection Ratio CMRR VIN = 100mVP-P, f = 217Hz 50 dB

MIC Input Resistance RIN_MIC All gain settings 30 50 kΩ

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

_______________________________________________________________________________________ 9

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AVPRE = 0dB,

VIN = 1VP-P, f = 1kHz -80

Total Harmonic Distortion + Noise THD+N AVPRE = +30dB,

VIN = 32mVP-P, f = 1kHz,

(1VP-P at ADC input)

-67

VAVDD = 1.65V to 1.95V, input referred 60 85

f = 217Hz, VRIPPLE = 100mV,

AVADC = 0dB, input referred 85

f = 1kHz, VRIPPLE = 100mV,

AVADC = 0dB, input referred 80

Power-Supply Rejection Ratio PSRR

f = 10kHz, VRIPPLE = 100mV,

AVADC = 0dB, input referred 80

MICROPHONE BIAS

Output Voltage VMICBIAS VAVDD = 1.8V, ILOAD = 1mA 1.5 1.525 1.55 V

Load Regulation ILOAD = 1mA to 2mA 0.2 10 V/A

Line Regulation VAVDD = 1.65V to 1.95V 10 µV/V

f = 217Hz, VRIPPLE = 100mVP-P 85

Power-Supply Rejection Ratio PSRR f = 10kHz, VRIPPLE = 100mVP-P 81 dB

Noise Voltage A-weighted 9.1 µVRMS

LINE INPUT

Full-Scale Input VIN AVLINE = 0dB 1.0 VP-P

Line Input Level Adjust Range AVLINE LIGL/LIGR = 0xF to 0x0 -6.5 +24.5 dB

Line Input Mute Attenuation f = 1kHz 100 dB

Input Resistance RIN_LINE AVLINE = +24dB 20 kΩ

Total Harmonic Distortion + Noise THD+N VIN = 0.1VP-P, f = 1kHz, differential output -83 dB

AUXIN INPUT

Input DC Voltage Range AUXEN = 1 0 0.738 V

AUXIN Input Resistance RIN AUXEN = 1, 0V ≤ AUXIN ≤ 0.738V 10 40 MΩ

JACK SENSE OPERATION

JDETEN = 1, SHDN = 1, JACKSNS 0.92 x

MICBIAS

0.95 x

MICBIAS

0.98 x

MICBIAS

Threshold VTH JDETEN = 1, SHDN = 0, JACKSNS,

LOUTP

AVDD -

0.8

AVDD -

0.4

AVDD -

0.15

JDETEN = 1, SHDN = 1,

JACKSNS = GND 4

Pullup Current IPU JDETEN = 1, SHDN = 0,

JACKSNS = LOUTP = GND 420

µA

Pullup Voltage JDETEN = 1, JACKSNS, LOUTP AVDD V

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

10 ______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL SIDETONE

Sidetone Gain Adjust Range AVSTGA Differential output mode,

DVST = 0x1F to 0x01 -60 0 dB

Voice Path Phase Delay PDLY MIC input to headphone output, f = 1kHz,

HP filter disabled, fS = 8kHz 2.2 ms

INPUT CLOCK CHARACTERISTICS

MCLK Input Frequency fMCLK For any LRCLK sample rate 10 60 MHz

Prescaler = /1 mode 40 60

MCLK Input Duty Cycle /2 or /4 modes 30 70 %

Maximum MCLK Input Jitter Maximum allowable RMS for performance

limits 100 psRMS

LRCLK Sample Rate Range 8 48 kHz

Rapid lock mode 2 7

LRCLK PLL Lock Time

Any allowable LRCLK

and PCLK rate, slave

mode

Nonrapid lock

mode 12 25 ms

LRCLK Acceptable Jitter for

Maintaining PLL Lock

Allowable LRCLK period change from

nominal for slave PLL mode at any

allowable LRCLK and PCLK rates

±100 ns

FREQ = 0x8 through 0xF 0 0 %

PCLK = 192xfS, 256xfS, 384xfS, 512xfS,

768xfS, and 1024xfS00

LRCLK Average Frequency Error

(Master and Slave Modes)

(Note 9)

All other modes -0.025 +0.025

DIGITAL INPUT (MCLK)

Input High Voltage VIH 1.2 V

Input Low Voltage VIL 0.6 V

Input Leakage Current IIH, IIL TA = +25°C ±1 µA

Input Capacitance 10 pF

DIGITAL INPUTS (SDIN, BCLK, LRCLK)

Input High Voltage VIH 0.7 x

DVDDIO V

Input Low Voltage VIL 0.3 x

DVDDIO V

Input Hysteresis 200 mV

Input Leakage Current IIH, IIL TA = +25°C ±1 µA

Input Capacitance 10 pF

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 11

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (SDA, SCL)

Input High Voltage VIH 0.7 x

DVDD V

Input Low Voltage VIL 0.3 x

DVDD V

Input Hysteresis 200 mV

Input Leakage Current IIH, IIL TA = +25°C ±1 µA

Input Capacitance 10 pF

DIGITAL INPUT (DIGMICDATA)

Input High Voltage VIH 0.65 x

DVDD V

Input Low Voltage VIL 0.35 x

DVDD V

Input Hysteresis 100 mV

Input Leakage Current IIH, IIL TA = +25°C ±35 µA

Input Capacitance 10 pF

CMOS DIGITAL OUTPUTS (BCLK, LRCLK, SDOUT)

Output Low Voltage VOL IOL = 3mA 0.4 V

Output High Voltage VOH IOH = 3mA DVDDIO

- 0.4 V

CMOS DIGITAL OUTPUT (DIGMICCLK)

Output Low Voltage VOL IOL = 1mA 0.4 V

Output High Voltage VOH IOH = 1mA DVDD -

0.4 V

OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ)

Output High Current IOH VOUT = VDVDD, TA = +25°C 1 µA

Output Low Voltage VOL IOL = 3mA 0.2 x

DVDD V

DIGITAL MICROPHONE TIMING CHARACTERISTICS (VDVDD = 1.65V)

MICCLK = 00 PCLK/8

DIGMICCLK Divide Ratio fMICCLK MICCLK = 01 PCLK/6 MHz

DIGMICDATA to DIGMICCLK

Setup Time tSU

MIC Either clock edge 20 ns

DIGMICDATA to DIGMICCLK

Hold Time tHD

MIC Either clock edge 0 ns

DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (VDVDD = 1.65V)

tBCLKS Slave operation 75 ns

Minimum BCLK Cycle Time tBCLKM Master operation 325 ns

MAX9867

Ultra-Low Power Stereo Audio Codec

12 ______________________________________________________________________________________

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Minimum BCLK High Time tBCLKH Slave operation 30 ns

Minimum BCLK Low Time tBCLKL Slave operation 30 ns

BCLK or LRCLK Rise and Fall tR, tFMaster operation, CL = 15pF 7 ns

SDIN or LRCLK to BCLK Setup

Time tSU 20 ns

SDIN or LRCLK to BCLK Hold

Time tHD 0ns

SDOUT Delay Time from BCLK

Rising Edge tDLY CL = 30pF 0 40 ns

I2C TIMING CHARACTERISTICS (VDVDD = 1.65V)

Serial-Clock Frequency fSCL 0 400 kHz

Bus Free Time Between STOP

and START Conditions tBUF 1.3 µs

Hold Time (REPEATED) START

Condition tHD

STA 0.6 µs

SCL Pulse-Width Low tLOW 1.3 µs

SCL Pulse-Width High tHIGH 0.6 µs

Setup Time for a REPEATED

START Condition tSU

STA 0.6 µs

Data Hold Time tHD

DAT RPU, SDA = 475Ω0 900 ns

Data Setup Time tSU

DAT 100 ns

SDA and SCL Receiving Rise

Time tR(Note 10) 20 +

0.1CB300 ns

SDA and SCL Receiving Fall

Time tF(Note 10) 20 +

0.1CB300 ns

SDA Transmitting Fall Time tFRPU, SDA = 475Ω

(Note 10)

20 +

0.1CB250 ns

Setup Time for STOP Condition tSU

STO 0.6 µs

Bus Capacitance CB400 pF

Pulse Width of Suppressed Spike tSP 050ns

Note 2: The MAX9867 is 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by design.

Note 3: Clocking all zeros into the DAC, master mode, and differential headphone mode.

Note 4: DAC performance measured at the headphone outputs.

Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.

f = 20Hz to 20kHz.

Note 6: Performance measured using microphone inputs, unless otherwise stated.

Note 7: Performance measured using line inputs.

Note 8: Performance measured using DAC, unless otherwise stated. LRCLK = 8kHz, unless otherwise stated.

Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.

Note 10: CBis in pF.

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL= ∞, headphone load (RL) connected between _OUTP and _OUTN in differential

mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =

0dB, MCLK = 13MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 13

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (DAC TO HEADPHONE)

MAX9867 toc01

POWER OUT (mW)

THD+N (dB)

1510 3052520

-50

-40

-30

-80

-70

-60

-20

-10

-90

035

MCLK = 13MHz

LRCLK = 8kHz

RLOAD = 32Ω

DIFFERENTIAL MODE

3kHz

20Hz

1kHz

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (DAC TO HEADPHONE)

MAX9867 toc02

POWER OUT (mW)

THD+N (dB)

50402010 30 60

-50

-40

-30

-80

-70

-60

-20

-10

-90

MCLK = 13MHz

LRCLK = 8kHz

RLOAD = 16Ω

DIFFERENTIAL MODE

3kHz

20Hz

1kHz

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (DAC TO HEADPHONE)

MAX9867 toc03

POWER OUT (mW)

THD+N (dB)

1510 3052520

-50

-40

-30

-80

-70

-60

-20

-10

-90

035

MCLK = 12.288MHz

LRCLK = 48kHz

RLOAD = 32Ω

DIFFERENTIAL MODE

6kHz

20Hz

1kHz

Typical Operating Characteristics

(VAVDD = VDVDD = VPVDD = +1.8V, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK =

8kHz, BW = 20Hz to fS/2, TA= +25°C, unless otherwise noted.)

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (DAC TO HEADPHONE)

MAX9867 toc04

POWER OUT (mW)

THD+N (dB)

50402010 30 60

-50

-40

-30

-80

-70

-60

-20

-10

-90

MCLK = 12.288MHz

LRCLK = 48kHz

RLOAD = 16Ω

DIFFERENTIAL MODE

6kHz

20Hz

1kHz

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (DAC TO HEADPHONE)

MAX9867 toc05

FREQUENCY (Hz)

THD+N (%)

1000100

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 10,000

MCLK = 13MHz

LRCLK = 8kHz

RLOAD = 32Ω

DIFFERENTIAL MODE

5mW

20mW

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (DAC TO HEADPHONE)

MAX9867 toc06

FREQUENCY (Hz)

THD+N (%)

1000100

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 10,000

MCLK = 13MHz

LRCLK = 8kHz

RLOAD = 16Ω

DIFFERENTIAL MODE

5mW

20mW

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (DAC TO HEADPHONE)

MAX9867 toc07

FREQUENCY (Hz)

THD+N (%)

100 10,000

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 1000 100,000

MCLK = 12.288MHz

LRCLK = 48kHz

RLOAD = 32Ω

DIFFERENTIAL MODE

5mW

20mW

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (DAC TO HEADPHONE)

MAX9867 toc08

FREQUENCY (Hz)

THD+N (%)

100 10,000

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 1000 100,000

MCLK = 12.288MHz

LRCLK = 48kHz

RLOAD = 16Ω

DIFFERENTIAL MODE

5mW

20mW

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (DAC TO HEADPHONE)

MAX9867 toc09

POWER OUT (mW)

THD+N (dB)

410682

-50

-40

-30

-80

-70

-60

-20

-10

-90

MCLK = 13MHz

LRCLK = 8kHz

RLOAD = 32Ω

CAPACITORLESS MODE

3kHz

20Hz

1kHz

MAX9867

Ultra-Low Power Stereo Audio Codec

14 ______________________________________________________________________________________

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (DAC TO HEADPHONE)

MAX9867 toc10

POWER OUT (mW)

THD+N (dB)

81042126

-50

-40

-30

-80

-70

-60

-20

-10

-90

MCLK = 12.288MHz

LRCLK = 48kHz

RLOAD = 32Ω

CAPACITORLESS MODE

6kHz

20Hz

1kHz

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (DAC TO HEADPHONE)

MAX9867 toc11

FREQUENCY (Hz)

THD+N (%)

1000100

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 10,000

MCLK = 13MHz

LRCLK = 8kHz

RLOAD = 32Ω

CAPACITORLESS MODE

1mW

5mW

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (DAC TO HEADPHONE)

MAX9867 toc12

FREQUENCY (Hz)

THD+N (%)

100 10,000

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 1000 100,000

MCLK = 12.288MHz

LRCLK = 48kHz

RLOAD = 32Ω

CAPACITORLESS MODE

1mW

5mW

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (DAC TO HEADPHONE)

MAX9867 toc13

POWER OUT (mW)

THD+N (dB)

410682

-50

-40

-30

-80

-70

-60

-20

-10

-90

MCLK = 13MHz

LRCLK = 8kHz

RLOAD = 32Ω, COUT = 220µF

SINGLE-ENDED MODE

3kHz

20Hz

1kHz

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (DAC TO HEADPHONE)

MAX9867 toc14

POWER OUT (mW)

THD+N (dB)

810426 12

-50

-40

-30

-80

-70

-60

-20

-10

-90

MCLK = 12.288MHz

LRCLK = 48kHz

RLOAD = 32Ω, COUT = 220µF

SINGLE-ENDED MODE

6kHz

20Hz

1kHz

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (DAC TO HEADPHONE)

MAX9867 toc15

FREQUENCY (Hz)

THD+N (%)

1000100

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 10,000

MCLK = 13MHz

LRCLK = 8kHz

RLOAD = 32Ω, COUT = 220µF

SINGLE-ENDED MODE

POUT SPECIFIED AT 1kHz

1mW

5mW

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (DAC TO HEADPHONE)

MAX9867 toc16

FREQUENCY (Hz)

THD+N (%)

100 10,000

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 1000 100,000

MCLK = 13MHz

LRCLK = 8kHz

RLOAD = 32Ω, COUT = 220µF

SINGLE-ENDED MODE

POUT SPECIFIED AT 1kHz

1mW

5mW

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (LINE IN TO HEADPHONE)

MAX9867 toc17

POWER OUT (mW)

THD+N (dB)

402515 2010 4535305

-50

-40

-30

-70

-60

-20

-10

-80

050

LINE IN PREAMP = +18dB

RLOAD = 32Ω

DIFFERENTIAL MODE

6kHz

20Hz 1kHz

TOTAL HARMONIC DISTORTION + NOISE

vs. POWER OUT (LINE IN TO HEADPHONE)

MAX9867 toc18

POWER OUT (mW)

THD+N (dB)

2510 20 3530155

-50

-40

-30

-70

-80

-60

-20

-10

-90

040

LINE IN PREAMP = 0dB

RLOAD = 32Ω

DIFFERENTIAL MODE

1kHz

6kHz

20Hz

Typical Operating Characteristics (continued)

(VAVDD = VDVDD = VPVDD = +1.8V, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK =

8kHz, BW = 20Hz to fS/2, TA= +25°C, unless otherwise noted.)

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 15

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (LINE IN TO HEADPHONE)

MAX9867 toc19

FREQUENCY (Hz)

THD+N (dB)

100 10,000

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 1000 100,000

LINE IN PREAMP = +18dB

RLOAD = 32Ω

DIFFERENTIAL MODE

5mW

20mW

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (LINE IN TO HEADPHONE)

MAX9867 toc20

FREQUENCY (Hz)

THD+N (dB)

100 10,000

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 1000 100,000

LINE IN PREAMP = 0dB

RLOAD = 32Ω

DIFFERENTIAL MODE

5mW

20mW

POWER OUT vs. HEADPHONE LOAD

MAX9867 toc21

HEADPHONE LOAD (Ω)

POWER OUT (mW)

1 100 1000

MCLK = 12.288MHz

LRCLK = 48kHz

THD+N = < 0.1%

DIFFERENTIAL MODE

POWER OUT vs. HEADPHONE LOAD

MAX9867 toc22

HEADPHONE LOAD (Ω)

POWER OUT (mW)

1 100 1000

MCLK = 12.288MHz

LRCLK = 48kHz

THD+N = < 0.1%

CAPACITORLESS MODE

POWER OUT vs. HEADPHONE LOAD

MAX9867 toc23

HEADPHONE LOAD (Ω)

POWER OUT (mW)

1 100 1000

MCLK = 12.288MHz

LRCLK = 48kHz

THD+N = < 0.1%

SINGLE-ENDED MODE

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (MICROPHONE TO ADC)

MAX9867 toc24

FREQUENCY (Hz)

THD+N (%)

1000100

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 10,000

MCLK = 13MHz

LRCLK = 8kHz

MICPRE = 0dB

VIN = 1VP-P

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (MICROPHONE TO ADC)

MAX9867 toc25

FREQUENCY (Hz)

THD+N (%)

1000100

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 10,000

MCLK = 13MHz

LRCLK = 8kHz

MICPRE = 20dB

VIN = 0.11VP-P

TOTAL HARMONIC DISTORTION + NOISE

vs. FREQUENCY (MICROPHONE TO ADC)

MAX9867 toc26

FREQUENCY (Hz)

THD+N (%)

1000100

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 10,000

MCLK = 13MHz

LRCLK = 8kHz

MICPRE = 30dB

VIN = 0.032VP-P

POWER-SUPPLY REJECTION RATIO

vs. FREQUENCY (DAC TO HEADPHONE)

MAX9867 toc27

FREQUENCY (Hz)

PSRR (dB)

100 10,000

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 1000 100,000

VRIPPLE = 100mVP-P

MCLK = 13MHz

LRCLK = 8kHz

Typical Operating Characteristics (continued)

(VAVDD = VDVDD = VPVDD = +1.8V, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK =

8kHz, BW = 20Hz to fS/2, TA= +25°C, unless otherwise noted.)

MAX9867

Ultra-Low Power Stereo Audio Codec

16 ______________________________________________________________________________________

POWER-SUPPLY REJECTION RATIO

vs. FREQUENCY (MIC TO ADC)

MAX9867 toc28

FREQUENCY (Hz)

PSRR (dB)

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 100 1000

VRIPPLE = 100mVP-P

MCLK = 13MHz

LRCLK = 8kHz

POWER-SUPPLY REJECTION RATIO

vs. FREQUENCY (MICBIAS)

MAX9867 toc29

FREQUENCY (Hz)

PSRR (dB)

-50

-40

-30

-80

-70

-60

-20

-10

-90

10 100 1000

VRIPPLE = 100mVP-P

FFT, DAC TO HEADPHONE,

0dBFS, MCLK = 13MHz, LRCLK = 8kHz

MAX9867 toc30

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

061218

FREQ = 0xA

FREQUENCY (kHz)

20281016414

FFT, DAC TO HEADPHONE,

-60dBFS, MCLK = 13MHz, LRCLK = 8kHz

MAX9867 toc31

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

FREQ = 0xA

0 6 12 18

FREQUENCY (kHz)

202 8 10 16414

FFT, DAC TO HEADPHONE,

0dBFS, MCLK = 12.288MHz, LRCLK = 48kHz

MAX9867 toc32

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

NI = 6000

0 6 12 18

FREQUENCY (kHz)

202 8 10 16414

FFT, DAC TO HEADPHONE,

-60dBFS, MCLK = 12.288MHz, LRCLK = 48kHz

MAX9867 toc33

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

NI = 6000

061218

FREQUENCY (kHz)

20281016414

FFT, DAC TO HEADPHONE,

0dBFS, MCLK = 13MHz, LRCLK = 48kHz

MAX9867 toc34

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

PLL MODE

0 6 12 18

FREQUENCY (kHz)

202 8 10 16414

FFT, DAC TO HEADPHONE,

-60dBFS, MCLK = 13MHz, LRCLK = 48kHz

MAX9867 toc35

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

PLL MODE

0 6 12 18

FREQUENCY (kHz)

202 8 10 16414

FFT, DAC TO HEADPHONE,

0dBFS, MCLK = 13MHz, LRCLK = 44.1kHz

MAX9867 toc36

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

PLL MODE

061218

FREQUENCY (kHz)

20281016414

Typical Operating Characteristics (continued)

(VAVDD = VDVDD = VPVDD = +1.8V, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK =

8kHz, BW = 20Hz to fS/2, TA= +25°C, unless otherwise noted.)

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 17

FFT, DAC TO HEADPHONE, -60dBFS,

MCLK = 13MHz, LRCLK = 44.1kHz

MAX9867 toc37

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

PLL MODE

0 6 12 18

FREQUENCY (kHz)

202 8 10 16414

FFT, MICROPHONE TO ADC,

0dBFS, MCLK = 13MHz, LRCLK = 8kHz

MAX9867 toc38

FREQUENCY (Hz)

AMPLITUDE (dB)

1000 3000

-60

-40

-20

-120

-100

-80

-140

0 2000 4000500 25001500 3500

FREQ = 0xA

FFT, MICROPHONE TO ADC,

-60dBFS, MCLK = 13MHz, LRCLK = 8kHz

MAX9867 toc39

FREQUENCY (Hz)

AMPLITUDE (dB)

1000 3000

-60

-40

-20

-120

-100

-80

-140

0 2000 4000500 25001500 3500

FREQ = 0xA

FFT, MICROPHONE TO ADC,

0dBFS, MCLK = 12.288MHz, LRCLK = 48kHz

MAX9867 toc40

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

NI = 6000

0 6 12 18

FREQUENCY (kHz)

202 8 10 16414

FFT, MICROPHONE TO ADC,

-60dBFS, MCLK = 12.288MHz, LRCLK = 48kHz

MAX9867 toc41

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

NI = 6000

0 6 12 18

FREQUENCY (kHz)

202 8 10 16414

FFT, MICROPHONE TO ADC,

0dBFS, MCLK = 13MHz, LRCLK = 48kHz

MAX9867 toc42

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

PLL MODE

061218

FREQUENCY (kHz)

20281016414

FFT, MICROPHONE TO ADC,

-60dBFS, MCLK = 13MHz, LRCLK = 48kHz

MAX9867 toc43

AMPLITUDE (dB)

-60

-40

-120

-100

-80

-20

-140

PLL MODE

0 6 12 18

FREQUENCY (kHz)

202 8 10 16414

WIDEBAND FFT, DAC TO HEADPHONE,

0dBFS, MCLK = 13MHz, LRCLK = 8kHz

MAX9867 toc44

FREQUENCY (kHz)

AMPLITUDE (dB)

40 100

-60

-40

-20

-120

-100

-80

-140

0 60 12020 80

FREQ = 0xA

WIDEBAND FFT, DAC TO HEADPHONE,

-60dBFS, MCLK = 13MHz, LRCLK = 8kHz

MAX9867 toc45

FREQUENCY (kHz)

AMPLITUDE (dB)

40 100

-60

-40

-20

-120

-100

-80

-140

06012020 80

FREQ = 0xA

Typical Operating Characteristics (continued)

(VAVDD = VDVDD = VPVDD = +1.8V, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK =

8kHz, BW = 20Hz to fS/2, TA= +25°C, unless otherwise noted.)

MAX9867

Ultra-Low Power Stereo Audio Codec

18 ______________________________________________________________________________________

DAC IIR HIGHPASS FILTER

FREQUENCY RESPONSE, MODE = 0

MAX9867 toc46

FREQUENCY (Hz)

AMPLITUDE (dB)

220 520320 420120

-40

-20

-80

-60

-100

DVFLT = 0

DVFLT = 3

DVFLT = 4

LRCLK = 8kHz

MODE = 0

DAC IIR HIGHPASS FILTER

FREQUENCY RESPONSE, MODE = 0

MAX9867 toc47

FREQUENCY (Hz)

AMPLITUDE (dB)

220 520320 420120

-40

-20

-80

-60

-100

AVFLT = 0

AVFLT = 3

AVFLT = 4

LRCLK = 8kHz

DAC IIR/FIR LOWPASS FILTER

FREQUENCY RESPONSE (8kHz)

MAX9867 toc48

AMPLITUDE (dB)

-30

-20

-70

-50

-10

-60

-40

-80

MODE = 0

MODE = 1

3.0 3.3 3.6 3.9

FREQUENCY (kHz)

4.03.1 3.4 3.5 3.83.2 3.7

ADC IIR/FIR LOWPASS FILTER

FREQUENCY RESPONSE (8kHz)

MAX9867 toc49

AMPLITUDE (dB)

-40

-20

-80

-60

-100

MODE = 0

MODE = 1

3.0 3.3 3.6 3.9

FREQUENCY (kHz)

4.03.1 3.4 3.5 3.83.2 3.7

SHUTDOWN TO DAC FULL OPERATION

(CAPACITORLESS OR DIFFERENTIAL MODE)

MAX9867 toc50

TIME (4ms/div)

LOUTP (500mV/div) SCL (2V/div)

SHUTDOWN TO DAC FULL OPERATION

(CLICKLESS SINGLE-ENDED MODE)

MAX9867 toc51

TIME (40ms/div)

LOUTP (500mV/div) SCL (2V/div)

SHUTDOWN TO DAC FULL OPERATION

(FAST TURN-ON SINGLE-ENDED MODE)

MAX9867 toc52

TIME (4ms/div)

LOUTP (500mV/div) SCL (2V/div)

Typical Operating Characteristics (continued)

(VAVDD = VDVDD = VPVDD = +1.8V, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK =

8kHz, BW = 20Hz to fS/2, TA= +25°C, unless otherwise noted.)

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 19

FULL OPERATION TO SHUTDOWN (DAC)

MAX9867 toc53

TIME (1ms/div)

LOUTP (500mV/div) SCL (2V/div)

ADC SOFT-START

MAX9867 toc54

TIME (4ms/div)

ADC OUT (500mV/div) SCL (2V/div)

TOTAL HARMONIC DISTORTION + NOISE

vs. MCLK FREQUENCY, 0dBFS

MAX9867 toc55

MCLK FREQUENCY (MHz)

THD+N (dB)

2015 40 5025 5545

-50

-40

-30

-80

-90

-70

-60

-20

-10

-100

10 6030 35

LRCLK = 48kHz

PLL MODE

DYNAMIC RANGE vs. MCLK FREQUENCY

MAX9867 toc56

MCLK FREQUENCY (MHz)

DYNAMIC RANGE (dB)

100

110

120

10 100

VIN = -60dBFS

LRCLK = 48kHz

PLL MODE

A-WEIGHTED

LINE INPUT RESISTANCE vs. GAIN SETTING

MAX9867 toc57

GAIN SETTING (dB)

INPUT RESISTANCE (kΩ)

170

220

120

270

-6 4 14 24-1 9 19

AUX CODE vs. INPUT VOLTAGE

MAX9867 toc58

INPUT VOLTAGE (V)

AUX CODE (SIGNED DECIMAL)

20,000

25,000

10,000

15,000

5000

30,000

-5000

-0.4 0.80.2 1.20.60.401.0-0.2

Typical Operating Characteristics (continued)

(VAVDD = VDVDD = VPVDD = +1.8V, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK =

8kHz, BW = 20Hz to fS/2, TA= +25°C, unless otherwise noted.)

MAX9867

Ultra-Low Power Stereo Audio Codec

20 ______________________________________________________________________________________

Pin Description

PIN/BUMP

TQFN-EP WLP NAME FUNCTION

1 A2 DGND Digital Ground

2 B3 SCL I2C Serial-Clock Input. Connect a pullup resistor to a 1.7V to 3.3V supply.

3 A3 SDA I2C Serial-Data Input/Output. Connect a pullup resistor to a 1.7V to 3.3V supply.

4C3 IRQ

Hardware Interrupt Output. IRQ can be programmed to pull low when bits in

status register 0x00 are set. Read status register 0x00 to clear IRQ once set.

Repeat faults have no effect on IRQ until it is cleared by reading register 0x00.

Connect a 10kΩ pullup resistor to a 1.7V to 3.3V supply.

5 A4 AVDD Analog Power Supply. Bypass to AGND with a 1µF capacitor.

6 B4 REF Converter Reference. Bypass to AGND with a 2.2µF capacitor (1.23V nominal).

7 A5 PREG Positive Internal Regulated Supply. Bypass to AGND with a 1µF capacitor (1.6V

nominal).

8 B5 REG PREG/2 Voltage Reference. Bypass to AGND with a 1µF capacitor (0.8V nominal).

9 A6 AGND Analog Ground

10 B6 MICBIAS Low-Noise Microphone Bias. Connect a 2.2kΩ to 470Ω resistor to the positive

output of a microphone (1.525V nominal). Bypass to AGND with a 1µF capacitor.

11 C5 MICLN/

DIGMICCLK

Left Negative Differential Microphone Input or Digital Microphone Clock Output.

For analog microphones, AC-couple to the negative output of a microphone with a

1µF capacitor. For digital microphones, connect to the clock input of the

microphone.

12 C6 MICLP/

DIGMICDATA

Left Positive Differential Microphone Input or Digital Microphone Data Input. For

analog microphones, AC-couple to the positive output of a microphone with a 1µF

capacitor. For digital microphones, connect to the data output of the

microphone(s). Up to two digital microphones can be connected.

13 C4 MICRP Right Positive Differential Microphone Input. AC-couple to the positive output of a

microphone with a 1µF capacitor.

14 D6 MICRN Right Negative Differential Microphone Input. AC-couple to the negative output of

a microphone with a 1µF capacitor.

15 D5 LINL Left-Line Input. AC-couple analog audio signal to LINL with a 1µF capacitor.

16 E6 LINR Right-Line Input. AC-couple analog audio signal to LINR with a 1µF capacitor.

17 D4 JACKSNS/AUX

Jack Sense or Auxiliary ADC Input. When configured for jack detection, JACKSNS

detects the presence or absence of a jack. See the Mode Configuration section

for details. When configured as an auxiliary ADC input, AUX is used to measure

DC voltages.

18 E5 PGND Headphone Power Ground

19 D3 ROUTP Positive Right-Channel Headphone Output. Connect directly to the load in

differential and capacitorless mode. AC-couple to the load in single-ended mode.

20 E4 ROUTN

Negative Right-Channel Headphone Output. Inverting output in differential mode.

Leave unconnected in capacitorless and fast turn-on single-ended mode. Bypass

with a 1µF capacitor to AGND in clickless, single-ended mode.

21 D2 LOUTN

Negative Left-Channel Headphone Output. Noninverting output in differential

mode. Common headphone return in capacitorless mode. Leave unconnected in

fast turn-on single-ended mode. Bypass with a 1µF capacitor to AGND in clickless

single-ended mode.

Detailed Description

The MAX9867 is a low-power stereo audio codec

designed for portable applications requiring minimum

power consumption.

The stereo playback path accepts digital audio through

a flexible interface compatible with I2S, TDM, and left-

justified signals. An oversampling sigma-delta DAC

converts the incoming digital data stream to analog

audio and outputs the audio through the stereo head-

phone amplifier. The headphone amplifier can be con-

figured in differential, single-ended, and capacitorless

output modes.

The stereo record path has two analog microphone

inputs with selectable gain. An integrated microphone

bias can be used to power the microphones. The left

analog microphone inputs can also accept data from

up to two digital microphones. An oversampling sigma-

delta ADC converts the microphone signals and out-

puts the digital bit stream over the digital audio

interface.

Integrated digital filtering provides a range of notch and

highpass filters for both the playback and record paths

to limit undesirable low-frequency signals and GSM

transmission noise. The digital filtering provides attenuation

of out-of-band energy by over 70dB, eliminating audi-

ble aliasing. A digital sidetone function allows audio

from the record path to be summed into the playback

path after digital filtering.

The MAX9867 also includes two stereo, single-ended

line inputs with gain adjustment, which can be record-

ed by the ADCs and/or output by the headphone ampli-

fiers. An auxiliary ADC accurately measures a DC

voltage by utilizing the right audio ADC and reporting

the DC voltage through the I2C interface. A jack detec-

tion function allows the detection of headphone, micro-

phone, and headset jacks. Insertion and removal

events can be programmed to trigger a hardware inter-

rupt and flag an I2C register bit.

The MAX9867’s flexible clock circuitry utilizes a program-

mable clock divider and a digital PLL, allowing the DAC

and ADC to operate at maximum dynamic range for all

combinations of master clock (MCLK) and sample rate

(LRCLK) without consuming extra supply current. Any

master clock between 10MHz and 60MHz is supported

as are all sample rates from 8kHz to 48kHz. Master and

slave modes are supported for maximum flexibility.

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 21

Pin Description (continued)

PIN/BUMP

TQFN-EP WLP NAME FUNCTION

22 E3 LOUTP Positive Left-Channel Headphone Output. Connect directly to the load in

differential and capacitorless mode. AC-couple to the load in single-ended mode.

23 E2 PVDD Headphone Power Supply. Bypass to PGND with a 1µF capacitor.

24, 25 — N.C. No Connection

26 E1 DVDDIO Digital Audio Interface Power Supply. Bypass to DGND with a 1µF capacitor.

27 D1 SDOUT Digital Audio Serial-Data ADC Output

28 C2 SDIN Digital Audio Serial-Data DAC Input

29 C1 LRCLK

Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock

and determines whether the audio data on SDIN is routed to the left or right

channel. In TDM mode, LRCLK is a frame synchronization pulse. LRCLK is an

input when the MAX9867 is in slave mode and an output when in master mode.

30 B1 BCLK Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9867 is in

slave mode and an output when in master mode.

31 B2 MCLK Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.

32 A1 DVDD Digital Power Supply. Supply for the digital circuitry and I2C interface. Bypass to

DGND with a 1µF capacitor.

— — EP Exposed Pad. Connect the exposed thermal pad to AGND.

MAX9867

I2C Registers

The MAX9867 audio codec is completely controlled

through software using an I2C interface. The power-on

default setting is complete shutdown, requiring that the

internal registers be programmed to activate the device.

See Table 1 for the device’s complete register map.

I2C Slave Address

The MAX9867 responds to the slave address 0x30 for

all write commands and 0x31 for all read operations.

Ultra-Low Power Stereo Audio Codec

22 ______________________________________________________________________________________

ADDRESS

POWER-

ON RESET

STATE

STATUS

Status (Read Only) CLD SLD ULK 0 0 0 JDET 0 0x00 —

Jack Sense (Read Only) LSNS JKSNS JKMIC 0 0 0 0 0 0x01 —

AUX High (Read Only) AUX[15:8] 0x02 —

AUX Low (Read Only) AUX[7:0] 0x03 —

Interrupt Enable ICLD ISLD IULK 0 0 SDODLY IJDET 0 0x04 0x00

CLOCK CONTROL

System Clock 0 0 PSCLK FREQ 0x05 0x00

Stereo Audio Clock

Control High PLL NI[14:8] 0x06 0x00

Stereo Audio Clock

Control Low NI[7:1] RLK/

NI[0] 0x07 0x00

DIGITAL AUDIO INTERFACE

Interface Mode MAS WCI BCI DLY HIZOFF TDM 0 0 0x08 0x00

Interface Mode 0 0 0 LVOLFIX DMONO BSEL 0x09 0x00

DIGITAL FILTERING

Codec Filters MODE AVFLT 0 DVFLT 0x0A 0x00

LEVEL CONTROL

Sidetone DSTS 0 DVST 0x0B 0x00

DAC Level 0 DACM DACG DACA 0x0C 0x00

ADC Level AVL AVR 0x0D 0x00

Left-Line Input Level 0 LILM 0 0 LIGL 0x0E 0x00

Right-Line Input Level 0 LIRM 0 0 LIGR 0x0F 0x00

Left Volume Control 0 VOLLM VOLL 0x10 0x00

Right Volume Control 0 VOLRM VOLR 0x11 0x00

Left Microphone Gain 0 PALEN PGAML 0x12 0x00

Right Microphone Gain 0 PAREN PGAMR 0x13 0x00

CONFIGURATION

ADC Input MXINL MXINR AUXCAP AUXGAIN AUXCAL AUXEN 0x14 0x00

Microphone MICCLK DIGMICL DIGMICR 0 0 0 0 0x15 0x00

Mode DSLEW VSEN ZDEN 0 JDETEN HPMODE 0x16 0x00

POWER MANAGEMENT

System Shutdown SHDN LNLEN LNREN 0 DALEN DAREN ADLEN ADREN 0x17 0x00

Revision REV 0xFF 0x42

Table 1. I2C Register Map

Device Status

Status registers 0x00 and 0x01 are read-only registers

that report the status of various device functions. The

status register bits are cleared upon reading the status

Registers 0x02 and 0x03 report the DC level applied to

AUX. See the

ADC

section for more details and Table 2.

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 23

ADDRESS

Status (Read Only) CLD SLD ULK 0 0 0 JDET 0 0x00

Jack S ense ( Read O nl y) LSNS JKSNS JKMIC 0 0 0 0 0 0x01

AUX High (Read Only) AUX[15:8] 0x02

AUX Low (Read Only) AUX[7:0] 0x03

BITS FUNCTION

CLD Clip Detect Flag

Indicates that a signal has reached or exceeded full scale in the ADC or DAC.

SLD

Slew Level Detect Flag

When volume or gain changes are made, the slewing circuitry smoothly steps through all intermediate

settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value. SLD

is also set when soft-start or stop is complete.

ULK Digital PLL Unlock Flag

Indicates that the digital audio PLL has become unlocked and digital signal data is not reliable.

JDET

Headset Configuration Change Flag

JDET is set whenever there is a change in register 0x01, indicating that the headset configuration has

changed.

LSNS

LOUTP State (Valid if SHDN = 0, JDETEN = 1)

LSNS is set when the voltage at LOUTP exceeds AVDD - 0.4V. An internal pullup from AVDD to LOUTP

causes this condition whenever there is no load on LOUTP. LSNS is only valid in differential and

capacitorless output modes.

JKSNS

JACKSNS State (Valid if JDETEN = 1)

JKSNS is set when the voltage at JACKSNS exceeds AVDD - 0.4V. An internal pullup from AVDD to

JACKSNS causes this condition whenever there is no load on JACKSNS.

JKMIC Microphone Detection (Valid if PALEN or PAREN ≠ 00 and JDETEN = 1)

JKMIC is set when JACKSNS exceeds 0.95 x VMICBIAS.

AUX

Auxiliary Input Measurement

AUX is a 16-bit signed two’s complement number representing the voltage measured at JACKSNS/AUX.

Before reading a value from AUX, set AUXCAP to 1 to ensure a stable reading. After reading the value,

set AUXCAP to 0.

Use the following formula to convert the AUX value into an equivalent JACKSNS/AUX voltage:

k = AUX value when AUXGAIN = 1. See the ADC section for complete details.

Table 2. Status Registers

Voltage V AUX

=×

⎛

⎝

⎜⎞

⎠

⎟

0 738.

MAX9867

Hardware Interrupts

Hardware interrupts are reported on the open-drain IRQ

pin. When an interrupt occurs, IRQ remains low until the

interrupt is serviced by reading the status register 0x00.

If a flag is set, it is reported as a hardware interrupt only

if the corresponding interrupt enable is set. Each bit

enables interrupts for the status flag in the respective

bit location in register 0x00. See Table 3.

SDODLY is used to control the SDOUT timing. See the

Digital Audio Interface

section for a detailed description.

Clock Control

The MAX9867 can work with a master clock (MCLK)

supplied from any system clock within the 10MHz-to-

60MHz range. Internally, the MAX9867 requires a

10MHz-to-20MHz clock. A prescaler divides MCLK by

1, 2, or 4 to create the internal clock (PCLK). PCLK is

used to clock all portions of the MAX9867. See Table 4.

The MAX9867 is capable of supporting any sample rate

from 8kHz to 48kHz, including all common sample rates

(8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz). To

accommodate a wide range of system architectures,

the MAX9867 supports three main clocking modes:

•Normal: This mode uses a 15-bit clock divider coeffi-

cient to set the sample rate relative to the prescaled

MCLK input (PCLK). This allows high flexibility in both

the MCLK and LRCLK frequencies and can be used

in either master or slave mode.

•Exact Integer: In both master and slave mode, com-

mon MCLK frequencies (12MHz, 13MHz, 16MHz,

and 19.2MHz) can be programmed to operate in

exact integer mode for both 8kHz and 16kHz sample

rates. In these modes, the MCLK and LRCLK rates

are selected by using the FREQ bits instead of the NI

and PLL control bits.

•PLL: When operating in slave mode, a PLL can be

enabled to lock onto externally generated LRCLK

signals that are not integer related to PCLK. Prior to

enabling the interface, program NI to the nearest

desired ratio and set the NI[0] = 1 to enable the

PLL’s rapid lock mode. If NI[0] = 0, then NI is ignored

and PLL lock time is slower.

Ultra-Low Power Stereo Audio Codec

24 ______________________________________________________________________________________

ADDRESS

Interrupt Enable ICLD ISLD IULK 0 0 SDODLY IJDET 0 0x04

Table 3. Interrupt Register

System Clock 0 0 PSCLK FREQ 0x05

Stereo Audio Clock

Control High PLL NI[14:8] 0x06

Stereo Audio Clock

Control Low NI[7:1] NI[0] 0x07

Table 4. Clock Control Registers

BITS FUNCTION

PSCLK

MCLK Prescaler

Divides MCLK to generate a PCLK between 10MHz and 20MHz.

00 = Disable clock for low-power shutdown.

01 = Select if MCLK is between 10MHz and 20MHz.

10 = Select if MCLK is between 20MHz and 40MHz.

11 = Select if MCLK is between 40MHz and 60MHz.

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 25

BITS FUNCTION

Exact Integer Modes

Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or 16kHz sample rates.

FREQ[3:0] PCLK (MHz) LRCLK (kHz) PCLK/LRCLK

0x00 Normal or PLL mode

0x1–0x7 Reserved Reserved Reserved

0x8

0x9

1500

750

0xA

0xB

1625

812.5

0xC

0xD

2000

1000

0xE

0xF

19.2

2400

1200

FREQ

Modes 0x8–0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK ratio

cannot be guaranteed, use PLL mode instead.

PLL

PLL Mode Enable

0 = Valid for slave and master mode. The frequency of LRCLK is set by the NI divider bits. In master mode, the

MAX9867 generates LRCLK using the specified divide ratio. In slave mode, the MAX9867 expects an

LRCLK as specified by the divide ratio.

1 = Valid for slave mode only. A digital PLL locks on to any externally supplied LRCLK signal.

Rapid Lock Mode

To enable rapid lock mode, set NI to the nearest desired ratio and set NI[0] = 1 before enabling the interface.

Normal Mode LRCLK Divider

When PLL = 0, the frequency of LRCLK is determined by NI. See Table 5 for common NI values.

NI = (65536 x 96 x fLRCLK)/fPCLK

fLRCLK = LRCLK frequency

fPCLK = Prescaled MCLK internal clock frequency (PCLK)

LRCLK > 24kHz is only valid for MODE = 0 (stereo audio mode). MODE = 1 (voice mode) requires LRCLK ≤

24kHz.

Table 4. Clock Control Registers (continued)

LRCLK (kHz)

MCLK (MHz) PSCLK 8 16 24 32 44.1 48

11.2896 01 0x116A 0x22D4 0x343F 0x45A9 0x6000 0x687D

12 01 0x1062 0x20C5 0x3127 0x4189 0x5A51 0x624E

12.288 01 0x1000 0x2000 0x3000 0x4000 0x5833 0x6000

13 01 0x0F20 0x1E3F 0x2D5F 0x3C7F 0x535F 0x5ABE

19.2 01 0x0A3D 0x147B 0x1EB8 0x28F6 0x3873 0x3D71

24 10 0x1062 0x20C5 0x1893 0x4189 0x5A51 0x624E

26 10 0x0F20 0x1E3F 0x16AF 0x3C7F 0x535F 0x5ABE

27 10 0x0E90 0x1D21 0x15D8 0x3A41 0x5048 0x5762

Note: Bolded values are exact integers that provide maximum full-scale performance.

Table 5. Common NI Values

MAX9867

Ultra-Low Power Stereo Audio Codec

26 ______________________________________________________________________________________

ADDRESS

Interface Mode MAS WCI BCI DLY HIZOFF TDM 0 0 0x08

Interface Mode 0 0 0 LVOLFIX DMONO BSEL 0x09

BITS FUNCTION

MAS

Master Mode

0 = The MAX9867 operates in slave mode with LRCLK and BCLK configured as inputs.

1 = The MAX9867 operates in master mode with LRCLK and BCLK configured as outputs.

WCI

LRCLK Invert

0 = Left-channel data is input and output while LRCLK is low.

1 = Right-channel data is input and output while LRCLK is low.

Note: WCI is ignored when TDM = 1.

BCI

BCLK Invert

In master and slave modes:

0 = SDIN is latched into the part on the rising edge of BCLK.

SDOUT transitions after the rising edge of BCLK as determined by SDODLY.

1 = SDIN is latched into the part on the falling edge of BCLK.

SDOUT transitions after the falling edge of BCLK as determined by SDODLY.

In master mode:

0 = LRCLK changes state immediately after the rising edge of BCLK.

1 = LRCLK changes state immediately after the falling edge of BCLK.

SDODLY

SDOUT Delay

0 = SDOUT transitions one half BCLK cycle after SDIN is latched into the part.

1 = SDOUT transitions on the same BCLK edge as SDIN is latched into the part.

See Figures 1–4 for complete details. See Register 0x04 (interrupt registers).

DLY

Delay Mode

0 = SDIN/SDOUT data is latched on the first BCLK edge following an LRCLK edge.

1 = SDIN/SDOUT data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge

following an LRCLK edge (I2S-compatible mode).

Note: DLY is ignored when TDM = 1.

HIZOFF

SDOUT High-Impedance Mode

0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9867,

allowing SDOUT to be shared by other devices.

1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9867.

Note: High-impedance mode is intended for use when TDM = 1.

LVOLFIX See the Line Inputs section.

Table 6. Digital Audio Interface Registers

Digital Audio Interface

The MAX9867’s digital audio interface supports a wide

range of operating modes to ensure maximum compati-

bility. See Figures 1–4 for timing diagrams. In master

mode, the MAX9867 outputs LRCLK and BCLK, while in

slave mode they are inputs. When operating in master

mode, BCLK can be configured in a number of ways to

ensure compatiblity with other audio devices.

LVOLFIX is used to fix the line input playback volume to

0dB regardless of VOLL and VOLR. See the

Line Inputs

section for complete details and Table 6.

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 27

BITS FUNCTION

TDM

TDM Mode Select

0 = LRCLK signal polarity indicates left and right audio.

1 = LRCLK is a framing pulse that transitions polarity to indicate the start of a frame of audio data consisting

of multiple channels.

When operating in TDM mode, the left channel is output immediately following the frame sync pulse. If right-

channel data is being transmitted, the 2nd channel of data immediately follows the 1st channel data.

DMONO

Mono Playback Mode

0 = Stereo data input on SDIN is processed separately.

1 = Stereo data input on SDIN is mixed to a single channel and routed to both the left and right DAC.

BSEL

BCLK Select

Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010, unless

sharing the bus with multiple devices:

000 = Off

001 = 64x LRCLK (192x internal clock divided by 3)

010 = 48x LRCLK (192x internal clock divided by 4)

011 = Reserved for future use.

100 = PCLK/2

101 = PCLK/4

110 = PCLK/8

111 = PCLK/16

Table 6. Digital Audio Interface Registers (continued)

AUDIO MASTER MODES:

LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 0

LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, BCI = 0, DLY = 0, SDODLY = 0

LEFT JUSTIFIED + BCLK INVERT: WCI = 0, BCI = 1, DLY = 0, SDODLY = 0

LRCLK

BCLK

SDOUT

SDIN

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1/fS

CONFIGURED BY BSEL

7ns (typ)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15

25ns (min)

7ns (typ)

0ns (min)

40ns (max)

0ns (min)

CONFIGURED BY BSEL

7ns (typ)

25ns (min)

7ns (typ)

0ns (min)

CONFIGURED BY BSEL

25ns (min) 0ns (min)

40ns (max)

0ns (min)

RELATIVE TO PCLK (SEE NOTE)

RIGHT

LRCLK

BCLK

SDOUT

SDIN

7ns (typ)7ns (typ)

RELATIVE TO PCLK (SEE NOTE)

LRCLK

BCLK

SDOUT

SDIN

D15

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15

7ns (typ) 7ns (typ)

40ns (max)

0ns (min)

RELATIVE TO PCLK (SEE NOTE)

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15

NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF

MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHZ, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.

LEFT

1/fS

7ns (typ)7ns (typ)

RIGHTLEFT

RIGHT

LEFT

Figure 1. Digital Audio Interface Audio Master Mode Example (Sheet 1 of 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

28 ______________________________________________________________________________________

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 29

I2S: WCI = 0, BCI = 0, DLY = 1, SDODLY = 0

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15

CONFIGURED BY BSEL

7ns (typ)

25ns (min)

7ns (typ)

0ns (min)

CONFIGURED BY BSEL

7ns (typ)

25ns (min)

7ns (typ)

0ns (min)

40ns (max)

0ns (min)

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

40ns (max)

0ns (min)

D15

LRCLK

BCLK

SDOUT

SDIN

NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF

MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHZ, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.

LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 1

LRCLK

BCLK

SDOUT

SDIN

RELATIVE TO PCLK (SEE NOTE)

1/fS

7ns (typ)7ns (typ)

RIGHTLEFT

RELATIVE TO PCLK (SEE NOTE)

1/fS

7ns (typ)7ns (typ)

RIGHTLEFT

Figure 1. Digital Audio Interface Audio Master Mode Example (Sheet 2 of 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

30 ______________________________________________________________________________________

VOICE (TDM, PCM) MASTER MODES:

BCI = 0, HIZOFF = 0, SDODLY = 0

LRCLK

BCLK

SDOUT

SDIN

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

CONFIGURED BY BSEL

25ns (min) 0ns (min)

40ns (max)

0ns (min)

L15

RELATIVE TO PCLK (SEE NOTE)

BCI = 1, HIZOFF = 0, SDODLY = 0

BCI = 0, HIZOFF = 1, SDODLY = 0

LRCLK

BCLK

SDOUT

LRCLK

BCLK

SDOUT

SDIN

R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

LRCLK

BCLK

SDOUT

SDIN

BCI = 0, HIZOFF = 0, SDODLY = 1

7ns (typ)

7ns (typ) 7ns (typ)

7ns (typ)

CONFIGURED BY BSEL

25ns (min) 0ns (min)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

7ns (typ) 7ns (typ)

CONFIGURED BY BSEL

25ns (min) 0ns (min)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

SDIN

CONFIGURED BY BSEL

25ns (min) 0ns (min)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

1/fS

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

40ns (max)

0ns (min)

L15

RELATIVE TO PCLK (SEE NOTE)

R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

7ns (typ)

7ns (typ) 7ns (typ)

7ns (typ)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

40ns (max)

0ns (min)

L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

1/fS

RELATIVE TO PCLK (SEE NOTE)

7ns (typ) 7ns (typ)

1/fS

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

40ns (max)

0ns (min)

L15

RELATIVE TO PCLK (SEE NOTE)

R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

7ns (typ)

7ns (typ) 7ns (typ)

7ns (typ)

1/fS

Figure 2. Digital Audio Interface Voice Master Mode Examples

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 31

AUDIO SLAVE MODES:

LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 0

LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, BCI = 0, DLY = 0, SDODLY = 0

LEFT JUSTIFIED + BCLK INVERT: WCI = 0, BCI = 1, DLY = 0, SDODLY = 0

LRCLK

BCLK

SDOUT

SDIN

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1/fS

30ns (min)

75ns (min)

30ns (min)75ns (min)

0ns (min)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15

25ns (min)

0ns (min)

40ns (max)

0ns (min)

30ns (min)

25ns (min)

40ns (max)

0ns (min)

25ns (min) 0ns (min)

RIGHT

LRCLK

BCLK

SDOUT

SDIN

LRCLK

BCLK

SDOUT

SDIN

D15

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15

40ns (max)

0ns (min)

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15

LEFT

1/fS

RIGHT

LEFT

RIGHT

LEFT

Figure 3. Digital Audio Interface Audio Slave Mode Examples (Sheet 1 of 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

32 ______________________________________________________________________________________

I2S: WCI = 0, BCI = 0, DLY = 1, SDODLY = 0

0ns (min)

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15

30ns (min)75ns (min)

30ns (min)

30ns (min)75ns (min)

30ns (min)

25ns (min)

25ns (min) 0ns (min)

40ns (max)

0ns (min)

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

40ns (max)

0ns (min)

D15

LRCLK

BCLK

SDOUT

SDIN

LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 1

LRCLK

BCLK

SDOUT

SDIN

1/fS

RIGHTLEFT

1/fS

RIGHTLEFT

Figure 3. Digital Audio Interface Audio Slave Mode Examples (Sheet 2 of 2)

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 33

VOICE (TDM, PCM) SLAVE MODES:

BCI = 0, HIZOFF = 0, SDODLY = 0

LRCLK

BCLK

SDOUT

SDIN

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

75ns (min)

25ns (min) 0ns (min)

40ns (max)

0ns (min)

L15

25ns (min)

BCI = 1, HIZOFF = 0, SDODLY = 0

BCI = 0, HIZOFF = 1, SDODLY = 0

LRCLK

BCLK

SDOUT

LRCLK

BCLK

SDOUT

SDIN

R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

LRCLK

BCLK

SDOUT

SDIN

BCI = 0, HIZOFF = 0, SDODLY = 1

30ns (min)

75ns (min) 30ns (min)

30ns (min)

40ns (max)

0ns (min)

25ns (min)

40ns (max)

0ns (min)

25ns (min)

40ns (max)

0ns (min)

25ns (min)

25ns (min) 0ns (min)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

25ns (min) 0ns (min)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

SDIN

25ns (min) 0ns (min)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

1/fS

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

1/fS

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0L15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R15

1/fS

75ns (min) 30ns (min)

30ns (min)

75ns (min) 30ns (min)

30ns (min)

0ns (min) 0ns (min)

Figure 4. Digital Audio Interface Voice Slave Mode Examples

MAX9867

Ultra-Low Power Stereo Audio Codec

34 ______________________________________________________________________________________

Digital Filtering

The MAX9867 incorporates both IIR (voice) and FIR

(audio) digital filters to accomodate a wide range of

audio sources. The IIR fiilters provide over 70dB of

stopband attenuation as well as selectable highpass fil-

ters. The FIR filters provide low-power consumption and

are linear phase to maintain stereo imaging. Table 7 is

the digital filtering register.

ADDRESS

Codec Filters MODE AVFLT 0 DVFLT 0x0A

BITS FUNCTION

MODE

Digital Audio Filter Mode

0 = IIR Voice Filters

1 = FIR Audio Filters

AVFLT

ADC Digital Audio Filter

MODE = 0

Select the desired digital filter response from Table 8. See the Frequency Response graph in the Typical

Operating Characteristics section for details on each filter.

MODE = 1

0x0 = DC-blocking filter is disabled. Any other setting = DC-blocking filter is enabled.

DVFLT

DAC Digital Audio Filter

MODE = 0

Select the desired digital filter response from Table 8. See the Frequency Response graph in the Typical

Operating Characteristics section for details on each filter.

MODE = 1

0x0 = DC-blocking filter is disabled. Any other setting = DC-blocking filter is enabled.

Table 7. Digital Filtering Register

CODE FILTER TYPE INTENDED SAMPLE

RATE (kHz)

HIGHPASS CORNER

FREQUENCY (Hz) 217Hz NOTCH

0x0 Disabled

0x1 Elliptical 16 256 Yes

0x2 Butterworth 16 500 No

0x3 Elliptical 8 256 Yes

0x4 Butterworth 8 500 No

0x5 Butterworth 8 to 24 fS/240 No

0x6 to 0x7 Reserved

Table 8. IIR Highpass Digital Filters

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 35

Digital Gain Control

The MAX9867 includes digital gain adjustment for the

playback and record paths. Independent gain adjust-

ment is provided for the two record channels. Sidetone

gain adjustment is also provided to set the sidetone

level relative to the playback level. Table 9 is the digital

gain registers.

ADDRESS

Sidetone DSTS 0 DVST 0x0B

DAC Level 0 DACM DACG DACA 0x0C

ADC Level AVL AVR 0x0D

BITS FUNCTION

DSTS

Digital Sidetone Source Mixer

00 = No sidetone is selected.

01 = Left ADC

10 = Right ADC

11 = Left + right ADC

Digital Sidetone Level Control

All gain settings are relative to the ADC input voltage.

Differential Headphone Output Mode

SETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB)

0x00 Off 0x0B -20 0x16 -42

0x01 0 0x0C -22 0x17 -44

0x02 -2 0x0D -24 0x18 -46

0x03 -4 0x0E -26 0x19 -48

0x04 -6 0x0F -28 0x1A -50

0x05 -8 0x10 -30 0x1B -52

0x06 -10 0x11 -32 0x1C -54

0x07 -12 0x12 -34 0x1D -56

0x08 -14 0x13 -36 0x1E -58

0x09 -16 0x14 -38 0x1F -60

0x0A -18 0x15 -40 — —

Capacitorless and Single-Ended Headphone Output Mode

SETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB)

0x00 Off 0x0B -25 0x16 -47

0x01 -5 0x0C -27 0x17 -49

0x02 -7 0x0D -29 0x18 -51

0x03 -9 0x0E -31 0x19 -53

0x04 -11 0x0F -33 0x1A -55

0x05 -13 0x10 -35 0x1B -57

0x06 -15 0x11 -37 0x1C -59

0x07 -17 0x12 -39 0x1D -61

0x08 -19 0x13 -41 0x1E -63

0x09 -21 0x14 -43 0x1F -65

DVST

0x0A -23 0x15 -45 — —

DACM

DAC Mute Enable

0 = No mute

1 = Mute

Table 9. Digital Gain Registers

MAX9867

Ultra-Low Power Stereo Audio Codec

36 ______________________________________________________________________________________

BITS FUNCTION

DACG

DAC Gain

00 = 0dB

01 = +6dB

10 = +12dB

11 = +18dB

Note: DACG is only used when MODE = 0. If MODE = 1, the DAC level is only set by DACA.

DAC Level Control

DACA works in all modes.

SETTING GAIN (dB) SETTING GAIN (dB)

0x0 0 0x8 -8

0x1 -1 0x9 -9

0x2 -2 0xA -10

0x3 -3 0xB -11

0x4 -4 0xC -12

0x5 -5 0xD -13

0x6 -6 0xE -14

DACA

0x7 -7 0xF -15

ADC Left/Right Level Control

SETTING GAIN (dB) SETTING GAIN (dB)

0x0 +3 0x8 -5

0x1 +2 0x9 -6

0x2 +1 0xA -7

0x3 0 0xB -8

0x4 -1 0xC -9

0x5 -2 0xD -10

0x6 -3 0xE -11

AVL/AVR

0x7 -4 0xF -12

Table 9. Digital Gain Registers (continued)

Line Inputs

The MAX9867 includes one pair of single-ended line

inputs. When enabled, the line inputs connect directly

to the headphone amplifier and can be optionally con-

nected to the ADC for recording. Table 10 lists the line

input registers.

Table 10. Line Input Registers

ADDRESS

Left-Line Input Level 0 LILM 0 0 LIGL 0x0E

Right-Line Input Level 0 LIRM 0 0 LIGR 0x0F

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 37

BITS FUNCTION

LILM/LIRM

Line-Input Left/Right Playback Mute

0 = Line input is connected to the headphone amplifiers.

1 = Line input is disconnected from the headphone amplifiers.

Line-Input Left/Right Gain

SETTING GAIN (dB) SETTING GAIN (dB)

0x0 +24 0x8 +8

0x1 +22 0x9 +6

0x2 +20 0xA +4

0x3 +18 0xB +2

0x4 +16 0xC 0

0x5 +14 0xD -2

0x6 +12 0xE -4

LIGL/LIGR

0x7 +10 0xF -6

LVOLFIX

Fix Line Input Volume

0 = Line input to headphone output volume tracks VOLL and VOLR bits.

1 = Line input to headphone output volume fixed at VOLL and VOLR bits.

See the Digital Audio Interface section.

Table 10. Line Input Registers (continued)

Playback Volume

The MAX9867 incorporates volume and mute control to

allow level control for the playback audio path. Program

registers 0x10 and 0x11 to set the desired volume. See

Table 11.

Table 11. Playback Volume Registers

ADDRESS

Left Volume Control 0 VOLLM VOLL 0x10

Right Volume Control 0 VOLRM VOLR 0x11

MAX9867

Ultra-Low Power Stereo Audio Codec

38 ______________________________________________________________________________________

Table 11. Playback Volume Registers (continued)

Microphone Inputs

Two differential microphone inputs and a low-noise micro-

phone bias for powering the microphones are provided

by the MAX9867. In typical applications, the left micro-

phone records a voice signal and the right microphone

records a background noise signal. In applications that

require only one microphone, use the left microphone

input and disable the right ADC. The microphone signals

are amplified by two stages of gain and then routed to

the ADCs. The first stage offers selectable 0dB, 20dB,

or 30dB settings. The second stage is a programmable

gain amplifier (PGA) adjustable from 0dB to 20dB in

1dB steps. Zero-crossing detection is included on the

PGA to minimize zipper noise while making gain

changes. See Figure 5 for a detailed diagram of the

microphone input structure. Table 12 is the microphone

input register.

Table 12. Microphone Input Registers

ADDRESS

Left Microphone Gain 0 PALEN PGAML 0x12

Right Microphone Gain 0 PAREN PGAMR 0x13

BITS FUNCTION

VOLLM/VOLRM

Left/Right Playback Mute

VOLLM and VOLRM mute both the DAC and line input audio signals.

0 = Audio playback is unmuted.

1 = Audio playback is muted

Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set, the output is muted

immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).

Left/Right Playback Volume

VOLL and VOLR control the playback volume for both the DAC and line input audio signals.

SETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB)

0x00 +6 0x0E -5 0x1C -42

0x01 +5.5 0x0F -6 0x1D -46

0x02 +5 0x10 -8 0x1E -50

0x03 +4.5 0x11 -10 0x1F -54

0x04 +4 0x12 -12 0x20 -58

0x05 +3.5 0x13 -14 0x21 -62

0x06 +3 0x14 -16 0x22 -66

0x07 +2 0x15 -18 0x23 -70

0x08 +1 0x16 -20 0x24 -74

0x09 0 0x17 -22 0x25 -78

0x0A -1 0x18 -26 0x26 -82

0x0B -2 0x19 -30 0x27 -84

0x0C -3 0x1A -34

0x0D -4 0x1B -38 0x28 to 0x3F MUTE

VOLL/VOLR

Note: Gain settings apply when the headphone amplifier is configured in differential mode. In the single-

ended and capacitorless modes, the actual gain is 5dB lower for each setting.

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 39

BITS FUNCTION

PALEN/PAREN

Left/Right Microphone Preamplifier Gain

Enables the microphone circuitry and sets the preamplifier gain.

00 = Disabled

01 = 0dB

10 = +20dB

11 = +30dB

Left/Right Microphone Programmable Gain Amplifier

SETTING GAIN (dB) SETTING GAIN (dB)

0x00 +20 0x0B +9

0x01 +19 0x0C +8

0x02 +18 0x0D +7

0x03 +17 0x0E +6

0x04 +16 0x0F +5

0x05 +15 0x10 +4

0x06 +14 0x11 +3

0x07 +13 0x12 +2

0x08 +12 0x13 +1

0x09 +10

PGAML/PGAMR

0x0A +11

0x14

to 0x1F 0

MICLN

MICLP

MICBIAS

PGA

PREAMP

MICRN

ADC

MICRP

1.5V

0/20/30dB

0dB TO +20dB

VREG

0/20/30dB

PREAMP

MAX9867

ADC

Figure 5. Microphone Input Signal Path

Table 12. Microphone Input Registers (continued)

MAX9867

Ultra-Low Power Stereo Audio Codec

40 ______________________________________________________________________________________

ADC

The MAX9867 includes two 16-bit ADCs. The first ADC

is used to record left-channel microphone and line-input

audio signals. The second ADC can be used to record

right-channel microphone and line-input signals, or it

can be configured to accurately measure DC voltages.

When measuring DC voltages, both the left and right

ADCs must be enabled by setting ADLEN and ADREN

in register 0x17. The input to the second ADC is JACK-

SNS/AUX and the output is reported in AUX (registers

0x02 and 0x03). Since the audio ADC is used to per-

form the measurement, the digital audio interface must

be properly configured. If the left ADC is being used to

convert audio, the DC measurement is performed at the

same sample rate. When not using the left ADC, config-

ure the digital interface for a 48kHz sample rate to

ensure the fastest possible settling time.

To ensure accurate results, the MAX9867 includes two

calibration routines. Calibrate the ADC each time the

MAX9867 is powered on. Calibration settings are not

lost if the MAX9867 is placed in shutdown. When mak-

ing a measurement, set AUXCAP to 1 to prevent AUX

from changing while reading the registers.

Setup Procedure

1) Ensure a valid MCLK signal is provided and config-

ure PSCLK appropriately.

2) Choose a clocking mode. The following options are

possible:

•Slave mode with LRCLK and BCLK signals pro-

vided. The measurement sample rate is deter-

mined by the external clocks.

•Slave mode with no LRCLK and BCLK signals

provided. Configure the device for normal clock

mode using the NI ratio. Select fS= 48kHz to allow

for the fastest settling times.

•Master mode with audio. Configure the device in

normal mode using the NI ratio or exact integer

mode using FREQ as required by the audio signal.

•Master mode without audio. Configure the

device in normal mode using the NI ratio. Select fS

= 48kHz to allow for the fastest settling times.

3) Ensure JACKSNS is disabled.

4) Enable the left and right ADC; take the MAX9867 out

of shutdown.

Offset Calibration Procedure

Perform the following steps before the first DC mea-

surement is taken after applying power to the

MAX9867:

1) Enable the AUX input (AUXEN = 1).

2) Enable the offset calibration (AUXCAL = 1).

3) Wait the appropriate time (see Table 13).

4) Complete calibration (AUXCAL = 0).

Gain Calibration Procedure

Perform the following steps the first time a DC measure-

ment is taken after applying power to the MAX9867 or if

the temperature changes significantly:

1) Enable the AUX input (AUXEN = 1).

2) Start gain calibration (AUXGAIN = 1).

3) Wait the appropriate time (see Table 13).

4) Freeze the measurement results (AUXCAP = 1).

5) Read AUX and store the value in memory to correct

all future measurements (k = AUX[15:0], k is typical-

ly 19500).

6) Complete calibration (AUXGAIN = AUXCAP = 0).

DC Measurement Procedure

Perform the following steps after offset and gain cali-

bration are complete:

1) Enable the AUX input (AUXEN = 1).

2) Wait the appropriate time (see Table 13).

3) Freeze the measurement results (AUXCAP = 1).

4) Read AUX and correct with the gain calibration

value:

5) Complete measurement (AUXCAP = 0).

VAUX

AUX =⎛

⎝

⎜⎞

⎠

⎟

0 738 15 0

.[:]

Table 13. AUX ADC Wait Times

WAIT TIMES

LRCLK (kHz) WAIT TIME (ms)

48 40

44.1 44

32 60

24 80

22.05 90

16 120

12 160

11.025 175

8 240

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 41

Complete DC Measurement Example

MCLK = 13MHz, slave mode, BCLK and LRCLK not

externally supplied:

1) Configure the digital audio interface for fS= 48kHz

(PSCLK = 01, FREQ = 0x0, PLL = 0, NI = 0x5ABE,

MAS = 0).

2) Disable JACKSNS (JDETEN = 0).

3) Enable the left and right ADC; take the MAX9867 out

of shutdown (ADLEN = ADREN = SHDN = 1).

4) Calibrate the offset:

a. Enable the AUX input (AUXEN = 1).

b. Enable the offset calibration (AUXCAL = 1).

c. Wait 40ms.

d. Complete calibration (AUXCAL = 0).

5) Calibrate the gain:

a. Start gain calibration (AUXGAIN = 1).

b. Wait 40ms.

c. Freeze the measurement results (AUXCAP = 1).

d. Read AUX and store the value in memory to cor-

rect all future measurements (k = AUX[15:0]).

e. Complete calibration (AUXGAIN = AUXCAP =

AUXEN = 0).

6) Measure the voltage on JACKSNS/AUX:

a. Enable the AUX input (AUXEN = 1).

b. Wait 40ms.

c. Freeze the measurement results (AUXCAP = 1).

d. Read AUX and correct with the gain calibration

value.

e. Complete measurement (AUXCAP = 0).

7) DC measurement complete.

Table 14. ADC Input Register

ADDRESS

ADC Input MXINL MXINR AUXCAP AU X GAIN AUXCAL AUXEN 0x14

BITS FUNCTION

MXINL/MXINR

Left/Right ADC Audio Input Mixer

00 = No input is selected.

01 = Left/right analog microphone

10 = Left/right line input

11 = Left/right analog microphone + line input

Note: If the right-line input is disabled, then the left-line input is connected to both mixers. Enabling the

left and right digital microphones disables the left and right audio mixers, respectively. See DIGMICL/

DIGMICR in Table 15 for more details.

AUXCAP

Auxiliary Input Capture

0 = Update AUX with the voltage at JACKSNS/AUX.

1 = Hold AUX for reading.

AUXGAIN

Auxiliary Input Gain Calibration

0 = Normal operation

1 = The input buffer is disconnected from JACKSNS/AUX and connected to an internal voltage reference.

While in this mode, read the AUX register and store the value. Use the stored value as a gain

calibration factor, K, on subsequent readings.

AUXCAL

Auxiliary Input Offset Calibration

0 = Normal operation

1 = JACKSNS/AUX is disconnected from the input and the ADC automatically calibrates out any internal

offsets.

AUXEN

Auxiliary Input Enable

0 = Use JACKSNS/AUX for jack detection.

1 = Use JACKSNS/AUX for DC measurements.

Note: For AUXEN = 1, set MXINR = 00, ADLEN = 1, and ADREN = 1.

MAX9867

Ultra-Low Power Stereo Audio Codec

42 ______________________________________________________________________________________

Digital Microphone Input

The MAX9867 can accept audio from up to two digital

microphones. When using digital microphones, the left

analog microphone input is retasked as a digital micro-

phone input. The right analog microphone input is still

available to allow a combination of analog and digital

microphones to be used. Figure 6 shows the digital

microphone interface timing diagram. See Table 15.

Table 15. Digital Microphone Input Register

ADDRESS

Microphone MICCLK DIGMICL DIGMICR 0 0 0 0 0x15

BITS FUNCTION

MICCLK

Digital Microphone Clock

00 = PCLK/8

01 = PCLK/6

10 = Reserved

11 = Reserved

Digital Left/Right Microphone Enable

DIGMICL DIGMICR Left ADC Input Right ADC Input

0 0 ADC input mixer ADC input mixer

Line input (left analog

microphone unavailable) Right digital microphone

1 0 Left digital microphone ADC input mixer

1 1 Left digital microphone Right digital microphone

DIGMICL/DIGMICR

Note: The left analog microphone input is never available when DIGMICL or DIGMICR = 1.

DIGMICCLK

DIGMICDATA

tSU, MIC

tHD, MIC tSU, MIC

tHD, MIC

LEFT RIGHT LEFT RIGHT

1/fMICCLK

Figure 6. Digital Microphone Timing Diagram

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 43

Mode Configuration

The MAX9867 includes circuitry to minimize click-and-

pop during volume changes, detect headsets, and con-

figure the headphone amplifier mode. Both volume

slewing and zero-crossing detection are included to

ensure click-and-pop free volume transitions. Table 16

is the mode configuration register.

Headset Detection Overview

The MAX9867 features headset detection that can detect

the insertion and removal of a jack as well as the load

type. When a jack is detected, an interrupt on IRQ can be

triggered to alert the microcontroller of the event. Figure 7

shows the typical configuration for jack detection.

Sleep-Mode Headset Detection

When the MAX9867 is in shutdown and the power supply

is available, sleep-mode headset detection can be

enabled to detect jack insertion. Sleep mode applies a

4µA pullup current to JACKSNS/AUX and LOUTP that

forces the voltage on JACKSNS/AUX and LOUTP to

AVDD when no load is applied. When a jack is inserted,

either JACKSNS, LOUTP (assuming the headphone

amplifier is not configured in single-ended mode), or both

are loaded sufficiently to reduce the output voltage to

nearly 0V and clear the JKSNS or LSNS bits, respectively.

The change in the LSNS and JKSNS bits sets JDET and

triggers an interrupt on IRQ if IJDET is set. The interrupt

signals the microcontroller that a jack has been inserted,

allowing the microcontroller to respond as desired.

Powered-On Headset Detection

When the MAX9867 is in normal operation and the micro-

phone interface is enabled, jack insertion and removal can

be detected through the JACKSNS/AUX pin. As shown in

Figure 7, VMIC is pulled up by MICBIAS. When a micro-

phone is connected, VMIC is assumed to be between 0V

and 95% of VMICBIAS. If the jack is removed, VMIC increas-

es to VMICBIAS. This event causes JKMIC to be set, alert-

ing the system that the headset has been removed.

Alternatively, if the jack is inserted, VMIC decreases to

below 95% of VMICBIAS and JKMIC is cleared, alerting the

system that a jack has been inserted. The JKMIC bit can

be configured to create a hardware interrupt that alerts the

microcontroller of jack removal and insertion events.

Headphone Modes

The headphone amplifier supports differential, single-

ended, and capacitorless output modes, as shown in

Figure 8. In each mode, the amplifier can be configured

for stereo or mono operation. The differential and

capacitorless modes are inherently click and pop free.

The single-ended mode optionally includes click-and-

pop reduction to eliminate the click and pop that would

normally be caused by the output coupling capacitor.

When click-and-pop reduction is not required in the sin-

gle-ended configuration, leave LOUTN and ROUTN

unconnected.

GND MIC HPR HPL

LOUTP

ROUTP

MICBIAS

JACKSNS/AUX

MICLP

LOUTN

Figure 7. Typical Configuration for Headset Detection

LOUTP

LOUTN

ROUTP

ROUTN

DIFFERENTIAL

LOUTP

LOUTN

ROUTP

ROUTN

CAPACITORLESS

1µF

LOUTP

220µF

LOUTN

SINGLE ENDED

1µF

ROUTP

220µF

ROUTN

OPTIONAL COMPONENTS REQUIRED FOR CLICK AND POP SUPPRESSION ONLY

Figure 8. Headphone Amplifier Modes

MAX9867

Ultra-Low Power Stereo Audio Codec

44 ______________________________________________________________________________________

Table 16. Mode Configuration Register

ADDRESS

Mode DSLEW VSEN ZDEN 0 JDETEN HPMODE 0x16

BITS FUNCTION

DSLEW

Digital Volume Slew Speed

0 = Digital volume changes are slewed over 10ms.

1 = Digital volume changes are slewed over 80ms.

VSEN

Volume Change Smoothing

0 = Volume changes slew through all intermediate values.

1 = Volume changes occur in one step.

ZDEN

Line Input Zero-Crossing Detection

0 = Line input volume changes occur at zero crossings in the audio waveform or after 62ms if no zero

crossing occurs.

1 = Line-input volume changes occur immediately.

JDETEN

Jack Detection Enable

SHDN = 0: Sleep Mode

Enables pullups on LOUTP and JACKSNS/AUX to detect jack insertion. LSNS and JKSNS are valid.

LOUTP detection is only valid in differential and capacitorless output modes.

SHDN = 1: Normal Mode

Enables the comparator circuitry on JACKSNS/AUX to detect voltage changes. JKMIC is valid if the

microphone circuitry is enabled.

Note: AUXEN must be set to 0 for jack detection to function.

Headphone Amplifier Mode

HPMODE Mode

000 Stereo differential (clickless)

001 Mono (left) differential (clickless)

010 Stereo capacitorless (clickless)

011 Mono (left) capacitorless (clickless)

100 Stereo single-ended (clickless)

101 Mono (left) single-ended (clickless)

110 Stereo single-ended (fast turn-on)

111 Mono (left) single-ended (fast turn-on)

HPMODE

Note: In mono operation, the right amplifier is disabled.

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 45

Power Management

The MAX9867 includes complete power management

control to minimize power usage. The DAC and both

ADC can be independently enabled so that only the

required circuitry is active. Toggle the SHDN bit when-

ever a configuration change is made. Table 17 is the

power-management register.

Table 17. Power-Management Register

ADDRESS

System Shutdown SHDN LNLEN LNREN 0 DALEN DAREN ADLEN ADREN 0x17

BITS FUNCTION

SHDN Shutdown

Places the device in low-power shutdown mode.

LNLEN

Left-Line Input Enable

Enables the left-line input preamp and automatically enables the left and right headphone amplifiers.

If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and right headphone

amplifier.

Note: Control of the right headphone amplifier can be overridden by HPMODE.

LNREN

Right-Line Input Enable

Enables the right-line input preamp and automatically enables the right headphone amplifier.

Note: Control of the right headphone amplifier can be overridden by HPMODE.

DALEN

Left DAC Enable

E nab l es the l eft D AC and autom ati cal l y enab l es the l eft and r i g ht head p hone am p l i fi er s. If D ARE N = 0, the

l eft D AC si g nal i s al so r outed to the r i g ht head p hone am p l i fi er .

Note: Control of the right headphone amplifier can be overridden by HPMODE.

DAREN

Right DAC Enable

Enabling the right DAC must be done in the same I2C write operation that enables the left DAC. Right

DAC operation requires DALEN = 1.

ADLEN Left ADC Enable

ADREN

Right ADC Enable

Enabling the right ADC must be done in the same I2C write operation that enables the left ADC. The right

ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must be toggled

to disable the right ADC in this case. Right ADC operation requires ADLEN = 1.

Revision Code

The MAX9867 includes a revision code to allow easy

identification of the device revision. The revision code is

0x42. See Table 18 for the revision code register.

Table 18. Revision Code Register

ADDRESS

Revision REV 0xFF

MAX9867

Ultra-Low Power Stereo Audio Codec

46 ______________________________________________________________________________________

I2C Serial Interface

The MAX9867 features an I2C/SMBus-compatible,

2-wire serial interface consisting of a serial-data line

(SDA) and a serial-clock line (SCL). SDA and SCL facili-

tate communication between the MAX9867 and the mas-

ter at clock rates up to 400kHz. Figure 9 shows the

2-wire interface timing diagram. The master generates

SCL and initiates data transfer on the bus. The master

device writes data to the MAX9867 by transmitting the

proper slave address followed by the register address

and then the data word. Each transmit sequence is

framed by a START (S) or REPEATED START (Sr) condi-

tion and a STOP (P) condition. Each word transmitted to

the MAX9867 is 8 bits long and is followed by an

acknowledge clock pulse. A master reading data from

the MAX9867 transmits the proper slave address

followed by a series of nine SCL pulses. The MAX9867

transmits data on SDA in sync with the master-generated

SCL pulses. The master acknowledges receipt of each

byte of data. Each read sequence is framed by a START

or REPEATED START condition, a not acknowledge, and

a STOP condition. SDA operates as both an input and an

open-drain output. A pullup resistor, typically greater

than 500Ωis required on SDA. SCL operates only as an

input. A pullup resistor, typically greater than 500Ω, is

required on SCL if there are multiple masters on the bus,

or if the single master has an open-drain SCL output.

Series resistors in line with SDA and SCL are optional.

Series resistors protect the digital inputs of the

MAX9867 from high-voltage spikes on the bus lines, and

minimize crosstalk, and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL cycle. The

data on SDA must remain stable during the high period

of the SCL pulse. Changes in SDA while SCL is high

are control signals. See the

START and STOP

Conditions

section.

START and STOP Conditions

SDA and SCL idle high when the bus is not in use. A

master initiates communication by issuing a START con-

dition. A START condition is a high-to-low transition on

SDA with SCL high. A STOP condition is a low-to-high

transition on SDA while SCL is high (Figure 10). A START

condition from the master signals the beginning of a

transmission to the MAX9867. The master terminates

transmission, and frees the bus, by issuing a STOP con-

dition. The bus remains active if a REPEATED START

condition is generated instead of a STOP condition.

SCL

SDA

tRtF

tBUF

START

CONDITION

STOP

CONDITION

REPEATED START CONDITION

START CONDITION

tSU, STO

tHD, STA

tSU, STA

tHD, DAT

tSU, DAT

tLOW

tHIGH

tHD, STA

tSP

Figure 9. 2-Wire Interface Timing Diagram

SCL

SDA

SSrP

Figure 10. START, STOP, and REPEATED START Conditions

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 47

Early STOP Conditions

The MAX9867 recognizes a STOP condition at any

point during data transmission except if the STOP con-

dition occurs in the same high pulse as a START condi-

tion. For proper operation, do not send a STOP

condition during the same SCL high pulse as the

START condition.

Slave Address

The slave address is defined as the 7 most significant

bits (MSBs) followed by the read/write bit. For the

MAX9867, the 7 most significant bits are 0011000.

Setting the read/write bit to 1 (slave address = 0x31)

configures the MAX9867 for read mode. Setting the

read/write bit to 0 (slave address = 0x30) configures

the MAX9867 for write mode. The address is the first

byte of information sent to the MAX9867 after the

START condition.

Acknowledge

The acknowledge bit (ACK) is a clocked 9th bit that the

MAX9867 uses to handshake receipt each byte of data

when in write mode (see Figure 11). The MAX9867 pulls

down SDA during the entire master-generated 9th clock

pulse if the previous byte is successfully received.

Monitoring ACK allows for detection of unsuccessful

data transfers. An unsuccessful data transfer occurs if

a receiving device is busy or if a system fault has

occurred. In the event of an unsuccessful data transfer,

the bus master retries communication. The master pulls

down SDA during the 9th clock cycle to acknowledge

receipt of data when the MAX9867 is in read mode. An

acknowledge is sent by the master after each read byte

to allow data transfer to continue. A not acknowledge is

sent when the master reads the final byte of data from

the MAX9867, followed by a STOP condition.

Write Data Format

A write to the MAX9867 includes transmission of a

START condition, the slave address with the R/Wbit set

to 0, 1 byte of data to configure the internal register

address pointer, 1 or more bytes of data, and a STOP

condition. Figure 12 illustrates the proper frame format

for writing 1 byte of data to the MAX9867. Figure 13

illustrates the frame format for writing n bytes of data to

the MAX9867.

0SLAVE ADDRESS REGISTER ADDRESS DATA BYTE

ACKNOWLEDGE FROM MAX9867

R/W 1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9867

B1 B0B3 B2B5 B4B7 B6

S AA P

Figure 12. Writing 1 Byte of Data to the MAX9867

SCL

START

CONDITION

SDA

CLOCK PULSE FOR

ACKNOWLEDGMENT

ACKNOWLEDGE

NOT ACKNOWLEDGE

Figure 11. Acknowledge

MAX9867

Ultra-Low Power Stereo Audio Codec

48 ______________________________________________________________________________________

The slave address with the R/Wbit set to 0 indicates

that the master intends to write data to the MAX9867.

The MAX9867 acknowledges receipt of the address

byte during the master-generated 9th SCL pulse.

The second byte transmitted from the master config-

ures the MAX9867’s internal register address pointer.

The pointer tells the MAX9867 where to write the next

byte of data. An acknowledge pulse is sent by the

MAX9867 upon receipt of the address pointer data.

The third byte sent to the MAX9867 contains the data

that is written to the chosen register. An acknowledge

pulse from the MAX9867 signals receipt of the data byte.

The address pointer autoincrements to the next register

address after each received data byte. This autoincre-

ment feature allows a master to write to sequential regis-

ters within one continuous frame. Figure 13 illustrates

how to write to multiple registers with one frame. The

master signals the end of transmission by issuing a

STOP condition. Register addresses greater than 0x17

are reserved. Do not write to these addresses.

Read Data Format

Send the slave address with the R/Wbit set to 1 to initi-

ate a read operation. The MAX9867 acknowledges

receipt of its slave address by pulling SDA low during

the 9th SCL clock pulse. A START command followed

by a read command resets the address pointer to reg-

ister 0x00.

The first byte transmitted from the MAX9867 is the con-

tent of register 0x00. Transmitted data is valid on the

rising edge of SCL. The address pointer autoincre-

ments after each read data byte. This autoincrement

feature allows all registers to be read sequentially within

one continuous frame. A STOP condition can be issued

after any number of read data bytes. If a STOP condi-

tion is issued followed by another read operation, the

first data byte to be read is from register 0x00.

The address pointer can be preset to a specific register

before a read command is issued. The master presets

the address pointer by first sending the MAX9867’s

slave address with the R/Wbit set to 0 followed by the

sent followed by the slave address with the R/Wbit set

to 1. The MAX9867 then transmits the contents of the

specified register. The address pointer autoincrements

after transmitting the first byte.

The master acknowledges receipt of each read byte

during the acknowledge clock pulse. The master must

acknowledge all correctly received bytes except the

last byte. The final byte must be followed by a not

acknowledge from the master and then a STOP condi-

tion. Figure 14 illustrates the frame format for reading 1

byte from the MAX9867. Figure 15 illustrates the frame

format for reading multiple bytes from the MAX9867.

1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9867

B1 B0B3 B2B5 B4B7 B6

AA0

ACKNOWLEDGE FROM MAX9867

R/W

1 BYTE

ACKNOWLEDGE FROM MAX9867

B1 B0B3 B2B5 B4B7 B6

SLAVE ADDRESS REGISTER ADDRESS DATA BYTE 1 DATA BYTE n

Figure 13. Writing n Bytes of Data to the MAX9867

ACKNOWLEDGE FROM MAX9867

1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9867

NOT ACKNOWLEDGE FROM MASTER

AAA P

ACKNOWLEDGE FROM MAX9867

R/W

R/WREPEATED START

Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE

Figure 14. Reading 1 Byte of Data from the MAX9867

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 49

ACKNOWLEDGE FROM MAX9867

1 BYTE

AUTOINCREMENT INTERNAL

ACKNOWLEDGE FROM MAX9867

AAA AP

ACKNOWLEDGE FROM MAX9867

R/W

REPEATED START

Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE

Figure 15. Reading n Bytes of Data from the MAX9867

Applications Information

Proper layout and grounding are essential for optimum

performance. When designing a PCB for the MAX9867,

partition the circuitry so that the analog sections of the

MAX9867 are separated from the digital sections. This

ensures that the analog audio traces are not routed

near digital traces.

Use a large continuous ground plane on a dedicated

layer of the PCB to minimize loop areas. Connect

AGND and DGND directly to the ground plane using

the shortest trace length possible. Proper grounding

improves audio performance, minimizes crosstalk

between channels, and prevents any digital noise from

coupling into the analog audio signals.

Ground the bypass capacitors on MICBIAS, REG,

PREG, and REF directly to the ground plane with mini-

mum trace length. Also be sure to minimize the path

length to AGND. Bypass AVDD directly to AGND.

Connect all digital I/O termination to the ground plane

with minimum path length to DGND. Bypass DVDD and

DVDDIO directly to DGND.

Route microphone signals from the microphone to the

MAX9867 as a differential pair, ensuring that the posi-

tive and negative signals follow the same path as close-

ly as possible with equal trace length. When using

single-ended microphones or other single-ended audio

sources, ground the negative microphone input as near

as possible to the audio source and then treat the posi-

tive and negative traces as differential pairs.

The MAX9867 TQFN package features an exposed

thermal pad on its underside. Connect the exposed

thermal pad to AGND.

An evaluation kit (EV Kit) is available to provide an

example layout for the MAX9867. The EV kit allows

quick setup of the MAX9867 and includes easy-to-use

software, allowing all internal registers to be controlled.

MAX9867

Ultra-Low Power Stereo Audio Codec

50 ______________________________________________________________________________________

MIX

VCM PREG

REF

DIGITAL

FILTERING

DIGITAL AUDIO

INTERFACE

LINEAR

REG

CLOCK

GEN

I2C

DIGITAL

FILTERING

ADCL

MXINL

PGAML:

+20dB TO 0dB

PALEN:

0/20/30dB

MICLP/

DIGMICDATA

MICLN/

DIGMICCLK

DACL

LOUTP

LOUTN

MIX

DMONO

MIX

DIGITAL

FILTERING

ADCR

DGND

() WLP PACKAGE

(A2)

PGND

(E5)

AGND

(A6)

MXINR

PGAMR:

+20dB TO 0dB

PAREN:

0/20/30dB

LIGL:

+24dB TO -6dB

AVL:

+3dB TO -12dB

AVR:

+3dB TO -12dB

1µF

0.22µF

2.2kΩ

1µF

(C6)

1µF8

(B5)

2.2µF6

(B4)

MICBIAS

REF

REG

(B6)

(C5)

MICRP

LINL

MICRN

0.22µF

2.2kΩ

(C4)

0.47µF15

(D5)

LIGR:

+24dB TO -6dB

LINR

0.47µF16

(E6)

(D6)

DACG:

0/6/12/18dB

MIX

DSTS

SDOUT

(D1)

(C2)

(C1)

(B1)

BCLK

DVST:

0dB TO -60dB

DACA:

0dB TO -15dB

DACG:

0/6/12/18dB

DACA:

0dB TO -15dB

VOLL:

+6dB TO -84dB

VOLL, LVOLFIX:

+6dB TO -84dB

VOLR, LVOLFIX:

+6dB TO -84dB

DIGITAL

FILTERING DACR

VOLR:

+6dB TO -84dB

MIX

(E3)

(D2)

ROUTP

ROUTN

MIX

JACK

DETECT

(D3)

JACKSNS/

AUX

(D4)

(E4)

SDIN

(B2)

MCLK

TO PROCESSORTO PROCESSOR

SYSTEM

CLOCK

(B3)

SCL

(A3)

SDA

(C3)

IRQ

(E1)

DVDDIO

1.7V–3.6V

LRCLK

1µF

(A1)

DVDD

1.8V

1µF

(E2)

PVDD

1.8V

1µF

(A4)

AVDD

1.8V

1µF

(A5)

PREG

MAX9867

Functional Diagram/Typical Operating Circuit

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 51

THIN QFN

(5mm ×

5mm)

TOP VIEW

SCL

IRQ

AVDD

REF

PREG

DGND

PVDD

LOUTN

ROUTN

N.C.

ROUTP

PGND

SDIN

4567

2324 22 20 19 18

LRCLK

BCLK

MICRN

MICRP

MICLP/DIGMICDATA

MICLN/DIGMICCLK

SDA LOUTP

31 10

MCLK MICBIAS

32 9

DVDD AGND

SDOUT

26 15 LINL

DVDDIO

25 16 LINR

REG JACKSNS/AUX

N.C.

MAX9867

*EP

*EP = EXPOSED PAD

Pin Configurations

TOP VIEW

(BUMP SIDE DOWN)

DGND SDA AVDDDVDD

234

WLP

(2.2mm x 2.7mm)

PREG AGND

MCLK SCL REFBCLK REG MICBIAS

SDIN IRQ MICRPLRCLK MICLN MICLP

LOUTN ROUTP JACKSNSSDOUT LINL MICRN

PVDD LOUTP ROUTNDVDDIO PGND LINR

MAX9867

Ultra-Low Power Stereo Audio Codec

52 ______________________________________________________________________________________

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

30 WLP W302A2+3 21-0211 —

32 TQFN-EP T3255+4 21-0140 90-0121

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the

package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the

package regardless of RoHS status.

MAX9867

Ultra-Low Power Stereo Audio Codec

______________________________________________________________________________________ 53

Package Information (continued)

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the

package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the

package regardless of RoHS status.

QFN THIN.EPS

MAX9867

Ultra-Low Power Stereo Audio Codec

54 ______________________________________________________________________________________

Package Information (continued)

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the

package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the

package regardless of RoHS status.

MAX9867

Ultra-Low Power Stereo Audio Codec

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 4/09 Initial release —

1 5/10 Added lead temperature and soldering temperatures, updated VOS

specification 2, 8

2 6/10 Corrected error in TOC20 15