74HC237 3-to-8 line decoder, demultiplexer with address latches Rev. 6 -- 23 August 2012 Product data sheet 1. General description The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC standard no. 7A. The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus-oriented systems. 2. Features and benefits Combines 3-to-8 decoder with 3-bit latch Multiple input enable for easy expansion or independent controls Active HIGH mutually exclusive outputs Low-power dissipation ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC237N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HC237D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC237DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches 4. Functional diagram 4 LE Y0 15 Y1 14 Y2 13 1 A0 Y3 12 2 A1 INPUT LATCHES 3 A2 3 TO 8 DECODER Y4 11 Y5 10 Y6 9 Y7 7 5 E1 6 E2 001aab871 Fig 1. Functional diagram DX 4 1 C8 1 0 0 8D,G 7 2 3 4 0 3 2 LE 4 Y0 Y1 1 2 3 Y2 A0 A1 INPUT LATCHES A2 Y3 3 TO 8 DECODER Y4 Y5 Y6 Y7 15 5 14 5 13 6 & 6 7 14 13 12 11 10 9 7 12 11 10 X/Y 9 4 7 1 2 3 E1 5 6 2 15 C8 0 8D,1 1 8D,2 2 8D,4 3 4 001aab869 5 E2 5 & 6 6 7 15 14 13 12 11 10 9 7 EN 001aab870 Fig 2. Logic symbol 74HC237 Product data sheet Fig 3. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 2 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches A0 LATCH A0 LE Y0 A0 LE Y1 A1 LATCH A1 LE A1 LE Y2 A2 A2 LATCH LE Y3 A2 LE Y4 LE Y5 Y6 Y7 E1 001aab872 E2 Fig 4. Logic diagram 5. Pinning information 5.1 Pinning 74HC237 A0 1 16 VCC A1 2 15 Y0 A2 3 14 Y1 74HC237 LE 4 E1 5 E2 Y7 GND A0 1 16 VCC A1 2 15 Y0 A2 3 14 Y1 LE 4 13 Y2 E1 5 12 Y3 E2 6 11 Y4 Y7 7 10 Y5 GND 8 13 Y2 12 Y3 6 11 Y4 7 10 Y5 9 8 Y6 Pin configuration DIP16 and SO16 74HC237 Product data sheet Y6 001aan382 001aab868 Fig 5. 9 Fig 6. Pin configuration SSOP16 All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 3 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches 5.2 Pin description Table 2. Pin description Symbol Pin Description A0 to A2 1, 2, 3 data input LE 4 latch enable input (active LOW) E1 5 data enable input 1 (active LOW) E2 6 data enable input 2 (active HIGH) Y0 to Y7 15, 14, 13, 12, 11, 10, 9, 7 output GND 8 ground (0 V) VCC 16 supply voltage 6. Functional description Table 3: Function table Enable Input Output LE E1 E2 A0 A1 A2 Y0 H L H X X X stable X H X X X X L Y1 Y2 Y3 Y4 Y5 Y6 Y7 L L L L L L L X X L X X X L L L L L L L L L L H L L L H L L L L L L L H L L L H L L L L L L L H L L L H L L L L L H H L L L L H L L L L L L H L L L L H L L L H L H L L L L L H L L L H H L L L L L L H L H H H L L L L L L L H [1] H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 25 mA ICC supply current - +50 mA IGND ground current - 50 mA Tstg storage temperature Ptot total power dissipation 74HC237 Product data sheet Conditions VI < 0.5 V or VI > VCC + 0.5 V Min Max Unit 0.5 +7 V - 20 mA 65 +150 C DIP16 package [1] - 750 mW SO16 and SSOP16 packages [2] - 500 mW All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 4 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches [1] [2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 74HC237 Product data sheet Tamb = 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V 3.15 VCC = 6.0 V 4.2 VCC = 2.0 V - VCC = 4.5 V - VCC = 6.0 V Tamb = 40 C to +85 C Tamb = 40 C to Unit +125 C Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 2.4 - 3.15 - 3.15 - V 3.2 - 4.2 - 4.2 - V 0.8 0.5 - 0.5 - 0.5 V 2.1 1.35 - 1.35 - 1.35 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VIH or VIL VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 5 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Min Tamb = 40 C to +85 C Tamb = 40 C to Unit +125 C Typ Max Min Max Min Max II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10. Symbol Parameter tpd propagation delay Tamb = 25 C Conditions Typ Max Min Max Min Max VCC = 2.0 V - 52 160 - 200 - 240 ns VCC = 4.5 V - 19 32 - 40 - 48 ns VCC = 5 V; CL = 15 pF - 16 - - - - - ns VCC = 6.0 V - 15 27 - 34 - 41 ns VCC = 2.0 V - 61 190 - 240 - 285 ns VCC = 4.5 V - 22 38 - 48 - 57 ns VCC = 5 V; CL = 15 pF - 19 - - - - - ns - 18 32 - 41 - 48 ns E1to Yn; see Figure 8 [1] [1] VCC = 2.0 V - 47 145 - 180 - 220 ns VCC = 4.5 V - 17 29 - 36 - 44 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns - 14 25 - 31 - 38 ns VCC = 2.0 V - 47 145 - 180 - 220 ns VCC = 4.5 V - 17 29 - 36 - 44 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns - 14 25 - 31 - 38 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 6.0 V E2 to Yn; see Figure 7 [1] VCC = 6.0 V 74HC237 Product data sheet Unit [1] VCC = 6.0 V transition time Tamb = 40 C to +125 C Min An to Yn; see Figure 7 LE to Yn; see Figure 7 tt Tamb = 40 C to +85 C Yn; see Figure 7 and Figure 8 [2] All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 6 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches Table 7. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10. Symbol Parameter tW pulse width set-up time tsu hold time th Tamb = 25 C Conditions power dissipation capacitance Tamb = 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 50 11 - 65 - 75 - ns VCC = 4.5 V 10 4 - 13 - 15 - ns VCC = 6.0 V 9 3 - 11 - 13 - ns VCC = 2.0 V 50 6 - 65 - 75 - ns VCC = 4.5 V 10 2 - 13 - 15 - ns VCC = 6.0 V 9 2 - 11 - 13 - ns VCC = 2.0 V 30 3 - 40 - 45 - ns VCC = 4.5 V 6 1 - 8 - 9 - ns 5 1 - 7 - 8 - ns - 60 - - - - - pF LE HIGH; see Figure 9 An to LE; see Figure 9 An to LE; see Figure 9 - VCC = 6.0 V CPD Tamb = 40 C to +85 C [3] CL = 50 pF; f = 1 MHz; VI = GND to VCC [1] tpd is the same as tPLH and tPHL. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 11. Waveforms An, E2, LE input VM tPHL Yn output tPLH 90 % 90 % VM 10 % 10 % tTHL tTLH 001aab873 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay input (An) and enable inputs (E2, LE) to output (Yn) and output transition time 74HC237 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 7 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches E1 input VM tPHL tPLH 90 % Yn output 90 % VM 10 % 10 % tTHL tTLH 001aab874 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Propagation enable inputs (E1) to output (Yn) and output transition time VM An input tsu LE input transparant th VM latched th tsu transparant latched tW 001aab875 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Table 8. The data input (An) to latch enable input (LE) set-up times, latch enable input (LE) to data input (An) hold times and latch enable input (LE) pulse width Measurement points Type 74HC237 74HC237 Product data sheet Input Output VM VM 0.5VCC 0.5VCC All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 8 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 10. Test circuit for measuring switching times Table 9. Test data Type Input VI tr, tf CL 74HC237 VCC 6.0 ns 15 pF, 50 pF 74HC237 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 Test tPLH, tPHL (c) NXP B.V. 2012. All rights reserved. 9 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches 12. Application information strobe decoder enable X0 X1 X2 LE A2 A1 A0 237 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 1 2 3 4 5 6 7 input address to five other decoders X3 X4 X5 LE A2 A1 A0 237 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 1 2 3 4 5 6 7 LE A2 A1 A0 237 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 8 9 10 11 12 13 14 15 outputs LE A2 A1 A0 237 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 16 17 18 19 20 21 22 23 outputs outputs 001aab876 Fig 11. 6-to-64 line decoder with input address storage 74HC237 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 10 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 12. Package outline SOT38-4 (DIP16) 74HC237 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 11 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT109-1 (SO16) 74HC237 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 12 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 14. Package outline SOT338-1 (SSOP16) 74HC237 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 13 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC237 v.6 20120823 Product data sheet - 74HC237 v.5 Modifications: 74HC237 v.5 Modifications: * Measurement points added to Figure 7 and Figure 8 (errata). 20111209 * Product data sheet - 74HC237 v.4 Legal pages updated. 74HC237 v.4 20110110 Product data sheet - 74HC237 v.3 74HC237 v.3 20041112 Product data sheet - 74HC_HCT237_CNV v.2 74HC_HCT237_CNV v.2 19970828 Product specification - 74HC_HCT237 v.1 74HC_HCT237 v.1 19901201 Product specification - - 74HC237 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 14 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74HC237 Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 15 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC237 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 23 August 2012 (c) NXP B.V. 2012. All rights reserved. 16 of 17 74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 August 2012 Document identifier: 74HC237