Package Thermal Considerations - Texas Instruments

Package Thermal Considerations

SCZA002C

June 1994 – Revised August 1996

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iii

Contents

Title Page

Abstract 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reliability 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Consumption 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Calculations 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMOS 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BiCMOS/Bipolar 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Thermal-Resistance Values 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Summary 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

References 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

1 Advanced Packages 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC Versus Frequency (One Switching, Unused Outputs Low) 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC Versus Frequency (All Outputs Switching) 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC Versus Frequency (All Switching, 50% Duty Cycle Enabled) 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC Versus Duty Cycle Enabled (25 MHz) 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 48-Pin SSOP ΘJA Versus Trace Length 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 48-Pin SSOP ΘJA Versus Air Flow 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 48/56-Pin SSOP K-Factor Board Modeling 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Abstract

Smaller packages with more functionality have greater power densities that increase junction temperatures, thereby adversely

affecting device and system reliability. Good thermal-design practices, both package and application specific, can lower the

junction temperature. Altering power consumption, trace length, heatsinks, air flow, and package design can mitigate effects of

greater power density. Formulas for calculating power consumption must account for static and dynamic currents. Although no

industry standard exists for calculating thermal resistance (ΘJA), variations in values among manufacturers of identical packages

can be attributed to physical aspects of board design rather than measurement methodology. Software has been developed that

calculates realistic values for ΘJA, taking into account significant conditions.

Introduction

To meet current and future system requirements of increasing speed and decreasing size, integrated-circuit manufacturers are

pushing the edge on existing packaging technology. A component’s performance is determined by process technology and the

thermal limitations of its package. As a leader in package technology, Texas Instruments (TI) has introduced a number of

fine-pitch packages and is acutely aware of the thermal considerations that must be examined by systems designers. This paper

is intended to create awareness and understanding of thermal issues and to explore factors that influence thermal performance.

Thermal awareness became an industry concern when surface-mount (SMT) packages began replacing through-hole (DIP)

packages in PCB designs. Circuits operating at the same VCC enclosed in a smaller package meant higher power consumption.

To add to the issue, systems required increased throughput, which resulted in higher frequencies, increasing the power density

even further. Not only are designers faced by these same concerns today, they progressively are becoming more severe.

Figure 1 shows part of the reason for increased attention to thermal issues. As a baseline for comparison, the 24-pin small-outline

integrated circuit (SOIC) is shown along with several fine-pitch packages supplied by TI, including the 24-pin SSOP (shrink small

outline), 48-pin SSOP , and the 100-pin TQFP (thin quad flat pack). The 24-pin SSOP (8, 9, and 10 bits) allows for the same circuit

functionality of the 24-pin SOIC to be packaged in less than half the area, while the 48-pin SSOP (16, 18, and 20 bits) occupies

just slightly more area but has twice the functionality of the 24-pin SOIC. This same phenomenon is expanded even further with

the 100-pin TQFP (32 and 36 bits), which is the functional equivalent of four 24-pin or two 48-pin devices, with additional board

savings over that of the SSOP packages. As the trend toward smaller packages continues, attention must be focused on the thermal

issues that are created.

24-Pin SOIC

Area = 165 mm2

24-Pin SOIC

Height = 2.65 mm

Volume = 437 mm3

Lead Pitch = 1.27 mm

48-Pin SSOP

Height = 2.74 mm

Volume = 469 mm3

Lead Pitch = 0.635 mm

48-Pin SSOP

Area = 171 mm2

24-Pin SSOP

Area = 70 mm2

Height = 2 mm

Volume = 140 mm3

Lead Pitch = 0.65 mm

24-Pin SSOP

100-Pin TQFP and

100-Pin Cavity TQFP

Area = 262 mm2

100-Pin TQFP

Height = 1.6 mm

Volume = 419 mm3

Lead Pitch = 0.5 mm

Figure 1. Advanced Packages

Reliability

The overriding effect of increased power densities in integrated circuits is a decrease in overall system reliability. A direct

relationship exists between junction temperature and reliability.

T able 1 provides an example of a device with an initial junction temperature of 150 °C and the calculated decrease in failure rate

as the in-use junction temperature is lowered. The data in Table 1 indicates that lower junction temperature results in increased

system reliability.

Table 1. Failure Rate Versus Junction Temperature

TEMPERATURE

°C% FR†

150 96

140 80

130 46

120 11

110 1

100 0.02

†Failure rate at 100,000 hours

A better understanding of the factors that contribute to junction temperature (TJ) provides a system designer with more flexibility

when attempting to solve thermal issues. Device junction temperature is determined by equation 1:

)

(

PT)

Where:

TJ= junction (die) temperature (°C)

TA= ambient temperature (°C)

ΘJA = thermal resistance of the package from the junction to the ambient (°C/W)

PT= total power of the device (W)

Junction temperature can be altered by lower chip power consumption, longer trace length, heatsinks, forced air flow, package

mold compound, lead-frame size and material, surface area, and die size. Some of these are mechanically inherent to a particular

package while others are controlled by the designer and are application specific. Understanding which variables can be influenced

by practicing good thermal-design techniques requires a more detailed investigation of power considerations as well as

thermal-resistance measurements.

Power Consumption

One way to lower the junction temperature of a device, thus improving reliability , is to lower the power consumption. A variety

of options are available to help achieve this, such as low-power process technologies, reduced output swing, and reduced

power-supply voltage. A closer look at the power performance and advantages of several popular logic families can assist in

choosing devices that best fit designers’ needs.

The choices available from TI for high-speed bus interfaces range from standard bipolar (F) to advanced CMOS (ACL/ACT)

to state-of-the-art BiCMOS (BCT) and advanced BiCMOS (ABT). Figures 2 through 4 show comparisons of current (ICC)

consumption of ’244 functions for these technologies across frequency. As expected, the bipolar device consumes more current

than the CMOS device at lower frequencies, but as frequency increases, this relationship no longer holds true. In fact, there is

a region in the frequency range where the CMOS device consumes more current than the bipolar device. The point where they

are equal is referred to as the crossover frequency.

(1)

0 102030405060708090100

Frequency – MHz

ACT

ABT

BCT

I– mA

Figure 2. ICC Versus Frequency (One Switching, Unused Outputs Low)

100

120

140

160

180

0 102030405060708090100

Frequency – MHz

ABT

BCT

ACT

I– mA

Figure 3. ICC Versus Frequency (All Outputs Switching)

100

0 102030405060708090100

Frequency – MHz

ACT

ABT

BCT

I– mA

Figure 4. ICC Versus Frequency (All Switching, 50% Duty Cycle Enabled)

T ypical applications for bus-interface devices require them to be disabled or in the standby mode during certain periods of time,

for instance, while other devices access the bus. This can result in a large decrease in current consumption for ABT, BCT, and

ACT devices, which have low standby currents. These values are given in the data sheets as ICC for ACT and ICCZ for ABT

(250 µA) and BCT (≅10 mA). Current consumption versus percent duty cycle enabled is shown in Figure 5. The frequency of

the data is held constant at 25 MHz and all outputs are switching.

0 102030405060708090100

Duty Cycle Enabled – %

ACT

ABT

BCT

I– mA

Figure 5. ICC Versus Duty Cycle Enabled (25 MHz)

Using this data, along with standard formulas, power consumption can be calculated for specific applications.

Power Calculations

When calculating the total power consumption of a circuit, both the static and the dynamic currents must be taken into account.

Both bipolar and BiCMOS devices have varying static-current levels, depending on the state of the output (ICCL, ICCH, or ICCZ),

while a CMOS device has a single value for ICC. These values can be found in the individual data sheets. ACT and ABT inputs,

when driven at TTL levels, also consume additional current because they may not be driven all the way to VCC or GND; therefore,

the input transistors are not completely turned off. This value is known as ∆ICC and is provided in the data sheet.

Dynamic power consumption results from charging and discharging of both internal parasitic capacitances and external load

capacitance. The parameter for ACT and AC devices that accounts for the parasitic capacitances is known as Cpd. It is obtained

using equation 2 and is found in the data sheet.

Cpd

+ƪ

ICC (dynamic)

VCC

ƫ*

Where:

fi= input frequency (Hz)

VCC = supply voltage (V)

CL= load capacitance (F)

ICC = measured value of current into the device

Although a Cpd value is not provided for ABT, BCT , or F devices, the ICC versus frequency curves display essentially the same

information. The slope of the curve provides a value in the form of mA/(MHz × bit), which when multiplied by the number of

outputs switching and the desired frequency, provides the dynamic power dissipated by the device without the load current.

Equations 3 through 7 can be used to calculate total power for CMOS, bipolar, and BiCMOS devices:

PS(static)

)

PD(dynamic)

(2)

(3)

CMOS

AC (CMOS-level inputs)

+ƪǒ

Cpd

Ǔ)

(CL

fo)

VCC2

NSW

VCC

ICC

ACT (TTL-level inputs)

+ƪǒ

Cpd

Ǔ)

(CL

fo)

VCC2

NSW

VCC[ICC

)

(NTTL

ICC

DCd)]

BiCMOS/Bipolar

VCC

DCen

ICCH

)

ICCL

Ǔ)

DCen)ICCZ

)

(NTTL

ICC

DCd)

Note: ∆ICC = 0 for bipolar devices

[DCen

Nsw

VCC

(VOH

VOL)

CL]

)ƪ

DCen

Nsw

VCC

MHz

bit

Ǔƫ

Where:

VCC = Supply voltage (V)

ICC = Power-supply current (A) (from the data sheet)

ICCL = Power-supply current (A) when outputs are in low state (from the data sheet)

ICCH = Power-supply current (A) when outputs are in high state (from the data sheet)

ICCZ = Power -supply current (A) when outputs are in high-impedance state (from the data sheet)

∆ICC = Power-supply current (A) when inputs are at a TTL level (from the data sheet)

DCen = % duty cycle enabled (50% = 0.5)

DCd= % duty cycle of the data (50% = 0.5)

NH= Number of outputs in high state

NL= Number of outputs in low state

Nsw = Total number of outputs switching

NT= Total number of outputs

fi= Input frequency (Hz)

fo= Output frequency (Hz)

f1= Operating frequency (Hz)

f2= Operating frequency (MHz)

VOH = Output voltage (V) in high state

VOL = Output voltage (V) in low state

CL= External load capacitance (F)

mA/(MHz × bit) = Slope of the ICC versus frequency curve

Thermal-Resistance Values

Design trends requiring board size reduction have made way for circuit manufacturers to produce fine-pitch packages that appear

to threaten the reliability of systems due to further thermal constraints. As a leader in packaging technology, TI has done

considerable research into the validity of traditional thermal measurements and data provided by circuit manufacturers.

(4)

(5)

(6)

(7)

Unlike data-sheet parameters, where the industry has adopted a standard load for measurement (50 pF , 500 Ω), the measurement

of ΘJA has no standard to which all manufacturers comply. The problem facing the designer wishing to make comparisons of

thermal data from several manufacturers is that this could be an apples-to-oranges type comparison. As a result, a software

package has been developed at TI to allow designers to obtain thermal data based on their specific application.

The validity and usefulness of the traditional approach to presenting ΘJA values became a pressing issue when TI and another

manufacturer measured an identical package and obtained results that varied by 40%. Extensive research led to the conclusion

that the methodology used to measure ΘJA did not cause the discrepancy but the physical aspects such as trace length, trace width,

number of devices per board, and proximity of the other devices did.

To demonstrate the extreme impact of trace length alone, Figure 6 shows the ΘJA values for TI’s 48-pin SSOP at 0 LFMP and

250 LFMP with varying trace lengths. The 48-pin SSOP is shown in Figure 1 for a side-by-side comparison with the standard

24-pin SOIC, the 24-pin SSOP, and the 100-pin TQFP. The data in Figure 6 clearly shows the need for more complete thermal

data, not simply a single data point.

110

130

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Trace Length – In

ΘC/W

JA_

0 LFPM

250 LFPM

Figure 6. 48-Pin SSOP ΘJA Versus Trace Length

There are other methods to lower the ΘJA of a device. Using heatsinks or blowing air across a device certainly improves the ability

to remove heat from its surface. Figure 7 provides ΘJA data for the 48-pin SSOP with trace lengths of 200 mils and 1 inch while

varying the amount of air flow. Although many applications tend to limit the amount of air flow, excellent benefits are possible

with increased air flow.

100

120

0 50 100 150 200 250 300 350 400 450 500

Air Flow – LFPM

ΘC/W

JA_

1000 Mils

200 Mils

Figure 7. 48-Pin SSOP ΘJA Versus Air Flow

Several variables that have a direct effect on ΘJA values were compared and results are shown in Figure 8. Surprisingly , the major

contributing factor is trace length, not air flow. Once again, this validates the need for improvement, not necessarily in the test

methodology used to calculate ΘJA values, but certainly in the way those values are provided.

ÄÄÄ

ÇÇ

ÍÍÍ

ÀÀÀÀ

ÁÁÁÁ

Trace Length

Air Flow

Board Extension

T race Thickness

Trace Width

Power

Total Interactions Between Factors

75 mils – 2000 mils

0 LFM – 500 LFM

0 mils – 400 mils

0 mils – 755 mils

1 oz – 2 oz

3 mils – 15 mils

0.5 W – 1.5 W

VARIABLE

41.4

28.8

6.5

2.6

2.2

2.1

0.1

16.3

% CONTRIBUTION

RANGE

ÄÄÄ

ÇÇÇ

ÍÍÍ

ÀÀÀ

ÁÁÁ

After Trace

After Package End

Figure 8. 48-/56-Pin SSOP K-Factor Board Modeling

TI provides ΘJA values for a variety of packages (including the SOIC, SSOP, and QSOP) in a user-friendly software package.

The program allows designers to specify their conditions, such as trace length, air flow, proximity of other devices, and trace width

in order to obtain realistic thermal solutions.

Summary

Adverse effects of increased power densities can be offset by decreasing the in-use junction temperatures of devices and by good

thermal design practices.

Power consumption, which increases with greater functionality and higher operating frequencies, can be held to acceptable levels

by careful selection of the logic family and duty cycle. When calculating power consumption, which varies among logic families,

both static and dynamic currents must be taken into account.

Thermal resistance values vary widely among circuit manufacturers. Although there is no industry standard for measuring this

parameter, variations in results are attributable to physical aspects of the circuit board rather than testing methodology. TI

provides software to aid designers in obtaining realistic solutions for their applications.

References

Thermal Software

Contact the factory at (903) 868-7682.

Power Dissipation

Advanced CMOS Logic Designer’s Handbook, 1988, Texas Instruments Incorporated, literature number SCAA001B

SSOP Designer’s Handbook, 1991, Texas Instruments Incorporated, literature number SCYA001