Intel® Celeron™ Processor up to
850 MHz Datasheet
The Intel® Celeron™ processor is designed for uni-processor based Value PC desktops and is
binary compatible with previous generation Intel architecture processors. The Intel® Ce leron
processor provides good performance for applications running on advanced operating systems
such as Windows* 98/ME, Windows* NT, and UNIX*. This is achieved by integrating the best
attributes of Intel processors—the dynamic execution performance of the P6 microarchitecture
plus the capabilities of MMX™ tech nolo gy—bringing a balanced level of performance to the
Value PC market segment. The Intel® Celeron processor offers the dependability you would
expect from Intel at an exceptional value. Systems based on Intel® Celeron processors also
include the latest features to simplify system management and lower the cost of ownership for
small business and home environments.
■Available at 850 MHz, 800 MHz, 766 MHz,
733 MHz, 700 MHz, 667 MHz, 633 MHz,
600 MHz, 566 MHz, 533 MHz, 533A MHz,
500 MHz, 466 MHz, 433 MHz, 400 MHz,
366 MHz, 333 MHz, and 300A MHz core
frequencies with 128 KB level-two cache
(on die); 300 MHz and 266 MHz core
frequencies without level-two cache.
■Intel’s latest Celeron™ processors in the
FC-PGA package are manufactured using
the adv a nced 0.18 micron technology.
■Binary compatible with applications running
on previous members of the Intel
microprocessor line.
■Dynamic execution microarchitecture.
■Operates on a 66/100 MHz, transaction-
oriented system bus.
■Specifically designed for uni-processor
based Value PC system s, with the
capabilities of MMX™ technology.
■Power Management capabilities.
■Optimized for 32-bit applications running on
advanced 32-bit operating systems.
■Uses cost-ef f ective packaging technology.
—Single Edge Processor (S.E.P.) Package
to maintain compatibility with SC242
(processor core frequencies (MHz):
266, 300, 300A, 333, 366, 400, 433).
—Plas tic Pin Grid Array (PPGA) Package
(processor core frequencies (MHz):
300A, 3 33, 366 , 400, 433 , 466, 50 0, 533) .
—Flip-Chip Pin Grid Array (FC-PGA)
Package (processor core frequencies
(MHz): 533A, 566, 600, 633, 667, 700,
733, 766, 800, 850)
■Integrated high performance 32 KB
instruction and data, nonblocking, level-one
cache: separate 16 KB instruction and
16 KB data caches.
■Integrated thermal diode.
S.E.P. PackagePPGA Package FC-PGA Package
Order Number: 243658-017
April 2001
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructuions marked “reserved“ or “undefined“. Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or imcompatibilities arising from future changes to them.
The Intel Celeron™ processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifcations. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1996, 1997, 1998, 1999, 2000, 2001.
*Third-party brands and names are the property of their respective owners.
Datasheet 3
Intel® Ce leron™ Processor up to 850 MHz
Contents
1.0 Introduction.........................................................................................................................9
1.1 Terminology...........................................................................................................9
1.1.1 Package Terminology.............................................................................10
1.1.2 Processor Naming Convention...............................................................11
1.2 References..........................................................................................................12
2.0 Electrical Specifications....................................................................................................13
2.1 System Bus and Vref...........................................................................................13
2.2 Clock Control and Low Power States..................................................................13
2.2.1 Normal State—State 1 ...........................................................................14
2.2.2 AutoHALT Power Down State—State 2.................................................14
2.2.3 Stop-Grant State—State 3 .....................................................................15
2.2.4 HALT/Grant Snoop State—State 4 ........................................................15
2.2.5 Sleep State—State 5..............................................................................15
2.2.6 Deep Sleep State—State 6 ....................................................................16
2.2.7 Clock Control.. ....... .......................................................... ...... ....... ...... ....16
2.3 Power and Ground Pins......................................................................................16
2.3.1 Phase Lock Loop (PLL) Power...............................................................17
2.4 Processor Decoupling.........................................................................................17
2.4.1 System Bus AGTL+ Decoupling.............................................................17
2.5 Voltage Identification...........................................................................................18
2.6 System Bus Unused Pins....................................................................................19
2.7 Processor System Bus Signal Groups................................................................19
2.7.1 Asynchronous Vs. Synchronous for System Bus Signals......................21
2.7.2 System Bus Frequency Select Signal (BSEL[1:0]).................................21
2.8 Test Access Port (TAP) Connection....................................................................21
2.9 Maximum Ratings................................................................................................21
2.10 Processor DC Specifications...............................................................................22
2.11 AGTL+ System Bus Specifications .....................................................................29
2.12 System Bus AC Specifications............................................................................30
3.0 System Bus Signal Simulations........................................................................................45
3.1 System Bus Clock (BCLK) Signal Quality Specifications and
Measurement Guidelines ....................................................................................45
3.2 AGTL+ Signal Quality Specifications and Measurement Guidelines ..................48
3.3 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........50
3.3.1 Overshoot/Undershoot Guidelines .........................................................50
3.3.2 Ringback Specification...........................................................................51
3.3.3 Settling Limit Guideline...........................................................................52
3.4 AGTL+ Signal Quality Specifications and Measurement
Guidelines (FC-PGA Package) ...........................................................................52
3.4.1 Overshoot/Undershoot Guidelines (FC-PGA Package) .........................52
3.4.2 Overshoot/Undershoot Magnitude (FC-PGA Package) .........................52
3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA Package)...................53
3.4.4 Activity Factor (FC-PGA Package).........................................................53
Intel® Celeron™ Processor up to 850 MHz
4 Datasheet
3.4.5 Reading Overshoot/Undershoot Specification
Tables (FC-PGA Packa ge).... ...... ....................................... ...... ....... ...... .54
3.4.6 Determining if a System meets the Overshoot/Undershoot
Specifications (FC-PGA Package).........................................................55
4.0 Thermal Specifications and Design Considerations.........................................................57
4.1 Thermal Specifications........................................................................................57
4.1.1 Thermal Diode........................................................................................59
5.0 Mechanical Specifications................................................................................................61
5.1 S.E.P. Package...................................................................................................61
5.1.1 Materials Information..............................................................................61
5.1.2 Signal Listing (S.E.P. Package) ............................................................62
5.2 PPGA Package...................................................................................................71
5.2.1 PPGA Package Materials Information....................................................71
5.2.2 PPGA Package Signal Listing................................................................73
5.3 FC-PGA Package................................................................................................84
5.3.1 Materials Information..............................................................................84
5.3.2 Proces sor Mark ing s ....... ....... ...... ................... ....... ...... ....... ...... ....... ...... .86
5.4 FC-PGA Signal List.............................................................................................87
5.5 Heat Sink Volum etr ic Keep out Zone Gu id elines................ ................... ....... ...... .98
6.0 Boxed Processor Specifications.......................................................................................99
6.1 Mechanical Specifications for the Boxed Intel® Celeron™ Processor ................99
6.1.1 Mechanical Specifications for the S.E.P. Package.................................99
6.1.1.1 Boxed Processor Heatsink Weight..........................................101
6.1.1.2 Boxed Processor Retention Mechanism.................................101
6.1.2 Mechanical Specifications for the PPGA Package...............................102
6.1.2.1 Boxed Processor Heatsink Dimensions..................................104
6.1.2.2 Boxed Processor Heatsink Weight..........................................104
6.1.3 Mechanical Specifications for the FC-PGA Package...........................104
6.1.3.1 Boxed Processor Heatsink Weight..........................................106
6.2 Thermal Specifications......................................................................................106
6.2.1 Thermal Requirements for the Boxed Intel® Celeron™ Processor......106
6.2.1.1 Boxed Processor Cooling Requirements ................................106
6.2.1.2 Boxed Processor Thermal Cooling Solution Clip ....................107
6.3 Electrical Requirements for the Boxed Intel® Celeron™ Processor..................108
6.3.1 Electrical Requirements .......................................................................108
7.0 Intel® Celeron™ Processor Signal Description..............................................................111
7.1 Signal Summaries.............................................................................................117
Datasheet 5
Intel® Celeron™ Processor up to 850 MHz
Figures 1 Clock Control State Machine...............................................................................14
2 BCLK to Core Logic Offset..................................................................................41
3 BCLK*, PICCLK, and TCK Generic Clock Waveform .........................................41
4 System Bus Valid Delay Timings ........................................................................42
5 System Bus Setup and Hold Timings..................................................................42
6 System Bus Reset and Configuration Timings
(For the S.E.P. and PPGA Packages).................................................................42
7 System Bus Reset and Configuration Timings (For the FC-PGA Package) .......43
8 Power-On Reset and Configuration Timings.......................................................43
9 Test Timings (TAP Connection) ..........................................................................44
10 Test Reset Timings .............................................................................................44
11 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins .....46
12 BCLK, TCK, PICCLK Generic Clock Waveform at the
Processor Edge Fingers......................................................................................47
13 Low to High AGTL+ Receiver Ringback Tolerance.............................................49
14 Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback .....................50
15 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
(FC-PGA Package) .............................................................................................56
16 Processor Functional Die Layout (CPUID 0686h)...............................................59
17 Processor Functional Die Layout (up to CPUID 0683h)......................................59
18 Processor Substrate Dimensions (S.E.P. Package) ...........................................62
19 Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)....62
20 Package Dimensions (PPGA Package)..............................................................71
21 PPGA Package (Pin Side View)..........................................................................73
22 Package Dimensions (FC-PGA Package)...........................................................84
23 Top Side Processor Markings (PPGA and FC-PGA Packages) .........................86
24 Package Dimensions (FC-PGA Package)...........................................................87
25 Retention Mechanism for the Boxed Intel® Celeron™
Processor in the S.E.P. Package......................................................................100
26 Side View Space Requirements for the Boxed Processor
in the S.E.P. Package .......................................................................................100
27 Front View Space Requirements for the Boxed Processor
the S.E.P. Package...........................................................................................101
28 Boxed Intel® Celeron™ Processor in the PPGA Package................................102
29 Side View Space Requirements for the Boxed Processor
in the PPGA Package........................................................................................102
30 Top View Space Requirements for the Boxed Processor in
the FC-PGA and PPGA Packages....................................................................103
31 Side View Space Requirements for the Boxed Processor
in the FC-PGA and PPGA Packages ................................................................103
32 Boxed Intel® Celeron™ processor in the 370-pin socket (FC-PGA Package) ..105
33 Dimensions of Notches in Heatsink Base .........................................................105
34 Dimensions of Mechanical Step Feature in Heatsink
Base for the FC-PGA Package .........................................................................106
35 Top View Airspace Requirements for the Boxed Processor
in the S.E.P. Package .......................................................................................107
36 Side View Airspace Requirements for the Boxed Intel® Celeron™
Processor in the FC-PGA and PPGA packages ...............................................107
37 Clip Keepout Requirements for the 370-Pin (Top View) ...................................108
38 Boxed Processor Fan Heatsink Power Cable Connector Description...............109
39 Motherboard Power Header Placement for the S.E.P. Package.......................109
40 Motherboard Power Header Placement Relative to the 370-pin Socket...........110
Intel® Celeron™ Processor up to 850 MHz
6 Datasheet
Tables 1 Proces sor Iden tific atio n.. ....... ...... ....... ...... ...... ....... ....................................... ...... .11
2 Voltage Identification Definition ..........................................................................18
3 Intel® Celeron™ Processor System Bus Signal Groups.....................................20
4 Absolute Maximum Ratings ...............................................................................22
5 Voltage and Current Specifications ....................................................................23
6 AGTL+ Signal Groups DC Specifications ...........................................................28
7 Non-AGTL+ Signal Group DC Specifications .....................................................29
8 P roc esso r AGTL+ Bus Speci ficat ion s ........... ....... ................... ....... ...... ....... ...... .30
9 System Bus AC Specifications (Clock) at the Processor
Edge Fingers (for S.E.P. Package) ....................................................................31
10 System Bus AC Specifications (Clock) at the Processor
Core Pins (for Both S.E.P. and PGA Packages) ................................................32
11 Valid I ntel® Celeron™ Processor System Bus, Core Frequency .......................33
12 System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Edge Fingers (for S.E.P. Package)....................................................33
13 System Bus AC Specifications (AGTL+ Signal Group) at
the Processor Core Pins (for S.E.P. Package) ..................................................34
14 Processor System Bus AC Specifications (AGTL+ Signal Group)
at the Processor Core Pins (for PPGA Package) ...............................................34
15 System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Core Pins (for FC-PGA Package)......................................................35
16 System Bus AC Specifications (CMOS Signal Group) at the
Processor Edge Fingers (for S.E.P. Package) ...................................................35
17 System Bus AC Specifications (CMOS Signal Group) at
the Processor Core Pins (for Both S.E.P. and PGA Packages) .........................36
18 System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages) ..............................................................36
19 System Bus AC Specifications (Reset Conditions)
(for the FC-PGA Package) .................................................................................37
20 System Bus AC Specifications (APIC Clock and APIC I/O)
at the Processor Edge Fingers (for S.E.P. Package) .........................................37
21 System Bus AC Specifications (APIC Clock and APIC I/O)
at the Processor Core Pins (For S.E.P. and PGA Packages) ............................38
22 System Bus AC Specifications (TAP Connection) at the
Processor Edge Fingers (For S.E.P. Package) ..................................................39
23 System Bus AC Specifications (TAP Connection) at the
Processor Core Pins (for Both S.E.P. and PPGA Packages) ............................40
24 BCLK Signal Quality Specifications for Simulation at the Processor Core
(for Both S.E.P. and PPGA Packages)...............................................................45
25 BCLK/PICCLK Signal Quality Specifications for Simulation
at the Processor Pins (for the FC-PGA Package) ..............................................46
26 BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package) ....................................................................................47
27 AGTL+ Signal Groups Ringback Tolerance Specifications at the
Processor Core (For Both the S.E.P. and PPGA Packages)..............................48
28 AGTL+ Signal Groups Ringback Tolerance Specifications at
the Processor Pins (For FC-PGA Packages) .....................................................48
29 AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger
Measurement on the S.E.P. Package ................................................................49
Datasheet 7
Intel® Celeron™ Processor up to 850 MHz
30 Signal Ringback Specifications for Non-AGTL+ Signal Simulation
at the Processor Core (S.E.P. and PPGA Packages) ........................................51
31 Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger
Measurement (S.E.P. Package) .........................................................................51
32 Signal Ringback Specifications for Non-AGTL+ Signal Simulation
at the Processor Pins (FC-PGA Package) .........................................................51
33 Example Platform Information.............................................................................54
34 66 MHz AGTL+ Signal Group Overshoot/Undershoot
Tolerance at Processor Pins (FC-PGA Package) ..............................................55
35 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance
at Processor Pins (FC-PGA Package) ...............................................................56
36 Processor Power for the S.E.P. Package............................................................57
37 Processor Power for the PPGA and FC-PGA Packages ....................................58
38 Thermal Diode Parameters (S.E.P. and PPGA Packages).................................60
39 Thermal Diode Parameters (FC-PGA Package) ................................................60
40 Thermal Diode Interface......................................................................................60
41 S.E.P. Package Signal Listing by Pin Number....................................................63
42 S.E.P. Package Signal Listing by Signal Name ..................................................67
43 Package Dimensions (PPGA Package)..............................................................72
44 Information Summary (PPGA Package)..............................................................72
45 PPGA Package Signal Listing by Pin Number....................................................74
46 PPGA Package Signal Listing in Order by Signal Name.....................................79
47 Package Dimensions...........................................................................................85
48 Processor Die Loading Parameters (FC-PGA Package) ....................................85
49 FC-PGA Signal Listing in Order by Signal Name................................................88
50 FC-PGA Signal Listing in Order by Pin Number..................................................94
51 Boxed Processor Fan Heatsink Spatial Dimensions for
the S.E.P. Package...........................................................................................101
52 Boxed Processor Fan Heatsink Spatial Dimensions for the
PPGA and FC-PGA Packages .........................................................................104
53 Fan Heatsink Power and Signal Specifications.................................................109
54 Alphabetical Signal Reference ..........................................................................111
55 Output Signals...................................................................................................117
56 Input Signa ls.......... ...... ....... ...... ....... ...... ...... ....... ....................................... ...... ..117
57 Input/Output Signals (Single Driver)..................................................................118
58 Input/Output Signals (Multiple Driver) ...............................................................118
Intel® Celeron™ Processor up to 850 MHz
8 Datasheet
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Datasheet 9
Intel® Celeron™ Processor up to 850 MHz
1.0 Introduction
The Intel® Celeron™ processo r is based on the P6 microarchitecture and is optimized for the Value
PC market segment. The Intel C eleron pro cessor, like the Intel® Pentium® II processor, features a
Dynamic Execution microarchitecture and executes MMX technology instructions for enhanced
media and communication performance. The Intel Celeron processor also utilizes multiple low-
power states such as AutoHALT, Stop-Grant , Sleep, and Deep Sleep to conserve power during idle
times.
The Intel Celer on processor is capable of runnin g today’s most common PC applications with up to
4 GB of cacheable memory space. As this processor is intended for Value PC systems, it does not
provide multiprocessor support. The Pentium II and Pentium® III processors should be used for
multiprocessor system designs.
To be cost-effective at both the processor and system level, the Intel Celeron processor utilizes
cost-effective packaging technologies. They are the S.E.P. (Single-Edge Processor) package, the
PPGA (Plastic Pin Grid Array) package, and the FC-PGA (Flip-Chip Pin Grid Array) package.
Refer to the Intel® Celeron™ Processor Specification Update for the latest packaging and
frequency support information (Order Number 243337).
Note: This datasheet describes the Intel Celeron proces sor for the PPGA package, FC-PGA package, and
the S.E.P. Package versions. Unless otherwise specified, the information in this document applies
to all versions and information on PGA packages, refer to both PPGA and FC-PGA packages.
1.1 Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable
interrupt has occurred. In the case of signals where the name does not imply an active state but
describes par t of a b inary seq uence (such as address or data), the ‘#’ symbol implies that the signal
is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also ref ers t o
a hex ‘A’ (H= High logic level, L= Low logic level).
The term “system bus” refers to the interface between the processor, system core logic (a.k.a. the
AGPset components), and other bus agents. The system bus is an interface to the processor,
memory, and I/O.
10 Datasheet
Intel® Celeron™ Processor up to 850 MHz
1.1.1 Package Terminology
The following terms are used often in this document and are explained here for clarification:
•Processor substrate—The structure on which passive components (resistors and capacitors)
are mounted.
•Processor core—The pro cessor’s execution engine.
•S.E.P. Package—Single-Edge Processor Package, which consists of a processor substrate,
processor core, and passive comp onents. This pack age differs from the S.E.C . Cartridge as this
processor has no external plastic cover, thermal plate, or latch arms.
•PPGA package—Plastic Pin Grid Array package. The package is a pinned laminated printed
circuit board structure.
•FC-PGA - F lip -Ch i p Pi n Grid Arr ay. The FC-PG A us es t he s ame 3 70 -pi n zero insert ion force
socket (PGA370) as the PPGA. Thermal solutions are attached directly to the back of the
processor core package without the use of a thermal plate or heat spreader.
•Keep-out zone - The area on or near a FC-PGA packaged processor that system designs can
not utilize.
•Keep-in zone - The area of a FC-PGA packaged processor that thermal solutions may utilize.
Additional terms referred to in this and other related documentati on:
•SC242—242-contact slot connector. A processor in the S.E.P. Package uses this connector to
interface with a system board.
•370-pin socket (PGA370)—The zero insertion force (ZIF) socket in which a processor in the
PPGA package will use to interface with a system board.
•Retention m echanism—A mechanical assembly which holds the package in the SC242
connector.
Datasheet 11
Intel® Celeron™ Processor up to 850 MHz
1.1.2 Processor Naming Convention
A letter(s) is added to certain proces sors (e.g ., 5 33A MHz) when the core freq uency alon e may no t
uniquely identify the processor. Below is a summary of what each letter means as well as a table
listing all the FC-PGA processors for the PGA370 socket.
NOTES:
1. Refer to the Celeron™ Processor Spec ification Update for the exact CPUID for each processor.
Table 1. Processor Identification
Processor Core Frequency (MHz) System Bus Frequency
(MHz) CPUID1
266 266 66 065xh
300 300 66 065xh
300A 300 66 066xh
366 366 66 066xh
400 400 66 066xh
433 433 66 066xh
466 466 66 066xh
500 500 66 066xh
533 533 66 066xh
533A 533 66 068xh
566 566 66 068xh
600 600 66 068xh
633 633 66 068xh
667 667 66 068xh
700 700 66 068xh
733 733 66 068xh
766 766 66 068xh
800 800 100 068xh
850 850 100 068xh
12 Datasheet
Intel® Celeron™ Processor up to 850 MHz
1.2 References1,2
The reader of this specification should also be familiar with material and concepts presented in the
following documents:
•AP-485, Intel® Processor Identification and the CPUID Instruction (Order Number 241618)1
•AP-589, Design for EMI (Order Number 243334)1
•AP-900, Identifying Support for Streaming SIMD Extensions in the Processor and Operating
System1
•AP-905, Intel® Pentium® III Processor Thermal Design Guidelines1
•AP-907, Intel® Pentium® III Processor Power Distribution Guidelines1
•Intel® Pentium® III Processor for the PGA370 Socket at 500 MHz to 933 MHz Datasheet
(Order Number 245264)
•Intel® Pentium® III Processor Thermal Metrology for CPUID 068h Family1
•Intel® Pentium® III Processor Software Application Development Application Notes1
•Intel® Celero n™ Processor Specification Update (Order Number 243748)
•370-Pin Socket (PGA370) Design Guidelines (Order Number 244410)
•Intel® Architecture Softw are Developer's Manual (Order Number 243193)
—Vo lume I: Basic Architecture (Order Number 243190)
—Volume II: Instruction Set Refe rence (Order Number 243191)
—Volume III: System Programming Guide (Order Number 243192)
•Intel® 440EX AGPset Design Guide ( Order Number 290637)
•Intel® Celeron™ Processor with the Intel® 440LX AGPset Design Guide
(Order Number 245088)
•Intel® 440BX AGPset Design Guide ( Order Number 290634)
•Intel® Celeron™ Processor with the Intel® 440ZX-66 AGPset Design Guide
(Order Number 245126)
•Intel® Celeron™ Processor (PPGA) at 466 MHz Therm al Solutions Guidelines
(Order Number 245156)
Notes:
1. This reference material can be found on the Intel Developer’s Website located at:
http://developer.intel.com
2. For a complete listing of the Intel® Celeron™ processor reference material, refer to the Intel
Developer’s Website wh en this processor is formally launched. The website is located at:
http://developer.intel.com/design/celeron/
Datasheet 13
Intel® Celeron™ Processor up to 850 MHz
2.0 Electrical Specifications
2.1 System Bus and VREF
Intel® Celeron™ processor signals use a variation of the low voltage Gunning Transceiver Logic
(GTL) signaling technology. The Intel Celeron processor system bus specification is similar to the
GTL specification, but ha s been enhanced to provide lar ger noise mar gins and reduced ringing. Th e
improvements are accomplished by increasing the termination voltage level and controlling the
edge rates. Because this specification is diff erent from the standard GTL specifi cation, it is referred
to as Assisted Gunning Transceiver Logic (AGTL+) in this document.
The Intel® Celeron processor varies from the Pentium Pro pr oces sor in its output buffer
implementation. The buffers that drive the system bus signals on the Intel® Celeron processor are
actively driven to VCCCORE for one clock cycle during the low- to-high transition. This improves
rise times and reduces overshoot. These signals should still be considered open-drain and require
termination to a supply that provides the logic-high signal level.
The AGTL+ inputs use dif feren tial receivers which require a ref erence signal ( VREF). VREF is used
by the receivers to determine if a signal is a logic-high or a logic-low, and is provided to the
processor core by either the processor substrate (S.E.P. Package) or the motherboard (PGA370
socket). Local VREF copies should be gener ated on the motherboard for a l l other devic es on the
AGTL+ system bus.
Termination is used to pull the bus up to the high voltage level and to control reflections on the
transmission line. The processor may contain termination resistors (S.E.P. Package and FC-PGA
Package) that provide termination for one end of the Intel Celeron processor system bus.
Otherwise, this term ination must exist on the mother boar d.
Solutions exist f or sin gle-ended termination as well, though this impl ementation changes system
design and eliminate backwards compatibility for Intel®Celeron™ processors in the PPGA
package. Single-ended terminat ion designs must still provide an AGTL+ termination resistor on
the motherboard for the RESET# signal.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+
signals are based on mot her board flight time as opposed to capacitive deratings. Analog signal
simulation of the Intel Celeron processor system bus, including trace lengths, is highly
recommended when designing a system. See the Pentium® II Pr ocessor AGTL+ Layout Guidelines
and the Pentium® II Processor I/O Buffer Models, Quad Format (Electronic Form) for details.
2.2 Clock Control and Low Power States
Intel® Celeron processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to
reduce power consumption by stopping the clock to internal sections of the processor, depending
on each particular state. See Figure 1 for a visual representation of the Intel Celeron processor low
power states.
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep
Sleep states, a Model Specific Register (MSR) bit must be s et. For th e MSR at 02AH (Hex), b it 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Pentium® II Processor Developer's Manual
(Order Number 243502).
14 Datasheet
Intel® Celeron™ Processor up to 850 MHz
2.2.1 Normal State—State 1
This is the normal operating state for the processor.
2.2.2 AutoHALT Power Down State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor will transitio n to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# will cause the processor to immed iately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Ar ch itec ture Software Developer's Manual,
Volume III: System Programmer's Guide (Order Number 243192) for more information.
FLUSH# will be ser vi ced d uring the AutoHALT state, and the processor will r e turn to the
AutoHALT state.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system d easserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
Figure 1. Clock Control State Machine
2. Auto HALT Power Down State
BCLK running.
Snoops and interrupts allowed.
4. Auto HALT Power Down State
BCLK running.
Snoops and interrupts allowed.
Snoop
Event
Occurs
Snoop
Event
Serviced
HALT Instruction and
HALT Bus Cycle generated
INIT#, BINIT#, INTR, SMI#,
RESET#
Snoop event occurs
Snoop event serviced
1. Normal State
Normal execution.
3. Stop Grant State
BCLK running.
Snoops and interrupts allowed.
STPCLK#
asserted STPCLK#
deasserted
5. Sleep State
BCLK running.
Snoops and interrupts allowed.
SLP#
asserted SLP#
deasserted
6. Deep Sleep State
BCLK stopped.
No Snoops and interrupts allowed.
BCLK
input
stopped
BCLK
input
restarted
STPCLK# Deasserted
and Stop Grant entered
from Auto HALT.
Datasheet 15
Intel® Celeron™ Processor up to 850 MHz
2.2.3 Stop-Grant State—Stat e 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VTT) for minimum pow er draw n by the t erm in at ion res i stors in thi s
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# will not be serviced while th e pro cessor is in Stop-Grant state. The event will b e latched
and can be serviced by software upon exit from Stop-Grant state.
FLUSH# will not be serviced during Stop-Grant state.
RESET# will cause the processor to immediately initialize itself, but the processo r wi ll stay in
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the
STPCLK# signal.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
system bus (see Section 2.2 .4). A transition to the Sleep state (s ee Section 2.2.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant State, SMI# , INIT#, and LINT[1:0] will be latched by the processor, and
only serviced when the processor returns to the Normal State. Only one occurrence of each event
will be recognized upon return to the Normal state.
2.2.4 HALT/Grant Snoop State—State 4
The processor will respond to snoop transactions on the Intel® Celeron processor system bus while
in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor
enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the Intel
Celeron processor system bus has been serviced (whether by the processor or another agent on the
Intel Celeron proces sor system bus). After the snoop is serviced, the processor will return to the
Stop-Grant state or AutoHALT Power Down state, as appropriate.
2.2.5 Sleep State—State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be
entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asser ted, caus ing
the processor to en ter the Sleep s tate. The SLP# pin is no t recognized in the Normal o r AutoHALT
states.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt sign als. No transitions or assertion s o f si gnals ( w ith the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the process or has returned to Stop-Grant state will result in unpredictable beh avior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ig nor ing the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
16 Datasheet
Intel® Celeron™ Processor up to 850 MHz
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input. (See Section 2.2.6.) Once in the Sleep state, the SLP# pin can
be deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum
assertion of one BCLK period.
2.2.6 Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BC LK input (after the Sleep state was entered from
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK is
stopped. It is recommended that the BLCK input be held low during the Deep Sleep State.
Stopping of the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep State. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to S top- G r a nt state will r e sult in unpredictable behavior.
2.2.7 Clock Control
BCLK provides the clock signal for the processor and on die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor processes a system bus snoop. The processor does not
stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into
the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in the Sleep or Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the
Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache
will be restarted o nly af ter the in ter nal cloc k ing m echanism for the processor is stable (i.e., the
processor has re-entered Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2.3 Power and Ground Pins
There are five pins defined on the S.E.P. Package for voltage identification (VID) and four pins on
the PPGA and FC-PGA packages. These pins specify the voltage required by the processor core.
These have been added to cleanly support voltage specification variations on current and future
Intel® Celeron processors.
For clean on-chip power distribution, Intel Celeron processors in the S.E.P. Package have 27 VCC
(power) and 30 VSS (ground) inputs. The 27 VCC pins are further divided to provide the different
voltage levels to the components. VCCCORE inputs for the processo r core account for 19 of the VCC
pins, while 4 V TT inputs (1.5 V) are used to provide a AGTL+ ter mination voltage t o the processor.
For only the S.E.P. Package, one VCC5 pin is provided for Voltage Transient Tools. VCC5 and
VCCCORE must remain electrically separated from each other.
Datasheet 17
Intel® Celeron™ Processor up to 850 MHz
The PPGA package has more power (88) and ground (80) pins than the S.E.P. Package. Of the
power pins, 77 are used for the processor core (VCCCORE) and 8 are used as a AGTL+ reference
voltage (VREF). The other 3 power pins are VCC1.5, VCC2.5 and VCCCMOS and are used for future
processor compatibility.
FC-PGA package has 77 VCCCORE, 77 ground pins, eight VREF, one VCC1.5, one VCC2.5, and one
VCCCMOS. VCCCORE inputs supply the processor core, including the on-die L2 cache. The VREF
inputs are used as the AGTL+ reference voltage for the processor.
The VCCCMOS pin is provided as a feature for future proces sor support in a flexible design. In such
a design, the VCCCMOS pin is used to provide the CMOS voltage for use by the platform.
Additionally, 2.5 V must be provided to the VCC2.5 input and 1.5 V m ust b e pr ovi ded t o the V cc1.5
input. The processor routes the CMOS voltage level through the package that it is compatible with.
For example, pro cess or s req uiri ng 1.5 V CMOS vol tage l evel s rou te 1.5 V to t he VCCCMOS out p ut .
Each power signal, regardless of package, must meet the specifications stated in Table 4. In
addition, all VCCCORE pins must be connected to a voltage island while all VSS pins have to
connect to a system ground plane. In addition, the motherboard must implement the VTT pins as a
voltage island or large trace. Similarly, all VSS pins must be connected to a system ground plane.
2.3.1 Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL.
2.4 Processor Decoupling
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating lar ge average current swings between low and full power states. This causes voltages on
power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be
taken in the board design to ensu re that the voltage provided to the processor remains within the
specifications listed in Table 5. Failure to do so can result in timing violations or a reduced lifetime
of the component.
2.4.1 System Bus AGTL+ Decoupling
The S.E.P. Package and FC-PGA package contain high frequency decoupling capacitance on the
processor substrate, where the PPGA package does not. Therefore, Intel® Celeron™ processors in
the PGA packages require high frequ ency decoupling on th e system motherboard. Bulk decoup ling
must be provided on the motherboard for pro per AGTL+ bus operation for all packages. See
AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 24333 0), AP-587 , Pentium® II
Proce sso r Pow er Di str ibut ion Gui deli nes (Order Numb er 24333 2), and the Pentium® II Proce sso r
Developer's Manual (Order Number 243502) for more information.
18 Datasheet
Intel® Celeron™ Processor up to 850 MHz
2.5 Voltage Identification
The processor’s voltage identification (VID) pins can be used to automatically select the VCCCORE
voltage from a compatible voltage regulator. There are five VID pins (VID[4:0]) on the S.E.P.
Package, while there are only four (VID[3:0]) on the PGA packages. This is because there are no
Intel® Celero n™ processors in the PGA package that require more than 2.05 V (see Table 2).
VID pins are not signals, but rather are an open or short circuit to VSS on the processor. The
combination of opens and shorts defines the processor core’s required voltage. The VID pins also
allow for compatibility with current and future Intel Celeron processors.
Note that the ‘11111’ (all opens) I D can be used to detect the abse nce of a pr ocessor cor e in a given
slot (S.E.P. Package only), as long as the power supply used does not affect the VID signals.
Detection logic and pull-ups should not affect VID inputs at the power source (see Section 7.0).
External logic monitoring the VID signals or th e voltage regulator may require the VID pins to be
pulled-up. If this is the case, the VID pins should be pulled up to a TTL-compatible level with
external resistors to the power source of the regulator.
The power source chosen must be guaranteed to be stable whenever the voltage regulator’s suppl y
is stable. This will prevent the possibility of the processor supply goi ng abov e the specified
VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC
converter, this can be accomplished by using the input voltage to the converter for the VID line
pull-ups. In addition, th e po wer supply must supply the requested voltage or disable itself.
NOTES:
1. 0 = Processor pin connected to VSS.
2. 1 = Open on processor; may be pulled up to TTL VIH on motherboard.
3. The Intel® Celeron™ processor core uses a 2.0 V power source.
4. V ID 4 applies only to the S.E.P. Package. VID[3:0] applies to both S.E.P. and PGA packages.
Table 2. Voltage Identification Definition 1, 2, 3
VID4
(S.E.P.P. only) VID3 VID2 VID1 VID0 VCCCORE
0 1 1 1 1 1.30
0 1 1 1 0 1.35
0 1 1 0 1 1.40
0 1 1 0 0 1.45
0 1 0 1 1 1.50
0 1 0 1 0 1.55
0 1 0 0 1 1.60
0 1 0 0 0 1.65
0 0 1 1 1 1.70
0 0 1 1 0 1.75
0 0 1 0 1 1.80
0 0 1 0 0 1.85
0 0 0 1 1 1.90
0 0 0 1 0 1.95
0 0 0 0 1 2.00
0 0 0 0 0 2.05
11111No Core
4
11110 2.1
4
Datasheet 19
Intel® Celeron™ Processor up to 850 MHz
2.6 System Bus Unused Pins
All RESERVED pins must remain unconnected. Connection of these pins to VCCCORE, VSS, or to
any other signal (including each other) can result in component malfunction or incompatibility
with future Intel® Celeron™ processor products. See Section 5.0 for a pin listing of the processor
and the location of each RESERVED pin.
For Intel Celeron processors in the S.E.P. Package, the TESTHI pin must be at a logic-high level
when the core power supply comes up. For more information, please refer to erratum C26 of the
Intel® Celeron™ Processor Specification Update (Order Number 243748). Also note that the
TESTHI signal is not available on I ntel Celeron p rocessors in the PGA package.
PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to
2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each
PICD line.
For reliable operation, always connect unused inputs or bi-directional signals to their deasserted
signal level. The pull-up or pull -down resistor value is system dep enden t and sh ould be chosen
such that the logic-high (VIH) and logic-l ow (VIL) requirements are met.
For the S.E.P. Package, unused AGTL+ inputs should not be connected as the package substrate
has termination resistors. On the other hand, the PGA packages do not have AGTL+ termination in
their package and must have any unused AGTL+ inputs terminated through a pull-up resistor. For
designs that intend to only support the FC-PGA processor, unused AGTL+ inputs will be
terminated by the processor ’s on-die termination resistors and, thus, do not need to be terminated
on the motherboard. However, the reset pin should always be terminated on the motherboard.
For unused CMOS inputs, active-low signals should be connected through a pull-up resistor to
meet VIH requirements and active-high s ignals should be connected th rough a pull-down resi stor to
meet VIL requirements. Unused CMOS outputs can be left unconnected. A resistor must be used
when tying bi-directional signals to power or ground. For any signal pulled to either power or
ground, a resistor will allo w for system testability.
2.7 Processor System Bus Signal Groups
To simplify the following discussion, the Intel® Celeron™ processor system bus signals have been
combined int o group s by buffer type. All Intel® Celeron™ processor system bus outputs are
open drain and require a high-level source provided externally by the termination or pull-up
resistor.
AGTL+ input signals have dif feren tial input buf fers, which use VREF as a reference signal. AGTL+
output signals require termination to 1.5 V. In this document, the term "AGTL+ Input" refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output"
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
EMI pins (S.E.P. Package only) should be connected to motherboard ground and/or to chassis
ground through zero ohm (0 Ω) resistors. The zero ohm resistors should be placed in close
proximit y to the SC242 connector. The path to ch assi s g rou nd s ho ul d be s ho rt i n le ng th and h a ve a
low impedance.
The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V. Other
CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and
STPCLK#) must be pulled up to VCCCMOS. In addition, the CMOS, APIC, and TAP outputs are
20 Datasheet
Intel® Celeron™ Processor up to 850 MHz
open dra in and should be pulled high to VCCCMOS. This ensures not only correct operation for
current Intel Celeron processors, but compatibility for future Intel Celeron processor products as
well.
The groups and the signals contained within each gro up are shown in Table 3. Refer to Section 7.0
for descriptions of these signals.
NOTES:
1. See Section 7.0 for information on the PWRGOOD signal.
2. See Section 7.0 for information on the SLP# signal.
3. See Section 7.0 for information on the THERMTRIP# signal.
4. Thes e signals are specified for 2.5 V operation for S.E.P.P. and PPGA packages; they are specified at 1.5V
operation for the FC-PGA package
5. VCCCORE is the power supply for the processor core.
VID[4:0] and VID[3:0] are described in Section 2.0.
VTT is used to terminate the system bus and generate VREF on the processor substrate.
VSS is system ground.
VCC5 is not connected to the Intel® Celeron™ processor. This supply is used for Voltage Tr ansient Tools.
SLOTOCC# is described in Section 7.0.
BSEL is described in Section 2.7.2 and Sec tion 7.0.
EMI pins are described in Section 7.0.
VCCL2 is a Pentium® II processor reserved signal provided to maintain compatibility with the Pentium® II
processor and may be left as a no-connect for “Intel Celeron processor-only” designs.
6. Only applies to Intel Celeron processors in the S.E.P. Package.
7. Only applies to Intel Celeron processors in the PPGA and FC-PGA packages.
8. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information.
9. These signals are specified for 2.5 V operation.
10.BSEL1 is not used in Celeron processors.
11.RESET# must always be terminated to VTT on the motherboard for PGA packages. On-die termination is not
provided for this signal on FC-PGA.
12.For the FC-PGA, this signal is used to control the value of the processor on-die termination resistance. Refer
to the specific platform design guide for the recommended pull-down resistor value.
13.Only applies to Intel Celeron processors in the FC-PGA Package.
14.S.E.P. Package and FC-PGA Package.
Table 3. Intel® Celeron™ Processor System Bus Signal Groups
Group Name Signal s
AGTL+ Input BPRI#, DEFER#, RESET#11, RS[2:0]#, TRDY#
AGTL+ Output PRDY#
AGTL+ I/O A[31:3]#, ADS#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#8, D[63:0]#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, REQ[4:0]#,
CMOS Input4A 20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#, SLP#2,
STPCLK#
CMOS Input PWRGOOD1,9
CMOS Output 4FERR#, IERR#, THERMTRIP#3
System Bus Clock BCLK9
APIC Clock PICCLK9
APIC I/ O4PICD[1:0]
TAP I nput4TCK, TDI, TMS, TRST#
TAP O utput 4TDO
Power/Other5CPUPRES#7, ED GC TRL7, EM I 6, PLL[2:1]7, SLOTOCC#6, THERMDP, THERMDN,
VCC1.57, VCC2.57, VCCL25, VCC56, VCCCMOS7, VCCCORE, VCOREDET7, VID[3:0]7,
VID[4:0]6, VREF[7:0]7, VSS, VTT14, RTTC TRL12, BSEL[1 :0]10, SLEWCTRL13
Datasheet 21
Intel® Celeron™ Processor up to 850 MHz
2.7.1 Asynchronous Vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, APIC, and TAP signals can be
applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP signals
are synchronous to TCK.
2.7.2 System Bus Frequency Select Signal (BSEL[1:0])
The BSEL pins have two functions. First, they can act as outputs and can be used by an external
clock generator to select the proper system bus frequency. Second, they can act as an inputs and
can be used by a system BIOS to detect and report the processor core frequency. See the Intel®
Celeron™ Processor with the Intel® 440ZX-66 AGPset Design Guide (Order N umb er 245 126 ) for
an example implementation of BSEL.
BSEL0 is 3.3 V tolerant for the S.E.P. Package, while it is 2.5 V tolerant on the PPGA package. A
logic-low on BSEL0 is defined as 66 MHz. On the FC-PGA a logic low on both BSEL0 and
BSEL1 are defined as 66 MHz and are 3.3V tolerant.
2.8 Test Access Port (TAP) Connection
Due to the voltage levels suppor ted by other components in the Test Access P ort (TAP) logic, it is
recommended that the Intel® Celeron™ processor be first in the TAP chain and followed by any
other components within the system. A translation buffer should be used to connect to the rest of
the chain unless one of the other components is capable of accepting a VccCMOS (1.5V or 2.5 V)
input. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signa l
may be required with each driving a different voltage level.
A Debug Port may be placed at the start and end of the TAP chain with the TDI of the first
component coming from the Debug P ort and t he TDO from th e last compo nent going t o the Deb ug
Port.
2.9 Maximum Ratings
Table 4 contains the Intel® Celeron™ processor stress ratings only. Functional operation at the
absolute maximum and minimum is not implied nor guaranteed . The processor sho uld not receive a
clock while subjected to thes e cond itions. Function al operating cond itions are given in the AC and
DC tables. Extended exposure to the ma ximum rating s ma y affect device reliability. Further more,
although the pro cess or cont ains prot ecti ve circui try t o res ist damag e from st ati c electr ic dis charge,
one should always take precautions to avoid high static voltages or electric fields.
22 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Oper ating voltage is the voltage to which the component is designed to operate. See Table 5.
2. This rat ing applies to the VCCCORE, VCC5, and any input (except as noted below) to the processor.
3. P aram eter applies to CMOS, APIC, and TAP bus signal groups only.
4. The electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion/
extraction cycles.
5. S.E.P. Package Only
6. P G A Pac kages On ly
7. Input voltage can never exceed VSS + 2.8 volts.
8. Input voltage can never go below VTT - 2.18 volts.
9. Parameter applies to CMOS (except BCLK, PICCLK, and PWRGOOD), APIC, and TAP bus signal groups
only f or VinCMOS on the FC-PGA Package only.
10.Parameter applies to CMOS signals BCLK, PICCLK, and PWRGOOD for VinCMOS1.5 on FC-PGA Package
only.
2.10 Processor DC Specificati ons
The processor DC specifications in this section are defined for the Intel® Celeron™ processor. See
Section 7.0 for signal definitions and Section 5.0 for signal listings.
Most of the signals on the Intel Celeron processor system bus are in the AGTL+ signal group.
These signals are specified to be terminated to 1.5 V. The DC specifications for these signals are
listed in Table 6.
To allow connection with other devices, the Clock, CMOS, APIC, and TAP signals are designed to
interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 7.
Table 5 through Table 8 list the DC specifications for Intel Celeron processors operating at 66 MHz
Intel Celeron processor system bus frequencies. Specifications are valid only while meeting
specifications for case temperature, clock frequency, and input voltages. Care should be taken to
read all notes associated with each parameter.
Table 4. Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
TSTORAGE Processor storage temperature –40 85 °C
VCC(All)
Any processor supply volt age with
respect to VSS
•PPGA and S.E.P.P. –0.5 Operating
voltage + 1.0 V1, 2
•FC-PGA –0.5 2.1 V
VinAGTL+
AGTL+ buffer DC input voltage with
respect to VSS
•PPGA and S.E.P.P. –0.3 VCCCORE + 0.7 V
•FC-PGA VTT - 2.18 2.18 V 7, 8
VinCMOS
CMOS buffer DC input voltage with
respect to VSS
•PPGA and S.E.P.P. -0.3 3.3 V 3
•FC-PGA VTT - 2.18
-0.58 2.18
3.18 V
V7, 8, 9
10
IVID Max VID pin current 5 mA
ISLOTOCC# Max SLOTOCC# pin current 5 mA 5
ICPUPRES# M ax CPU PRE S# pin current 5 mA 6
Mech Max
Edge Fingers5Mechanica l integrity of processor
edge fingers 50 Insertions/
Extractions 4, 5
Datasheet 23
Intel® Celeron™ Processor up to 850 MHz
Table 5. Voltage and Current Specifications 1 (Sheet 1 of 5)
Symbol Parameter Processor Min Typ Max Unit Notes
Core Freq CPUID
VCCCORE VCC for processor
core
266 MHz 0650h
—
2.00
—V
2, 3, 4
0651h 2.00 2, 3, 4
300 MHz 0650h 2.00 2, 3, 4
0651h 2.00 2, 3, 4
300A MHz 0660h 2.00 2, 3, 4
0665h 2.00 2, 3, 4
333 MHz 0660h 2.00 2, 3, 4
0665h 2.00 2, 3, 4
366 MHz 0660h 2.00 2, 3, 4
0665h 2.00 2, 3, 4
400 MHz 0660h 2.00 2, 3, 4
0665h 2.00 2, 3, 4
433 MHz 0660h 2.00 2, 3, 4
0665h 2.00 2, 3, 4
466 MHz 0665h 2.00 2, 3, 4
500 MHz 0665h 2.00 2, 3, 4
533 MHz 0665h 2.00 2, 3, 4
533A MHz 0683h 1.50 2, 3, 4
0686h 1.70 2, 3, 4
566 MHz 0683h 1.50 2, 3, 4
0686h 1.70 2, 3, 4
600 MHz 0683h 1.50 2, 3, 4
0686h 1.70 2, 3, 4
633 MHz 0683h 1.65 2, 3, 20
0686h 1.70 2, 3, 20
667 MHz 0683h 1.65 2, 3, 20
0686h 1.70 2, 3, 20
700 MHz 0683h 1.65 2, 3, 20
0686h 1.70 2, 3, 20
733 MHz 0683h 1.65 2, 3, 20
0686h 1.70 2, 3, 20
766 MHz 0683h 1.65 2, 3, 20
0686h 1.70 2, 3, 20
800 MHz 0683h 1.65 2, 3, 20
0686h 1.70 2, 3, 20
850 MHz 0683h 1.65 2, 3, 20
0686h 1.70 2, 3, 20
24 Datasheet
Intel® Celeron™ Processor up to 850 MHz
VREF19 AGTL+ input
reference voltage ——
2/3VTT – 2% 2/3VTT + 2% V ± 2%, 11
VCC1.516
Static AGTL+ bus
termination voltage ——1.455 1.50 1.545 V 1.5 ± 3%
Transient AGTL+
bus termination
voltage ——1.365 1.50 1.365 V 1.5 ± 3%
VCC2.518 VCC for VCCCMOS ——2.375 2.5 2.625 V 2.5 ± 5%
VTT AGTL+ bus
termination voltage ——1.365 1.50 1.635 V 1.5 ± 9%5
Baseboard
Tolerance, Static
Processor core
voltage static
tolerance level at
SC242 pins
——–0.070 —0.100 V 6
Baseboard
Tolerance,
Transient
Processor core
voltage transient
tolerance level at
SC242 pins
——–0.120 —0.120 V 6
VCCCORE
Tolerance, Static
Processor core
voltage static
tolerance level at:
•SC242 edge
fingers ——–0.085 —0.100 V 7
•PPGA
processor pins ——-0.089 —0.100 V 8
•FC-PGA
processor pins ——-0.080 —0.040 V 17
VCCCORE
Tolerance,
Transient
Processor core
voltage transient
tolerance level at:
•SC242 edge
fingers ——–0.140 —0.140 V 7
•PPGA
processor pins ——-0.144 —0.144 V 8
•FC-PGA
processor pins ——-0.130 —0.080 V 17
Table 5. Voltage and Current Specifications 1 (Sheet 2 of 5)
Symbol Parameter Processor Min Typ Max Unit Notes
Core Freq CPUID
Datasheet 25
Intel® Celeron™ Processor up to 850 MHz
ICCCORE ICC for processor
core
266 MHz
———
8.2
A 9, 10
300 MHz 9.3
300A MHz 9.3
333 MHz 10.1
366 MHz 11.2
400 MHz 12.2
433 MHz 12.6
466 MHz 13.4
500 MHz 14.2
533 MHz 14.9
533A MHz 11.4
566 MHz 11.9
600 MHz 12.0
633 MHz 12.7
667 MHz 13.3
700 MHz 14.0
733 MHz 14.6
766 MHz 15.5
800 MHz 16.0
850 MHz 16.2
IVTT Term ination voltage
supply current ————2.7 A 11
Table 5. Voltage and Current Specifications 1 (Sheet 3 of 5)
Symbol Parameter Processor Min Typ Max Unit Notes
Core Freq CPUID
26 Datasheet
Intel® Celeron™ Processor up to 850 MHz
ISGnt ICC Stop-Grant for
processor core
266 MHz
———
1.12
A12
300 MHz 1.15
300A MHz 1.15
333 MHz 1.18
366 MHz 1.21
400 MHz 1.25
433 MHz 1.30
466 MHz 1.35
500 MHz 1.43
533 MHz 1.52
533A MHz 2.5
566 MHz 2.5
600 MHz 2.5
633 MHz 2.5
667 MHz 2.5
700 MHz 2.5
733 MHz 2.5
766 MHz 2.5
800 MHz 2.5
850 MHz 2.5
Table 5. Voltage and Current Specifications 1 (Sheet 4 of 5)
Symbol Parameter Processor Min Typ Max Unit Notes
Core Freq CPUID
Datasheet 27
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VCCCORE and ICCCORE supply the processor core.
3. These volt ages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required.
4. Use the T ypical Voltage specification with the Tolerance specifications to provide correct voltage regulation to
the processor .
ISLP ICC Sleep for
processor core
266 MHz
———
0.90
A
300 MHz 0.94
300A MHz 0.94
333 MHz 0.96
366 MHz 0.97
400 MHz 0.99
433 MHz 1.01
466 MHz 1.03
500 MHz 1.09
533 MHz 1.16
533A MHz 2.5
566 MHz 2.5
600 MHz 2.5
633 MHz 2.5
667 MHz 2.5
700 MHz 2.5
733 MHz 2.5
766 MHz 2.5
800 MHz 2.5
850 MHz 2.5
IDSLP
ICC Deep Sleep for
processor core:
•S.E.P.P and
PPGA ————0.90 A
•FC-PGA ————2.2 A
ICCCMOS
ICC for VCCCMOS
•S.E.P.P and
PPGA ————500 mA
•FC-PGA ————250 mA
dICCCORE/dt
Power supply
current slew rate
•S.E.P.P ————20 A/µs 13, 14, 15
•PPGA and FC-
PGA ————240 A/µs 13, 14
dICCVTT/dt Termination current
slew rate ————8A/µs
See
Table 8,
Table 18,
Table 20
Table 5. Voltage and Current Specifications 1 (Sheet 5 of 5)
Symbol Parameter Processor Min Typ Max Unit Notes
Core Freq CPUID
28 Datasheet
Intel® Celeron™ Processor up to 850 MHz
5. VTT must be held to 1.5 V ± 9%. It is recommended that V TT be held to 1.5 V ± 3% while the Intel®
Celeron™ processor sy stem b us is idle. This is measured at the processor edge fingers.
6. Thes e are the tolerance requirements , across a 20 MHz bandwidth, at the SC242 connector pin on the
bottom side of the baseboard. The requirements at the SC242 connector pins account for voltage drops
(and impedance discontinuities) across the connector, processor edge fingers, and to the processor core.
VCCCORE must return to within the static voltage specification within 100 µs after a transient event.
7. Thes e are the tolerance requirements , across a 20 MHz bandwidth, at the processor edge fingers. The
requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the
processor edge fingers and to the processor core. VCCCORE must return to within the static voltage
specification within 100 µs after a transient event.
8. Thes e are the tolerance requirements , across a 20 MHz bandwidth, at the top of the PPGA package.
VCCCORE must return to within the static voltage specification within 100 µs after a transient event.
9. M ax ICCCORE measurements are measured at VCCCORE max voltage (VCCCORE_TYP + maximum static
tolerance), under maximum signal loading conditions.
10.Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of VCCCORE
(VCCCORE_TYP). In this case, the maximum current level for the regulator , ICCCORE_REG, can be reduced from
the specified maximum current ICCCORE_MAX and is calculated by the equation:
ICCCORE_REG = ICCCORE_MAX × VCCCORE_TYP / (V CCCORE_TYP + VCCCORE Tolerance, Transient)
11.The current specified is the current required for a single Intel Celeron processor. A similar amount of current
is drawn through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended
termination is used (see Section 2.1).
12.The curr ent specified is also for AutoHALT state.
13.M axim um values are specif ied by design/character ization at nominal VCCCORE.
14.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
15.dICC/dt specifications are measured and specified at the SC242 connector pins.
16.FC-P G A only
17.Thes e are the tolerance requirements across a 20 MH z bandwidth at the FC-PGA socket pins on the solder
side of the motherboard. VCCCORE must return to within the static voltage specification within 100 µs after a
transient event.
18.P GA only
19.S.E.P Package and FC-PGA Packages only
20.These processors implement independent VTT and VCCCORE power planes.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies and
cache sizes.
2. VIH and VOH for the Intel Celeron processor may experience exc ursions of up to 200 mV above VTT for a
single system bus clock. However, input signal drivers must comply with the signal quality specifications in
Section 3.0.
3. Minimum and maximum VTT are given in Ta ble 8.
4. P aram eter correlated to measurement into a 25 Ω resistor terminated to 1.5 V.
5. IOH for the Intel Celeron processor may experience excursions of up to 12 mA for a single system bus clock.
6. ( 0 ≤ VIN ≤ 2.0 V +5%) for S.E.P Package and PPGA Package; (0 ≤ VIN ≤ 1.5V +3%) for FC-PGA package.
7. ( 0 ≤ VOUT ≤ 2.0 V +5%) for S.E.P Package and PPGA Package; (0 ≤ VOUT ≤ 1.5V + 3 % ) fo r FC-P GA
package.
8. R e fer to the I/O Buffer Models for IV characteristics.
9. Steady state input voltage must not be above VSS + 1.65V or below VTT - 1.65V.
Table 6. AGTL+ Signal Groups DC Specifications 1
Symbol Parameter Min Max Unit Notes
VIL
Input Low Voltage
•S.E.P.P and PPGA –0.3 0.82 V
•FC-PGA –0.150 VREF - 0.200 V 9
VIH
Input High Voltage
•S.E.P.P and PPGA 1.22 VTT V2, 3
•FC-PGA VREF + 0.200 VTT V2, 3
RON Buffer On Resistance 16.67 Ω 8
ILLeakage Current for
inputs, outputs, and I/O ±100 µA 6, 7
Datasheet 29
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. P aramet er meas ured at 14 mA (for use with TTL inputs) for S.E.P Package and PPGA Package. It is 9 mA
for FC-PGA.
3. (0 ≤ VIN ≤ 2.5 V +5%) for PPGA Package and S.E.P Package only.
4. (0 ≤ VOUT ≤ 2.5 V +5%) for PPGA Package and S.E.P Pac kage only.
5. (0≤ VIN ≤ 1.5V +3%) for FC-PGA Package only.
6. (0≤ VOUT ≤ 1.5V +3%) for FC-PGA Package only.
7. Applies to non-AGTL+ signals BCLK, PICCLK, and PWRGOOD for FC-PGA Package only.
8. Applies to non-AGTL+ signals except BCLK, PICCLK, and PWRGOOD for F C-PG A Package only.
9. These values are specified at the processor pins for FC-PGA Package only.
10.S.E.P. Package and PPGA Package only.
2.11 AGTL+ System Bus Specifi cations
It is recommended that the AG TL+ bus be routed in a daisy-chain fashion with termination
resistors to VTT at each end of the signal trace. These termination resistors are placed electrically
between the ends of the signal traces and the VTT voltage su ppl y and gener ally are chosen to
approximate the substrate impedance. The valid high and low levels are determined by the input
buffers using a reference voltage called VREF. Single ended termination may be possible if trace
lengths are tightly controlled, see the Intel® 440EX AGPset Design Guide (Or der Number 290 637)
or the Intel® Celeron™ Proces sor (PPGA) with the Intel® 440LX AG Pset Design Guide (Order
Number 245088) for more information.
Table 8 below lists the nominal specification for the AGTL+ terminat ion v oltage ( VTT). The
AGTL+ reference voltage (VREF) is generated on the p rocess or sub strate (S.E. P. Package only) for
the processor core, but sho uld be set to 2/3 VTT for other AGTL+ logic using a voltage divider on
the motherboard. It is important that the motherboard impedance be specified and held to:
•±20% tolerance (S.E.E.P. and PPGA)
•±15% tolerance (FC-PGA)
Table 7. Non-AGTL+ Signal Group DC Specifications 1
Symbol Parameter Min Max Unit Notes
VIL Input Low Volt age –0.3 0.7 V 10
VIH Input High Voltage 1.7 2.625 V 2. 5 V +5% maxim um,
Note 10
VIL1.5 Input Low Volt age –0.150 VREF - 0.200 V 8, 9
VIL2.5 Input Low Voltage -0.58 0.700 V 7, 9
VIH1.5 Input High Voltage VREF + 0.200 VTT V 5, 8, 9
VIH2.5 Input High Vo ltage 2.0 3.18 V 7, 9
VOL Output Low Vol tage 0.4 V 2
VOH
Output High V oltage
•S.E.P.P and PPGA N/A 2.625 V All outputs are open-
drain to 2.5 V +5%
•FC-PGA VTT V 6, 8, 9
IOL
Output Low Current
•S.E.P.P and PPGA 14 mA
•FC-PGA 9 mA 9
ILLeakage Current for
Inputs, Outputs, and I/O ±100 µA 3, 4, 5, 6
30 Datasheet
Intel® Celeron™ Processor up to 850 MHz
It is also important that the intrins ic trace capacitance fo r the AGTL+ s ign al group traces is known
and well-controlled. For mor e details on AGTL+, see the Pentium® II Processor Developer's
Manual (Order Number 24350 2) and AP-5 85, Pentium® II Processor AGTL+ Guidelines (Or der
Number 243330).
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. VTT must be held to 1.5 V ± 9%; dICCVTT/dt is specified in Table 5. It is recommended that VTT be held to
1.5 V ± 3% while the Intel Celeron processor system bus is idle. This is measured at the processor edge
fingers.
3. VREF is generated on the processor substrate to be 2/3 VTT nominally with the S.E.P. package. It must be
created on the motherboard for processors in the PPGA package.
4. VTT and Vcc1.5 must be held to 1.5V ±9%. It is required that VTT and Vcc1.5 be held to 1.5V ±3% while the
processor syst em bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
5. The value of the on-die RTT is determined by the resistor value measured by the RTTCTRL signal pin. The
on- die RTT tolerance is ±15% based on the RTTCTRL resistor pull-down of ±1%. See Section 7.0 for more
details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific chipset/processor
combination.
6. VREF is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate
VREF decoupling on the motherboard.
2.12 System Bus AC Specifications
The Intel® Cel er on™ processor system bus timings specified in this section are defined at the Intel
Celeron processor edge fingers and the processor core pins. Timings specified at the processor
edge fingers only apply to the S.E.P. Package and timings given at the processor cor e p i ns apply to
all S.E.P. Package and PGA packages. Unless otherwise specified, timings are tested at the
processor cor e during m anufacturing . Timin gs at the p rocessor edge fin gers are s pecified b y design
characterization. See Section 7.0 for the Intel Celero n processor signal definitions. Note that at
66 MHz system bus operation, the Intel Celeron processor timings at the processor edge
fingers are identical to the Pentium II processor timings at the edge fingers. See the Intel®
Pentium® II Processor at 233, 266, 300, and 333 MHz (Order Number 243335) for more detail.
Table 9 through Table 23 list the AC specifications associated with the Intel Celeron processor
system bus. These specifications are broken into the following categories: Table 9 through Table 11
contain the system bus clock specifications, Table 12 and Table 13 contain the AGTL+
specifications, Table 16 an d Table 17 are the CMOS signal group specifications, Table 18 contains
timings fo r the Reset conditions, Table 20 and Table 21 cove r APIC bus timing, and Table 22 and
Table 8. Processor AGTL+ Bus Specifications 1
Symbol Parameter Min Typ Max Units Notes
VTT
Bus Termination Voltage
•S.E.P.P and PPGA 1.365 1.50 1.635 V 1.5 V ± 9% 2
•FC-PGA 1.50 V 4
RTT
Termination Resistor
•S.E.P.P and PPGA 56 Ω± 5%
•FC-PGA (on die RTT) 40 130 Ω5
VREF
Bus Reference Voltage
•S.E.P.P and PPGA 2/3 VTT V± 2% 3
•FC-PGA 0.950 2/3 VTT 1.05 V 6
Datasheet 31
Intel® Celeron™ Processor up to 850 MHz
Table 23 cover TAP timing. For each pair o f tables, the first tabl e contains timing specifications for
measurement or simulation at the processor edge fingers. The second table contains specifications
for simulation at the processor core pads.
All Intel Celeron processor system bus AC specifications for the AGTL+ signal group are relative
to the rising edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and
‘1’ logic levels unless otherwise specified.
The timings specified in this sectio n should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available in
Quad format as the Intel® Cel e ron™ Processor I/O Buffer Models, Quad XTK Format (Electronic
Form). AGTL+ layout guidelines are also available in AP-585, Intel®Pentium® II Processor
AGTL+ Guidelines (Order Number 243330).
Care should be taken to read all notes associated with a particular timing parameter.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All AGTL+ signal timings (address bus, data
bus, etc.) are referenced at 1.00 V at the processor edge fingers.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All CMOS signal timings (compatibility
signals, etc.) are referenced at 1.25 V at the processor edge fingers.
4. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
bus clock to core clock ratio is determined during initialization. Table 11 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. This specif ication applies to Intel Celeron processors when operating at a system bus frequency of 66 MHz.
7. The BCLK offset time is the absolute difference needed between the BCLK signal arriving at the Intel Celeron
processor edge finger at 0.5 V vs. arriving at the core logic at 1.25 V. The positive offset is needed to account
for the delay between the SC242 connector and processor core. The positive offset ensures both the
processor core and the core logic receive the BCLK edge concurrently.
8. See S ection 3.1 for Intel Celeron processor system bus clock signal quality specifications.
9. Not 100% tested. Specified by design characterization as a clock driver requirement.
Table 9. System Bus AC Specifications (Clock) at the Processor Edge Fingers
(for S.E.P. Package) 1, 2, 3
T# Parameter Min Nom Max Unit Figure Notes
System Bus Frequency 66.67 MHz
T1’: BCLK Period 15.0 ns 34, 5, 6
T1B’: SC242 to Core Logic BCLK Offset 0.78 ns 3Absolute Value 7,8
T2’: BCLK Period Stability ± 300 ps See Table 10
T3’: BCLK High Time 4.44 ns 3@>2.0 V 6
T4’: BCLK Low Time 4.44 ns 3@<0.5 V 6
T5’: BCLK Rise Time 0.84 2.31 ns 3(0.5 V–2.0 V) 6, 9
T6’: BCLK Fall Time 0.84 2.31 ns 3(2.0 V–0.5 V) 6, 9
32 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core
pins.
3. A ll AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All CMOS signal timings (compatibili ty signals, etc.) are referenced at 1.25 V at the processor core pins.
4. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
bus clock to core clock ratio is determined during initialization. Table 11 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. This specification applies to the Intel Celeron processor when operating at a system bus frequency of
66 MHz.
7. See Section 3.1 for Intel Celeron processor system bus clock signal quality specifications.
8. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor core pin. The jitter
present must be accounted for as a component of BCLK timing skew between devices.
9. The clock drive r’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer.
10.N ot 100% tested. Specified by design characterization as a clock driver requirement.
11.BCLK Rise time is measure between 0.5V–2.0V. BCLK fall time is measured between 2.0V–0.5V.
Table 10. System Bus AC Specifications (Clock) at the Processor
Core Pins (for Both S.E.P. and PGA Packages) 1, 2, 3, 7
T# Parameter Min Nom M ax Unit Figure Notes
System Bus Frequency 66.67 MHz
T1: BCLK Period 15.0 ns 34, 5, 6
T2: BCLK Period Stability ± 300 ps 36, 8, 9
T3: BCLK High Time 4.94 ns 3@>2.0 V 6
T4: BCLK Low Time 4.94 ns 3@<0.5 V 6
T5: BCLK Rise Time
•S.E.P.P. and PPGA
•FC-PGA 0.34
0.40 1.36
1.6 ns
ns 3
3(0.5 V–2.0 V) 6, 10
10, 11
T6: BCLK Fall Time
•S.E.P.P. and PPGA
•FC-PGA 0.34
0.40 1.36
1.6 ns
ns 3
3(2.0 V–0.5 V) 6, 10
10, 11
Datasheet 33
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
2. While other bus ratios are defined, operation at frequencies other than those listed are not supported.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.50 V at the processor edge
fingers. All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor edge
fingers.
4. This specif ication applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Valid delay timings for these signals are specified into 50 Ω to 1.5 V and with VREF at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
8. Specification is for a minimum 0.40 V swing.
9. Specification is for a maximum 1.0 V swing.
10.After VCCCORE, and BCLK become stable.
Table 11. Valid Intel® Celeron™ Processor System Bus, Core Frequency 1, 2
Core Frequency (MHz) BCLK Frequency (MHz) Frequency Multiplier
266 66 4
300 66 4.5
333 66 5
366 66 5.5
400 66 6
433 66 6.5
466 66 7
500 66 7.5
533 66 8
566 66 8.5
600 66 9
633 66 9.5
667 66 10
700 66 10.5
733 66 11
766 66 11.5
800 100 8
850 100 8.5
Table 12. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Edge
Fingers (for S.E.P. Package) 1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T7’: AGTL+ Outp u t Valid Delay 1.07 6.37 ns 44, 5
T8’: AGTL+ Input Setup Time 1.96 ns 54, 6, 7, 8
T9’: AGTL+ Input Hold Time 1.53 ns 54, 9
T10’: RESET# Pulse Width 1.00 ms 610
34 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor core pins.
4. This specification applies to the Intel Celeron processor operating with a 66 MHz Intel Celeron processor
system bus only.
5. Valid delay timings for these signals are specified into 25 Ω to 1.5 V and with VREF at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. R ESET# can be asserted (active) asynchronously, but must be deasserted synch ronously.
8. S pecification is for a minimum 0.40 V swing.
9. Specification is for a maximum 1.0 V swing.
10.A fter VCCCORE and BCLK become stable.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are REFerenced to the BCLK rising edge at 1.25 V at the processor pin.
All GTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor pins.
4. This specification applies to the processor operating with a 66 MHz system bus only.
5. Valid delay timings for these signals are specified into 25 Ω to 1.5 V and with VREF at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. R ESET# can be asserted (active) asynchronously, but must be deasserted synch ronously.
8. After VCCCORE and BCLK become stable.
Table 13. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins
(for S.E.P. Package) 1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T7: AGTL+ Output Valid Delay 0.17 5.16 ns 45
T8: AGTL+ Input Setup Time 2. 10 ns 55, 6, 7, 8
T9: AGTL+ Input Hold Time 0. 77 ns 59
T10: RESET# Pulse Width 1.00 ms 67, 10
Table 14. Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Core Pins (for PPGA Package) 1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T7: AGTL+ Output Valid Delay 0.30 4.43 ns 45
T8: AGTL+ Input Setup Time 2.10 ns 55, 6, 7
T9: AGTL+ Input Hold Time 0.85 ns 5
T10: RESET# Pulse Width 1.00 ms 67, 8
Datasheet 35
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processors at all
frequencies and cache sizes.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. Valid delay timings for these signals are specified into 50 Ω to 1.5V and with V REF at 1.0 V.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing from VREF - 200 m V to VREF + 200 mV. This ass umes an edge
rate of 0.3V/ns.
8. Specification is for a maximum 1.0 V swing from VTT - 1V to VTT. This assumes an edge rate of 3V/ns.
9. This should be me asured after VCCCORE, VCCCMOS, and BCLK become stable.
10.This specification applies to the FC-PGA running at 66 MHz system bus frequency.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.50 V at the processor edge
fingers. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. This specif ication only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an
edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies.
PWRGOOD must remain below VIL,max (Table 6) until all the voltage planes meet the voltage tolerance
specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 10 for at least 10 clock
cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V.
6. When driven in active or after VCCCORE, and BCLK become stable.
7. If the BCLK signal meets its AC spec ification within 150 ns of turn ing on, then the PWRGOOD inactiv e puls e
width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still
remain below VIL,max until all the voltage planes meet the voltage tolerance specifications.
Table 15. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins
(for FC-PGA Package)1, 2, 3
T# Parameter Min Max Unit Figure Notes
T7: AGTL+ Output Valid Delay 0.40 3.25 ns 44, 10
T8: AGTL+ Input Setup Time 1.20 ns 55, 6, 7, 10
T9: AGTL+ Input Hold Time 1.00 ns 58, 10
T10: RESET# Pulse Width 1.00 ms 76, 9, 10
Table 16. System Bus AC Specifications (CMOS Signal Gr oup) at the Processor Edge Fingers
(for S.E.P. Package) 1 , 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T14’: CMOS Input Pulse Width, except
PWRGOOD 2BCLKs8Active and
Inactive states
T14B: LINT[1:0] Input Pulse Width 6 BCLKs 85
T15’: PWRGOOD Inactive Pulse Width 10 BCLKs 86, 7
36 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. These specifications are tested during manufacturing.
3. A ll AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pins. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an
edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies.
6. When driven inactive or after VCCCORE, and BCLK become stable.
7. If the BCLK signal meets its A C s peci fication within 150 ns of turning on, then t he P WRGOOD inactive pulse
width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD mus t still
remain below VIL,max until all the voltage planes meet the voltage tolerance specifications.
PWRGOOD must remain below VIL,max (Table 6) until all the voltage planes meet the voltage tolerance
specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 10 for at least 10 clock
cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel ®Celeron™ processor frequencies.
Table 17. System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins
(for Both S.E.P. and PGA Packages) 1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T14: CMOS Input Pulse Width, except
PWRGOOD 2BCLKs8Active and
Inactive states
T14B: LINT[1:0] Input Pulse Width
(S.E.P.P. Only) 6BCLKs85
T15: PWRGOOD Inactive Pulse Width 10 BCLKs 86, 7
Table 18. System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages) 1
T# Parameter Min Max Unit Figure Notes
T16: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Setup Time 4BCLKs6Before deassertion
of RESET#
T17: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Hold Time 220BCLKs6After clock that
deasserts RES ET#
Datasheet 37
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel® Celeron™ FC-PGA processor s at all
frequencies and cache sizes.
2. For a reset, the clock ratio defined by these signals must be a safe value (their final or a lower-multiplier)
within this delay unless PWRGOOD is being driven inactive.
3. These param eters apply to processor engineering samples only. For production units, the processor core
frequency will be determined through the processor internal logic.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. A ll AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.7 V at the processor
edge fingers. All APIC I/O signal timings are referenced at 1.25 V at the processor edge fingers.
4. This specif ication applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Referenced to PICCLK rising edge.
6. For open drain signals, valid delay is synonymous with float delay.
7. Valid delay timings for these signals are specified to 2.5 V +5%.
Table 19. System Bus AC Specifications (Reset Conditions) (for the FC-PGA Package) 1
T# Parameter Min Max Unit Figure Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#)
Setup Time 4BCLKs7Before deassertion of
RESET#
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold
Time 220BCLKs7After clock that
deasserts RESET #
T18: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Setup Time 1ms7Before deassertion of
RESET#, 3
T19: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Delay Time 5BCLKs7After assertion of
RESET#, 2, 3
T20: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Hold Time 220BCLKs7After clock that
deasserts RESET#, 3
Table 20. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge
Fingers (for S.E.P. Package) 1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T21’: PICCLK Frequency 2.0 33.3 MHz
T22’: PICCLK Period 30.0 500.0 ns 3
T23’: PICCLK High Time 12.0 ns 3
T24’: PICCLK Low Time 12.0 ns 3
T25’: PICCLK Rise Time 0.25 3.0 ns 3
T26’: PICCLK Fall Time 0.25 3.0 ns 3
T27’: PICD[1:0] Setup Time 8.5 ns 55
T28’: PICD[1:0] Hold Time 3.0 ns 55
T29’: PICD[1:0] Valid Delay 3.0 12.0 ns 45, 6, 7
38 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
core pins. All APIC I/O signal timings are referenced at 1.25 V at the processor core pins.
4. This spec ification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. R eferenc ed to PICCLK rising edge.
6. For open drain signals, valid delay is synonymous with float delay.
7. Valid delay timings for these signals are specified to 2.5 V +5%.
8. Valid delay timings for these signals are specified to 1.5 V +5%.
Table 21. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core
Pins (For S.E.P. and PGA Packages) 1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T21: PICCLK Frequency 2.0 33.3 MHz
T22: PICCLK Period 30.0 500.0 ns 3
T23: PICCLK High Time
•S.E.P.P and PPGA
•FC-PGA 11.0
10.5 ns
ns 3
3@>2.0V
@>2.0V
T24: PICCLK Low Time
•S.E.P.P and PPGA
•FC-PGA 11.0
10.5 ns
ns 3
3@<0.5V
@<0.5V
T25: PICCLK Rise Time 0.25 3.0 ns 3(0.5V-2.0V)
T26: PICCLK Fall Time 0.25 3.0 ns 3(2.0V-0.5V)
T27: PICD[1:0] Setup Time
•S.E.P.P and PPGA
•FC-PGA 8.0
5.0 ns
ns 5
55
5
T28: PICD[1:0] Hold Time 2.5 ns 55
T29: PI CD[ 1:0] Valid Delay (S.E.P.P
and PPGA only) 1.5 10.0 ns 45, 6, 7
T29a: PICD[1:0] Valid Delay (Rising
Edge) (FC-PGA only) 1.5 8.7 ns 45, 6, 8
T29b: PICD[1:0] Valid Delay (Falling
Edge) (FC-PGA only) 1.5 12.0 ns 45, 6, 8
Datasheet 39
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel ®Celeron™ processor frequencies.
2. A ll AC timings for the TAP signals are referenced to the TCK rising edge at 0.70 V at the processor edge
fingers. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor edge fingers.
3. Not 100% tested. Specified by design characterization.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%.
8. Non- Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
Table 22. System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers
(For S.E.P. Package) 1, 2, 3, 4, 5
T# Parameter Min Max Unit Figure Notes
T30’: TCK Frequency 16.667 MHz
T31’: TCK Period 60.0 ns 3
T32’: TCK High T ime 25.0 ns 3@1.7 V
T33’: TCK Low Time 25.0 ns 3@0.7 V
T34’: TCK Rise Time 5.0 ns 3(0.7 V–1.7 V) 4
T35’: TCK Fall Time 5.0 ns 3(1.7 V–0.7 V) 4
T36’: TRST# Pulse Width 40.0 ns 6Asynchronous
T37’: TDI, TMS Setup Time 5.5 ns 95
T38’: TDI, TMS Hold Time 14.5 ns 95
T39’: TDO Valid Delay 2.0 13.5 ns 96, 7
T40’: TDO Float Delay 28.5 ns 96, 7
T41’: All Non-Test Outputs Valid
Delay 2.0 27.5 ns 96, 8, 9
T42’: All Non-Test Inputs Setup Time 27.5 ns 96, 8, 9
T43’: All Non-Test Inputs Setup Time 5.5 ns 95, 8, 9
T44’: All Non-Test Inputs Hold Time 14.5 ns 95, 8, 9
40 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. For the S.E.P. and PPGA packages: All AC timings for the T AP signals are referenced to the TCK rising edge
at 1.25 V at the processor core pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the
processor core pin s.
For the FC-PGA package: All AC timings for the T AP signals are referenced to the TCK rising edge at 0.75 V
at the processor pins. All TAP signal timings (TMS , TDI, etc.) are reference d at 0.75 V at the processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. For th e S.E.P. and PPGA packages: Valid delay timing for this signal is specified to 2.5 V +5%.
For the FC-PGA package: Valid delay timing for this signal is specified to 1.5 V +3%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. D uring Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.N ot 100% tested. Specified by design characterization.
Table 23. System Bus AC Specifications (TAP Connection) at the Processor Core Pins
(for Both S.E.P. and PPGA Packages) 1, 2, 3
T# Parameter Min Max Unit Figure Notes
T30: TCK Frequency 16.667 M Hz
T31: TCK Period 60.0 ns 3
T32: TCK High Time 25.0 ns 3@1.7 V 10
T33: TCK Low Time 25.0 ns 3@0.7 V 10
T34: TCK Rise Time 5.0 ns 3(0.7 V–1.7 V) 4, 10
T35: TCK Fall Time 5.0 ns 3(1.7 V–0.7 V) 4, 10
T36: TRST# Pulse Width 40.0 ns 6Asynchronous 10
T37: TDI, TMS Setup T ime 5.0 ns 95
T38: TDI, TMS Hold Time 14.0 ns 95
T39: TDO Valid Delay 1.0 10.0 ns 96, 7
T40: TDO Float Delay 25.0 ns 96, 7, 10
T41: All Non-Test Outputs Valid Delay 2.0 25.0 ns 96, 8, 9
T42: All Non-Test Inputs Setup Time 25.0 ns 96, 8, 9, 10
T43: All Non-Test Inputs Setup Time 5.0 ns 95, 8, 9
T44: All Non-Test Inputs Hold Time 13.0 ns 95, 8, 9
Datasheet 41
Intel® Celeron™ Processor up to 850 MHz
Note: For Figure 3 through Figure 10, the following apply:
1. Figure 3 through Figure 10 are to be used in conjunction with Table 9 through Table 23.
2. All AC timings for the AGTL+ signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the
processor edge fingers.
3. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK
rising edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are reference d at
1.00 V at the processor core pins.
4. All AC timings for the CMOS signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the
processor edge fingers.
5. All AC timings for the APIC I/O signals at the processor edge fingers are referenced to the
PICCLK rising edge at: 0.7 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA
package. All APIC I/O signal timings are referenced at 1.25 V for S.E.P. and PPGA packages
and 0.75 V for the FC-PGA package at the processor edge fingers.
6. All AC timings for the TAP signals at the processor edge fingers are referenced to the TCK
rising edge at 0.70 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA package. All
TA P signal timings (TMS, TDI, etc.) are referenced at 1.25 V for S.E.P. and PPGA packages
and 0.75 V for the FC-PGA package at the processor edge fingers.
Figure 2. BCLK to Core Logic Offset
Figure 3. BCLK*, PICCLK, and TCK Generic Clock Waveform
BCLK at
Edge Fingers 0.5V
BCLK at
Core Logic 1.25V
T1B'
Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK is referenced to 0.7 V and 1.7 V.
For S.E.P. and PPGA packages, TCK is referenced to 0.7 V and 1.7 V.
For the FC-PGA package, TCK is referenced to V
REF
±200mV.
1.7V (2.0V*) 1.25V
0.7V (0.5V*)
t
r
t
p
t
f
t
h
t
l
CLK
T
r
= T5, pT25, T34 (Rise Time)
T
f
= T6, T26, T35 (Fall Time)
T
h
= T3, T23, T32 (High Time)
T
l
= T4, T24, T33 (Low Time)
T
p
= T1, T22, T31 (BLCK, TCK, PICCLK Period)
42 Datasheet
Intel® Celeron™ Processor up to 850 MHz
Figure 4. System Bus Valid Delay Timings
Figure 5. System Bus Setup and Hold Timings
Figure 6. System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages)
V = 1.0V for AGTL+ signal group;
For S.E.P and PPGA packages, 1.25V for CMOS, APIC and JTAG signal groups
For FC-PGA package, 0.75V for CMOS, APIC and TAP signal groups
CLK
Signal Valid Valid
Tx
V
Tx
Tpw
Tx = T7, T11, T29a, T29b (Valid Delay)
Tpw = T14, T14B, T15 (Pulse Width)
CLK
Signal Valid
Ts
V
Th
Ts = T8, T12, T27 (Setup Time)
Th = T9, T13, T28 (Hold Time)
V = 1.0V for AGTL+ signal group;
For S.E.P. and PPGA packages, 1.25V for APIC and JTAG signal groups
For the FC-PGA package, 0.75V for APIC and TAP signal groups
Valid
Tv
TwTx
Tu
Tt
BCLK
RESET#
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
Tt= T9 (AGTL+ Input Hold Time)
Tu= T8 (AGTL+ Input Setup Time)
Tv= T10 (RESET# Pulse Width)
Tw= T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
Tx= T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
Datasheet 43
Intel® Celeron™ Processor up to 850 MHz
Figure 7. System Bus Reset and Configuration Timings (For the FC-PGA Package)
Figure 8. Power-On Reset and Configuration Timings
T
y
Safe Valid
T
z
Valid
T
v
T
w
T
x
T
u
T
t
BCLK
RESET#
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
T
t
= T9 (AGTL+ Input Hold Time)
T
u
= T8 (AGTL+ Input Setup Time)
T
v
= T10 (RESET# Pulse Width)
T
w
= T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
T
x
= T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
T
a
Valid Ratio
T
C
T
b
PWRGOOD
RESET#
Configuration
(A20M#, IGNNE#,
INTR, NMI)
T
a
= T15 (PWRGOOD Inactive Pulse)
T
b
= T10 (RESET# Pulse Width)
T
c
= T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) (FC-PGA)
BCLK
V
IL, max
V
IH, min
Vcc
CORE
, V
TT
,
V
REF
44 Datasheet
Intel® Celeron™ Processor up to 850 MHz
Figure 9. Test Timings (TAP Connection)
Figure 10. Test Reset Timings
TCK
DI, TMS
Input
Signals
TDO
Output
Signals
1
.25V
T
v
T
w
T
r
T
s
T
x
Tu
T
y
Tz
1
.25V
T
r
T4 3 (All Non-Test In p uts Se tup Time)
=
T
s
T44 (All Non-Test Inputs Hold Time)
=
T
u
T40 (TDO Float Delay)
=
T
v
T37 (TDI, TMS Setup Time)
=
T
w
T38 (TDI, TMS Hold Time)
=
T
x
T39 (TDO Valid Delay)
=
T
y
T41 (All Non-Test Outputs Valid Delay)
=
T
z
T42 (All Non-Test Outputs Float Delay)
=
TRST#
1
.25V
T
q
T
q
T37 (TRST# Pulse Wi dth)=
Datasheet 45
Intel® Celeron™ Processor up to 850 MHz
3.0 System Bus Signal Simulations
Signals driven on the Intel® Celeron™ processor system bus should meet signal quality
specifications to ensure that the components read data prop erly and to en sure that incoming s ignals
do not affect the long term reliability of the component. Specifications are provided for simulation
at the processor core; guidelines are provided for correlation to the processor edge fingers. These
edge finger guidelines are intended for use during testing and measurement of system signal
integrity . Violations of these guidelines are permitted, but if they occur , simulation of signal quality
at the processor core should be performed to ensure that no violations of signal quality
specifications occur. Meeting the specifications at the processor core in Table 24, Table 27, and
Table 30 ensures that s ignal q uali ty effects will not adversely affect processor operation, but does
not necessarily guarantee that the guidelines in Table 26, Table 29, and Table 31 will be met.
3.1 System Bus Clock (BCLK) Signal Quality Specifications
and Measurement Guidelines
Table 24 describes the BCLK signal quality specifications at the processor core for both S.E.P. and
PPGA Packages. Table 25 shows the BCLK and PICCLK signal quality specifications at th e
processor core for the FC-PGA package. Table 26 describes guidelin es f or signal quality
measurement at the processor edge fing ers. Figure 1 1 describes the signal quality waveform f or th e
system bus clock at the processor core pins; Figure 12 describes the signal quality waveform for
the system bus clock at the processor edge fingers.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot specification for 66 MHz
system bus operation.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Table 24. BCLK Signal Quality Specifications for Simulation at the Processor Core
(for Both S.E.P. and PPGA Packages)1
T# Parameter Min Nom Max Unit Figure Notes
V1: BCLK VIL 0.5 V 11
V2: BCLK VIH 2.0 V 11 2
V3: VIN Absolute Voltage Range –0.7 3.5 V 11 2
V4: Rising Edge Ringback 1.7 V 11 3
V5: Falling Edge Ringback 0.7 V 11 3
46 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to FC-PGA processors frequencies and cache
sizes.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
Table 25. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins
(for the FC-PGA Package) 1
T# Parameter Min Nom Max Unit Figure Notes
V1: BCLK VIL 0.50 V 11
V1: PICCLK VIL 0.70 V 11
V2: BCLK VIH 2.00 V 11
V2: PICCLK VIH 2.00 V 11
V3: VIN Absolute Voltage Range –0.58 3.18 V 11
V4: BCLK Rising Edge Ringback 2.00 V 11 2
V4: PICCLK Rising Edge Ringback 2.00 V 11 2
V5: BCLK Falling Edge Ringback 0.50 V 11 2
V5: PICCLK Falling Edge Ringback 0.70 V 11 2
Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins
V2
V1
V3
V3
T3
V5
V4
T6 T4 T5
Datasheet 47
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot measurement guideline.
3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal may dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
guideline is an absolute value.
4. The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The
midpoint voltage level of this ledge should be within the range of the guideline.
5. The ledge (V7) is allowed to have peak-to-peak oscillation as given in the guideline.
Table 26. BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package) 1
T# Parameter Min Nom Max Unit Figure Notes
V1’: BCLK VIL 0.5 V 12
V2’: BCLK VIH 2.0 V 12
V3’: VIN Absolute Voltage Range –0.5 3.3 V 12 2
V4’: Rising Edge Ringback 2.0 V 12 3
V5’: Falling Edge Ringback 0.5 V 12 3
V6’: Tline Ledge Voltage 1.0 1.7 V 12 At Ledge Midpoint 4
V7’: Tline Ledge Oscillation 0.2 V 12 Peak-to-Peak 5
Figure 12. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers
T3
V3
V5
V3
2
1
V7
V6
T6 T4 T5
V4
48 Datasheet
Intel® Celeron™ Processor up to 850 MHz
3.2 AGTL+ Signal Quality Specifications and Measurement
Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 24 333 0). R efer t o
the Pentium® II Processor Developer's Manual (Order Number 243502) for the AGTL+ buffer
specification.
Table 27 provides the AGTL+ signal quality specifications (for both the S.E.P. and PPGA
Packages) for use in simulating signal quality at the processor core. Table 28 provides the AGTL+
signal quality speci fi c ations (f or the FC-PGA Packages) for use in simulating signal quality at the
processor core. Table 29 provides AGTL+ signal quality guidelines for measu ri ng and testing
signal quality at the processor edge fingers. Figure 13 describes the signal quality waveform for
AGTL+ signals at the processor core and edge fingers. For more information on the AGTL+
interface, see the Pentium® II Processor Developer's Manual (Order Number 243502).
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
2. Specifications are for the edge rate of 0.3 - 0.8 V/ns. See Figure 13 for the generic waveform.
3. All values specified by design characterization.
4. This spec ification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. R ingback below VREF + 20 mV is not supported.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processo r frequencies.
2. Specifications are for the edge rate of 0.3 - 0.8V/ns. See Figure 13 for the generic waveform.
3. All values specified by design characterization.
4. See Table 32 for maximum allowable overshoot.
5. R ingback betwee n VREF + 100 mV and VREF + 200 mV or VREF - 200 mV and VREF - 100 mVs requires the
flight time measurements to be adjusted as described in the Intel AGTL+ Specifications (Intel®Pentium®II
Developers Ma nual). Ringback below VREF + 100 mV or above VREF - 100 mV is not supported.
6. Intel recommends simulations not exceed a ringback value of VREF ±200 mV to allow margin for other
sources of system noise.
7. A negative value for ρ indicates that the amplitude of ringback is above VREF. (i.e., φ = -100 mV specifies the
signal cannot ringback below VREF + 100 m V).
8. φ and ρ: are measured relative to VREF. α: is measured relative to VREF + 200 mV.
9. A ll Ringback entering the Overdrive Region must have flight time correction.
10.Overshoot specifications for Ringback do not correspond to Overshoot specifications in Section 3.4.
Table 27. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core
(For Both the S.E. P. and PP GA Packages) 1, 2, 3
T# Parameter Min Unit Figure Notes
α: Overshoot 100 mV 13 4
τ: Minimum Time at High 1.00 ns 13 4
ρ: Amplitude of Ringback –100 mV 13 4, 5
φ: Final Settling Voltage 100 mV 13 4
δ: Duration of Squarewave Ringback N/A ns 13
Table 28. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Pins
(For FC-PGA Packages) 1, 2, 3
T# Parameter Min Unit Figure Notes
α: Overshoot 100 mV 13 4, 8, 9, 10
τ: Minimum Time at High 0.50 ns 13 9
ρ: Amplitude of Ringback –200 mV 13 5, 6, 7, 8
φ: Final Settling Voltage 200 mV 13 8
δ: Duration of Squarewave Ringback N/A ns 13
Datasheet 49
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Unless otherwise noted, all guidelines in this table apply to all Intel® Celeron™ processor frequencies.
2. Guidelines are for the edge rate of 0.3 - 0.8 V/ns. See Figure 13 for the generic waveform.
3. A ll values specified by design characterization.
4. This guide line applies to Intel Celeron processors operating with a 66 MHz system bus only.
5. Ringback below VREF + 250 mV is not supported.
Table 29. AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger
Measurement on the S.E.P. Package 1, 2, 3
T# Parameter Min Unit Figure No tes
α’: Overshoot 100 mV 13
τ’: Minimum Time at High 1.5 ns 13 4
ρ’: Amplitude of Ringback –250 mV 13 4, 5
φ’: Final Settling Voltage 250 mV 13 4
δ’: Duration of Squarewave Ringback N/A ns 13
Figure 13. Low to High AGTL+ Receiver Ringback Tolerance
τ
α
ρ
φ
Vstart
V +0.2
REF
V
R
EF
V –0.2
REF
T
ime
C
lock
Note: High t o Low case is analogous.
δ
0
.7V Clk Ref
50 Datasheet
Intel® Celeron™ Processor up to 850 MHz
3.3 Non-AGTL+ Signal Quality Specifications and Measurement
Guidelines
There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in Figure 14 for the non-
AGTL+ signal group.
NOTES:
1. For the FC-PGA package, VHI = 1.5V for all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD.
VHI = 2.5 V for BCLK, PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in Section 3.1.
3.3.1 Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot/under shoot guideline limits transitions beyond VCC or VSS
due to the fast signal edge rates. (See Figure 14 for non-AGTL+ signals.) The processor can be
damaged by repeated overshoot events on the voltage tolerant buff ers if the charge is large enoug h
(i.e., if the overshoot is great enough). The PPGA and S.E.P. packages have 2.5V tolerant buffers
and the FC-PGA package has 1.5V or 2.5V tolerant buffers.
However, excessive ringback is the dominant det rimen tal system timing effect resulting from
overshoot/undershoot (i.e., violating the overshoot/undershoot guideline will make satisfying the
ringback specification dif ficult). The overshoot/undershoot g uideline is 0.7 V for the PPGA and
S.E.P. packages and 0.3 V for the FC-PGA package and assumes the absence of diodes on the
input. These guidelines should be verified in simulations without the on-chip ESD protection
diodes present because the diodes will begin clamping the signals (2.5 V tolerant signals for the
S.E.P. and PPGA package s, and 2.5 V or 1.5 V tolerant sign als for the FC-PGA p ackage) beginning
at approximately 0.7 V above the appropriate supply and 0.7 V below VSS. If signals are not
reaching the clamping voltage, this will not be an issue. A system should not rely on the diodes for
overshoot/under shoot protection as this will negatively affect the life of the components and make
meeting the ringback specification very difficult.
Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback
U
ndershoot
Overshoot Settling Limit
S
ettling Limit
R
ising-Edge
R
ingback Falling-Edge
Ringback
V
L
O
V
S
STime
V
H
I
Datasheet 51
Intel® Celeron™ Processor up to 850 MHz
3.3.2 Ringback Specification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. (See Figure 14 for an illustration of ringback.) Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ signals.
Ringback can be simulated with or with o ut the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See Table 30 for the signal ringback specifications for non-AGTL+ signals for simulations at the
processor core, and Table 31 for guidelines on measuring ringback at the edge fingers. Table 32
lists the ringback specifications for the FC-PGA package.
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Intel® Celeron™ processor frequencies.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all FC-PGA processor frequencies and cache
sizes.
Table 30. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Core (S.E.P. and PPGA Packages) 1
Input Signal Gro up Transition Maximum Ringback
(with Input Diodes Present) Un it Figure Notes
Non-AGTL+ Signals 0 → 11.7V14
Non-AGTL+ Signals 1 → 00.7V14
Table 31. Signal Ringback Guidel ines for Non-AGTL+ Signal Edge Finger Measurement
(S.E.P. Package) 1
Input Signal Gro up Transition Maximum Ringback
(with Input Diodes Present) Un it Figure Notes
Non-AGTL+ Signals 0 → 12.0V14
Non-AGTL+ Signals 1 → 00.7V14
Table 32. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Pins (FC-PGA Package) 1
Input Signal Group Transition Maximum Ringback
(with Input Diodes Present) Un it Figure
Non-AGTL+ Signals 0 → 1V
REF + 0.200 V 16
PWRGOOD 0
→ 1 2.0 V 16
Non-AGTL+ Signals 1 → 0V
REF - 0.200 V 16
52 Datasheet
Intel® Celeron™ Processor up to 850 MHz
3.3.3 Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10 percent of the total sig nal swing (VHI – VLO)
above and below its final value. A signal should be within the settling limits of its final value, when
either in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillation s wh ich coul d jeopard ize signal integrity. Simulatio ns to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
3.4 AGTL+ Signal Quality Specifications and Measurement
Guidelines (FC-PGA Package)
3.4.1 Overshoot/Undershoot Guidelines (FC-PGA Package)
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or bel ow VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates. The processor can be damaged by repeated overshoot events on 1.5 V or 2.5 V
tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining
the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse
direction and the activity f actor ( AF) . Perman ent damage to the processor is the likely result of
excessive overshoot/undershoot. Vio lating the overshoot/undershoo t guid eline will also make
satisfying the ringback specification difficult.
When performing simulations to determine impact of overshoot and overshoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not
clamp undershoo t or ov ers hoo t and will y ield correct s imul at ion res ult s . If other I/O buffer model s
are being used to characterize the FC-PGA processor performance, care must be taken to ensure
that ESD models do not clamp extreme voltage levels. Intel I/O Buffer models also contain I/O
capacitance characterization. Therefore, removing the ESD diodes from an I/O Buffer model will
impact results and may yield excessive overshoot/undershoot.
3.4.2 Overshoot/Undershoot Magnitude (FC-PGA Package)
Magnitude describes the maximum potential difference between a signal and its voltage reference
level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS
using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to
VTT. This can be accomplished by simultaneously measuring the VTT plane while measuring the
signal und ershoot . Today’s oscilloscopes can easily calculate the true undershoot waveform using a
Math function where the Signal waveform is subtracted from the VTT waveform. The true
undershoot waveform can also be obtained with the following oscilloscope data file analysis:
Converted Undershoot Waveform = VTT- Signal_measured
Note: The converted undershoot waveform appears as a positive (overshoot) signal.
Note: Overshoot (risi ng edge) and und ersh oo t (falli ng edge) condi tio ns are separate and their impact
must be determined independently.
Datasheet 53
Intel® Celeron™ Processor up to 850 MHz
After the true waveform conversion, the undershoot/overshoot specifications shown in Table 34
and Table 35 can be applied to the converted undershoot waveform using the same magnitude and
pulse duration specifications used with an overshoot waveform.
Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed
in Table 34 and Table 35. These specifications must not be violated at any time regardless of bus
activity or system state. Within these specifications are threshold levels that define different
allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the
Absolute Maximum Specifications (2.18V), the pulse magnitude, duration and activity factor must
all be used to determine if the oversho ot /und e rshoo t pulse is within specifications.
3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA Package)
Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/
undershoot reference voltage (Vos_ref = 1.635V). The total time could encompass several
oscillations above the referen ce voltage. Multiple overshoot/undershoo t pulses within a single
overshoot/undershoot event may need to be measured to determine the total pulse duration.
Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot
pulse dur ation.
Note: Multiple Overshoot/Undershoot events occurring within the same clock cycle must be consider ed
together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the
individual Pulse Durations to determine the total Overshoot/Undershoot Puls e Duration for that
total event.
3.4.4 Activity Factor (FC-PGA Package)
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of an AGTL+ or a CMOS signal is every other
clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY
OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot)
waveform occurs one time in every 200 clock cycles.
The specifications provided in Table 34 and Table 35 show the Maximum Pu lse Duration allowed
for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each Table entry is
independent of all others, meaning that the Pulse Duration reflects the existence of overshoot/
undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just
meets the pulse duration for a specific magnitude where the AF < 1, means that there can be NO
other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event
occurs at all times and no other events can occur).
Note: Activity factor for AGTL+ signals is referenced to BCLK frequenc y.
Note: Activity factor for CMOS signals is referenced to PICCLK frequency.
54 Datasheet
Intel® Celeron™ Processor up to 850 MHz
3.4.5 Reading Overshoot/Undershoot Specification Tables (FC-PGA
Package)
The overshoot/undershoot specification for the FC-PGA package processor is not a simple single
value. Instead, many factors are needed to determine the over/und ershoo t specification. In addition
to the magnitude of the overshoot, the following parameters must also be known: the junction
temperature the processo r will be operating, the width of the overshoot (a s m easured above
1.635 V) and the Activity Factor (AF). To determ ine the allowed overshoot for a particular
overshoot event, the following must be done:
1. Determine the signal gr oup that particul ar signal fa lls in to. If the signal is an AGTL+ signal
operating with a 66 MHz system bus, use Table 34 (66 MHz AGTL+ signal group). If the
signal is a CMOS signal, use Table 35 (33 MHz CMOS signal group).
2. Determine the maximum junction temperature (Tj) for the range of processors that the system
will support (80oC or 90oC).
3. Determine the Magnitude of the overshoot (relative to Vs s)
4. Determine th e Ac tivity Factor (how often does this overshoot occur?)
5. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns)
allowed.
6. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse
Duration measured is less than the Pulse Duration shown in the table, th en the sig nal meets the
specifications.
The above procedure is si mila r for un ders ho ot s afte r the un ders ho ot wave for m has been converted
to look like an overshoot. Undershoot events must be analyzed separately from Overshoot events
as they are mutually exclusive.
Table 33 shows an example of how the maximum pulse duration is determined for a given
waveform.
NOTES:
1. C orresponding Maximum Pulse Duration Specification - 3.2 ns
2. P ulse Durat ion (measured) - 2.0 ns
Given the above parameters, and using Table 34 (90oC/AF=0.1 column) the maximum allowed
pulse dur at ion i s 3. 2 ns. Since the measu red p ul s e dur atio n i s 2 .0n s, t h is par tic u lar overshoot ev ent
passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/
undershoot events meet the specifications.
Table 33. Example Platform Information
Required Information Maximum Platform Support Notes
FSB Signal Group 66 MHz AGTL+
Max Tj 90 °C
Overshoot Magnitude 2.13V M easured Value
Activity Factor (AF) 0.1 Measured overshoot occurs on
average every 20 clocks
Datasheet 55
Intel® Celeron™ Processor up to 850 MHz
3.4.6 Determining if a System meets the Overshoot/Undershoot
Specifications (FC-PGA Package)
The overshoot/undershoot specifications listed in the following tables specify the allowable
overshoot/undershoot for a single overshoot/undershoot ev ent. However most systems will ha ve
multiple overshoot and/or undershoot events that each have their own set of parameters (duration,
AF and magnitude). While each overshoot on its own may meet the overshoot specification, when
the total impact of all overshoot events is accou nted for, the system may fail. A gu ideline to ens ure
a system passes the overshoot and unders hoot specifications is s hown below. It is impor tant to meet
these guidelines; otherwise, contact your Intel field representative.
1. Insure no signal (CMOS or AGTL+) ever exceed the 1.635V; OR
2. If only on e oversh oot/u nder shoot ev ent magni tude occurs, ensure it meets the ov er/unders hoot
specifications in the follo wing tab les; OR
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse
duration for each magn itude and co mpare the results against the AF = 1 specifications . If all of
these worst case overshoot or undershoot events meet the specifications
(measured time < specifications) in the table (where AF=1), then the system passes.
The following notes apply to Table 34 and Table 35.
NOTES:
1. Overshoot/Undershoot Magnitude = 2.18V is an Absolute value and should never be exceeded
2. Overshoot is measured relative to VSS
3. Undershoot is measured relative to VTT
4. Overshoot/Un dershoot Pulse Duration is meas ured relati ve to 1.635V.
5. Ringbacks below VTT can not be subtracted from Overshoots/Undershoots.
6. Lesser Undershoot does not allocate longer or larger Overshoot.
7. Consult the appropriate layout guidelines provided in the specific platform design guide.
8. All values specified by design characterization.
NOTES:
1. BCLK period is 30.0 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
Table 34. 66 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins
(FC-PGA Package) 1, 2
Overshoot/
Undershoot
Magnitude
Maximum Pulse Duration at Tj = 80 °C
(ns) Maximum Pulse Duration at Tj = 90 °C
(ns)
AF = 0.01 AF = 0.1 AF = 1 AF = 0.01 AF = 0.1 AF = 1
2.18 V 30 3.8 0.38 18 1.8 0.18
2.13 V 30 7.4 0.74 30 3.2 0.32
2.08 V 30 13.6 1.36 30 6.4 0.64
2.03 V 30 25 2.5 30 12 1.1
1.98 V 30 30 4.56 30 22 2
1.93 V 30 30 8.2 30 30 3.8
1.88 V 30301530306.8
56 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. P ICC LK period is 30 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
Table 35. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins
(FC-PGA Package) 1, 2
Overshoot/
Undershoot
Magnitude
Maximum Pulse Duration at Tj = 80 °C
(ns) Maximum Pulse Duration at Tj = 90 °C
(ns)
AF = 0.01 AF = 0.1 AF = 1 AF = 0.01 AF = 0.1 AF = 1
2.18 V 60 7. 6 0.76 36 3.6 0.36
2.13 V 60 14.8 1.48 60 6.4 0.64
2.08 V 60 27.2 2.7 60 12.8 1.2
2.03 V 60 50 5 60 24 2. 2
1.98 V 60 60 9.1 60 44 4
1.93 V 60 60 16. 4 60 60 7.6
1.88 V 606030606013.6
Figure 15. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
(FC-PGA Package)
Vss
Undershoot
Magnitude = V
TT
- Signal
Overshoot
Magnitude = Signal - Vss
V
TT
2.18V
2.08V
1.98V
1.88V
1.635V
Max
Overshoot
Magnitude
Time Dependent
Overshoot Converted Undershoot
Waveform
Undershoot
Magnitude
Time Dependent
Undershoot
Datasheet 57
Intel® Celeron™ Processor up to 850 MHz
4.0 Thermal Specifications and Design Considerations
This section provides needed data for designing a thermal solution. However, for the correct
thermal measuring processes, refer to AP-905, Intel® Pentium® III Processor Thermal Design
Guidelines (Order Number 245087). For the FC-PGA using flip chip pin grid array packaging
technology, Intel specifies the junction temperature (Tjunction). For the S.E.P. package and PPGA
package, Intel specifies the case temperature (Tcase).
4.1 Thermal Specifications
Table 36 and Table 37 provide both the Processor Power and Heat Sink Design Target for Intel®
Celeron™ processors. Processor Power is defined as the total power dissipated by the processor
core and its package. Therefore, the S.E.P. Package’s Processor Power would also include power
dissipated by the AGTL+ termination resistors. The overall system chassis thermal design must
comprehend the entire Processor Power. The Heat Sink Design Target consists of only the
processor core, which dissipates th e majority of the thermal power.
Systems should design for the highest possible thermal power, even if a processor with a lower
thermal dissipation is planne d. The processo r’s heatslug is the attach location for all therm a l
solutions. The maximum and minimum case temperatures are also specified in Table 36 and
Table 37. A thermal solution should be designed to ensure the temperature of the case never
exceeds these specifications. Refer to the “developer.intel.com” site for more information.
NOTES:
1. These values are specif ied at nominal VCCCORE for the processor core.
2. Processor Power is power generated from the S.E.P. Package’s substrate, which includes the processor core
and the AGTL+ termination resistors.
3. Heat Sink Design Target refers to the power consumption of the processor core.
Table 36. Processor Power for the S.E.P. Package 1
Processor Core
Frequency
(MHz)
L2 Cache
Size
(KB)
Processor
Power
(W)2
Heat Sink
Design Target
(W)3Minimum TCASE
(°C) Maximum TCASE
(°C)
266 0 16.6 16.0 5 85
300 0 18.4 17.8 5 85
300A 128 18.4 17.8 5 85
333 128 20.2 19.7 5 85
366 128 22.2 21.7 5 85
400 128 24.2 23.7 5 85
433 128 24.6 24.1 5 85
58 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. These values are specified at nominal VCCCORE for the processor core.
2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to
dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the
maximum Tjunction specification.
3. FC -P GA package only.
4. The Thermal Design Power (TDP) Celeron™ processors in production has been redefined. The updated
TDP values are based on device characterization and do not reflect any silicon design changes to lower
processor power consumption. The TDP values represent the thermal design point required to cool
Celeron™ processors in the platform environment while executing thermal validation type software.
5. Power density is the maximum power the processor die can dissipate (i.e., processor power) divided by the
die area over which the power is generated. Power for these processors is generated from the core area
shown in Figure 16.
6. Tjunctionoffset is the worst-case difference between the thermal reading from the on-die thermal diode and the
hottest location on the processor ’s core. Tjunctionoffset values do not include any thermal diode kit
measurement error. Diode kit measurement error must be added to the Tjunctionoffset value from the table.
Intel has characterized the use of the Analog Devices AD1021 diode measurement kit and found its
measurement error to be ±1 oC.
7. For processors with a CPUID of 0683h, the TDP number is 11.2W.
8. For processors with a CPUID of 0683h, the TDP number is 11.9W.
9. For processors with a CPUID of 0683h, the TDP number is 12.6W.
Figure 16 is a block diagram of the Intel Celeron FC-PGA processor die layout. The layout
differentiates the processor core from the cache die area. In effect, the thermal design power
identified in Table 37 is dissipated entirely from the processor core area. Thermal solution designs
should compensate for this smaller heat flux area and not assume that the power is uniformly
distributed across the entire die area.
Table 37. Processor Power for the PPGA and FC-PGA Packages 1
Processor
Core
Frequency
(MHz)
L2 Cache
Size
(KB)
Thermal
Design
Power
(TDP)2
(W)
Power
Density 5
(W/cm2)
Up to
CPUID
0683h
Power
Density 5
(W/cm2)
For
CPUID
0686h
Min TCASE
(°C) Max TCASE
(°C) Max
TJUNCTION
(°C)
Min
TJUNCTION
(°C)
TJUNCTION
Offset 6
(°C)
300A 128 17.8 NA NA 5 85 NA NA NA
333 128 19.7 NA NA 5 85 NA NA NA
366 128 21.7 NA NA 5 85 NA NA NA
400 128 23.7 NA NA 5 85 NA NA NA
433 128 24.1 NA NA 5 85 NA NA NA
466 128 25.6 NA NA 5 70 NA NA NA
500 128 27.0 NA NA 5 70 NA NA NA
533 128 28.3 NA NA 5 70 NA NA NA
533A3128 14.04,7 15.4417.54NA NA 90 0 2.5
5663128 14.94,8 16.4418.54NA NA 90 0 2.6
6003128 15.84,9 17.4419.74NA NA 90 0 2.6
633 128 16.5422.7425.84NA NA 82 0 2.6
667 128 17.5424.1427.34NA NA 82 0 2.6
700 128 18.3425.2428.64NA NA 80 0 2.7
733 128 19.1426.3429.84NA NA 80 0 2.8
766 128 20.0427.5431.34NA NA 80 0 3.0
800 128 20.8428.7432.64NA NA 80 0 3.0
850 128 22.5431.0435.24NA NA 80 0 3.3
Datasheet 59
Intel® Celeron™ Processor up to 850 MHz
4.1.1 Thermal Diode
The Intel® Celeron™ Processor incorporates an on-die diode that can be used to monitor the die
temperature. A thermal sensor located on the motherboard or a standalone measurement kit may
monitor the die temperature of the Intel Celeron processor for thermal management purposes.
Table 38 to Table 40 provide the diode parameter and interface specifications.
Note: The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the
temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor, on-
die temperature gradients between the location of the thermal diode and the hottest location on the
die at a given point in time, and time based variations in the die temperature measurement. Time
based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is
slower than the rate at which the Tjunction temperature can change.
Figure 16. Processor Functional Die Layout (CPUID 0686h)
Figure 17. Processor Functional Die Layout (up to CPUID 0683h)
Cache Area
0.04 in2
0.337”
0.275”
0.146”
0.414”Core Area
0.10 in2
Die Area
0.14 in2
Die Area = 0.90 cm2
Cache Area = 0.26 cm2
Core Area = 0.64 cm2
Cache Area
0.05 in2
0.362”
0.292”
0.170”
0.448”Core Area
0.11 in2
Die Area
0.16 in2
Die Area = 1.05 cm2
Cache Area = 0.32 cm2
Core Area = 0.73 cm2
60 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. A t room temperature with a forward bias of 630 mV.
3. n _ideality is the diode ideality factor parameter, as represented by the diode equation:
I-Io(e (Vd*q)/(nkT) - 1).
4. N ot 100% tested. Specified by design characterization.
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. C haract erized at 100° C with a forward bias current of 5–300 µA.
3. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:
Ifw=Is(e^ ((Vd*q)/(nkT)) - 1), where Is = saturation current, q = electronic charge, Vd = voltage across the
diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).
4. N ot 100% tested. Specified by design characterization.
Table 38. Thermal Diode Parameters (S.E.P. and PPGA Packages) 4
Symbol Min Typ Max Unit Notes
Iforward bias 5 500 uA 1
n_ideality 1.0000 1.0065 1.0173 2,3
Table 39. Thermal Diode Parameters (FC-PGA Package) 1
Symbol Min Typ Max Unit Notes
Iforward bias 5 300 uA 1
n_ideality 1. 0057 1.0080 1.0125 2, 3
Table 40. Thermal Diode Interface
Pin Nam e SC242 Connector
Signal # 370-Pin Socket Pin # Pin Description
THERMDP B14 AL31 diode anode (p junction)
THERMDN B15 AL29 diode cathode (n junction)
Datasheet 61
Intel® Celeron™ Processor up to 850 MHz
5.0 Mechanical Specifications
There are three package technologies which Intel® Celeron™ processors use. They are the S.E.P.
Package, the PPGA package, and the FC-PGA package. Th e S. E.P. Package and FC-PGA package
contain the processor core and passive components, while the PPGA package does not have
passive components.
The processor edge connector defined in this document is referred to as the “SC242 connector.”
See the SC242 Design Guidelines (Order Number 243397) for further details on the edge
connector.
The processor socket connector is defined in this document is referred to as the “370-pin socket.”
See the 370-Pin S ocket (PGA370) Desi gn Guidelines (Ord er Number 244 410) for further d etails on
the socket.
5.1 S.E.P. Package
This section defines the mechanical specifications and signal definitions for the Intel® Cele ron ™
processor in the S.E.P. Package.
5.1.1 Materials Information
The Intel® Celeron™ processor requires a retention mechanism. This retention mechanism may
require motherboard h oles to be 0.1 59" d iameter if low cos t plastic fastener s are u sed to secure the
retention mechanisms. Th e larger diameter holes are necessary to pro vide a robust structur al design
that can shock and vi be testing. If cap tive nuts are us ed in place o f the plastic fastener s, th en either
the 0.159" or the 0.140" diameter holes will suffice as long as the attach mount is used.
Figure 18 with su bstrat e dimen sions is p rov id e d to aid in the design of a heat sink and clip. In
Figure 19 all area on the secondary side of the substrate is zoned “keep out”, except for 25 mils
around the tooling holes and the top and side edges of the substrate.
62 Datasheet
Intel® Celeron™ Processor up to 850 MHz
5.1.2 Signal Listing (S.E.P. Pack age)
Table 41 and Table 42 provide the processor edge finger and SC242 connector signal definitio ns
for Intel® Celeron™ processor. The signal locations on the SC242 edge connector are to be used
for signal routing, simulation, and component placement on the motherboard.
Figure 18. Processor Substrate Dimensions (S.E.P. Package)
Figure 19. Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)
-Y-
1.660
.615
1.196
3.804 .814
.323
2.608
1.370
-Y-
27.4 mm SR
Opening Square 25.4 mm Copper
Slug Square
-Z-
-Y- .062 +.007
-.005
-E-
-D-
-G-
-H-
-E-
-D-
-G-
-H-
Typ Max.
Non-Keepout Area
.025 Typ Max.
Non-Keepout Area
.025
Typ Max.
Non-Keepout Area
.025 Typ Max.
Non-Keepout Area
.025
Secondary Side
Primary Side
There Will be No Components on
Secodonary Side
Datasheet 63
Intel® Celeron™ Processor up to 850 MHz
T able 41. S.E.P. Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
A1 VTT Power/Other
A2 VSS Power/Other
A3 VTT Power/Other
A4 IERR# CMOS Output
A5 A20M# CMOS Input
A6 VSS Power/Other
A7 FERR# CM O S Output
A8 IGNNE# CMOS Input
A9 TDI TAP Input
A10 VSS Power/Other
A11 TDO TAP Output
A12 PWRGOOD CMOS Input
A13 TES TH I C M O S Test Input
A14 VSS Power/Other
A15 THER MTRIP# CMOS Outpu t
A16 Reserved Reserved for Future Use
A17 LINT0/INTR CMOS Input
A18 VSS Power/Other
A19 PICD0 APIC I/O
A20 PREQ# CM O S Input
A21 BP3# A GTL+ I/O
A22 VSS Power/Other
A23 BPM0# AGTL+ I/O
A24 Reserved Reserved for Pentium II
processor
A25 Reserved Reserved for Pentium II
processor
A26 VSS Power/Other
A27 Reserved Reserved for Pentium II
processor
A28 Reserved Reserved for Pentium II
processor
A29 Reserved Reserved for Pentium II
processor
A30 VSS Power/Other
A31 Reserved Reserved for Pentium II
processor
A32 D61# AGTL+ I/O
A33 D55# AGTL+ I/O
A34 VSS Power/Other
A35 D60# AGTL+ I/O
A36 D53# AGTL+ I/O
A37 D57# AGTL+ I/O
A38 VSS Power/Other
A39 D46# AGTL+ I/O
A40 D49# AGTL+ I/O
A41 D51# AGTL+ I/O
A42 VSS Power/Other
A43 D42# AGTL+ I/O
A44 D45# AGTL+ I/O
A45 D39# AGTL+ I/O
A46 VSS Power/Other
A47 Reserved Reserved for Future Use
A48 D43# AGTL+ I/O
A49 D37# AGTL+ I/O
A50 VSS Power/Other
A51 D33# AGTL+ I/O
A52 D35# AGTL+ I/O
A53 D31# AGTL+ I/O
A54 VSS Power/Other
A55 D30# AGTL+ I/O
A56 D27# AGTL+ I/O
A57 D24# AGTL+ I/O
A58 VSS Power/Other
A59 D23# AGTL+ I/O
A60 D21# AGTL+ I/O
A61 D16# AGTL+ I/O
A62 VSS Power/Other
A63 D13# AGTL+ I/O
A64 D11# AGTL+ I/O
A65 D10# AGTL+ I/O
A66 VSS Power/Other
A67 D14# AGTL+ I/O
A68 D9# AGTL+ I/O
A69 D8# AGTL+ I/O
A70 VSS Power/Other
A71 D5# AGTL+ I/O
A72 D3# AGTL+ I/O
A73 D1# AGTL+ I/O
A74 VSS Power/Other
A75 BCLK System Bus Clock Input
A76 Reserved Reserved for Pentium II
processor
T able 41. S.E.P. Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Ty pe
64 Datasheet
Intel® Celeron™ Processor up to 850 MHz
A77 Reserved Reserved for Pentium II
processor
A78 VSS Power/Other
A79 Reserved Reserved for Pentium II
processor
A80 Reserved Reserved for Pentium II
processor
A81 A30# AGTL+ I/O
A82 VSS Power/Other
A83 A31# AGTL+ I/O
A84 A27# AGTL+ I/O
A85 A22# AGTL+ I/O
A86 VSS Power/Other
A87 A23# AGTL+ I/O
A88 Reserved Reserved for Future Use
A89 A19# AGTL+ I/O
A90 VSS Power/Other
A91 A18# AGTL+ I/O
A92 A16# AGTL+ I/O
A93 A13# AGTL+ I/O
A94 VSS Power/Other
A95 A14# AGTL+ I/O
A96 A10# AGTL+ I/O
A97 A5# AGTL+ I/O
A98 VSS Power/Other
A99 A9# AGTL+ I/O
A100 A4# AGTL+ I/O
A101 BNR# AGTL+ I/O
A102 VSS Power/Other
A103 BPRI# A GTL+ Input
A104 TRDY# AGTL+ Input
A105 DEFER# AGTL+ Input
A106 VSS Power/Other
A107 RE Q2# AGTL+ I/O
A108 RE Q3# AGTL+ I/O
A109 HITM# AGTL+ I/O
A110 VSS Power/Other
A111 DBSY# AGTL+ I/ O
A112 RS1# AGTL+ Input
A113 Reserved Reserved for Future Use
A114 VSS Power/Other
T able 41. S.E.P. Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
A115 ADS# AGTL+ I/O
A116 Reserved Reserved for Future Use
A117 Reserved Reserved for Pentium II
processor
A118 VSS Power/Other
A119 VID2 Power/Other
A120 VID1 Power/Other
A121 VID4 Power/Other
B1 EMI Power/Other
B2 FLUSH# CMOS Input
B3 SMI# CMOS Input
B4 INIT# CMOS Input
B5 VTT Power/Other
B6 STPCLK# CMOS Input
B7 TCK TAP Input
B8 SLP# CMOS Input
B9 VTT Power/Other
B10 TMS TAP Input
B13 VCCCORE Power/Other
B14 THERMDP Power/Other
B15 THERMDN Power/Other
B16 LINT1/NMI CMOS Input
B17 VCCCORE Power/Other
B18 PICCLK APIC Clock Input
B19 BP2# A GTL+ I/O
B20 Reserved Reserved for Futur e Use
B21 BSEL Power/Other
B22 PICD1 APIC I/O
B23 PR DY# AGTL+ Output
B24 BPM1# AGTL+ I/O
B25 VCCCORE Power/Other
B26 Reserved Reserved for Pentium II
processor
B27 Reserved Reserved for Pentium II
processor
B28 Reserved Reserved for Pentium II
processor
B29 VCCCORE Power/Other
B30 D62# AGTL+ I/O
B31 D58# AGTL+ I/O
B32 D63# AGTL+ I/O
B33 VCCCORE Power/Other
T able 41. S.E.P. Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
Datasheet 65
Intel® Celeron™ Processor up to 850 MHz
B34 D56# AGTL+ I/O
B35 D50# AGTL+ I/O
B36 D54# AGTL+ I/O
B37 VCCCORE Power/Other
B38 D59# AGTL+ I/O
B39 D48# AGTL+ I/O
B40 D52# AGTL+ I/O
B41 EMI Power/Other
B42 D41# AGTL+ I/O
B43 D47# AGTL+ I/O
B44 D44# AGTL+ I/O
B45 VCCCORE Power/Other
B46 D36# AGTL+ I/O
B47 D40# AGTL+ I/O
B48 D34# AGTL+ I/O
B49 VCCCORE Power/Other
B50 D38# AGTL+ I/O
B51 D32# AGTL+ I/O
B52 D28# AGTL+ I/O
B53 VCCCORE Power/Other
B54 D29# AGTL+ I/O
B55 D26# AGTL+ I/O
B56 D25# AGTL+ I/O
B57 VCCCORE Power/Other
B58 D22# AGTL+ I/O
B59 D19# AGTL+ I/O
B60 D18# AGTL+ I/O
B61 EMI Power/Other
B62 D20# AGTL+ I/O
B63 D17# AGTL+ I/O
B64 D15# AGTL+ I/O
B65 VCCCORE Power/Other
B66 D12# AGTL+ I/O
B67 D7# AGTL+ I/O
B68 D6# AGTL+ I/O
B69 VCCCORE Power/Other
B70 D4# AGTL+ I/O
B71 D2# AGTL+ I/O
B72 D0# AGTL+ I/O
B73 VCCCORE Power/Other
T able 41. S.E.P. Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
B74 RESET# AGTL+ Input
B75 Reserved Reserved for Future Use
B76 Reserved Reserved for Future Use
B77 VCCCORE Power/Other
B78 Reserved Reserved for Pentium II
processor
B79 Reserved Reserved for Pentium II
processor
B80 A29# AGTL+ I/O
B81 EMI Power/Other
B82 A26# AGTL+ I/O
B83 A24# AGTL+ I/O
B84 A28# AGTL+ I/O
B85 VCCCORE Power/Other
B86 A20# AGTL+ I/O
B87 A21# AGTL+ I/O
B88 A25# AGTL+ I/O
B89 VCCCORE Power/Other
B90 A15# AGTL+ I/O
B91 A17# AGTL+ I/O
B92 A11# AGTL+ I/O
B93 VCCCORE Power/Other
B94 A12# AGTL+ I/O
B95 A8# AGTL+ I/O
B96 A7# AGTL+ I/O
B97 VCCCORE Power/Other
B98 A3# AGTL+ I/O
B99 A6# AGTL+ I/O
B100 EMI Power/Other
B101 SLOTOCC# Power/Other
B102 REQ0# AGTL+ I/O
B103 REQ1# AGTL+ I/O
B104 REQ4# AGTL+ I/O
B105 VCCCORE Power/Other
B106 LOCK# AGTL+ I/O
B107 DRDY# AGTL+ I/O
B108 RS0# AGTL+ Input
B109 VCC5Power/Other
B11 TRST# TAP Input
B110 HIT# AGTL+ I/O
B111 RS2# AGTL+ I nput
T able 41. S.E.P. Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Ty pe
66 Datasheet
Intel® Celeron™ Processor up to 850 MHz
B112 Reserved Reserved for Future Use
B113 VCCL2 Power/Other. Reserved
for Pent ium II processor
B114 Reserved Reserved for Pentium II
processor
B115 Reserved Reserved for Pentium II
processor
B116 Reserved Reserved for Pentium II
processor
T able 41. S.E.P. Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
B117 VCCL2 Power/Oth e r. Reserved
for Pentium II processor
B118 Reserved Reserved for Pentium II
processor
B119 VID3 Power/Other
B12 Reserved Reserved for Futur e Use
B120 VID0 Power/Other
B121 VCCL2 Power/ Oth e r. Rese r ved
for Pentium II processor
T able 41. S.E.P. Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
Datasheet 67
Intel® Celeron™ Processor up to 850 MHz
T able 42. S.E.P. Package Signal Listing
by Signal Name
Pin Nam e Pin
No. Signal Buf fer Type
A3# B98 AGTL+ I/ O
A4# A100 AGTL+ I/O
A5# A97 AGTL+ I/ O
A6# B99 AGTL+ I/ O
A7# B96 AGTL+ I/ O
A8# B95 AGTL+ I/ O
A9# A99 AGTL+ I/ O
A10# A96 AGTL+ I/O
A11# B92 AGTL+ I/O
A12# B94 AGTL+ I/O
A13# A93 AGTL+ I/O
A14# A95 AGTL+ I/O
A15# B90 AGTL+ I/O
A16# A92 AGTL+ I/O
A17# B91 AGTL+ I/O
A18# A91 AGTL+ I/O
A19# A89 AGTL+ I/O
A20# B86 AGTL+ I/O
A20M# A5 CMOS Input
A21# B87 AGTL+ I/O
A22# A85 AGTL+ I/O
A23# A87 AGTL+ I/O
A24# B83 AGTL+ I/O
A25# B88 AGTL+ I/O
A26# B82 AGTL+ I/O
A27# A84 AGTL+ I/O
A28# B84 AGTL+ I/O
A29# B80 AGTL+ I/O
A30# A81 AGTL+ I/O
A31# A83 AGTL+ I/O
ADS# A115 AGTL+ I/O
BCLK A75 System Bus Cl ock In put
BNR# A101 AGTL+ I/O
BP2# B19 AGTL+ I/O
BP3# A21 AGTL+ I/O
BPM0# A23 AGTL+ I/O
BPM1# B24 AGTL+ I/O
BPRI# A103 AGTL+ Input
BSEL B21 Power/Other
D00# B72 A GTL+ I/O
D1# A73 AGTL+ I/O
D2# B71 AGTL+ I/O
D3# A72 AGTL+ I/O
D5# A71 AGTL+ I/O
D6# B68 AGTL+ I/O
D7# B67 AGTL+ I/O
D8# A69 AGTL+ I/O
D9# A68 AGTL+ I/O
D10# A65 A GTL+ I/O
D11# A64 A GTL+ I/O
D12# B66 A GTL+ I/O
D13# A63 A GTL+ I/O
D14# A67 A GTL+ I/O
D15# B64 A GTL+ I/O
D16# A61 A GTL+ I/O
D17# B63 A GTL+ I/O
D18# B60 A GTL+ I/O
D19# B59 A GTL+ I/O
D20# B62 A GTL+ I/O
D21# A60 A GTL+ I/O
D22# B58 A GTL+ I/O
D23# A59 A GTL+ I/O
D24# A57 A GTL+ I/O
D25# B56 A GTL+ I/O
D26# B55 A GTL+ I/O
D27# A56 A GTL+ I/O
D28# B52 A GTL+ I/O
D29# B54 A GTL+ I/O
D30# A55 A GTL+ I/O
D31# A53 A GTL+ I/O
D32# B51 A GTL+ I/O
D33# A51 A GTL+ I/O
D34# B48 A GTL+ I/O
D35# A52 A GTL+ I/O
T able 42. S.E.P. Package Signal Listing
by Signal Name
Pin Name Pin
No. Signal Buffer Type
68 Datasheet
Intel® Celeron™ Processor up to 850 MHz
D36# B46 AGTL+ I/O
D37# A49 AGTL+ I/O
D38# B50 AGTL+ I/O
D39# A45 AGTL+ I/O
D4# B 70 AG TL+ I/O
D40# B47 AGTL+ I/O
D41# B42 AGTL+ I/O
D42# A43 AGTL+ I/O
D43# A48 AGTL+ I/O
D44# B44 AGTL+ I/O
D45# A44 AGTL+ I/O
D46# A39 AGTL+ I/O
D47# B43 AGTL+ I/O
D48# B39 AGTL+ I/O
D49# A40 AGTL+ I/O
D50# B35 AGTL+ I/O
D51# A41 AGTL+ I/O
D52# B40 AGTL+ I/O
D53# A36 AGTL+ I/O
D54# B36 AGTL+ I/O
D55# A33 AGTL+ I/O
D56# B34 AGTL+ I/O
D57# A37 AGTL+ I/O
D58# B31 AGTL+ I/O
D59# B38 AGTL+ I/O
D60# A35 AGTL+ I/O
D61# A32 AGTL+ I/O
D62# B30 AGTL+ I/O
D63# B32 AGTL+ I/O
DBSY# A111 AGTL+ I/O
DEFER# A105 AGTL+ Input
DRDY# B107 AGTL+ I/O
EMI B1 Power/Other
EMI B41 Power/Other
EMI B61 Power/Other
EMI B81 Power/Other
EMI B100 Power/Other
T able 42. S.E.P. Package Signal Listing
by Signal Name
Pin Name Pin
No. Signal Buff e r Type
FERR# A7 CMOS Output
FLUSH# B2 CMOS Input
HIT# B110 AGTL+ I/O
HITM# A109 AGTL+ I/O
IERR# A4 CMOS Output
IGNNE# A8 CMOS Input
INIT# B4 CMOS Input
LINT0/INTR A17 CMOS Input
LINT1/NMI B16 CMOS Input
LOCK# B 106 AGTL+ I/O
PICCLK B18 APIC Clock Input
PICD0 A19 AP IC I/O
PICD1 B22 AP IC I/O
PRDY# B23 AGTL+ Output
PREQ# A20 CMOS Input
PWRGOOD A12 CMOS Input
REQ0# B102 AGTL+ I/O
REQ1# B103 AGTL+ I/O
REQ2# A107 AGTL+ I/O
REQ3# A108 AGTL+ I/O
REQ4# B104 AGTL+ I/O
Reserved A16 Reserved for Future Use
Reserved A47 Reserved for Future Use
Reserved A77 Reserved for Pentium II
processor
Reserved A88 Reserved for Future Use
Reserved A116 Reserv ed for Future Use
Reserved B12 Reserved for Future Use
Reserved A113 Reserv ed for Future Use
Reserved B20 Reserved for Future Use
Reserved B76 Reserved for Future Use
Reserved B112 Reserv ed for Future Use
Reserved B79 Reserved for Pentium II
processor
Reserved B114 Reserved for Pentium II
processor
Reserved B115 Reserved for Pentium II
processor
T able 42. S.E.P. Package Signal Listing
by Signal Name
Pin Nam e Pin
No. Signal Buffer Type
Datasheet 69
Intel® Celeron™ Processor up to 850 MHz
Reserved A117 Reserved for Pentium II
processor
Reserved B116 Reserved for Pentium II
processor
Reserved A24 Reserved for Pentium II
processor
Reserved A76 Reserved for Pentium II
processor
Reserved B75 Reserved for Future Use
Reserved A79 Reserved for Pentium II
processor
Reserved A80 Reserved for Pentium II
processor
Reserved B78 Reserved for Pentium II
processor
Reserved B118 Reserved for Pentium II
processor
Reserved A25 Reserved for Pentium II
processor
Reserved A27 Reserved for Pentium II
processor
Reserved B26 Reserved for Pentium II
processor
Reserved A28 Reserved for Pentium II
processor
Reserved B27 Reserved for Pentium II
processor
Reserved A29 Reserved for Pentium II
processor
Reserved A31 Reserved for Pentium II
processor
Reserved B28 Reserved for Pentium II
processor
RESET# B74 AGTL+ Input
RS0# B108 AGTL+ Input
RS1# A112 AGTL+ Input
RS2# B111 AGTL+ Input
SLOTOCC# B101 Power/Other
SLP# B8 CMOS Input
SMI# B3 CMOS Input
STPCLK# B6 CMOS Input
TCK B7 TAP Input
TDI A9 TAP Input
TDO A11 TAP Outpu t
T able 42. S.E.P. Package Signal Listing
by Signal Name
Pin Nam e Pin
No. Signal Buf fer Type
TESTHI A13 CMOS Test Input
THERMDN B15 Power/Other
THERMDP B14 Power/Other
THERMTRIP# A15 CMOS Output
TMS B10 TAP Input
TRDY# A104 AGTL+ Input
TRST# B11 TAP Input
VCC5B109 Power/Other
VCCCORE B13 Power/Other
VCCCORE B17 Power/Other
VCCCORE B25 Power/Other
VCCCORE B29 Power/Other
VCCCORE B33 Power/Other
VCCCORE B37 Power/Other
VCCCORE B45 Power/Other
VCCCORE B49 Power/Other
VCCCORE B53 Power/Other
VCCCORE B57 Power/Other
VCCCORE B65 Power/Other
VCCCORE B69 Power/Other
VCCCORE B73 Power/Other
VCCCORE B77 Power/Other
VCCCORE B85 Power/Other
VCCCORE B89 Power/Other
VCCCORE B93 Power/Other
VCCCORE B97 Power/Other
VCCCORE B105 Power/Other
VCCL2 B113 Power/Other. Reserved
for Pentium II processor
VCCL2 B117 Power/Other. Reserved
for Pentium II processor
VCCL2 B121 Power /Other. Reserved
for Pentium II processor
VID0 B120 Power/Other
VID1 A120 Power/Other
VID2 A119 Power/Other
VID3 B119 Power/Other
VID4 A121 Power/Other
VSS A114 Power/Other
T able 42. S.E.P. Package Signal Listing
by Signal Name
Pin Name Pin
No. Signal Buffer Type
70 Datasheet
Intel® Celeron™ Processor up to 850 MHz
VSS A118 Power/Other
VSS A46 Power/Other
VSS A38 Power/Other
VSS A42 Power/Other
VSS A50 Power/Other
VSS A54 Power/Other
VSS A58 Power/Other
VSS A62 Power/Other
VSS A66 Power/Other
VSS A70 Power/Other
VSS A74 Power/Other
VSS A78 Power/Other
VSS A82 Power/Other
VSS A86 Power/Other
VSS A2 Power/Other
VSS A6 Power/Other
T able 42. S.E.P. Package Signal Listing
by Signal Name
Pin Name Pin
No. Signal Buff e r Type
VSS A10 Power/Other
VSS A14 Power/Other
VSS A18 Power/Other
VSS A22 Power/Other
VSS A26 Power/Other
VSS A30 Power/Other
VSS A34 Power/Other
VSS A98 Power/Other
VSS A102 Power/Other
VSS A106 Power/Other
VSS A110 Power/Other
VTT A1 Power/Other
VTT A3 Power/Other
VTT B5 Power/Other
VTT B9 Power/Other
T able 42. S.E.P. Package Signal Listing
by Signal Name
Pin Nam e Pin
No. Signal Buffer Type
Datasheet 71
Intel® Celeron™ Processor up to 850 MHz
5.2 PPGA Package
This section defines the mechanical specifications and signal definitions for the Intel® Cele ron ™
processor in the PPGA packages.
5.2.1 PPGA Package Materials Information
Figure 20 and Table 43 are provided to aid in the design of a heat sink and clip.
Figure 20. Package Dimensions (PPGA Package)
D1
D
D
S1
B1 B2
Heat Slug Solder Resist
D2
A1
L
Seating Plane
e1
φ
B
AA2
Side View
Bottom View Top View
45° x 0.085
72 Datasheet
Intel® Celeron™ Processor up to 850 MHz
Table 43. Package Dimensions (PPGA Package)
Millimeters Inches
Symbol Min Max Notes Min Max Notes
A 1.83 2.23 0.072 0.088
A1 1.00 0.039
A2 2.72 3.33 0.107 0.131
B 0.40 0.51 0.016 0.020
D 49.43 49.63 1.946 1.954
D1 45.59 45.85 1.795 1.805
D2 25.15 25.65 0.099 1.010
e1 2.29 2.79 0.090 0.110
L 3.05 3.30 0.120 0.130
N 370 Lead Count 370 Lead Count
S1 1.52 2.54 0.060 0.100
Table 44. Information Summary (PPGA Package)
Package Type Total Pins Pin Array Package Size
Plastic Staggered Pin Grid Array (PPGA) 370 37 x 37 1.95" x 1.95"
4.95 cm x 4.95 cm
Datasheet 73
Intel® Celeron™ Processor up to 850 MHz
5.2.2 PPGA Package Signal Listing
Figure 21. PPGA Package (Pin Side View)
A13#
A16#
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
VSS
VCC
VSS
D35#
D29#
D33#
D26#
D28#
D21# D23#
D25#
VSS
VCC
VSS
D31#
VCC
D43#
VCC VSS
D34#
D38#
VCC
VSS
D39#
D36#
VCC
D37# D44#
VCC VCC D32# D22# Rsvd D27#
VSS
D42#
D45# D49#
VSS
VCC D63# VREF1 VSS VCC VSS VCC VSS VCC VSS VCC VSS
VCC VSS VCC VSS V
CORE
DET
Rsvd D62# Rsvd Rsvd Rsvd VREF0 BPM1# BP3#
D41# D52# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC
D40# D59# D55# D54# D58# D50# D56# Rsvd Rsvd Rsvd BPM0# CPUPRES#
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC Rsvd
D51# D47# D48# D57# D46# D53# D60# D61# Rsvd Rsvd Rsvd PRDY# VSS
BP2# Rsvd Rsvd
VCC VSS VCC
PICCLK PICD0 PREQ#
VCC VCC VSS
Rsvd PICD1 LINT1
VCC VSS LINT0
Rsvd Rsvd Rsvd
VSS VCC VSS
Rsvd Rsvd Rsvd
VCC VSS VCC
Rsvd Rsvd Rsvd
VSS VCC VSS
PLL2 Rsvd Rsvd
VCC VSS VCC
VSS VCC VSS
VCC VSS V2.5
Rsvd Rsvd VCC
VSS VCC VCMOS
VSS FERR# Rsvd
VCC VSS V1.5
A20M# IERR# FLUSH#
VSS VCC VSS
INIT#
VSS VCC VSS
PLL1 Rsvd BCLK
STPCLK# IGNNE#
VSS D16# D19#
D7# D30# VCC
VCC VREF2 D24#
D13# D20# VSS
VSS D11# D3#
D2# D14# VCC
VCC D18# D9#
D12# D10# VSS
Rsvd D17# VREF3
D8# D5# VCC
VCC D1# D6#
D4# D15# VSS
VSS Rsvd VREF4
D0# Rsvd VCC
Rsvd RESET# Rsvd
Rsvd A26# VSS
VSS A29# A18#
A27# A30# VCC
VCC A24# A23#
Rsvd A20# VSS
VSS A31# VREF5
A17# A22# VCC
VCC Rsvd A25#
EDGCTRL A19# VSS
VSS Rsvd A10# A5# A8# A4# BNR# REQ1# REQ2# Rsvd RS1# VCC RS0# THERMTRIP# SLP# VCC VSS VCC
A21# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS BSEL# SMI# VID3
VCC VSS A28# A3# A11# VREF6 A14# Rsvd REQ0# LOCK# VREF7 Rsvd PWRGD RS2# Rsvd TMS VCC VSS
VSS VSS A15# A9# Rsvd Rsvd A7# REQ4# REQ3# Rsvd HITM# HIT# DBSY# THRMDN THRMDP TCK VID0 VID2
VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VID1
VSS A12# A6# Rsvd Rsvd Rsvd BPRI# DEFER# Rsvd Rsvd TRDY# DRDY# BR0# ADS# TRST# TDI TDO
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10111213141516171819202122 23 24252627282930313233 34353637
1 2 3 4 5 6 7 8 9 10111213141516171819202122 23 24252627282930313233 34353637
74 Datasheet
Intel® Celeron™ Processor up to 850 MHz
Table 45. PPGA Package Signal Lis ting
by Pin Number
Pin
No. Pin Name Signal Buffer Type
A3 D29# AGTL+ I/O
A5 D28# AGTL+ I/O
A7 D43# AGTL+ I/O
A9 D37# AGTL+ I/O
A11 D44# AGTL+ I/O
A13 D51# AGTL+ I/O
A15 D47# AGTL+ I/O
A17 D48# AGTL+ I/O
A19 D57# AGTL+ I/O
A21 D46# AGTL+ I/O
A23 D53# AGTL+ I/O
A25 D60# AGTL+ I/O
A27 D61# AGTL+ I/O
A29 Reserv ed Reserved for Future Use
A31 Reserv ed Reserved for Future Use
A33 Reserv ed Reserved for Future Use
A35 PRDY# AGTL+ Output
A37 VSS Power/Other
AA1 A27# AGTL+ I/O
AA3 A30# AGTL+ I/O
AA5 VCCCORE Power/Other
AA33 Reserved Reserved for Future Use
AA35 Reserved Reserved for Future Use
AA37 VCCCORE Power/Other
AB2 VCCCORE Power/Other
AB4 A24# AGTL+ I/O
AB6 A23# AGTL+ I/O
AB32 VSS Power/Other
AB34 VCCCORE Power/Other
AB36 VCCCMOS Power/Other
AC1 R eserv ed Reserved for Future Use
AC3 A20# AGTL+ I/O
AC5 VSS Power/Other
AC33 VSS Power/Other
AC35 FERR# CMOS Output
AC37 Reserved Reserved for Future Use
AD2 VSS Power/Other
AD4 A31# AGTL+ I/O
AD6 VREF5Power/Other
AD32 VCCCORE Power/Other
AD34 VSS Power/Other
AD36 VCC1.5 Power/Other
AE1 A17# A GTL+ I/O
AE3 A22# A GTL+ I/O
AE5 VCCCORE Power/Other
AE33 A20M# CMOS Input
AE35 IERR# CMOS Output
AE37 FLU SH# CMOS Input
AF2 VCCCORE Power/Other
AF4 Reserved Reserved for Future Use
AF6 A25# AGTL+ I/O
AF32 VSS Power/Other
AF34 VCCCORE Power/Other
AF36 VSS Power/Other
AG1 EDGCTRL Power/Other
AG3 A19# AGTL+ I/O
AG5 VSS Power/Other
AG33 INIT# CM O S Input
AG35 STPCLK # CMOS Input
AG37 IGNNE# CMOS Input
AH2 VSS Power/Other
AH4 Reserved Reserved for Future Use
AH6 A10# AGTL+ I/O
AH8 A5# AG TL+ I/ O
AH10 A8# AGTL+ I/ O
AH12 A4# AGTL+ I/ O
AH14 BNR# AG TL+ I/ O
AH16 REQ1# AGTL+ I/O
AH18 REQ2# AGTL+ I/O
AH20 Reserved Reserved for Future Use
AH22 RS1# A G TL+ Input
AH24 VCCCORE Power/Other
AH26 RS0# A G TL+ Input
AH28 THERMTRI P# CMO S Output
AH30 SLP# CMOS Input
Table 45. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
Datasheet 75
Intel® Celeron™ Processor up to 850 MHz
AH32 VCCCORE Power/Other
AH34 VSS Power/Other
AH36 VCCCORE Power/Other
AJ01 A21# AGTL+ I/O
AJ03 VSS Power/Other
AJ05 VCCCORE Power/Other
AJ07 VSS Power/Other
AJ09 VCCCORE Power/Other
AJ11 VSS Power/Other
AJ13 VCCCORE Power/Other
AJ15 VSS Power/Other
AJ17 VCCCORE Power/Other
AJ19 VSS Power/Other
AJ21 VCCCORE Power/Other
AJ23 VSS Power/Other
AJ25 VCCCORE Power/Other
AJ27 VSS Power/Other
AJ29 VCCCORE Power/Other
AJ31 VSS Power/Other
AJ33 BSEL Power/Other
AJ35 SM I# CMOS Input
AJ37 VID3 Power/Other
AK02 VCCCORE Power/Other
AK04 VSS Power/Other
AK06 A28# AGTL+ I/O
AK08 A3# AGTL+ I/O
AK10 A11# AG TL+ I/O
AK12 VREF6 Power/Other
AK14 A14# AGTL+ I/O
AK16 Reserved Reserved for Future Use
AK18 REQ0# A GTL+ I/O
AK20 LOCK# AGTL+ I/O
AK22 VREF7 Power/Other
AK24 Reserved Reserved for Future Use
AK26 PWRGOOD CMOS Input
AK28 RS2# AG TL+ Input
AK30 Reserved Reserved for Future Use
AK32 TMS TA P Input
Table 45. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
AK34 VCCCORE Power/Other
AK36 VSS Power/Other
AL01 VSS Power/Other
AL03 VSS Power/Other
AL05 A15# AGTL+ I/O
AL07 A13# AGTL+ I/O
AL09 A9# AGTL+ I/O
AL11 Reserved Reserved for Future Use
AL13 Reserved Reserved for Future Use
AL15 A7# AGTL+ I/O
AL17 REQ4# AGTL+ I/O
AL19 REQ3# AGTL+ I/O
AL21 Reserved Reserved for Future Use
AL23 HITM# AGTL+ I/O
AL25 HIT# AGTL+ I/O
AL27 DBSY# AGTL+ I/O
AL29 THERMDN Power/Other
AL31 THERMDP Power/Other
AL33 TCK TAP Input
AL35 VID0 Voltage Identification
AL37 VID2 Voltage Identification
AM04 VCCCORE Power/Other
AM06 VSS Power/Other
AM08 VCCCORE Power/Other
AM10 VSS Power/Other
AM12 VCCCORE Power/Other
AM14 VSS Power/Other
AM16 VCCCORE Power/Other
AM18 VSS Power/Other
AM2 VSS Power/Other
AM20 VCCCORE Power/Other
AM22 VSS Power/Other
AM24 VCCCORE Power/Other
AM26 VSS Power/Other
AM28 VCCCORE Power/Other
AM30 VSS Power/Other
AM32 VCCCORE Power/Other
AM34 VSS Power/Other
Table 45. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
76 Datasheet
Intel® Celeron™ Processor up to 850 MHz
AM36 VID1 Voltage Identification
AN3 VSS Power/Other
AN5 A12# AGTL+ I/O
AN7 A16# AGTL+ I/O
AN9 A6# AGTL+ I/O
AN11 Reserv ed Reserved for Future Use
AN13 Reserved Reserved for Future Use
AN15 Reserved Reserved for Future Use
AN17 BPRI# AGTL+ Input
AN19 DEFER# AGTL+ Input
AN21 Reserved Reserved for Future Use
AN23 Reserved Reserved for Future Use
AN25 TRDY# AGTL+ Input
AN27 DRDY# AGTL+ I/O
AN29 BR0# AGTL+ I/O
AN31 ADS# AGTL+ I/O
AN33 TRST# TAP Input
AN35 TDI TAP Input
AN37 TDO TAP Output
B2 D35# AGTL+ I/O
B4 VSS Power/Other
B6 VCCCORE Power/Other
B8 VSS Power/Other
B10 VCCCORE Power/Other
B12 VSS Power/Other
B14 VCCCORE Power/Other
B16 VSS Power/Other
B18 VCCCORE Power/Other
B20 VSS Power/Other
B22 VCCCORE Power/Other
B24 VSS Power/Other
B26 VCCCORE Power/Other
B28 VSS Power/Other
B30 VCCCORE Power/Other
B32 VSS Power/Other
B34 VCCCORE Power/Other
B36 Reserv ed Reserved for Future Use
C1 D33# AGTL+ I/O
Table 45. PPGA Package Signal Lis ting
by Pin Number
Pin
No. Pin Name Signal Buffer Type
C3 VCCCORE Power/Other
C5 D31# AGTL+ I/O
C7 D34# AGTL+ I/O
C9 D36# AGTL+ I/O
C11 D45# A GTL+ I/O
C13 D49# AGTL+ I/O
C15 D40# AGTL+ I/O
C17 D59# AGTL+ I/O
C19 D55# AGTL+ I/O
C21 D54# AGTL+ I/O
C23 D58# AGTL+ I/O
C25 D50# AGTL+ I/O
C27 D56# AGTL+ I/O
C29 Reserved Reserved for Future Use
C31 Reserved Reserved for Future Use
C33 Reserved Reserved for Future Use
C35 BPM0# AGTL+ I/O
C37 CPUPRES# Power/Other
D2 VSS Power/Other
D4 VSS Power/Other
D6 VCCCORE Power/Other
D8 D38# AGTL+ I/O
D10 D39# AGTL+ I/O
D12 D42# AGTL+ I/O
D14 D41# AGTL+ I/O
D16 D52# AGTL+ I/O
D18 VSS Power/Other
D20 VCCCORE Power/Other
D22 VSS Power/Other
D24 VCCCORE Power/Other
D26 VSS Power/Other
D28 VCCCORE Power/Other
D30 VSS Power/Other
D32 VCCCORE Power/Other
D34 VSS Power/Other
D36 VCCCORE Power/Other
E1 D26# AGTL+ I/O
E3 D25# AGTL+ I/O
Table 45. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
Datasheet 77
Intel® Celeron™ Processor up to 850 MHz
E5 VCCCORE Power/Other
E7 VSS Power/Other
E9 VCCCORE Power/Other
E11 VSS Power/Other
E13 VCCCORE Power/Other
E15 VSS Power/Other
E17 VCCCORE Power/Other
E19 VSS Power/Other
E21 VCOREDET Power/Other
E23 Reserved Reserved for Future Use
E25 D62# Power/Other
E27 Reserved Reserved for Future Use
E29 Reserved Reserved for Future Use
E31 Reserved Reserved for Future Use
E33 VREF0 Power/Other
E35 BPM1# AGTL+ I/O
E37 BP3# AGTL+ I/O
F2 VCCCORE Power/Other
F4 VCCCORE Power/Other
F6 D32# AGTL+ I/O
F8 D22# AGTL+ I/O
F10 Reserved Reserved for Future Use
F12 D27# AGTL+ I/O
F14 VCCCORE Power/Other
F16 D63# AGTL+ I/O
F18 VREF1 Power/Other
F20 VSS Power/Other
F22 VCCCORE Power/Other
F24 VSS Power/Other
F26 VCCCORE Power/Other
F28 VSS Power/Other
F30 VCCCORE Power/Other
F32 VSS Power/Other
F34 VCCCORE Power/Other
F36 VSS Power/Other
G1 D21# A G TL+ I/O
G3 D23# A G TL+ I/O
G5 VSS Power/Other
Table 45. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
G33 BP2# AGTL+ I/O
G35 Reserved Reserved for Future Use
G37 Reserved Reserved for Future Use
H2 VSS Power/Other
H4 D16# AGTL+ I/O
H6 D19# AGTL+ I/O
H32 VCCCORE Power/Other
H34 VSS Power/Other
H36 VCCCORE Power/Other
J1 D7# AGTL+ I/ O
J3 D30# AGTL+ I/O
J5 VCCCORE Power/Other
J33 PICCLK APIC Clock Input
J35 PICD0 APIC I/O
J37 PREQ# CMOS Input
K2 VCCCORE Power/Other
K4 VREF2 Power/Other
K6 D24# AGTL+ I/O
K32 VCCCORE Power/Other
K34 VCCCORE Power/Other
K36 VSS Power/Other
L1 D13# AGTL+ I/O
L3 D20# AGTL+ I/O
L5 VSS Power/Other
L33 Reserved Reserved for Future Use
L35 PICD1 APIC I/O
L37 LINT1/NMI CMOS Input
M2 VSS Power/Other
M4 D11# AGTL+ I /O
M6 D3# AGTL+ I/O
M32 VCCCORE Power/Other
M34 VSS Power/Other
M36 LINT0/INTR CMOS Input
N1 D2# AGTL+ I/O
N3 D14# AGTL+ I/O
N5 VCCCORE Power/Other
N33 Reserved Reserved for Future Use
N35 Reserved Reserved for Future Use
Table 45. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
78 Datasheet
Intel® Celeron™ Processor up to 850 MHz
N37 Reserv e d Reserved for Future Use
P2 VCCCORE Power/Other
P4 D18# AGTL+ I/O
P6 D9# AGTL+ I/O
P32 VSS Power/Other
P34 VCCCORE Power/Other
P36 VSS Power/Other
Q1 D12# AGTL+ I/O
Q3 D10# AGTL+ I/O
Q5 VSS Power/Other
Q33 Reserved Reserved for Fu ture Use
Q35 Reserved Reserved for Fu ture Use
Q37 Reserved Reserved for Fu ture Use
R2 Reserved Reserved for Future Use
R4 D17# AGTL+ I/O
R6 VREF3 Power/Other
R32 VCCCORE Power/Other
R34 VSS Power/Other
R36 VCCCORE Power/Other
S1 D8# AGTL+ I/O
S3 D5# AGTL+ I/O
S5 VCCCORE Power/Other
S33 Reserv ed Reserved for Future Use
S35 Reserv ed Reserved for Future Use
S37 Reserv ed Reserved for Future Use
T2 VCCCORE Power/Other
T4 D1# AGTL+ I/O
T6 D6# AGTL+ I/O
T32 VSS Power/Other
T34 VCCCORE Power/Other
T36 VSS Power/Other
U1 D4# AGTL+ I/O
U3 D15# AGTL+ I/O
Table 45. PPGA Package Signal Lis ting
by Pin Number
Pin
No. Pin Name Signal Buffer Type
U5 VSS Power/Other
U33 PLL2 Power/Other
U35 Reserved Reserved for Future Use
U37 Reserved Reserved for Future Use
V2 VSS Power/Other
V4 Reserved Reserved for Future Use
V6 VREF4 Power/Other
V32 VCCCORE Power/Other
V34 VSS Power/Other
V36 VCCCORE Power/Other
W1 D0# A GTL+ I/O
W3 Reserved Reserved for Future Use
W5 VCCCORE Power/Other
W33 PLL1 Power/Other
W35 Reserved Reserved for Future Use
W37 BCLK System Bus Clock Input
X2 Reserved Reserved for Future Use
X4 RESET# AGTL+ Input
X6 Reserved Reserved for Future Use
X32 VSS Power/Other
X34 VCCCORE Power/Other
X36 VSS Power/Other
Y1 Reserved Reserved for Future Use
Y3 A26# AG TL+ I/ O
Y5 VSS Power/Other
Y33 VSS Power/Other
Y35 VCCCORE Power/Other
Y37 VSS Power/Other
Z2 VSS Power/Other
Z4 A29# AGTL+ I/O
Z6 A18# AGTL+ I/O
Z32 VCCCORE Power/Other
Z34 VSS Power/Other
Z36 VCC2.5 Power/Other
Table 45. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
Datasheet 79
Intel® Celeron™ Processor up to 850 MHz
Table 46. PPGA Package Signal Listing
in Order by Signal Name
Pin Name Pin
No. Signal Buffer Type
A3# AK8 AGTL+ I/O
A4# AH1 2 AGT L + I/O
A5# AH8 AGTL+ I/O
A6# AN9 AGTL+ I/O
A7# AL15 AGTL+ I/O
A8# AH1 0 AGT L + I/O
A9# AL9 AGTL+ I/O
A10# AH6 AGTL+ I/O
A11# AK10 AGTL+ I/O
A12# AN5 AGTL+ I/O
A13# AL7 AGTL+ I/O
A14# AK14 AGTL+ I/O
A15# AL5 AGTL+ I/O
A16# AN7 AGTL+ I/O
A17# AE1 AGTL+ I/O
A18# Z6 AGTL+ I/O
A19# AG3 A GTL+ I/O
A20# AC3 AGTL+ I/O
A21# AJ1 AGTL+ I/O
A22# AE3 AGTL+ I/O
A23# AB6 AGTL+ I/O
A24# AB4 AGTL+ I/O
A25# AF6 AGTL+ I/O
A26# Y3 AGTL+ I/O
A27# AA1 AGTL+ I/O
A28# AK6 AGTL+ I/O
A29# Z4 AGTL+ I/O
A30# AA3 AGTL+ I/O
A31# AD4 AGTL+ I/O
A20M# AE33 CMOS Input
ADS# AN31 AGTL+ I/O
BCLK W37 System Bus Clock Input
BNR# AH14 AGTL+ I/O
BP2# G33 AGTL+ I/O
BP3# E37 AGTL+ I/O
BPM0# C35 AGTL+ I/O
BPM1# E35 AGTL+ I/O
BPRI# AN17 A GTL+ Input
BR0# AN29 AGTL+ I/O
BSEL AJ33 Power/Other
CPUPRES# C37 Power/Other
D0# W1 AGTL+ I/O
D1# T4 AGTL+ I/O
D2# N1 A GTL+ I/O
D3# M6 AGTL+ I/O
D4# U1 A GTL+ I/O
D5# S3 AGTL+ I/O
D6# T6 AGTL+ I/O
D7# J1 AGTL+ I/O
D8# S1 AGTL+ I/O
D9# P6 AGTL+ I/O
D10# Q3 AGTL+ I/O
D11# M4 A G TL+ I/O
D12# Q1 AGTL+ I/O
D13# L1 AGTL+ I/O
D14# N3 A GTL+ I/O
D15# U3 A GTL+ I/O
D16# H4 A GTL+ I/O
D17# R4 A GTL+ I/O
D18# P4 AGTL+ I/O
D19# H6 A GTL+ I/O
D20# L3 AGTL+ I/O
D21# G1 AGTL+ I/O
D2 2 # F8 AGTL+ I/O
D23# G3 AGTL+ I/O
D24# K6 AGTL+ I/O
D25# E3 AGTL+ I/O
D26# E1 AGTL+ I/O
D27# F12 A GTL+ I/O
D28# A5 AGTL+ I/O
D29# A3 AGTL+ I/O
D30# J3 AG TL+ I/O
D31# C5 A GTL+ I/O
D3 2 # F6 AGTL+ I/O
D33# C1 A GTL+ I/O
D34# C7 A GTL+ I/O
D35# B2 AGTL+ I/O
D36# C9 A GTL+ I/O
D37# A9 AGTL+ I/O
D38# D8 A GTL+ I/O
Table 46. PPGA Package Signal Listing
in Order by Signal Name
Pin Name Pin
No. Signal Buffer Type
80 Datasheet
Intel® Celeron™ Processor up to 850 MHz
D39# D10 AGTL+ I/O
D40# C15 AGTL+ I/O
D41# D14 AGTL+ I/O
D42# D12 AGTL+ I/O
D43# A7 AGTL+ I/O
D44# A11 AGTL+ I/O
D45# C11 AGTL+ I/O
D46# A21 AGTL+ I/O
D47# A15 AGTL+ I/O
D48# A17 AGTL+ I/O
D49# C13 AGTL+ I/O
D50# C25 AGTL+ I/O
D51# A13 AGTL+ I/O
D52# D16 AGTL+ I/O
D53# A23 AGTL+ I/O
D54# C21 AGTL+ I/O
D55# C19 AGTL+ I/O
D56# C27 AGTL+ I/O
D57# A19 AGTL+ I/O
D58# C23 AGTL+ I/O
D59# C17 AGTL+ I/O
D60# A25 AGTL+ I/O
D61# A27 AGTL+ I/O
D62# E25 AGTL+ I/O
D63# F16 AGTL+ I/O
DBSY# AL27 AGTL+ I/O
DEFER# AN19 AGTL+ Input
DRDY# AN27 AGTL+ I/O
EDGCTRL AG1 Power/Other
FERR# AC35 CMOS Output
FLUSH# AE37 CMOS Input
HIT# AL25 AGTL+ I/O
HITM# AL23 AGTL+ I/O
IERR# AE35 CMOS Output
IGNNE# AG37 CMOS Input
INIT# AG33 CMOS Input
LINT0/INTR M36 CMOS Input
LINT1/NMI L37 CMOS Input
LOCK# AK20 AGTL+ I/O
PICCLK J33 AP IC Clock Input
Table 46. PPGA Package Signal Lis ting
in Order by Signal Name
Pin Nam e Pin
No. Signal Buffer Type
PICD0 J35 APIC I/O
PICD1 L35 APIC I/O
PLL1 W33 Power/Other
PLL2 U33 Power/Other
PRDY# A 35 AGTL+ Output
PREQ# J37 CMOS Input
PWRGOOD AK26 CMOS Input
REQ0 # AK1 8 AGTL+ I/O
REQ1 # A H 1 6 AGT L + I/O
REQ2 # A H 1 8 AGT L + I/O
REQ3 # A L 1 9 A GT L + I/O
REQ4 # A L 1 7 A GT L + I/O
Reserved AC1 Reserved for Future Use
Reserved AC37 Reserved for Future Use
Reserved AF4 Reserved for Future Use
Reserved AK16 Reserved for Future Use
Reserved AK24 Reserved for Future Use
Reserved AK30 Reserved for Future Use
Reserved AL11 Reserved for Future Use
Reserved AL13 Reserved for Future Use
Reserved AL21 Reserved for Future Use
Reserved AN11 Reserved for Future Use
Reserved AN13 Reserved for Future Use
Reserved AN15 Reserved for Future Use
Reserved AN21 Reserved for Future Use
Reserved AN23 Reserved for Future Use
Reserved B36 Reserved for Future Use
Reserved C29 Reserved for Future Use
Reserved C31 Reserved for Future Use
Reserved C33 Reserved for Future Use
Reserved E23 Reserved for Future Use
Reserved E29 Reserved for Future Use
Reserved E31 Reserved for Future Use
Reserved F10 Reserved for Futur e Use
Reserved G35 Reserved for Futur e Use
Reserved G37 Reserved for Futur e Use
Reserved L33 Reserved for Future Use
Reserved N33 Reserved for Future Use
Reserved N35 Reserved for Future Use
Reserved N37 Reserved for Future Use
Table 46. PPGA Package Signal Listing
in Or d e r by Si gn al Name
Pin Name Pin
No. Signal Buffer Type
Datasheet 81
Intel® Celeron™ Processor up to 850 MHz
Reserved Q33 Reserved for Future Use
Reserved Q35 Reserved for Future Use
Reserved Q37 Reserved for Future Use
Reserved S33 Reserved for Future Use
Reserved S37 Reserved for Future Use
Reserved U35 Reserved for Future Use
Reserved U37 Reserved for Future Use
Reserved V4 Reserved for Future Use
Reserved W3 Reserved for Future Use
Reserved W35 Reserved for Future Use
Reserved AH20 Reserved for Future Use
Reserved AH4 Reserved for Future Use
Reserved A29 Reserved for Future Use
Reserved A31 Reserved for Future Use
Reserved A33 Reserved for Future Use
Reserved AA33 Reserved for Future Use
Reserved AA35 Reserved for Future Use
Reserved X6 Reserved for Future Use
Reserved Y1 Reserved for Future Use
Reserved E27 Reserved for Future Use
Reserved R2 Reserved for Future Use
Reserved S35 Reserved for Future Use
Reserved X2 Reserved for Future Use
RESET# X4 AGTL+ Input
RS0# AH26 AGTL+ Input
RS1# AH22 AGTL+ Input
RS2# AK28 A GTL+ Input
SLP# A H30 CMOS Input
SMI# AJ35 CM O S Input
STPCLK# AG35 C M O S Input
TCK AL33 TAP Input
TDI AN35 TAP Input
TDO AN37 TAP Output
THERMDN AL29 Power/Other
THERMDP AL31 Power/Other
THERMT RIP# AH28 CMOS Output
TMS AK32 TAP Input
TRDY# AN25 AGTL+ Input
TRST# AN33 TAP Input
VCC1.5 AD36 Power/Other
Table 46. PPGA Package Signal Listing
in Order by Signal Name
Pin Name Pin
No. Signal Buffer Type
VCC2.5 Z36 Power/Other
VCCCMOS AB36 Power/Other
VCCCORE AJ25 Power/Other
VCCCORE AJ29 Power/Other
VCCCORE AJ5 Power/Other
VCCCORE AJ9 Power/Other
VCCCORE AK2 Power/Other
VCCCORE AK34 Power/Other
VCCCORE AM12 Power/Other
VCCCORE AM16 Power/Other
VCCCORE AM20 Power/Other
VCCCORE AM24 Power/Other
VCCCORE AM28 Power/Other
VCCCORE AM32 Power/Other
VCCCORE AM4 Power/Other
VCCCORE AM8 Power/Other
VCCCORE B10 Power/Other
VCCCORE B14 Power/Other
VCCCORE B18 Power/Other
VCCCORE B22 Power/Other
VCCCORE B26 Power/Other
VCCCORE B30 Power/Other
VCCCORE B34 Power/Other
VCCCORE B6 Power/Other
VCCCORE C3 Power/Other
VCCCORE D20 Power/Other
VCCCORE D24 Power/Other
VCCCORE D28 Power/Other
VCCCORE D32 Power/Other
VCCCORE D36 Power/Other
VCCCORE D6 Power/Other
VCCCORE E13 Power/Other
VCCCORE E17 Power/Other
VCCCORE E5 Power/Other
VCCCORE E9 Power/Other
VCCCORE F14 Power/Other
VCCCORE F2 Power/Other
VCCCORE F22 Power/Other
VCCCORE F26 Power/Other
VCCCORE AA37 Power/Other
Table 46. PPGA Package Signal Listing
in Order by Signal Name
Pin Name Pin
No. Signal Buffer Type
82 Datasheet
Intel® Celeron™ Processor up to 850 MHz
VCCCORE AA5 Power/Other
VCCCORE AB2 Power/Other
VCCCORE AB34 Power/Other
VCCCORE AD32 Power/Other
VCCCORE AE5 Power/Other
VCCCORE AF2 Power/Other
VCCCORE AF34 Power/Other
VCCCORE AH24 Power/Other
VCCCORE AH32 Power/Other
VCCCORE AH36 Power/Other
VCCCORE AJ13 Power/Other
VCCCORE AJ17 Power/Other
VCCCORE AJ21 Power/Other
VCCCORE F30 Power/Other
VCCCORE F34 Power/Other
VCCCORE F4 Power/Other
VCCCORE H32 Power/Other
VCCCORE H36 Power/Other
VCCCORE J5 Power/Other
VCCCORE K2 Power/Other
VCCCORE K32 Power/Other
VCCCORE K34 Power/Other
VCCCORE M32 Power/Other
VCCCORE N5 Power/Other
VCCCORE P2 Power/Other
VCCCORE P34 Power/Other
VCCCORE R32 Power/Other
VCCCORE R36 Power/Other
VCCCORE S5 Power/Other
VCCCORE T2 Power/Other
VCCCORE T34 Power/Other
VCCCORE V32 Power/Other
VCCCORE V36 Power/Other
VCCCORE W5 Power/Other
VCCCORE X34 Power/Other
VCCCORE Y35 Power/Other
VCCCORE Z32 Power/Other
VCOREDET E21 Power/Other
VID0 AL35 Power/Other
VID1 AM36 Power/Other
Table 46. PPGA Package Signal Lis ting
in Order by Signal Name
Pin Nam e Pin
No. Signal Buffer Type
VID2 AL37 Power/Other
VID3 AJ37 Power/Other
VREF0 E33 Power/Other
VREF1 F18 Power/Other
VREF2 K4 Power/Other
VREF3 R6 Power/Other
VREF4 V6 Power/Other
VREF5 AD6 Power/Other
VREF6 AK12 Power/Other
VREF7 AK22 Power/Other
VSS B16 Power/Other
VSS B20 Power/Other
VSS B24 Power/Other
VSS B28 Power/Other
VSS B32 Power/Other
VSS B4 Power/Other
VSS B8 Power/Other
VSS D18 Power/Other
VSS D2 Power/Other
VSS D22 Power/Other
VSS D26 Power/Other
VSS D30 Power/Other
VSS D34 Power/Other
VSS D4 Power/Other
VSS E11 Power/Other
VSS E15 Power/Other
VSS E19 Power/Other
VSS E7 Power/Other
VSS F20 Power/Other
VSS F24 Power/Other
VSS F28 Power/Other
VSS F32 Power/Other
VSS F36 Power/Other
VSS G5 Power/Other
VSS H2 Power/Other
VSS H34 Power/Other
VSS K36 Power/Other
VSS L5 Power/Other
VSS M2 Power/Other
VSS M34 Power/Other
Table 46. PPGA Package Signal Listing
in Or d e r by Si gn al Name
Pin Name Pin
No. Signal Buffer Type
Datasheet 83
Intel® Celeron™ Processor up to 850 MHz
VSS P32 Power/Other
VSS P36 Power/Other
VSS Q5 Power/Other
VSS R34 Power/Other
VSS T32 Power/Other
VSS T36 Power/Other
VSS U5 Power/Other
VSS V2 Power/Other
VSS A37 Power/Other
VSS AB32 Power/Other
VSS AC33 Power/Other
VSS AC5 Power/Other
VSS AD2 Power/Other
VSS AD34 Power/Other
VSS AF32 Power/Other
VSS AF36 Power/Other
VSS AG5 Power/Other
VSS AH2 Power/Other
VSS AH34 Power/Other
VSS AJ11 Power/Other
VSS AJ15 Power/Other
VSS AJ19 Power/Other
VSS AJ23 Power/Other
VSS AJ27 Power/Other
VSS AJ3 Power/Other
Table 46. PPGA Package Signal Listing
in Order by Signal Name
Pin Name Pin
No. Signal Buffer Type
VSS AJ7 Power/Other
VSS AK36 Power/Other
VSS AK4 Power/Other
VSS AL1 Power/Other
VSS AL3 Power/Other
VSS AM10 Power/Other
VSS AM14 Power/Other
VSS AM18 Power/Other
VSS AM2 Power/Other
VSS AM22 Power/Other
VSS AM26 Power/Other
VSS AM30 Power/Other
VSS AM34 Power/Other
VSS AM6 Power/Other
VSS AN3 Power/Other
VSS B12 Power/Other
VSS V34 Power/Other
VSS X32 Power/Other
VSS X36 Power/Other
VSS Y37 Power/Other
VSS Y5 Power/Other
VSS Z2 Power/Other
VSS Z34 Power/Other
VSS AJ31 Power/Other
VSS Y33 Power/Other
Table 46. PPGA Package Signal Listing
in Order by Signal Name
Pin Name Pin
No. Signal Buffer Type
84 Datasheet
Intel® Celeron™ Processor up to 850 MHz
5.3 FC-PGA Package
This section defines the mechanical specifications and signal definitions for the Intel® Celeron™
processor in the FC-PGA package.
5.3.1 Materials Information
Figure 22 with package dimensions is provided to aid in the design of heatsink and clip solutions as
well as demonstrate where pin-side capacitors will be located on the processor. Table 47 includes
the measurements for thes e dimen sions in both inches and millimeters.
NOTES:
1. Unless otherwise specified, the following drawings are dimensioned in inches.
2. A ll dimensions provided with tolerances are guaranteed to be met for all normal production product.
3. Figures and drawings labeled as “Reference Dimensions” are provided for informational purposes only.
Reference dimensions are extracted from the mechanical design database and are nominal dimensions with
no tolerance information applied. Reference dimensions are NOT checked as part of the processor
manufacturing. Unless noted as such, dimensions in parentheses without tolerances are reference
dimensions.
4. Drawing not to scale.
Figure 22. Package Dimensions (FC-PGA Package)
Datasheet 85
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. Capac itors and resistors may be placed on the pin-side of the FC-PGA package in the area defined by G1,
G2, and G3. This area is a keepout zone for motherboard designers.
The bare processor die has mechanical load limits that should not be exceeded during heat sink
assembly, mechani cal str e ss testing, or standard drop and shipping conditio ns. The heatsin k attach
solution must not induce permanent stress into the processor substrate with the exception of a
uniform load to maintain the heatsi nk to the proces sor thermal interfac e. The packag e dynamic an d
static loading parameters are listed in Table 48.
For Table 48, the following apply:
1. It is not recommended to use any portion of the processor substrate as a mechanical reference
or load bearing surface for thermal solutions.
2. Parameters assume uniformly applied loads
NOTES:
1. This specif ication applies to a uniform and a non-uniform load.
2. This is the maximu m static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface.
Table 47. Package Dimensions
Millimeters Inches
Symbol Min Max Notes Min Max Notes
A1 0.787 0.889 0.031 0.035
A2 1.000 1.200 0.039 0.047
B1 11.183 11.285 0.440 0.445
B2 9.225 9.327 0.363 0.368
C1 23.495 max 0. 925 max
C2 21.590 max 0. 850 max
D 49.428 49.632 1.946 1.954
D1 45.466 45.947 1.790 1.810
G1 0.000 17.780 1 0.000 0.700
G2 0.000 17.780 1 0.000 0.700
G3 0.000 0.889 1 0.000 0.035
H 2.540 Nominal 0.100 Nominal
L 3.048 3.302 0.120 0.130
ϕP 0.431 0.483 0.017 0.019
Pin TP 0.508 Diametric True Position (Pin-to-Pin) 0.020 Diametric True Position (Pin-to-Pin)
Table 48. Processor Die Loading Parameters (FC-PGA Package)
Parameter Dynamic (max)1Static (max)2Unit
Silicon Die Surface 200 50 lbf
Silicon Die Edge 100 12 lbf
86 Datasheet
Intel® Celeron™ Processor up to 850 MHz
5.3.2 Processor Markings
Figure 23 exemplifies the processor top-side markings and it is provided to aid in the identification
of an Penti um III process or for the PGA370 so cket. Table 47 lists the measurements for the package
dimensions.
Figure 23. Top Side Processor Markings (PPGA and FC-PGA Packages)
intel ®
i (m) (c) ’99
Static Mark ink printed at
substrate supplier Country of Origin
Dynamic Laser Mark
Swatch
RB80526RX566128
FFFFFFFF-0001 SSSSS
FPO # - S/N S-spec#
Celeron logo
MALAY
Celeron™
Product Code
Datasheet 87
Intel® Celeron™ Processor up to 850 MHz
5.4 FC-PGA Si gnal Li st
Table 49 and Table 50 provide the processor pin definitions. The signal lo cations on the PGA370
socket are to be used for signal routing, simulation, and component placement on the baseboard.
Figure 24 provides a pin-side view of the Intel® Celeron™ FC-PGA processor pin-out.
.
Figure 24. Package Dimensions (FC-PGA Package)
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
VSS
VCC
VSSD35
D29
D33
D26
D28
D21 D23
D25
VSS
VCC
VSS
D31
VCC
D43
VCC VSS
D34
D38
VCCVSS
D39
D36
VCC
D37 D44
VCC VCC D32 D22 RSV D27
VSS
D42
D45 D49
VSS
VCC D63 VREF1 VSS VCC VSS VCC VSS VCC VSS VCC VSS
VCC VSS VCC VSS RSV RSV D62
SLEW
CTRL
RSV RSV VREF0 BPM1 BP3
D41 D52 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC
D40 D59 D55 D54 D58 D50 D56 RSV RSV RSV BPM0
CPUPRES
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC RSV
D51 D47 D48 D57 D46 D53 D60 D61 RSV RSV RSV PRDY VSS
BP2 RSV RSV
VCC VSS VCC
PICCLK PICD0 PREQ
VCC VCC VSS
RSV PICD1 LINT1
VCC VSS LINT0
RSV RSV RSV
VSS VCC VSS
RSV RSV RSV
VCC VSS VCC
RSV
RTT
CTRL
RSV
VSS VCC VSS
PLL2 RSV RSV
VCC VSS VCC
RSV
VCC VSS
VCC VSS V_2.5
RSV RSV VCC
VSS VCC V_CMOS
VSS FERR RSV
VCC VSS V_1.5
A20M IERR FLUSH
VSS VCC VSS
INIT
VSS VCC VSS
PLL1 RSV BCLK
STPCLK IGNNE
VSS D16 D19
D7 D30 VCC
VCC VREF2 D24
D13 D20 VSS
VSS D11 D3
D2 D14 VCC
VCC D18 D9
D12 D10 VSS
RSV D17 VREF3
D8 D5 VCC
VCC D1 D6
D4 D15 VSS
VSS RSV VREF4
D0 RSV VCC
RSV RESET RSV
RSV A26 VSS
VSS A29 A18
A27 A30 VCC
VCC A24 A23
RSV A20 VSS
VSS A31 VREF5
A17 A22 VCC
VCC RSV A25
EDGCTRL
A19 VSS
VSS RSV A10 A5 A8 A4 BNR REQ1 REQ2 RSV RS1 VCC RS0 THERM
TRIP SLP VCC VSS VCC
A21 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC BSEL1 BSEL0 SMI VID3
VCC VSS A28 A3 A11 VREF6 A14 RSV REQ0 LOCK VREF7 RSV PWRGD RS2 RSV TMS VCC VSS
VSS VSS A15 A13 A9 RSV RSV A7 REQ4 REQ3 RSV HITM HIT DBSY THRMDN THRMDP TCK VID0 VID2
RSV
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VID1
VSS A12 A16 A6 RSV RSV RSV BPRI DEFER RSV RSV TRDY DRDY BR0 ADS TRST TDI TDO
PIN SIDE VIEW
1 2 3 4 5 6 7 8 9 10111213141516171819202122 23 24252627282930313233 34353637
1 2 3 4 5 6 7 8 9 10111213141516171819202122 23 24252627282930313233 34353637
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
88 Datasheet
Intel® Celeron™ Processor up to 850 MHz
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Nam e Pin
No. Signal Group
A3# AK8 AGTL+ I/O
A4# AH12 AGTL+ I/O
A5# AH8 AG TL+ I/ O
A6# AN9 AG TL+ I/ O
A7# AL15 A GTL+ I/O
A8# AH10 AGTL+ I/O
A9# AL9 AGTL+ I/ O
A10# AH6 AGTL+ I/O
A11# AK10 AGTL+ I/ O
A12# AN5 AGTL+ I/O
A13# AL7 AG TL+ I/O
A14# AK14 AGTL+ I/O
A15# AL5 AG TL+ I/O
A16# AN7 AGTL+ I/O
A17# AE1 AGTL+ I/O
A18# Z6 AGTL+ I/O
A19# AG3 AGTL+ I/O
A20# AC3 AGTL+ I/O
A21# AJ1 AGTL+ I/O
A22# AE3 AGTL+ I/O
A23# AB6 AGTL+ I/O
A24# AB4 AGTL+ I/O
A25# AF6 AGTL+ I/O
A26# Y3 AGTL+ I/O
A27# AA1 AGTL+ I/O
A28# AK6 AGTL+ I/O
A29# Z4 AGTL+ I/O
A30# AA3 AGTL+ I/O
A31# AD4 AGTL+ I/O
A20M# AE3 3 CMOS Input
ADS# AN31 AG TL+ I/ O
BCLK W37 S ystem Bus Clock
BNR# AH14 AGTL+ I/O
BP2# G33 AGTL+ I/O
BP3# E37 AGTL+ I/O
BPM0# C35 A G TL+ I/ O
BPM1# E35 AGTL+ I/ O
BPRI# AN17 A GTL+ Input
BR0# AN29 AG TL + I/O
BSEL0 AJ33 CMOS I/O
BSEL15AJ31 Power/Other
CPUPRES# C37 Power/Other
D0# W1 AGTL+ I/O
D1# T4 AGTL+ I/O
D2# N1 AGTL+ I/O
D3# M6 AGTL+ I/O
D4# U1 AGTL+ I/O
D5# S3 AGTL+ I/O
D6# T6 AGTL+ I/O
D7# J1 AGTL+ I/O
D8# S1 AGTL+ I/O
D9# P6 AGTL+ I/O
D10# Q3 AGTL+ I/O
D11# M4 AGTL+ I/O
D12# Q1 AGTL+ I/O
D13# L1 AGTL + I/O
D14# N3 AGTL+ I/O
D15# U3 AGTL+ I/O
D16# H4 AGTL+ I/O
D17# R4 AGTL+ I/O
D18# P4 AGTL+ I/O
D19# H6 AGTL+ I/O
D20# L3 AGTL + I/O
D21# G1 AGTL+ I/O
D22# F8 AGTL+ I/O
D23# G3 AGTL+ I/O
D24# K6 AGTL+ I/O
D25# E3 AGTL+ I/O
D26# E1 AGTL+ I/O
D27# F12 A GTL + I/O
D28# A5 AGTL+ I/O
D29# A3 AGTL+ I/O
D30# J3 A G TL + I/O
D31# C5 AGTL+ I/O
D32# F6 AGTL+ I/O
D33# C1 AGTL+ I/O
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Name Pin
No. Signal Gr oup
Datasheet 89
Intel® Celeron™ Processor up to 850 MHz
D34# C7 AGTL+ I/O
D35# B2 AGTL+ I/O
D36# C9 AGTL+ I/O
D37# A9 AGTL+ I/O
D38# D8 AGTL+ I/O
D39# D10 AGTL+ I/O
D40# C15 AGTL+ I/O
D41# D14 AGTL+ I/O
D42# D12 AGTL+ I/O
D43# A7 AGTL+ I/O
D44# A11 AGTL+ I/O
D45# C11 AGTL+ I/O
D46# A21 AGTL+ I/O
D47# A15 AGTL+ I/O
D48# A17 AGTL+ I/O
D49# C13 AGTL+ I/O
D50# C25 AGTL+ I/O
D51# A13 AGTL+ I/O
D52# D16 AGTL+ I/O
D53# A23 AGTL+ I/O
D54# C21 AGTL+ I/O
D55# C19 AGTL+ I/O
D56# C27 AGTL+ I/O
D57# A19 AGTL+ I/O
D58# C23 AGTL+ I/O
D59# C17 AGTL+ I/O
D60# A25 AGTL+ I/O
D61# A27 AGTL+ I/O
D62# E25 AGTL+ I/O
D63# F16 AGTL+ I/O
DBSY# AL27 AGTL+ I/O
DEFER# AN19 AGTL+ Input
DRDY# AN27 AGTL+ I/O
EDGCTRL 2AG1 Power/Other
FERR# AC35 CMOS Output
FLUSH# AE37 CMOS Input
GND A37 Power/Other
GND AB32 Power/Other
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Name Pin
No. Signal Group
GND AC5 Power/Other
GND AC33 Power/Other
GND AD2 Power/Other
GND AD34 Power/Other
GND AF32 Power/Other
GND AF36 Power/Other
GND AG5 Power/Other
GND AH2 Power/Other
GND AH34 Power/Other
GND AJ3 Power/Other
GND AJ7 Power/Other
GND AJ11 Power/Other
GND AJ15 Power/Other
GND AJ19 Power/Other
GND AJ23 Power/Other
GND AJ27 Power/Other
GND AK4 Power/Other
GND AK36 Power/Other
GND AL1 Power/Other
GND AL3 Power/Other
GND AM6 Power/Other
GND AM10 Power/Other
GND AM14 Power/Other
GND AM18 Power/Other
GND AM22 Power/Other
GND AM26 Power/Other
GND AM30 Power/Other
GND AM34 Power/Other
GND AN3 Power/Other
GND B4 Power/Other
GND B8 Power/Other
GND B12 Power/Other
GND B16 Power/Other
GND B20 Power/Other
GND B24 Power/Other
GND B28 Power/Other
GND B32 Power/Other
GND D2 Power/Other
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Name Pin
No. Signal Group
90 Datasheet
Intel® Celeron™ Processor up to 850 MHz
GND D4 Power/Other
GND D18 Power/Other
GND D22 Power/Other
GND D26 Power/Other
GND D30 Power/Other
GND D34 Power/Other
GND E7 Power/Other
GND E11 Power/Other
GND E15 Power/Other
GND E19 Power/Other
GND F20 Power/Other
GND F24 Power/Other
GND F28 Power/Other
GND F32 Power/Other
GND F36 Power/Other
GND G5 Power/Other
GND H2 Power/Other
GND H34 Power/Other
GND K36 Power/Other
GND L5 Power/Other
GND M2 Power/Other
GND M34 Power/Other
GND P32 Power/Other
GND P36 Power/Other
GND Q5 Power/Other
GND R34 Power/Other
GND T32 Power/Other
GND T36 Power/Other
GND U5 Power/Other
GND V2 Power/Other
GND V34 Power/Other
GND X32 Power/Other
GND X36 Power/Other
GND Y5 Power/Other
GND Y37 Power/Other
GND Z2 Power/Other
GND Z34 Power/Other
HIT# AL25 AG TL+ I/O
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Nam e Pin
No. Signal Group
HITM# AL23 AG TL+ I/O
IERR# AE35 C MOS Output
IGNNE# AG37 CMOS Input
INIT # A G33 CMO S In put
LINT0/INTR M36 CMO S Inp u t
LINT1/NMI L37 CMOS Input
LOCK# AK20 A GTL+ I/O
PICCLK J33 APIC Clock Input
PICD0 J35 APIC I/O
PICD1 L35 APIC I/O
PLL1 W33 Power/Other
PLL2 U33 Power/Other
PRDY# A 35 A G TL + Output
PREQ# J37 CMOS Input
PWRGOOD AK26 CMOS Input
REQ0 # A K18 A GTL+ I/O
REQ1# AH16 AGTL+ I/O
REQ2# AH18 AGTL+ I/O
RE Q3 # A L 1 9 AG TL+ I/O
RE Q4 # A L 1 7 AG TL+ I/O
Reserved A29 Reserved for future use
Reserved A31 Reserved for future use
Reserved A33 Reserved for future use
Reserved AC1 Reserved for future use
Reserved AC37 Reserved for future use
Reserved AF4 Reserved for future use
Reserved AH4 Reserved for future use
Reserved AH20 Reserved for future use
Reserved AK16 Reserved for future use
Reserved AK24 Reserved for future use
Reserved AK30 Reserved for future use
Reserved AL11 Reserved for future use
Reserved AL13 Reserved for future use
Reserved AL21 Reserved for future use
Reserved AN11 Reserved for future use
Reserved AN13 Reserved for future use
Reserved AN15 Reserved for future use
Reserved AN21 Reserved for future use
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Name Pin
No. Signal Gr oup
Datasheet 91
Intel® Celeron™ Processor up to 850 MHz
Reserved AN23 Reserved for future use
Reserved B36 Reserved for future use
Reserved C29 Reserved for future use
Reserved C31 Reserved for future use
Reserved C33 Reserved for future use
Reserved E23 Reserved for future use
Reserved E29 Reserved for future use
Reserved E31 Reserved for future use
Reserved F10 Reserved for future use
Reserved G35 Reserved for future use
Reserved G37 Reserved for future use
Reserved L33 Reserved for future use
Reserved N33 Reserved for future use
Reserved N35 Reserved for future use
Reserved N37 Reserved for future use
Reserved Q33 Reserved for future use
Reserved Q35 Reserved for future use
Reserved Q37 Reserved for future use
Reserved R2 Reserved for future use
Reserved S33 Reserved for future use
Reserved S37 Reserved for future use
Reserved U35 Reserved for future use
Reserved U37 Reserved for future use
Reserved V4 Reserved for future use
Reserved W3 Reserved for future use
Reserved W35 Reserved for future use
Reserved X6 Reserved for future use
Reserved X20 Reserved for future use
Reserved Y1 Reserved for future use
Reserved AA33 Reserved for future use
Reserved AA35 Reserved for future use
Reserved3AM2 Reserved for future use
Reserved4Y33 Reserved for future use
RESET# X4 Power/Other
RS0# AH26 AGTL+ Input
RS1# AH22 AGTL+ Input
RS2# AK28 AGTL+ Input
RTTCTRL S35 Power/Other
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Name Pin
No. Signal Group
SLEWCTRL E27 Power/Other
SLP# AH30 CMOS Input
SMI# AJ35 CMOS Input
STPCLK# AG35 CMOS Input
TCK AL33 TAP Input
TDI AN35 TAP Input
TDO A N 37 TAP Output
THERMDN AL29 Power/Other
THERMDP AL31 Power/Other
THERMTRIP# AH28 CMOS Output
TMS AK32 TAP I nput
TRDY# AN25 AGTL+ Input
TRST# A N33 TAP Input
VCC1.5 1AD36 Power/Other
Vcc2.5 Z36 Power/Other
VCCCMOS AB36 Power/Other
VCCCORE AA5 Power/Other
VCCCORE AA37 Power/Other
VCCCORE AB2 Power/Other
VCCCORE AB34 Power/Other
VCCCORE AD32 Power/Other
VCCCORE AE5 Power/Other
VCCCORE AF2 Power/Other
VCCCORE AF34 Power/Other
VCCCORE AH24 Power/Other
VCCCORE AH32 Power/Other
VCCCORE AH36 Power/Other
VCCCORE AJ5 Power/Other
VCCCORE AJ9 Power/Other
VCCCORE AJ13 Power/Other
VCCCORE AJ17 Power/Other
VCCCORE AJ21 Power/Other
VCCCORE AJ25 Power/Other
VCCCORE AJ29 Power/Other
VCCCORE AK2 Power/Other
VCCCORE AK34 Power/Other
VCCCORE AM4 Power/Other
VCCCORE AM8 Power/Other
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Name Pin
No. Signal Group
92 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. VCC1.5 must be supplied by the same voltage
source supplying VTT on the motherboard.
2. Prev iously this pin functioned as the EDGCTRL
signal.
3. Prev iously, PGA370 designs defined this pin as a
GND. For flexible PGA370 designs, it must be left
unconnected (N/C).
4. Prev iously, PGA370 designs defined this pin as a
GND.
5. Intel® Celero n™ processor in the FC-PGA
package does not make use of this pin.
VCCCORE AM12 Power/Other
VCCCORE AM16 Power/Other
VCCCORE AM20 Power/Other
VCCCORE AM24 Power/Other
VCCCORE AM28 Power/Other
VCCCORE AM32 Power/Other
VCCCORE B6 Power/Other
VCCCORE B10 Power/Other
VCCCORE B14 Power/Other
VCCCORE B18 Power/Other
VCCCORE B22 Power/Other
VCCCORE B26 Power/Other
VCCCORE B30 Power/Other
VCCCORE B34 Power/Other
VCCCORE C3 Power/Other
VCCCORE D6 Power/Other
VCCCORE D20 Power/Other
VCCCORE D24 Power/Other
VCCCORE D28 Power/Other
VCCCORE D32 Power/Other
VCCCORE D36 Power/Other
VCCCORE E5 Power/Other
VCCCORE E9 Power/Other
VCCCORE E13 Power/Other
VCCCORE E17 Power/Other
VCCCORE F2 Power/Other
VCCCORE F4 Power/Other
VCCCORE F14 Power/Other
VCCCORE F22 Power/Other
VCCCORE F26 Power/Other
VCCCORE F30 Power/Other
VCCCORE F34 Power/Other
VCCCORE H32 Power/Other
VCCCORE H36 Power/Other
VCCCORE J5 Power/Other
VCCCORE K2 Power/Other
VCCCORE K32 Power/Other
VCCCORE K34 Power/Other
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Nam e Pin
No. Signal Group
VCCCORE M32 Power/Other
VCCCORE N5 Power/Other
VCCCORE P2 Power/Other
VCCCORE P34 Power/Other
VCCCORE R32 Power/Other
VCCCORE R36 Power/Other
VCCCORE S5 Power/Other
VCCCORE T2 Power/Other
VCCCORE T34 Power/Other
VCCCORE V32 Power/Other
VCCCORE V36 Power/Other
VCCCORE W5 Power/Other
VCCCORE X34 Power/Other
VCCCORE Y35 Power/Other
VCCCORE Z32 Power/Other
VCORE_DET E21 Power/Other
VID0 AL35 Power/Other
VID1 AM36 Power/Other
VID2 AL37 Power/Other
VID3 AJ37 Power/Other
VREF0 E33 Power/Other
VREF1 F18 Power/Other
VREF2 K4 Power/Other
VREF3 R6 Power/Other
VREF4 V6 Power/Other
VREF5 AD6 Power/Other
VREF6 AK12 Power/Other
VREF7 AK22 Power/Other
Table 49. FC-PGA Signal Listing in
Order by Signal Name
Pin Name Pin
No. Signal Gr oup
Datasheet 93
Intel® Celeron™ Processor up to 850 MHz
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Name Signal Group
A3 D29# AGTL+ I/O
A5 D28# AGTL+ I/O
A7 D43# AGTL+ I/O
A9 D37# AGTL+ I/O
A11 D44# AGTL+ I/O
A13 D51# AGTL+ I/O
A15 D47# AGTL+ I/O
A17 D48# AGTL+ I/O
A19 D57# AGTL+ I/O
A21 D46# AGTL+ I/O
A23 D53# AGTL+ I/O
A25 D60# AGTL+ I/O
A27 D61# AGTL+ I/O
A29 Reserved Reserved for future use
A31 Reserved Reserved for future use
A33 Reserved Reserved for future use
A35 PRDY# AGTL+ Out put
A37 GND Power/Other
AA1 A27# AGTL+ I/O
AA3 A30# AGTL+ I/O
AA5 VCCCORE Power/Other
AA33 Reserved Reserved for future use
AA35 Reserved Reserved for future use
AA37 VCCCORE Power/Other
AB2 VCCCORE Power/Other
AB4 A24# AGTL+ I/O
AB6 A23# AGTL+ I/O
AB32 GND Power/Other
AB34 VCCCORE Power/Other
AB36 VCCCMOS Power/Other
AC1 Reserved Reserved for future use
AC3 A20# AGTL+ I/O
AC5 GND Power/Other
AC33 GND Power/Other
AC35 FERR# CMOS Output
AC37 Reserved Reserved for future use
AD2 GND Power/Other
AD4 A31# AGTL+ I/O
AD6 VREF5 Power/Other
AD32 VCCCORE Power/Other
AD34 GND Power/Other
AD36 VCC1.5 1Power/Other
AE1 A17# AGTL+ I/O
AE3 A22# AGTL+ I/O
AE5 VCCCORE Power/Other
AE33 A20M# CMOS Input
AE35 IERR# CMOS Output
AE37 FLUSH# CMOS Input
AF2 VCCCORE Power/Other
AF4 Reser ved Reser ved for future use
AF6 A25# AGTL+ I/O
AF32 GND Power/Other
AF34 VCCCORE Power/Other
AF36 GND Power/Other
AG1 EDGCTRL 2Power/Other
AG3 A19# AGTL+ I/O
AG5 GND Power/Other
AG33 INIT# CMOS Input
AG35 STPCLK# CMOS Input
AG37 IGNNE# CMOS Input
AH2 GND Power/Other
AH4 Reserved Reserved for future use
AH6 A10# AGTL+ I/O
AH8 A5# AGTL+ I/O
AH10 A8# AGTL+ I/O
AH12 A4# AGTL+ I/O
AH14 BNR# AGTL+ I/O
AH16 REQ1# AGTL+ I/O
AH18 REQ2# AGTL+ I/O
AH20 Reserved Reserved for future use
AH22 RS1# AGTL+ Input
AH24 VCCCORE Power/Other
AH26 RS0# AGTL+ Input
AH28 THERMTRIP# CMOS Output
AH30 SLP# CMOS Input
AH32 VCCCORE Power/Other
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Name Signal Gro up
94 Datasheet
Intel® Celeron™ Processor up to 850 MHz
AH34 GND Power/Other
AH36 VCCCORE Power/Other
AJ1 A21# AGTL+ I/O
AJ3 GND Power/Other
AJ5 VCCCORE Power/Other
AJ7 GND Power/Other
AJ9 VCCCORE Power/Other
AJ11 GND Power/Other
AJ13 VCCCORE Power/Other
AJ15 GND Power/Other
AJ17 VCCCORE Power/Other
AJ19 GND Power/Other
AJ21 VCCCORE Power/Other
AJ23 GND Power/Other
AJ25 VCCCORE Power/Other
AJ27 GND Power/Other
AJ29 VCCCORE Power/Other
AJ31 BSEL15Power/Other
AJ33 BSEL0 CMOS I/O
AJ35 S MI# CM O S Input
AJ37 VID3 Power/Other
AK2 VCCCORE Power/Other
AK4 GND Power/Other
AK6 A28# A G TL+ I/O
AK8 A 3# AG TL+ I/ O
AK10 A 11# A G TL+ I/O
AK12 VREF6 Power/Other
AK14 A 14# A GTL+ I/O
AK16 Reserved Reserved for future use
AK18 REQ0# A GTL+ I/O
AK20 LOCK # AGTL+ I/O
AK22 VREF7 Power/Other
AK24 Reserved Reserved for future use
AK26 P W RGOOD CMOS Input
AK28 RS 2# AGTL+ Input
AK30 Reserved Reserved for future use
AK32 TMS TAP Input
AK34 VCCCORE Power/Other
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Na me Signal Gr oup
AK36 GND Power/Other
AL1 GND Power/Other
AL3 GND Power/Other
AL5 A 15# A G TL + I/O
AL7 A 13# A G TL + I/O
AL9 A9# AGTL+ I/ O
AL11 Reserved Reserved for future use
AL13 Reserved Reserved for future use
AL15 A7# AGTL+ I/O
AL17 REQ4# AGTL+ I/O
AL19 REQ3# AGTL+ I/O
AL21 Reserved Reserved for future use
AL23 HITM# AGTL+ I/O
AL25 HIT# AGTL + I/ O
AL27 DBSY# AGTL+ I/O
AL29 THERMDN Power/Other
AL31 THERMDP Power/Other
AL33 TCK TAP Input
AL35 VID0 Power/Other
AL37 VID2 Power/Other
AM2 Reserved3Reserved fo r future u se
AM4 VCCCORE Power/Other
AM6 GND Power/Other
AM8 VCCCORE Power/Other
AM10 GND Power/Other
AM12 VCCCORE Power/Other
AM14 GND Power/Other
AM16 VCCCORE Power/Other
AM18 GND Power/Other
AM20 VCCCORE Power/Other
AM22 GND Power/Other
AM24 VCCCORE Power/Other
AM26 GND Power/Other
AM28 VCCCORE Power/Other
AM30 GND Power/Other
AM32 VCCCORE Power/Other
AM34 GND Power/Other
AM36 VID1 Power/Other
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Name Signal Group
Datasheet 95
Intel® Celeron™ Processor up to 850 MHz
AN3 GND Power/Other
AN5 A12# AGTL+ I/O
AN7 A16# AGTL+ I/O
AN9 A6# AGTL+ I/O
AN11 Reserved Reserved for future use
AN13 Reserved Reserved for future use
AN15 Reserved Reserved for future use
AN17 BPRI# AGTL+ Input
AN19 DEFER# AGTL+ Input
AN21 Reserved Reserved for future use
AN23 Reserved Reserved for future use
AN25 TRDY# AGTL+ Input
AN27 DRDY# AGTL+ I/ O
AN29 BR0# AGTL+ I/O
AN31 ADS# AGTL+ I/O
AN33 TRST# TAP Input
AN35 TDI TA P Input
AN37 TDO TA P Output
B2 D35# AGTL+ I/O
B4 GND Power/Other
B6 VCCCORE Power/Other
B8 GND Power/Other
B10 VCCCORE Power/Other
B12 GND Power/Other
B14 VCCCORE Power/Other
B16 GND Power/Other
B18 VCCCORE Power/Other
B20 GND Power/Other
B22 VCCCORE Power/Other
B24 GND Power/Other
B26 VCCCORE Power/Other
B28 GND Power/Other
B30 VCCCORE Power/Other
B32 GND Power/Other
B34 VCCCORE Power/Other
B36 Reserved Reserved for future use
C1 D33# AGTL+ I/O
C3 VCCCORE Power/Other
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Name Signal Group
C5 D31# AGTL+ I/O
C7 D34# AGTL+ I/O
C9 D36# AGTL+ I/O
C11 D45# AGTL+ I/O
C13 D49# AGTL+ I/O
C15 D40# AGTL+ I/O
C17 D59# AGTL+ I/O
C19 D55# AGTL+ I/O
C21 D54# AGTL+ I/O
C23 D58# AGTL+ I/O
C25 D50# AGTL+ I/O
C27 D56# AGTL+ I/O
C29 Reserved Reser ved for future use
C31 Reserved Reser ved for future use
C33 Reserved Reser ved for future use
C35 BPM0# AGTL+ I/O
C37 CPUPRES# Power/Other
D2 GND Power/Other
D4 GND Power/Other
D6 VCCCORE Power/Other
D8 D38# AGTL+ I/O
D10 D39# AGTL+ I/O
D12 D42# AGTL+ I/O
D14 D41# AGTL+ I/O
D16 D52# AGTL+ I/O
D18 GND Power/Other
D20 VCCCORE Power/Other
D22 GND Power/Other
D24 VCCCORE Power/Other
D26 GND Power/Other
D28 VCCCORE Power/Other
D30 GND Power/Other
D32 VCCCORE Power/Other
D34 GND Power/Other
D36 VCCCORE Power/Other
E1 D26# AGTL+ I/O
E5 VCCCORE Power/Other
E7 GND Power/Other
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Name Signal Gro up
96 Datasheet
Intel® Celeron™ Processor up to 850 MHz
E9 VCCCORE Power/Other
E11 GND Power/Other
E13 VCCCORE Power/Other
E15 GND Power/Other
E17 VCCCORE Power/Other
E19 GND Power/Other
E21 VCORE_DET Power/Other
E23 Reserved Reserved for future use
E25 D62# AGTL+ I/O
E27 SLEWCTRL Power/Other
E29 Reserved Reserved for future use
E3 D25# A GTL+ I/O
E31 Reserved Reserved for future use
E33 VREF0 Power/Other
E35 BPM 1# AGTL+ I/ O
E37 BP3# AGTL+ I/O
F2 VCCCORE Power/Other
F4 VCCCORE Power/Other
F6 D32# A GTL+ I/O
F8 D22# A GTL+ I/O
F10 Reserved Reserved for future use
F12 D27# AGTL+ I/O
F14 VCCCORE Power/Other
F16 D63# AGTL+ I/O
F18 VREF1 Power/Other
F20 GND Power/Other
F22 VCCCORE Power/Other
F24 GND Power/Other
F26 VCCCORE Power/Other
F28 GND Power/Other
F30 VCCCORE Power/Other
F32 GND Power/Other
F34 VCCCORE Power/Other
F36 GND Power/Other
G1 D21# AGTL+ I/O
G3 D23# AGTL+ I/O
G5 GND Power/Other
G33 B P2# AGTL+ I/O
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Na me Signal Gr oup
G35 Reserved Reserved for future use
G37 Reserved Reserved for future use
H2 GND Power/Other
H4 D16# A G TL + I/O
H6 D19# A G TL + I/O
H32 VCCCORE Power/Other
H34 GND Power/Other
H36 VCCCORE Power/Other
J1 D7# AGTL+ I/O
J3 D30# A G TL + I/O
J5 VCCCORE Power/Other
J33 P IC CLK A PIC Clock Input
J35 P ICD0 AP I C I/O
J37 PREQ# C MOS Input
K2 VCCCORE Power/Other
K4 VREF2 Power/Other
K6 D24# AGTL + I/O
K32 VCCCORE Power/Other
K34 VCCCORE Power/Other
K36 GND Power/Other
L1 D 13# AGTL+ I/O
L3 D 20# AGTL+ I/O
L5 GND Power/Other
L33 Reserved Reserved for future use
L35 P ICD 1 APIC I/O
L37 L INT1/N MI CMOS Input
M2 GND Power/Other
M4 D11# AGTL+ I/O
M6 D3# AGTL+ I/O
M32 VCCCORE Power/Other
M34 GND Power/Other
M36 LINT 0 /INTR CM O S In put
N1 D2# AGTL+ I/O
N3 D14# A G TL + I/O
N5 VCCCORE Power/Other
N33 Reserved Reserved for future use
N35 Reserved Reserved for future use
N37 Reserved Reserved for future use
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Name Signal Group
Datasheet 97
Intel® Celeron™ Processor up to 850 MHz
NOTES:
1. VCC1.5 must be supplied by the same voltage
source supplying VTT on the motherboard.
2. Previously this pin functioned as the EDGCTRL
signal.
3. Pr eviously, PGA370 designs defined this pin as a
GND. For flexible PGA370 designs, it must be left
unconnected (N/C).
4. Pr eviously, PGA370 designs defined this pin as a
GND.
5. Intel® Celeron™ processor in the FC-PGA
package does not make use of this pin.
P2 VCCCORE Power/Other
P4 D18# AGTL+ I/O
P6 D9# AGTL+ I/O
P32 GND Power/Other
P34 VCCCORE Power/Other
P36 GND Power/Other
Q1 D12# AGTL+ I/O
Q3 D10# AGTL+ I/O
Q5 GND Power/Other
Q33 Reserved Reser ved for future use
Q35 Reserved Reser ved for future use
Q37 Reserved Reser ved for future use
R2 Reser ved Reser ved for future use
R4 D17# AGTL+ I/O
R6 VREF3 Power/Other
R32 VCCCORE Power/Other
R34 GND Power/Other
R36 VCCCORE Power/Other
S1 D8# AGTL+ I/O
S3 D5# AGTL+ I/O
S5 VCCCORE Power/Other
S33 Reserved Reserved for future use
S35 RTTCTRL Power/Other
S37 Reserved Reserved for future use
T2 VCCCORE Power/Other
T4 D1# AGTL+ I/O
T6 D6# AGTL+ I/O
T32 GND Power/Other
T34 VCCCORE Power/Other
T36 GND Power/Other
U1 D4# AGTL+ I/O
U3 D15# AGTL+ I/O
U5 GND Power/Other
U33 PLL2 Power/Other
U35 Reser ved Reser ved for future use
U37 Reser ved Reser ved for future use
V2 GND Power/Other
V4 Reserved Reser ved for future use
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Name Signal Group
V6 VREF4 Power/Other
V32 VCCCORE Power/Other
V34 GND Power/Other
V36 VCCCORE Power/Other
W1 D0# AGTL+ I/ O
W3 Reserved Reserved for future use
W5 VCCCORE Power/Other
W33 PLL1 Power/Other
W35 Reserved Reserved for future use
W37 BCLK System Bus Clock
X4 RESET# Power/Other
X6 Reserved Reser ved for future use
X20 Reserved Reserved for future use
X32 GND Power/Other
X34 VCCCORE Power/Other
X36 GND Power/Other
Y1 Reserved Reser ved for future use
Y3 A26# AGTL+ I/O
Y5 GND Power/Other
Y33 Reserved4Reserved for future use
Y35 VCCCORE Power/Other
Y37 GND Power/Other
Z2 GND Power/Other
Z4 A29# AGTL+ I/O
Z6 A18# AGTL+ I/O
Z32 VCCCORE Power/Other
Z34 GND Power/Other
Z36 Vcc2.5 Power/Other
Table 50. FC-PGA Signal Listing in
Order by Pin Number
Pin
No. Pin Name Signal Gro up
98 Datasheet
Intel® Celeron™ Processor up to 850 MHz
5.5 Heat Sink Volumetric Keepout Zone Gui deli nes
When designing a system platform it is necessary to ensure suff icient space is left for a heat sink to
be installed without mechanical interference. Due to the large number of proprietary heat sink
designs, Intel cannot specify a keepout zone that covers all passive and active-fan heat sinks. It is
the system designer’s responsibility to consider their own proprietary solution when desig ning the
desired keepout zone in their system platform. Please refer to the Intel® Celeron™ Processor
(PPGA) at 466 MHz Thermal Solu tio ns Gui deli nes (Order Number 245156) for furthe r guidance .
Note: The heat sink keepout zones found in Section 6.0, “Boxed Processor Specifications” on page 99
refer specifically to the Boxed Processor’s active-fan heat sink. This does not reflect the worst-case
dimensions that may exist with other third party passive or active-fan heat sinks. Contact your
vendor of choice for their passive or active-fan heat sink dimensions to ensure that mechanical
interference with system platform components does not occur.
Datasheet 99
Intel® Celeron™ Processor up to 850 MHz
6.0 Boxed Processor Specifications
The Intel® Celeron™ processor is also offere d as an In tel bo xed pr oces so r in the FC -PGA, PPGA,
and S.E.P. Package. Intel boxed processors are intended for system integrators who build systems
from motherboards and standard components. The boxed Celeron processor in the S.E.P. Package
is supplied with an attached fan heatsink. The boxed Celeron processors in FC-PGA and PPGA
packages are supplied with unattached fan heatsinks.
This section documents motherboard and system requirements for the fan heatsink that is supplied
with the boxed Intel Celeron processor. This s ectio n is particularly important for OEMs that
manufacture motherboard s f or sy stem integrators. Unless otherw ise noted, all figures in this
section are dimensioned in inches.
Note: Drawings in this section reflect only the specifications of the Intel boxed processor product. These
dimensions should not be used as a generic keep-out zone for all heatsinks. It is the system
designer’s responsibility to consider their proprietary solution when designing to the required keep-
out zone on their system platform and chassis. Refer to the package specific Thermal /Mechanical
Solution Functional Specificat ions for further guidance. Contact your local Intel Sales
Representative for these documents.
6.1 Mechanical Specifications for the Boxed Intel® Celeron™
Processor
6.1.1 Mechanical Specifications for the S.E.P. Package
This section documen ts the m echanical s pecifications of the b oxed In tel® Cel e ro n™ processor fan
heatsink in the S.E.P. Package. The boxed processor in the S.E.P. Package ships with an attached
fan h eatsink. Figure 25 shows a mechanical representation of the boxed Intel Celeron processor in
a S.E.P. Package in the retention mechanism, which is not shipped with the boxed Intel Celeron
processor.
The space r equirements and dimens ions fo r the b oxed proces sor in the S.E.P. Package are s hown in
Figure 26 and Figure 27. Also, a conceptual attachment interface to low profile retention
mechanism is shown in Figure 35.
Note: The heatsink airflow keepout zones found in Table 51 and Figure 35 refer specifically to the b oxed
processor’s active fan heatsink. This does no t reflect the wor st-case dimens ions that may exist with
other third party passive or active fan heatsinks.
100 Datasheet
Intel® Celeron™ Processor up to 850 MHz
Figure 25. Ret ent ion Mech anism for the Boxed Intel® Celeron™ Processor in the S.E.P.
Package
Figure 26. Side View Space Requirements for the Boxed Processor in the S.E. P.
Package
242-Contact Slot Connector
Fan Heatsink
S.E.P.P.
1.386
(A)
0.576 (B)
Datasheet 101
Intel® Celeron™ Processor up to 850 MHz
6.1.1.1 Boxed Processor Heatsink Weight
The heatsink for the boxed Intel Celeron processor in the S.E.P. Package will not weigh more than
225 grams.
6.1.1.2 Boxed Processor Retention Mechanism
The boxed Intel Celeron processor requires a S.E.P. Package retention mechanism to secure the
processor in the 242-contact slot connector. A S.E.P. Package retention mechanism are provided
with the boxed processor. Motherboards designed for use by system integrators should include a
retention mechanism and approp ri ate installation instructions.
The boxed Intel Celeron processor does not require additio nal fan heatsink su pports. Fan heatsink
supports are not shipped with the boxed Intel Celeron processor.
Motherboards desig ned for flexible use by system integrators must still recognize the boxed
Pentium II processor’s fan heatsink clearance requirements, which ar e described in the Pentium® II
Processor at 233, 266, 300, and 333 MHz Datasheet (Order Number 243335).
Figure 27. Front View Space Requirements for the Boxed Processor the S.E.P. Package
Table 51. Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package
Fig. R e f .
Label Dimensions (Inches) Min Typ M ax
A Fan Heatsink Depth (see Figure 24) 1.40
B Fan Heatsink Height from Motherboard (see Figure 24) 0.58
C F an Heatsink Height (see Figure 25) 2.00
D F an Heatsink Width (see Figure 25) 4.80
E Fan Heatsink Base Wi dth (see Figure 25) 5.4
F Airflow Keepout Zones from end of Fan Heatsink 0.4
G Airflow Keepout Zones from face of Fan Heatsink 0.2
4.74 (D)
2.02 (C)
5.40 (E)
102 Datasheet
Intel® Celeron™ Processor up to 850 MHz
6.1.2 Mechanical Specifications for the PPGA Package
This section documents the mechanical specifications for the fan heatsink of the boxed Intel®
Celeron™ processor in the PPGA package. The boxed processor in the PPGA package ships with
an unattached fan heatsink which has an integrated clip. Figu re 28 shows a mechanical
representation of the boxed Intel Celeron processor in the PPGA package.
Note that the airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
Clearance is required aroun d the fan heatsin k to ens ure unimp eded airf low for pro per coo ling. Th e
space requirements and dimensions for the boxed processor with an integrated fan heatsink are
shown in Figu re 29, Figure 30, and Figure 31. All dimensions are in inches.
Note: The heatsink airflow k eepou t zon es fou nd in Table 52 and Figure 36 refer specifically to the boxed
processor’s active fan heatsink. This does not reflect the worst-case dimen sions that m ay exist with
other third party passive or active fan heatsinks.
Figure 28. Boxed Intel® Celeron™ Processor in the PPGA Package
Figure 29. Side View Space Requirements for the Boxed Processor in the PPGA Package
Datasheet 103
Intel® Celeron™ Processor up to 850 MHz
Figure 30. Top View Space Requirements for the Boxed Processor in the FC-PGA and PPGA
Packages
Figure 31. Side View Space Requirements for the Boxed Processor in the FC-PGA and PPGA
Packages
2.00
2.52
Note: The Intel® Celeron™
processor at frequencies
of 533 MHz and greater
ship with a 3-wire fan.
Note
104 Datasheet
Intel® Celeron™ Processor up to 850 MHz
6.1.2.1 Boxed Processor Heatsink Dimensions
NOTES:
1. D rawings reflect only the specifications of the Intel boxed processor product. These dimensions should not
be used as a universal keepout zone that covers all heatsinks. It is the system designer’s responsibility to
consider their own proprietary solution when designing the desired keepout zone in their system platform.
2. A pplies to the heatsinks provided with the boxed Intel Celeron processors from 300A MHz to 433 MHz.
3. Applies to the heatsink provided with the Intel Celeron processors from 466 MHz to 533 MHz in the PPGA
package and the boxed Intel Celeron processors from 533A to 700 MHz in the FC-PGA package.
6.1.2.2 Boxed Processor Heatsink Wei ght
The heatsink for the b oxed In tel Celeron processor in the PPGA package will not weigh more than
180 grams.
6.1.3 Mechanical Specifications for the FC-PGA Package
This section documents the mechanical specifications of the fan heatsink for the boxed Intel
Celeron processo r in the FC- PGA (Flip-Chip Pin Grid Array) packag e. Th e bo xed pro cessor in the
FC-PGA package ships with a fan heatsink which has an integrated clip. Figure 32 shows a
mechanical representation of the boxed Intel Celeron processor in the FC-PGA package.
The dimensions for the boxed processor with integrated fan heatsink are shown in Figure 30 and
Figure 31. General spatial specifications are also outlined in Table 52.
The fan heatsink is designed to allow visibility of the FC-PGA processor markings located on the
top of the package. The FC-PGA processor markings are visible after installation of the fan
heatsink due to notched si des of the hea t sink base (See Figure 33). The boxed proc essor fan
heatsink is also asymmetrical in that the mechanical step feature (specified in Figure 34) must sit
over the s ocket’s cam. The step allows the heatsink to securely interface with the processor in ord er
to meet the processors thermal requirements.
Table 52. Boxed Processor Fan Heatsink Spatial Dimensions for the PPGA and FC-PGA
Packages 1
Dimensions (Inches) Min Typ Max Notes
Fan Heatsink Length (see Figure 28) 2.52
Fan Heatsink Height from Motherboard (see
Figure 27) 0.34
Fan Heatsink Height (see Figure 27) 1.22
1.77 2
3
Fan Heatsink Width (see Figure 28) 2.00
Airflow Keepout Zones from end of Fan Heatsink 0.20
Airflow Keepout Zones from face of Fan Heatsink 0.20
Datasheet 105
Intel® Celeron™ Processor up to 850 MHz
Figure 32. Boxed Intel® Celeron™ processor in the 370-pin socket (FC-PGA Package)
Figure 33. Dimensions of Notches in Heatsink Base
106 Datasheet
Intel® Celeron™ Processor up to 850 MHz
6.1.3.1 Boxed Processor Heatsink Wei ght
The heatsink for the boxed Intel Celeron processor in the FC-PGA package will not weigh more
than 180 grams.
6.2 Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution utilized by the boxed
processors.
6.2.1 T hermal Requirements for the Boxed Intel® Celeron™ Processor
6.2.1.1 Boxed Processor Cooling Requirements
The boxed processor is directly cooled with a fan heatsink. However, meeting the processor's
temperature specification is also a function of the thermal design of the entire system, and
ultimately the responsibility of the system integrat or. The processor temperature specification is
found in Section 4.0 of this document. The boxed processor fan heatsink is able to keep the
processor temperature within the specifications (see Section 4.0) in chassis that provide good
thermal management.
For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to
the fan heatsink is u nimpeded. Airflow of the fan heatsink is into the center and out of th e sides of
the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked . Block ing the airf low to the fan heats ink reduces the coo ling efficiency and
decreases fan life. Figure 35 and Figure 36 illustrate an acceptable airspace clearance for the fan
heatsink. It is also recommended that the air temperature entering the fan be kept below 45 °C.
Again, meeting the processor's temperature specification is the responsibility of the system
integrator. The processor temperature specification is found in Section 4.0 of this document.
Figure 34. Dimensions of Mechanical Step Feature in Heatsink Base for the FC-PGA Package
Datasheet 107
Intel® Celeron™ Processor up to 850 MHz
6.2.1.2 Boxed Processor Thermal Cooling Solution Clip
The boxed processor thermal solution requires installation by a system integrator to secure the
thermal cooling solutio n to the processor after it is installed in the 370-pin socket ZIF socket.
Motherboards designed for use by system integrators should take care to consider the implications
of clip installation and potential scraping of the motherboard PCB underneath the 370-pin socket
attach tabs. Motherboard components should not be placed too close to the 370-pin socket attach
tabs in a way that interferes with the installation of the boxed processor thermal cooling solution
(see Figure 37 for specifications).
Figure 35. Top View Airspace Requirements for the Boxed Processor in the S.E.P. Package
Figure 36. Side View Airspace Requirements for the Boxed Intel® Celeron™ Processor in the
FC-PGA and PPGA packages
0.40 Min Air Space (F)
(both ends)
0.20 Min
Air Space
(G)
Measure ambient temperature
0.3" above center of fan inlet
Fan Heatsink Processor Airspace
Measure ambient temperature 0.3"
above center of fan inlet
0.20 Min
Air Space
0.20 Min
Air Space
Fan Heatsink
Processor
108 Datasheet
Intel® Celeron™ Processor up to 850 MHz
6.3 Electrical Requirements for the Boxed Intel® Cele ron™
Processor
6.3.1 Electrical Requirements
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable is shipped
with the boxed proces sor to draw power from a power header on the mother board. The power ca ble
connector and pin-out are shown in Fi gure 38. Mother boards mu st provide a matched power header
to support the boxed processor. Table 53 contains specifications for the input and output signals at
the fan heatsink connector. The fan heatsink outputs a SENSE signal (an open-collector output)
that pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides VOH
to match the motherboard-mounted fan speed monitor requirements, if applicable. Use of the
SENSE signal is op tio nal. If t he S ENSE si gnal i s not us ed, pin 3 of the connector s hou l d be ti ed t o
GND.
The boxed Intel Celeron processors in the PPGA package at 500 MHz and below are shipped with
an unattached fan heatsink with two wire power-supply cables. These two wire fans do NOT
support the motherboard-mounted fan speed monitor feature. The Intel Celeron processor at
533 MHz and above ship with unattached fan heatsinks that have three power-supply cables. These
three wire fans DO support the motherboard-mounted fan speed monitor feature.
The power header on the baseboard must be positioned to allow the fan heatsink power cable to
reach it. The power header identification and location should be documented in the motherboard
documentation or on the motherboard. Figure 39 shows the recommended location of the fan
power connector relative to the 242-contact slot connector. Figure 40 shows the recommended
Figure 37. Clip Keepout Requirements for the 370-Pin (Top Vie w)
Datasheet 109
Intel® Celeron™ Processor up to 850 MHz
location of the fan power connector relative to the 370-pin socket. For the S.E.P. Package, the
motherboard power header should be positioned within 4.75 inches (lateral) of the fan power
connector. The motherboard power header should be positioned within 4.00 inches (lateral) of the
fan power connector for the PPGA and FC-PGA packages.
Figure 38. Boxed Processor Fan Heatsink Power Cable Connector Description
Table 53. Fan Heatsink Power and Signal Specifications
Description Min Typ Max
+12V : 12 volt fan power supply 10.2V 12V 13.8V
IC: Fan current draw 100 mA
SENSE: SENSE frequency (motherboard should pull this
pin up to appropriate Vcc with resistor) 2 pulses per
fan revolution
Figure 39. Motherboard Power Header Placement for the S.E.P. Package
Pin Signal
Straight square pin, 3-pin terminal housing with
polarizing ribs and friction locking ramp.
0.100" pin pitch, 0.025" square pin width.
Waldom*/Molex* P/N 22-01-3037 or equivalent.
Match with straight pin, friction lock header on motherboard
Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3,
or equivalent.
1
2
3
GND
+12V
SENSE
123
242-Contact Slot Connector
1.449"
1.428" Fan power connector location
(1.56 inches above motherboard
Motherboard fan power header should be
positioned within 4.75 inches of the fan
power connector (lateral distance).
r = 4.75"
110 Datasheet
Intel® Celeron™ Processor up to 850 MHz
Figure 40. Motherboard Power Header Placement Relative to the 370-pin Socket
PGA370
ppga1.vsd
R = 4.00"
Datasheet 111
Intel® Celeron™ Processor up to 850 MHz
7.0 Intel® Celeron™ Processor Signal Description
Table 54 provides an alphabetical listing of all Intel® Celeron™ processor signals. Th e tables at the
end of this section summarize the signals by direction: output, input, and I/O.
Note: Unless otherwise noted, the signals apply to S.E.P., PPGA, and FC-PGA Packages.
Table 54. Alphabetical Signal Reference (Sheet 1 of 7)
Signal Type Description
A[31:3]# I/O
The A[31:3]# (Address) signals define a 232-byte physical memory addres s space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the Intel® Celeron™ processor system
bus. The A[31:24]# signals are parity-protected by the AP1# parity signal, and the
A[23:3]# signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[31:3]#
pins to determine their power-on configuration. See the Pentium® II Processor
Developer’s Manual (Order Number 243502) for details.
A20M# I
If the A20M# (Address-20 Mask) input signal is asserted, the Intel Celeron
processor masks phys ical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the bus. Asserting
A20M# emulates the 8086 processor's address wrap-around at the 1 MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
ADS# I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[31:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all Intel Celeron processor system
bus agents.
BCLK I
The BCLK (Bus Clock) signal determines the bus frequency. All Intel Celeron
processor system bus agents must receive this signal to drive their outputs and latch
their inputs on the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
BNR# I/O
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at t he same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all Intel Celeron
processor system bus agents. In order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, BNR# is activated on
specific clock edges and sampled on specific clock edges.
BP[3:2]# I/O The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.
BPM[1:0]# I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.
BPRI# I
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
Intel Celeron processor system bus. It must connect the appropriate pins of all Intel
Celeron processor system bus agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new requests, unless such
requests are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed, then releases the bus by deasserting
BPRI#.
112 Datasheet
Intel® Celeron™ Processor up to 850 MHz
BSEL[1:0] I/O
These signals are used to select the system bus frequency. The frequency is
determined by the processor(s), chipset, and frequency synthesizer capabilities. All
system bus agents must operate at the same frequency. Individual processors will
only operate at their specified front side bus (FSB) frequency. On motherboards
which support operation at either 66 MHz or 100 MHz, a BSEL[1:0] = “x1” will select
a 100 MHz system bus frequency and a BSEL[1:0] = “x0” will select a 66 MHz
system bus frequency.
These signals must be pulled up to 2.5 V or 3.3 V with 1 KΩ resistor and provided as
a frequency selection signal to the clock driver/synthesizer. See Section 2.7.2 for
implementation examples.
Note: BSEL1 is not used by the Intel® Celeron™ processor.
BR0# I/O
The BR0# (Bus Request) pin drives the BREQ[0]# signal in the system. During
power-up configuration, the central agent asserts the BREQ0# bus signal in the
system to assign the symm etric agent ID to the processor. The processor samples
it’s BR0# pin on the active-to-inactive transition of RESET# to obtain it’s sym metric
agent ID. The processor asserts BR0# to request the system bus.
CPUPRES#
(PPGA and
FC-PGA only) O
The CPUPRES# signal provides the ability for a system board to detect the
presence of a processor. This pin is a ground on the processor indicating to the
system that a processor is installed.
The CPUPRES# signal is defined to allow a system design to detect the presence of
a terminator device or processor in a PGA370 socket. Combined with the VID
combination of VID[3:0]= 11 11 (see Section 2.5), a system can determine if a socket
is occupied, and whether a processor core is present. See the table below for states
and values for determining the presence of a device.
D[63:0]# I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data
path between the Intel Celeron processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
DBSY# I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the Intel Celeron processor system bus to indicate that the data bus is in
use. The data bus is released after DBSY# is deasserted. This signal must connect
the appropriate pins on all Intel Celeron processor system bus agents.
DEFER# I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all Intel Celeron processor system bus agent s.
DRDY# I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multicycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all Intel Celeron processor system bus agent s.
EDGCTRL I The EDGCTRL input provides AGTL+ edge control and should be pulled up to
VCCCORE with a 51 Ω ± 5% resistor.
Note: This signal is NOT used on the FC-PGA package.
Table 54. Alphabetical Signal Reference (Sheet 2 of 7)
Signal Type Description
PGA370 Socket Occupation Truth Table
Signal Value Status
CPUPRES#
VID[3:0]
0
Anything other
than ‘1111’
Processor core installed in the PGA370
socket.
CPUPRES#
VID[3:0] 0
1111 Term inator device installed in the
PGA370 socket (i.e., no core present).
CPUPRES#
VID[3:0] 1
Any va lue P GA370 socket not occupied.
Datasheet 113
Intel® Celeron™ Processor up to 850 MHz
EMI
(S.E.P.P. o n ly ) I
EMI pins should be connected to motherboard ground and/or to chassis ground
through zero ohm (0 Ω) resistors. The zero ohm resistors should be placed in close
proximity to the Intel Celeron processor connector. The path to chassis ground
should be short in length and have a low impedance. These pins are used for EMI
management purposes.
FERR# O
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting.
FLUSH# I
When the FLUSH# input signal is asserted, the processor writes back all dat a in the
Modified state from the internal cache and invalidates all i nternal cache lines. At the
completion of this operation, the processor issues a Flush Acknowledge transaction.
The processor does not cache any new data while the FLUSH# signal remains
asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, the processor samples FLUSH# to
determine its power-on configuration. See Pentium® Pro Family Developer’s
Manual, Volume 1: Specifications (Order Number 242690) for details.
HIT#, HITM# I/O
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all Intel Celeron
processor system bus age nts. Any such agent may asser t both HIT# and HITM#
together to indicate that it requires a snoop stall, which can be continued by
reasserting HIT# and HITM# together.
IERR# O
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the Intel Celeron processor system bus. This transaction may
optionally be converted to an external error signal (e.g., NMI) by system core logic.
The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or
INIT#.
IGNNE# I
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point instructions.
If IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
INIT# I
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1) caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector configured
during power-on configuration. The processor continues to handle snoop requests
during INIT# assertion. INIT# is an asynchronous signal and must connect the
appropriate pins of all bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
LINT[1:0] I
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all
APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Intel® Pentium® proces sor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
Table 54. Alphabetical Signal Reference (Sheet 3 of 7)
Signal Type Description
114 Datasheet
Intel® Celeron™ Processor up to 850 MHz
LOCK# I/O
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the system bus,
it will wait until it observes LOCK# deasserted. This enables symmetric agents to
retain ownership of the system bus throughout the bus locked operation and ensure
the atomicity of lock.
PICCLK I The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors , core logic, and I/O APIC
components on the APIC bus.
PICD[1:0] I/O The PICD[1:0] (APIC Data) signals are used for bidirectional serial message passing
on the APIC bus, and must connect the appropriate pins of the Intel Celeron
processor for proper initialization.
PLL1, PLL2
(PGA packages
only) I
All Intel Celeron processors have internal analog PLL clock generators that require
quiet power supplies. PLL1 and PLL2 are inputs to the internal PLL and should be
connected to VCCCORE through a low-pass filter that minimizes jitter. S ee the
platform design guide for implementation details.
PRDY# O The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.
PREQ# I The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
PWRGOOD I
The PWRGOOD (Power Go od) signal is a 2.5 V tolerant processor input. The
processor requires this signal to be a clean indication that the clocks and power
supplies (VCCCORE, etc.) are stable and within their specifications. Clean implies
that the signal will remain low (capable of sinking leakage current), without glitches,
from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high (2.5 V) state.
Figure 39 illustrates the relationship of PWRGOOD to other system signals.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. It must also meet the
minimum pulse width specification in Table 16 and Table 17, and be followed by a
1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
PWRGOOD Relationship at Power-On
REQ[4:0]# I/O T he REQ[4:0]# (Request Command) signals mus t connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
Table 54. Alphabetical Signal Reference (Sheet 4 of 7)
Signal Type Description
BCLK
PWRGOOD
RESET#
1 ms
VCCCORE,
VREF
Datasheet 115
Intel® Celeron™ Processor up to 850 MHz
RESET# I
Asserting the RESET# signal resets the processor to a known state and invalidates
the L1 cache without writing back any of the contents. RESET# must stay active for
at least one millisecond after VCCCORE and CLK have reached their proper
specifications. On observing active RESET#, all system bus agents will deassert
their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
Pentium® Pro Family Developer’s Manual, V olume 1: Specifications (Order Number
242690).
The processor may have its outputs tristated via power-on configuration. Otherwise,
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in S elf-Test (BIST). Whether or not BIST is executed,
the processor will begin program execution at the power on Reset vector (default
0_FFFF_FFF0h). RESE T# must connect the appropriate pins of all processor
system bus agents.
RS[2:0]# I The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RTTCTRL I
The RTTCTRL input signal provides AGTL+ termination control. The Intel®
Celeron™ FC-PGA processor samples this input to sense the presence of
motherboard AGTL+ termination. See the platform design guide for implementation
details.
SLEWCTRL I
The SLEWCTRL input signal provides AGTL+ slew rate control. The Intel®
Celeron™ FC-PGA processor samples this input to determine the slew rate for
AGTL+ signals when it is the driving agent. See the platform design guide for
implementation details.
SLOTOCC#
(S.E.P.P. o n ly ) O
SLOTOCC# is defined to allow a system design to detect the presence of a
terminator card or processor in a SC242 connector. This pin is not a signal; rather, it
is a short to VSS. Combined with the VID combination of VID[4:0]= 11111 (see
Section 2.5), a system can determine if a SC242 connector is occupied, and
whether a processor core is present. The states and values for determining the type
of cartridge in the SC242 connector is shown below.
SLP# I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
SMI# I
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM ). An SMI Ac knowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
Table 54. Alphabetical Signal Reference (Sheet 5 of 7)
Signal Type Description
SC242 Occupation Truth Table
Signal Value Status
SLOTOCC#
VID[4:0] 0
Anything other than ‘11111’Processor with core in SC242
connector.
SLOTOCC#
VID[4:0] 0
11111 Terminator cartridge in SC242
connector (i.e., no core present).
SLOTOCC#
VID[4:0] 1
Any value SC242 connector not occupied.
116 Datasheet
Intel® Celeron™ Processor up to 850 MHz
STPCLK# I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and may latch interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units, resumes execution, and services
any pending interrupt. The assertion of STPCLK# has no ef fect on the bus clock;
STPCLK# is an asynchronous input.
TCK I The TCK (Test Clock) signal provides the clock input for the Intel Celeron processor
Te st Ac cess Port.
TDI I The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO O The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TESTHI
(S.E.P.P. only) I Ref er to Section 2.6 for implementation details.
THERMDN O Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1.
THERMDP I Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1.
THERMTRIP# O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal T rip) pin. Once activated, the signal remains latched,
and the processor stopped, until RESET# goes active. There is no hysteresis built
into the thermal sensor itself; as long as the die temperature drops below the trip
level, a RESET# pulse will reset the processor and execution will continue. If the
temperature has not dropped below the trip level, the processor will reassert
THERMTRIP# and remain stopped.
TMS I The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
TRDY# I The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready
to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all system bus agents.
TRST# I The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. Intel
Celeron processors require this signal to be driven low during power on Reset. A
680 ohm resistor is the suggested value for a pull down resistor on TRST#.
VCC1.5
(PGA packages
only) I
The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V
must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 1.5 V input to the VCCCMOS output via the package. The
supply for VCC1.5 must be the same one used to supply VTT.
VCC2.5
(PGA packages
only) IThe VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V
must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 2.5 V input to the VCCCMOS output via the package.
VCCCMOS
(PGA packages
only) OThe VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V
must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input.
VCOREDET
(PGA packages
only) OThe VCOREDET signal will float for 2.0 V core processors and will be grounded for
Celeron™ FC-PGA processor with a 1.5V core voltage.
VID[4:0]
(S.E.P.P.)
VID[3:0]
(PGA packages
only)
O
The VID (Volt age ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to V SS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on Intel Celeron processors. See Table 2 for
definitions of these pins. The power supply must supply the voltage that is requested
by these pins, or disable itself.
Table 54. Alphabetical Signal Reference (Sheet 6 of 7)
Signal Type Description
Datasheet 117
Intel® Celeron™ Processor up to 850 MHz
7.1 Signal Summaries
Table 55 through Table 58 list attributes of the Intel® Celeron™ processor output, input, and I/O
signals.
VREF[7:0]
(PGA packages
only) I
These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+
inputs are differential receivers and will use this voltage to determine whether the
signal is a logic high or logic low.
For the FC-PGA package, V REF is typically 2/3 of VTT
Table 54. Alphabetical Signal Reference (Sheet 7 of 7)
Signal Type Description
Table 55. Output Signals
Name Active Level Clock Signal Group
CPUPRES# (PGA
packages only) Low Asynch Power/Other
FERR# Low Asynch CMO S Output
IERR# Low Asynch CMOS Output
PRDY# Low BCLK AGTL+ Output
SLOTOCC#
(S.E.P.P. only ) Low Asynch Power/Other
TDO High TCK TAP Output
THERMDN N/A Asynch Power/Other
THERMT RIP# Low Asynch CMOS Output
VCOREDET
(PGA packages only) High Asynch Power/Other
VID[4:0] (S.E.P.P.)
VID[3:0] (PGA
packages) High Asynch Power/Other
Table 56. Input Signals (Sheet 1 of 2)
Name Active Level Clock S ignal Group Qualified
A20M# Low As ynch CMOS Input Always 1
BPRI# Low BCLK AGTL+ Input Always
BCLK High —System Bus Clock Always
DEFER# Low B CLK AGT L+ Input Always
FLUSH# Low Asynch CMOS Input Always 1
IGNNE# Low Asynch CMOS In put Always 1
INIT# Low Asynch CMOS In put Always 1
INTR High Asynch CMOS In put APIC disabled mode
LINT[1:0] High Asynch CMOS In put APIC enabled mode
NMI High Asynch CMOS In put APIC disabled mode
PICCLK High —APIC Clock Always
PREQ# Low Asynch CMOS Input Always
118 Datasheet
Intel® Celeron™ Processor up to 850 MHz
NOTE:
1. S ync hronous ass ertion with active TRDY# ensures synchronization.
PWRGOOD High Asynch CMOS Input Always
RESET# Low BCLK AGTL+ Input Always
RS[2:0]# Low BCLK AGTL+ Input Always
RTTCTRL N/A Asynch Power/Other
SLEWCTRL N/A Asynch Power/Other
SLP# Low Asynch CMOS Input During Stop-Grant state
SMI# Low Asynch CMOS Input
STPCLK# Low Asynch CMOS Input
TCK High —TAP Input
TDI High TCK TAP Input
TESTHI
(S.E.P.P.
only) High Asynch Power/Other Always
THERMDP N/A Asynch Power/Other
TMS High TCK TAP Input
TRST# Low Asynch TAP Input
TRDY# Low BCLK AGTL+ Input
Table 56. Input Signals (Sheet 2 of 2)
Name Active Level Clock Signal Group Qualified
Table 57. Input/Output Signals (Single Driver)
Name Active Level Clock S ign al Group Qualified
BSEL[1:0] Low Asynch Power/Other Always
BP[3:2] Low BCLK AGTL+ I/O Always
BR0# Low BCLK AGTL+I/O Always
A[31:3]# Low BCLK AGTL+ I/O ADS#, ADS#+1
ADS# Low BCLK AGTL+ I/O Always
BPM[1:0]# Low BCLK AGTL+ I/O Always
D[63:0]# Low BCLK AGTL+ I/O DRDY#
DBSY# Low BCLK AGTL+ I/O Always
DRDY# Low BCLK AGTL+ I/O A lways
LOCK# Low BCLK AGTL+ I/O Always
REQ[4:0]# Low BCLK AGTL+ I/O ADS#, ADS#+1
Table 58. Input/Output Signals (Multiple Driver)
Name Active Level Clock Signal Group Qu alified
BNR# Low BCLK A GTL+ I/O Always
HIT# Low BCLK AGTL+ I/O Always
HITM# Low BCLK A GTL+ I/O Always
PICD[1:0] High PICCLK APIC I/O Always
