2015-2017 Microchip Technology Inc. DS00001855E-page 1
Highlights
• USB Hub Feature Controller IC with 4 USB 3.1
Gen 1 / USB 2.0 downstream ports
• USB-IF Battery Charger revision 1.2 support on
up & downstream ports (DCP, CDP, SDP)
• USB Link Power Management (LPM) support
• Enhanced OEM configuration options available
through either OTP or SPI ROM
• Available in 56-pin (7 x 7 mm) VQFN lead-free,
RoHS compliant package
• Commercial and industrial grade temperature
support
• Configuration Straps: Predefined configuration of
system level functions
Target Applications
• Standalone USB Hubs
• Laptop Docks
• PC Motherboards
• PC Monitor Docks
• Multi-function USB 3.1 Gen 1 Peripherals
Key Benefits
• USB 3.1 Gen 1 compliant 5 Gbps, 480 Mbps,
12 Mbps and 1.5 Mbps operation
- 5 V tolerant USB 2.0 pins
- 1.32 V tolerant USB 3.1 Gen 1 pins
- Integrated termination & pull-up/pull-down resistors
• Supports per port battery charging of most popu-
lar battery powered devices
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
-Apple
portable product charger emulation
- Chinese YD/T 1591-2006 charger emulation
- Chinese YD/T 1591-2009 charger emulation
- European Union universal mobile charger support
- Support for Microchip USC100x family of battery
charging controllers
- Supports additional portable devices
• Smart port controller operation
- Firmware handling of companion port controllers
• On-chip microcontroller
- Manages I/Os, VBUS, and other signals
• 8 KB RAM, 64 KB ROM
• 8 KB One Time Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP ROM, SPI
ROM, or SMBus
•PortSwap
- Configurable differential intro-pair signal swapping
•PHYBoost
™
- Programmable USB transceiver drive strength for
recovering signal integrity
• VariSense™
- Programmable USB receiver sensitivity
• Compatible with Microsoft Windows 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and
low thermal dissipation
• Package
- 56-pin VQFN (7 x 7 mm)
• Environmental
- 3 kV HBM JESD22-A114F ESD protection
- Commercial temperature range (0°C to +70°C)
- Industrial temperature range (-40°C to +85°C)
USB5744
4-Port SS/HS USB Controller Hub
USB5744
DS00001855E-page 2 2015-2017 Microchip Technology Inc.
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2015-2017 Microchip Technology Inc. DS00001855E-page 3
USB5744
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 6
3.0 Pin Description and Configuration .................................................................................................................................................. 8
4.0 Device Connections ...................................................................................................................................................................... 17
5.0 Modes of Operation ...................................................................................................................................................................... 19
6.0 Device Configuration ..................................................................................................................................................................... 22
7.0 Device Interfaces .......................................................................................................................................................................... 23
8.0 Functional Descriptions ................................................................................................................................................................. 24
9.0 Operational Characteristics ........................................................................................................................................................... 30
10.0 Package Information ................................................................................................................................................................... 39
USB5744
DS00001855E-page 4 2015-2017 Microchip Technology Inc.
1.0 PREFACE
1.1 General Terms
TABLE 1-1: GENERAL TERMS
Term Description
ADC Analog-to-Digital Converter
Byte 8 bits
CDC Communication Device Class
CSR Control and Status Registers
DWORD 32 bits
EOP End of Packet
EP Endpoint
FIFO First In First Out buffer
FS Full-Speed
FSM Finite State Machine
GPIO General Purpose I/O
HS Hi-Speed
HSOS High Speed Over Sampling
Hub Feature Controller The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2CInter-Integrated Circuit
LS Low-Speed
lsb Least Significant Bit
LSB Least Significant Byte
msb Most Significant Bit
MSB Most Significant Byte
N/A Not Applicable
NC No Connect
OTP One Time Programmable
PCB Printed Circuit Board
PCS Physical Coding Sublayer
PHY Physical Layer
PLL Phase Lock Loop
RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK Software Development Kit
SMBus System Management Bus
UUID Universally Unique IDentifier
WORD 16 bits
2015-2017 Microchip Technology Inc. DS00001855E-page 5
USB5744
1.2 Reference Documents
1. UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http://
www.usb.org
2. Universal Serial Bus Revisi on 3.1 Specification, http://www.usb.org
3. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
4. I2C-Bus Specification, Version 1.1, http://www.nxp.com
5. System Management Bus Specification, Version 1.0, http://smbus.org/specs
USB5744
DS00001855E-page 6 2015-2017 Microchip Technology Inc.
2.0 INTRODUCTION
2.1 General Description
The Microchip USB5744 hub is low-power, OEM configurable, USB 3.1 Gen 1 hub feature controller with 4 downstream
ports and advanced features for embedded USB applications. The USB5744 is fully compliant with the Universal Serial
Bus Revision 3.1 Specification and USB 2.0 Link Power Management Addendum. The USB5744 supports 5 Gbps
SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB down-
stream devices on all enabled downstream ports.
The USB5744 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub feature controller that is
the culmination of five generations of Microchip hub feature controller design and experience with proven reliability,
interoperability, and device compatibility. The SuperSpeed hub feature controller operates in parallel with the USB 2.0
controller, decoupling the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB5744 supports downstream battery charging. The USB5744 integrated battery charger detection circuitry sup-
ports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5744 provides the bat-
tery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A with data)
• Custom profiles loaded via SMBus or OTP
Additionally, the USB5744 includes many powerful and unique features such as:
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity.
This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.
The USB5744 can be configured for operation through internal default settings. Custom OEM configurations are sup-
ported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility, and are available as GPIOs for customer specific use.
The USB5744 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB5744 is shown in Figure 2-1.
2015-2017 Microchip Technology Inc. DS00001855E-page 7
USB5744
FIGURE 2-1: INTERNAL BLOCK DIAGRAM
USB5744
DS00001855E-page 8 2015-2017 Microchip Technology Inc.
3.0 PIN DESCRIPTION AND CONFIGURATION
3.1 Pin Assignments
Note 1: Configuration straps are identified by an underlined symbol name. Signals that function as configurations
traps must be augmented with an external resistor when connected to a load. Refer to Section 3.4, "Config-
uration Straps and Programmable Functions" for additional information.
FIGURE 3-1: 56-VQFN PIN ASSIGNMENTS
Note:Exposed pad (VSS) on bottom of package must be connected to ground with a via field.
(Connect exposed pad to ground with a via field)
VSS
USB5744
56-VQFN
(Top View)
4
5
6
7
8
9
10
11
18
19
20
21
22
23
24
25
39
38
37
36
35
34
33
32
53
52
51
50
49
48
47
46
USB3DN_RXDM1
USB3DN_RXDP1
USB2DN_DP2/PRT_DIS_P2
USB2DN_DM2/PRT_DIS_M2
USB3DN_TXDP2
USB3DN_TXDM2
VDD12
USB3DN_RXDP2
SPI_CE_N/CFG_NON_REM
SPI_DI/CFG_BC_EN
SPI_CLK/SMCLK
VDD12
VDD33
USB3DN_RXDM4
USB3UP_RXDP
VDD12
VDD12
USB3UP_RXDM
USB3UP_TXDM
USB2DN_DM4/PRT_DIS_M4
USB3DN_RXDP3
USB3DN_TXDP3
USB2DN_DM3/PRT_DIS_M3
USB2DN_DP3/PRT_DIS_P3
VDD33
USB2UP_DP
VBUS_DET
USB2UP_DM
USB3DN_TXDP4
USB3UP_TXDP
VDD12
SPI_DO/SMDAT
45
44
55
54
2
3
12
13
16
17
26
27
31
30
41
40
USB3DN_TXDM3
USB3DN_RXDM3
USB2DN_DP4/PRT_DIS_P4
USB3DN_TXDM4
VDD12
USB3DN_TXDM1
USB3DN_TXDP1
USB2DN_DM1/PRT_DIS_M1
ATEST
XTALO
XTALI/CLK_IN
VDD33
PRT_CTL1
PRT_CTL2
PRT_CTL3
PRT_CTL4/GANG_PWR
1
USB2DN_DP1/PRT_DIS_P1
14USB3DN_RXDM2
15
VDD12
VDD12 28
29 USB3DN_RXDP4
RESET_N
42
43
VDD33
RBIAS
56
2015-2017 Microchip Technology Inc. DS00001855E-page 9
USB5744
Table 3-1 details the package pin assignments in table format.
TABLE 3-1: 56-VQFN PIN ASSIGNMENTS
Pin
Number Pin Name Pin
Number Pin Name
1USB2DN_DP1/PRT_DIS_P1 29 USB3DN_RXDP4
2USB2DN_DM1/PRT_DIS_M1 30 USB3DN_RXDM4
3USB3DN_TXDP1 31 VDD33
4USB3DN_TXDM1 32 PRT_CTL4/GANG_PWR
5VDD12 33 VDD12
6USB3DN_RXDP1 34 PRT_CTL3
7USB3DN_RXDM1 35 PRT_CTL2
8USB2DN_DP2/PRT_DIS_P2 36 PRT_CTL1
9USB2DN_DM2/PRT_DIS_M2 37 VBUS_DET
10 USB3DN_TXDP2 38 SPI_CLK/SMCLK
11 USB3DN_TXDM2 39 SPI_DO/SMDAT
12 VDD12 40 SPI_DI/CFG_BC_EN
13 USB3DN_RXDP2 41 SPI_CE_N/CFG_NON_REM
14 USB3DN_RXDM2 42 RESET_N
15 VDD12 43 VDD12
16 VDD33 44 VDD33
17 USB2DN_DP3/PRT_DIS_P3 45 USB2UP_DP
18 USB2DN_DM3/PRT_DIS_M3 46 USB2UP_DM
19 USB3DN_TXDP3 47 USB3UP_TXDP
20 USB3DN_TXDM3 48 USB3UP_TXDM
21 VDD12 49 VDD12
22 USB3DN_RXDP3 50 USB3UP_RXDP
23 USB3DN_RXDM3 51 USB3UP_RXDM
24 USB2DN_DP4/PRT_DIS_P4 52 ATEST
25 USB2DN_DM4/PRT_DIS_M4 53 XTALO
26 USB3DN_TXDP4 54 XTALI/CLK_IN
27 USB3DN_TXDM4 55 VDD33
28 VDD12 56 RBIAS
USB5744
DS00001855E-page 10 2015-2017 Microchip Technology Inc.
3.2 Pin Descriptions
This section contains descriptions of the various USB5744 pins. This pin descriptions have been broken into functional
groups as follows:
•USB 3.1 Gen 1 Pin Descriptions
•USB 2.0 Pin Descriptions
•USB Port Control Pin Descriptions
•SPI/SMBus Pin Descriptions
•Miscellaneous Pin Descriptions
•Power and Ground Pin Descriptions
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage
level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal
name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “Active high” signals. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-
tive.
Note: The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables. A
description of the buffer types is provided in Section 3.3, "Buffer Types," on page 14.
For additional information on configuration straps and configurable pins, refer to Section 3.4, "Configuration
Straps and Programmable Functions".
TABLE 3-2: USB 3.1 GEN 1 PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1USB3UP_TXDP IO-U USB 3.1 Gen 1 upstream SuperSpeed transmit data plus.
1USB3UP_TXDM IO-U USB 3.1 Gen 1 upstream SuperSpeed transmit data minus.
1USB3UP_RXDP IO-U USB 3.1 Gen 1 upstream SuperSpeed receive data plus.
1USB3UP_RXDM IO-U USB 3.1 Gen 1 upstream SuperSpeed receive data minus.
4USBDN_TXDP[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed transmit data plus.
4USBDN_TXDM[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed transmit data
minus.
4USBDN_RXDP[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed receive data plus.
4USBDN_RXDM[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed receive data
minus.
TABLE 3-3: USB 2.0 PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1USB2UP_DP IO-U USB 2.0 upstream data plus (D+).
1USB2UP_DM IO-U USB 2.0 upstream data minus (D-).
2015-2017 Microchip Technology Inc. DS00001855E-page 11
USB5744
Note 2: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as con-
figurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
4
USB2DN_DP[4:1] IO-U USB 2.0 downstream ports 4-1 data plus (D+).
PRT_DIS_P[4:1] I
Port 4-1 D+ Disable Configuration Strap.
These configuration straps are used in conjunction with the corre-
sponding PRT_DIS_M[4:1] straps to disable the related port (4-1).
Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] /
PRT_DIS_M[4:1])" for more information.
See Note 2.
4
USB2DN_DM[4:1] IO-U USB 2.0 downstream ports 4-1 data minus (D-).
PRT_DIS_M[4:1] I
Port 4-1 D- Disable Configuration Strap.
These configuration straps are used in conjunction with the corre-
sponding PRT_DIS_P[4:1] straps to disable the related port (4-1).
Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] /
PRT_DIS_M[4:1])" for more information.
See Note 2.
1VBUS_DET IS
This signal detects the state of the upstream bus power.
When designing a detachable hub, this pin must be connected to the
VBUS power pin of the upstream USB port through a resistor divider
(50 k by 100 k) to provide 3.3 V.
For self-powered applications with a permanently attached host, this
pin must be connected to either 3.3 V or 5.0 V through a resistor
divider to provide 3.3 V.
In embedded applications, VBUS_DET may be controlled (toggled)
when the host desires to renegotiate a connection without requiring a
full reset of the device.
GPIO16 I/O6 General purpose input/output 16.
TABLE 3-4: USB PORT CONTROL PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1PRT_CTL1 I
(PU)
Port 1 Power Enable / Overcurrent Sense.
As an output, this signal is an active high control signal used to enable
power to the downstream port 1. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 1.
1PRT_CTL2 I
(PU)
Port 2 Power Enable / Overcurrent Sense.
As an output, this signal is an active high control signal used to enable
power to the downstream port 2. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 2.
TABLE 3-3: USB 2.0 PIN DESCRIPTIONS (CONTINUED)
Num
Pins Symbol Buffer
Type Description
USB5744
DS00001855E-page 12 2015-2017 Microchip Technology Inc.
Note 3: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as con-
figurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
1PRT_CTL3 I
(PU)
Port 3 Power Enable / Overcurrent Sense.
As an output, this signal is an active high control signal used to enable
power to the downstream port 3. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 3.
1
PRT_CTL4 I
(PU)
Port 4 Power Enable / Overcurrent Sense.
As an output, this signal is an active high control signal used to enable
power to the downstream port 4. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 4.
GANG_PWR I
(PU)
When pulled high enables gang mode. Gang power pin when used in
gang mode.
TABLE 3-5: SPI/SMBUS PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1
SPI_CE_N O12 Active low SPI chip enable output.
GPIO7 I/O12 General purpose input/output 7.
CFG_NON_REM I
Non-Removable Port Configuration Strap.
This configuration strap is used to configure the number of non-
removable ports. Refer to Section 3.4.3, "Non-Removable Port Con-
figuration (CFG_NON_REM)" for more information.
See Note 3.
1
SPI_CLK O6 SPI clock output to the serial ROM, when configured for SPI opera-
tion.
SMCLK OD12 SMBus clock pin, when configured for SMBus slave operation.
GPIO4 I/O6 General purpose input/output 4.
1
SPI_DO O6 SPI data output, when configured for SPI operation.
SMDAT I/O12 SMBus data pin, when configured for SMBus slave operation.
GPIO5 I/O6 General purpose input/output 5.
1
SPI_DI IS SPI data input, when configured for SPI operation.
GPIO9 I/O12 General purpose input/output 9.
CFG_BC_EN I
Battery Charging Configuration Strap.
This configuration strap is used to enable battery charging. Refer to
Section 3.4.4, "Battery Charging Configuration (CFG_BC_EN)" for
more information.
See Note 3.
TABLE 3-4: USB PORT CONTROL PIN DESCRIPTIONS (CONTINUED)
Num
Pins Symbol Buffer
Type Description
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USB5744
TABLE 3-6: MISCELLANEOUS PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1RESET_N IS The RESET_N pin puts the device into Reset Mode, as the name of
the pin and function then align.
1
XTALI ICLK External 25 MHz crystal input
CLK_IN ICLK
External reference clock input.
The device may alternatively be driven by a single-ended clock oscil-
lator. When this method is used, XTALO should be left unconnected.
1XTALO OCLK External 25 MHz crystal output
1RBIAS AI A 12.0 k (+/- 1%) resistor is attached from ground to this pin to set
the transceiver’s internal bias settings.
1ATEST AI
Analog test pin.
This signal is used for test purposes and must always be connected to
ground.
TABLE 3-7: POWER AND GROUND PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
4VDD33 P
+3.3 V power and internal regulator input
Refer to Section 4.1, "Power Connections" for power connection infor-
mation.
8VDD12 P
+1.2 V core power
Refer to Section 4.1, "Power Connections" for power connection infor-
mation.
Pad VSS P
Common ground.
This exposed pad must be connected to the ground plane with a via
array.
USB5744
DS00001855E-page 14 2015-2017 Microchip Technology Inc.
3.3 Buffer Types
TABLE 3-8: BUFFER TYPES
Buffer Type Description
I Input
IS Schmitt-triggered input
O6 Output with 6 mA sink and 6 mA source
O12 Output with 12 mA sink and 12 mA source
OD12 Open-drain output with 12 mA sink
PU 50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
PD 50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled low, an external resistor must be added.
IO-U Analog input/output as defined in USB specification
AI Analog input
ICLK Crystal oscillator input pin
OCLK Crystal oscillator output pin
P Power pin
Note: Refer to Section 9.5, "DC Specifications" for individual buffer DC electrical characteristics.
2015-2017 Microchip Technology Inc. DS00001855E-page 15
USB5744
3.4 Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following de-
assertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various
device configuration straps and associated programmable pin functions.
3.4.1 SPI/SMBUS CONFIGURATION
The SPI/SMBus pins can be configured into one of two functional modes:
• SPI Mode
• SMBus Slave Mode
If 10 k pull-up resistors are detected on SPI_DO and SPI_CLK, the SPI/SMBus pins are configured into SMBus Slave
Mode. If no pull-ups or pull-downs are detected on SPI_DO and SPI_CLK, the SPI/SMBus pins are first configured into
SPI Mode. The strap settings for these supported modes are detailed in Table 3-9. The individual pin function assign-
ments for each mode are detailed in Table 3-10. For additional device connection information, refer to Section 4.0,
"Device Connections".
Note 4: In order to use the SPI interface, an SPI ROM containing a valid signature of 2DFU (device firmware
upgrade) beginning at address 0xFFFA must be present. Refer to Section 7.1, "SPI Master Interface" for
additional information.
Note: The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 9.6.2, "Power-On and Configuration Strap Timing," on page 34 and Section 9.6.3, "Reset and Con-
figuration Strap Timing," on page 35. If configuration straps are not at the correct voltage level prior to being
latched, the device may capture incorrect strap values.
TABLE 3-9: SPI/SMBUS MODE CONFIGURATION SETTINGS
Pin SPI Mode
(Note 4)SMBus Slave Mode
39
(SPI_DO)No pull-up/down 10 k pull-up
38
(SPI_CLK)No pull-up/down 10 k pull-up
TABLE 3-10: SPI/SMBUS MODE PIN ASSIGNMENTS
Pin SPI Mode SMBus Slave Mode
41 SPI_CE_N CFG_NON_REM
40 SPI_DI CFG_BC_EN
39 SPI_DO SMDAT
38 SPI_CLK SMCLK
USB5744
DS00001855E-page 16 2015-2017 Microchip Technology Inc.
3.4.2 PORT DISABLE CONFIGURATION (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])
The PRT_DIS_P[4:1] and PRT_DIS_M[4:1] configuration straps are used in conjunction to disable the related port (4-1).
For PRT_DIS_Px (where x is the corresponding port 4-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 4-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
3.4.3 NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown
in Table 3-11.
3.4.4 BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in
Table 3-12.
Note: Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.1
Gen 1 port.
TABLE 3-11: CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value Setting
200 kΩ Pull-Down All ports removable
200 kΩ Pull-Up Port 1 non-removable
10 kΩ Pull-Down Port 1, 2 non-removable
10 kΩ Pull-Up Port 1, 2, 3, non-removable
10 Ω Pull-Down Port 1, 2, 3, 4 non-removable
TABLE 3-12: CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value Setting
200 kΩ Pull-Down No battery charging
200 kΩ Pull-Up Port 1 battery charging
10 kΩ Pull-Down Port 1, 2 battery charging
10 kΩ Pull-Up Port 1, 2, 3, battery charging
10 Ω Pull-Down Port 1, 2, 3, 4 battery charging
2015-2017 Microchip Technology Inc. DS00001855E-page 17
USB5744
4.0 DEVICE CONNECTIONS
4.1 Power Connections
Figure 4-1 illustrates the device power connections.
4.2 SPI ROM Connections
Figure 4-2 illustrates the device SPI ROM connections. Refer to Section 7.1, "SPI Master Interface," on page 23 for
additional information on this device interface.
FIGURE 4-1: POWER CONNECTIONS
FIGURE 4-2: SPI ROM CONNECTIONS
+3.3V
Supply
USB5744
3.3V Internal Logic
VDD33
(4x)
VSS
1.2V Internal Logic
+1.2V
Supply
VDD12
(8x)
USB5744
SPI_CE_N
SPI_CLK
SPI_DO
SPI_DI
SPI ROM
CE#
CLK
DO
DI
USB5744
DS00001855E-page 18 2015-2017 Microchip Technology Inc.
4.3 SMBus Slave Connections
Figure 4-3 illustrates the device SMBus slave connections. Refer to Section 7.2, "SMBus Slave Interface," on page 23
for additional information on this device interface.
FIGURE 4-3: SMBUS SLAVE CONNECTIONS
+3.3V
USB5744SMCLK
SMDAT
SMBus
Master
Clock
Data
10K
+3.3V
10K
2015-2017 Microchip Technology Inc. DS00001855E-page 19
USB5744
5.0 MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Tab le 5- 1.
The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode
stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.
TABLE 5-1: MODES OF OPERATION
RESET_N Input Summary
0 St andby Mode: This is the lowest power mode of the device. No functions are active
other than monitoring the RESET_N input. All port interfaces are high impedance and
the PLL is halted. Refer to Section 8.2.2, "External Chip Reset (RESET_N)" for addi-
tional information on RESET_N.
1 Hub (Normal) Mode: The device operates as a configurable USB hub with battery
charger detection. This mode has various sub-modes of operation, as detailed in
Figure 5-1. Power consumption is based on the number of active ports, their speed,
and amount of data received.
FIGURE 5-1: HUB MODE FLOWCHART
Combine OTP
Config Data
In SPI Mode &
Ext. SPI ROM
present?
YES
NO
Run From
External SPI ROM
(SPI_INIT)
SMBus Host Present?
RESET_N deasserted
Modify Config
Based on Config
Straps
(CFG_RD)
Load Config from
Internal ROM
YES
NO
(STRAP)
Perform SMBus/I2C
Initialization
SOC Done?
YES
NO
(SOC_CFG)
(OTP_CFG)
Hub Connect
(Hub.Connect)
Normal operation
USB5744
DS00001855E-page 20 2015-2017 Microchip Technology Inc.
5.1 Boot Sequence
5.1.1 STANDBY MODE
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maxi-
mum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.1.2 SPI INITIALIZATION STAGE (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the
external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signa-
ture is not found, then execution continues from internal ROM (CFG_RD stage).
When using an external SPI ROM, a 1 Mbit, 60 MHz or faster ROM must be used. Both 1- and 2-bit SPI operation are
supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also
supported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_RD stage).
5.1.3 CONFIGURATION READ STAGE (CFG_RD)
In this stage, the internal firmware loads the default values from the internal ROM and then uses the configuration strap-
ping options to override the default values. Refer to Section 3.4, "Configuration Straps and Programmable Functions"
for information on usage of the various device configuration straps.
5.1.4 STRAP READ STAGE (STRAP)
In this stage, the firmware registers the configuration strap settings on the SPI_DO and SPI_CLK pins. Refer to Section
3.4.1, "SPI/SMBus Configuration" for information on configuring these straps. If configured for SMBus Slave Mode, the
next state will be SOC_CFG. Otherwise, the next state is OTP_CFG.
5.1.5 SOC CONFIGURATION STAGE (SOC_CFG)
In this stage, the SOC can modify any of the default configuration settings specified in the integrated ROM, such as USB
device descriptors and port electrical settings.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. When
the SOC has completed configuring the device, it must write to register 0xFF to end the configuration.
5.1.6 OTP CONFIGURATION STAGE (OTP_CFG)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is pro-
grammed.
After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present.
Once VBUS is present, and battery charging is enabled, the device will transition to the Battery Charger Detection
Stage. If VBUS is present, and battery charging is not enabled, the device will transition to the Connect stage.
5.1.7 HUB CONNECT STAGE (HUB.CONNECT)
Once the CHGDET stage is completed, the device enters the Hub Connect stage. USB connect can be initiated by
asserting the VBUS pin function high. The device will remain in the Hub Connect stage indefinitely until the VBUS pin
function is deasserted.
2015-2017 Microchip Technology Inc. DS00001855E-page 21
USB5744
5.1.8 NORMAL MODE
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the sys-
tem.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated
hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub.Connect stage until
the soft disconnect is negated.
USB5744
DS00001855E-page 22 2015-2017 Microchip Technology Inc.
6.0 DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. The hub can be configured either internally or externally depending on
the implemented interface.
Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5744 functions,
registers and OTP memory. All configuration is to be performed via the Pro-Touch programming tool. For additional infor-
mation on the Pro-Touch programming tool, refer to the Software Libraries within the Microchip USB5744 product page
at www.microchip.com/USB5744.
6.1 Customer Accessible Functions
The following USB or SMBus accessible functions are available to the customer via the Pro-Touch Programming Tool.
6.1.1 USB ACCESSIBLE FUNCTIONS
6.1.1.1 OTP Access over USB
The OTP ROM in the device is accessible via the USB bus. All OTP parameters can be modified to the USB Host. The
OTP operates in Single Ended mode. For more information, refer to the Microchip USB5744 product page and SDK at
www.microchip.com/USB5744
6.1.1.2 Battery Charging Access over USB
The Battery charging behavior of the device can be dynamically changed by the USB Host when something other than
the preprogrammed or OTP programmed behavior is desired. For more information, refer to the Microchip USB5744
product page and SDK at www.microchip.com/USB5744
6.1.2 SMBUS ACCESSIBLE FUNCTIONS
OTP access and configuration of specific device functions are possible via the USB5744 SMBus. All OTP parameters
can be modified via the SMBus Host. The OTP can be programmed to operate in Single-Ended, Differential, Redundant,
or Differential Redundant mode, depending on the level of reliability required. For more information, refer to AN1903 -
“Configuration Options for the USB5734 and USB5744” application note at www.microchip.com/AN1903.
Note: Device configuration straps and programmable pins are detailed in Section 3.4, "Configuration Straps and
Programmable Functions," on page 15.
Refer to Section 7.0, "Device Interfaces" for detailed information on each device interface.
Note: For additional programming details, refer to the Pro-Touch programming tool.
2015-2017 Microchip Technology Inc. DS00001855E-page 23
USB5744
7.0 DEVICE INTERFACES
The USB5744 provides multiple interfaces for configuration and external memory access. This section details the vari-
ous device interfaces and their usage:
•SPI Master Interface
•SMBus Slave Interface
7.1 SPI Master Interface
The device is capable of code execution from an external SPI ROM. When configured for SPI Mode, on power up the
firmware looks for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) begin-
ning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins
at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal
ROM.
7.2 SMBus Slave Interface
The device includes an integrated SMBus slave interface, which can be used to access internal device run time registers
or program the internal OTP memory. SMBus slave detection is accomplished by detection of pull-up resistors on both
the SMDAT and SMCLK signals. Refer to Section 3.4.1, "SPI/SMBus Configuration" for additional information.
Note: For details on how to enable each interface, refer to Section 3.4.1, "SPI/SMBus Configuration".
For information on device connections, refer to Section 4.0, "Device Connections". For information on
device configuration, refer to Section 6.0, "Device Configuration".
Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5744
functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch programming
tool. For additional information on the Pro-Touch programming tool, refer to Software Libraries within Micro-
chip USB5744 product page at www.microchip.com/USB5744.
Note: For SPI timing information, refer to Section 9.6.7, "SPI Timing".
Note: All device configuration must be performed via the Pro-Touch Programming Tool. For additional information
on the Pro-Touch programming tool, refer to Software Libraries within Microchip USB5744 product page at
www.microchip.com/USB5744.
USB5744
DS00001855E-page 24 2015-2017 Microchip Technology Inc.
8.0 FUNCTIONAL DESCRIPTIONS
This section details various USB5744 functions, including:
•Downstream Battery Charging
•Resets
•Link Power Management (LPM)
•Port Control Interface
8.1 Downstream Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTL[4:1] pins, is
on a per port basis. For example, the OEM can configure two ports to support battery charging through high current
power FETs and leave the other two ports as standard USB ports.
For additional information, refer to the Microchip USB5744 Battery Charging application note on the Microchip.com
USB5744 product page at www.microchip.com/USB5744.
FIGURE 8-1: BATTERY CHARGING EXTERNAL POWER SUPPLY
SOC
VBUS[n]
PRT_CTL[n]
INT
SCL
SDA
Microchip
Hub
DC Power
2015-2017 Microchip Technology Inc. DS00001855E-page 25
USB5744
8.2 Resets
The device includes the following chip-level reset sources:
•Power-On Reset (POR)
•External Chip Reset (RESET_N)
•USB Bus Reset
8.2.1 POWER-ON RESET (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the
device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, "Power-On
and Configuration Strap Timing," on page 34.
8.2.2 EXTERNAL CHIP RESET (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the
specifications in Section 9.6.3, "Reset and Configuration Strap Timing," on page 35. While reset is asserted, the device
(and its associated external circuitry) enters Standby Mode and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
4. The external crystal oscillator is halted.
5. The PLL is halted.
8.2.3 USB BUS RESET
In response to the upstream port signaling a reset to the device, the device performs the following:
1. Sets default address to 0.
2. Sets configuration to Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with the USB Specification for behavior after completion of a reset sequence.
The host then configures the device in accordance with the USB Specification.
8.3 Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.
Note: All power supplies must have reached the operating levels mandated in Section 9.2, "Operating Condi-
tions**," on page 30, prior to (or coincident with) the assertion of RESET_N.
Note: The device does not propagate the upstream USB reset to downstream devices.
TABLE 8-1: LPM STATE DEFINITIONS
State Description Entry/Exit Time to L0
L2 Suspend Entry: ~3 ms
Exit: ~2 ms (from start of RESUME)
L1 Sleep Entry: <10 us
Exit: <50 us
L0 Fully Enabled (On) -
USB5744
DS00001855E-page 26 2015-2017 Microchip Technology Inc.
8.4 Port Control Interface
Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled
directly from the USB hub, or via the processor.
The device can be configured into the following port control modes:
• Ganged Mode
• Combined Mode
Port connection in various modes are detailed in the following subsections.
8.4.1 PORT CONNECTION IN GANGED MODE
In this mode, one pin (GANG_PWR) is used to control port power and over-current sensing.
8.4.2 PORT CONNECTION IN COMBINED MODE
8.4.2.1 Port Power Control using USB Power Switch
When operating in combined mode, the device will have one port power control and over-current sense pin for each
downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation,
the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable
the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert
the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not inter-
fere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up.
When the port is enabled, the PRT_CTLx pin input is constantly sampled. Overcurrent events can be detected in one
of two ways:
• Single, continuous low pulse (consecutive low samples over tocs_single), as shown in Figure 8-3.
• Two short low pulses within a rolling window (two groupings of 1 or more low samples over tocs_double), as shown
in Figure 8-4.
FIGURE 8-2: PORT POWER CONTROL WITH USB POWER SWITCH
FIGURE 8-3: SINGLE LOW PULSE OVERCURRENT DETECTION
USB Power
Switch
50k
PRTPWR
EN
OCS
OCS
Pull-Up Enable
5V
USB
Device
FILTER
PRT_CTLx
PRT_CTLx IS VIL
tocs_single
2015-2017 Microchip Technology Inc. DS00001855E-page 27
USB5744
8.4.2.2 Port Power Control using Poly Fuse
When using the device with a poly fuse, there is no need for an output power control. To maintain consistency, the same
circuit will be used. A single port power control and over-current sense for each downstream port is still used from the
Hub's perspective. When disabling port power, the driver will actively drive a '0'. This will have no effect as the external
diode will isolate pin from the load. When port power is enabled, it will disable the output driver and enable the pull-up
resistor. This means that the pull-up resistor is providing 3.3 volts to the anode of the diode. If there is an over-current
situation, the poly fuse will open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will
be at 0.7 volts, and the Schmidt trigger input will register this as a low resulting in an over-current detection. The open
drain output does not interfere.
FIGURE 8-4: DOUBLE LOW PULSE OVERCURRENT DETECTION
TABLE 8-2: OVERCURRENT PULSE TIMING
Symbol Description Min Max Units
tocs_single single low pulse assertion time 5 - ms
tocs_double double low pulse window - 20 ms
Note: The USB 2.0 and USB 3.1 Gen 1 bPwrOn2PwrGood descriptors must be set to 0 when using poly-fuse
mode. Refer to Microchip application note AN1903 “Configuration Options for the USB5734 and USB5744”
for details on how to change these values.
FIGURE 8-5: PORT POWER CONTROL USING A POLY FUSE
PRT_CTLx IS VIL
tocs_double
PRT_CTLx
50k
PRTPWR
OCS
USB
Device
Pull-Up Enable
5V
Poly Fuse
FILTER
USB5744
DS00001855E-page 28 2015-2017 Microchip Technology Inc.
8.4.2.3 Port Power Control with Single Poly Fuse and Multiple Loads
Many customers use a single poly fuse to power all their devices. For the ganged situation, all power control pins must
be tied together.
8.4.3 PORT CONTROLLER CONNECTION EXAMPLE
FIGURE 8-6: PORT POWER CONTROL WITH GANGED CONTROL WITH POLY FUSE
FIGURE 8-7: USB5744 WITH 4 GENERIC PORT POWER CONTROLLERS (2 BC ENABLED)
USB5744
Port 1
Connector
Generic Port
Power Controller
POWER
(High Current)
(BC Enabled)
OCS
D+
D-
VBUS
D+
D-
Port 2
Connector
Generic Port
Power Controller
POWER
(High Current)
(BC Enabled)
OCS
D+
D-
VBUS
D+
D-
PRT_CTL2
PRT_CTL1
Port 3
Connector
Generic Port
Power Controller
POWER
OCS
D+
D-
VBUS
D+
D-
PRT_CTL3
Port 4
Connector
Generic Port
Power Controller
POWER
OCS
D+
D-
VBUS
D+
D-
PRT_CTL4
2015-2017 Microchip Technology Inc. DS00001855E-page 29
USB5744
Note: The CFG_BC_EN configuration strap must be properly configured to enable battery charging on the appro-
priate ports. For example, in the application shown in Figure 8-7, CFG_BC_EN must be connected to an
external 10 kΩ pull-down resistor to enable battery charging on Ports 1 and 2. For more information on the
CFG_BC_EN configuration strap, refer to Section 3.4.4, "Battery Charging Configuration (CFG_BC_EN)".
USB5744
DS00001855E-page 30 2015-2017 Microchip Technology Inc.
9.0 OPERATIONAL CHARACTERISTICS
9.1 Absolute Maximum Ratings*
+1.2 V Supply Voltage (VDD12) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +1.32 V
+3.3 V Supply Voltage (VDD33) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V
Positive voltage on input signal pins, with respect to ground (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6 V
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V
Positive voltage on XTALI/CLK_IN, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.63 V
Positive voltage on USB DP/DM signal pins, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0 V
Positive voltage on USB 3.1 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground. . . . . 1.32 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +150oC
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125oC
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute max-
imum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit.
Note 2: This rating does not apply to the following pins: All USB DM/DP pins, XTAL1/CLK_IN, and XTALO
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Section 9.2, "Operating Conditions**", Section 9.5,
"DC Specifications", or any other applicable section of this specification is not implied.
9.2 Operating Conditions**
+1.2 V Supply Voltage (VDD12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.08 V to +1.32 V
+3.3 V Supply Voltage (VDD33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V
Input Signal Pins Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +3.6 V
XTALI/CLK_IN Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +3.6 V
USB 2.0 DP/DM Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +5.5 V
USB 3.1 Gen 1 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +1.32 V
Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 3
+1.2 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 µs
+3.3 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 µs
Note 3: 0oC to +70oC for commercial version, -40oC to +85oC for industrial version.
**Proper operation of the device is guaranteed only within the ranges specified in this section.
Note: Do not drive input signals without power supplied to the device.
2015-2017 Microchip Technology Inc. DS00001855E-page 31
USB5744
9.3 Package Thermal Specifications
FIGURE 9-1: SUPPLY RISE TIME MODEL
TABLE 9-1: PACKAGE THERMAL PARAMET E R S
Symbol °C/W Velocity (Meters/s)
JA
30 0
26 1
JT
0.2 0
0.3 1
JC
2.6 0
2.6 1
Note: Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51.
TABLE 9-2: MAXIMUM POWER DISSIPATION
Parameter Value Units
PD(max) 1400 mW
t10%
10%
90%
Voltage TRT
t90% Time
100%
3.3 V
VSS
VDD33
90%
100%
1.2 V
VDD12
USB5744
DS00001855E-page 32 2015-2017 Microchip Technology Inc.
9.4 Power Consumption
This section details the power consumption of the device as measured during various modes of operation. Power dis-
sipation is determined by temperature, supply voltage, and external source/sink requirements.
TABLE 9-3: DEVICE POWER CONSUMPTION
Typical (mA) Typical Power
VDD33 VDD12 (mW)
Reset 0.8 1.8 4.8
No VBUS 2.0 5.0 12.6
Global Suspend 2.0 5.2 12.9
4 FS Ports 39 35 170
4 HS Ports 53 42 222
4 SS Ports 55 683 1001
4 SS/HS Ports 93 688 1132
2015-2017 Microchip Technology Inc. DS00001855E-page 33
USB5744
9.5 DC Specifications
Note 4: XTALI can optionally be driven from a 25 MHz singled-ended clock oscillator.
Note 5: Refer to the USB 3.1 Gen 1 Specification for USB DC electrical characteristics.
TABLE 9-4: I/O DC ELECTRICAL CHARACTERISTICS
Parameter Symbol Min Typical Max Units Notes
I Type Input Buffer
Low Input Level
High Input Level
VIL
VIH 2.1
0.9 V
V
IS Type Input Buffer
Low Input Level
High Input Level
Schmitt Trigger Hysteresis
(VIHT - VILT)
VIL
VIH
VHYS
1.9
920
0.9
40
V
V
mV
O6 Type Output Buffer
Low Output Level
High Output Level
VOL
VOH VDD33-0.4
0.4 V
V
IOL = 6 mA
IOH = -6 mA
O12 Type Output Buffer
Low Output Level
High Output Level
VOL
VOH VDD33-0.4
0.4 V
V
IOL = 12 mA
IOH = -12 mA
OD12 Type Ou tput Buffer
Low Output Level VOL 0.4 V IOL = 12 mA
ICLK Type I nput Buffer
(XTALI Input)
Low Input Level
High Input Level
VIL
VIH 0.85
0.50
VDD33
V
V
Note 4
IO-U Type Buffer
(See Note 5)Note 5
USB5744
DS00001855E-page 34 2015-2017 Microchip Technology Inc.
9.6 AC Specifications
This section details the various AC timing specifications of the device.
9.6.1 POWER SUPPLY AND RESET_N SEQUENCE TIMING
Figure 9-2 illustrates the recommended power supply sequencing and timing for the device. VDD33 should rise after or
at the same rate as VDD12. Similarly, RESET_N and/or VBUS_DET should rise after or at the same rate as VDD33.
VBUS_DET and RESET_N do not have any other timing dependencies.
9.6.2 POWER-ON AND CONFIGURATION STRAP TIMING
Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where
RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following
timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in Section
9.2, "Operating Conditions**," on page 30.
Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, "Reset and Con-
figuration Strap Timing" for additional details.
FIGURE 9-2: POWER SUPPLY AND RESET_N SEQUENCE TIMING
TABLE 9-5: POWER SUPPLY AND RESET_N SEQUENCE TIMING
Symbol Description Min Typ Max Units
tVDD33 VDD12 to VDD33 rise time 0 ms
treset VDD33 to RESET_N/VBUS_DET rise time 0 ms
FIGURE 9-3: POWER-ON CONFIGURA TI ON STRAP VALID TIMING
TABLE 9-6: POWER-ON CONFIGURATION STRAP LATCHING TIMING
Symbol Description Min Typ Max Units
tcsh Configuration strap hold after external power supplies at opera-
tional levels
1ms
VDD12
VDD33
RESET_N/
VBUS_DET
All External
Power Supplies
Vopp
Configuration
Straps
tcsh
2015-2017 Microchip Technology Inc. DS00001855E-page 35
USB5744
9.6.3 RESET AND CONFIGURATION STRAP TIMING
Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of
RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to Section
8.2, "Resets" for additional information on resets. Refer to Section 3.4, "Configuration Straps and Programmable Func-
tions" for additional information on configuration straps.
9.6.4 USB TIMING
All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Uni-
versal Serial Bus Specification. Please refer to the Universal Seria l Bus Revision 3.1 Specification, available at http://
www.usb.org/developers/docs.
9.6.5 I2C TIMING
All device I2C signals conform to the 400KHz Fast Mode (Fm) voltage, power, and timing characteristics/specifications
as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus Specification, available at http://www.nxp.com/doc-
uments/user_manual/UM10204.pdf.
9.6.6 SMBUS TIMING
All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Sys-
tem Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available
at http://smbus.org/specs.
FIGURE 9-4: RESET_N CONFIGURATION ST RAP TIMING
TABLE 9-7: RESET_N CONFIGURATION STRAP TIMING
Symbol Description Min Typ Max Units
trstia RESET_N input assertion time 5 s
tcsh Configuration strap pins hold after RESET_N deassertion 1 ms
Note: The clock input must be stable prior to RESET_N deassertion.
Configuration strap latching and output drive timings shown assume that the Power-On reset has finished
first otherwise the timings in Section 9.6.2, "Power-On and Configuration Strap Timing" apply.
RESET_N
Configuration
Straps
trstia
tcsh
USB5744
DS00001855E-page 36 2015-2017 Microchip Technology Inc.
9.6.7 SPI TIMING
This section specifies the SPI timing requirements for the device.
FIGURE 9-5: SPI TIMING
TABLE 9-8: SPI TIMING (30 MHZ OPERATION)
Symbol Description Min Typ Max Units
tfc Clock frequency 30 MHz
tceh Chip enable (SPI_CE_EN) high time 100 ns
tclq Clock to input data 13 ns
tdh Input data hold time 0 ns
tos Output setup time 5 ns
toh Output hold time 5 ns
tov Clock to output valid 4 ns
tcel Chip enable (SPI_CE_EN) low to first clock 12 ns
tceh Last clock to chip enable (SPI_CE_EN) high 12 ns
TABLE 9-9: SPI TIMING (60 MHZ OPERATION)
Symbol Description Min Typ Max Units
tfc Clock frequency 60 MHz
tceh Chip enable (SPI_CE_EN) high time 50 ns
tclq Clock to input data 9 ns
tdh Input data hold time 0 ns
tos Output setup time 5 ns
toh Output hold time 5 ns
tov Clock to output valid 4 ns
tcel Chip enable (SPI_CE_EN) low to first clock 12 ns
tceh Last clock to chip enable (SPI_CE_EN) high 12 ns
SPI_CLK
SPI_DI
SPI_DO
SPI_CE_N
tcel tfc
tclq
tceh
tdh
toh
tos tov toh
2015-2017 Microchip Technology Inc. DS00001855E-page 37
USB5744
9.7 Clock Specifications
The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input. If the single-
ended clock oscillator method is implemented, XTALO should be left unconnected and XTALI/CLK_IN should be
driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). The following circuit design (Figure 9-6) and specifications (Table 9 - 10) are required to ensure proper
operation.
9.7.1 CRYSTAL SPECIFICATIONS
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). Refer to Table 9-10 for the recommended crystal specifications.
Note 6: Frequency Deviation Over Time is also referred to as Aging.
FIGURE 9-6: 25MHZ CRYSTAL CIRCUIT
TABLE 9-10: CRYSTAL SPECIFICATIONS
Parameter Symbol Min Nom Max Units Notes
Crystal Cut AT, typ
Crystal Oscillation Mode Fundamental Mode
Crystal Calibration Mode Parallel Resonant Mode
Frequency Ffund - 25.000 - MHz
Frequency Tolerance @ 25oCF
tol - - ±50 PPM Note 6
Frequency Stability Over Temp Ftemp - - ±50 PPM Note 6
Frequency Deviation Over Time Fage - ±3 to 5 - PPM
Total Allowable PPM Budget - - ±100 PPM Note 7
Shunt Capacitance CO- 7 typ - pF
Load Capacitance CL- 20 typ - pF
Drive Level PW100 - - uW
Equivalent Series Resistance R1--50Ω
Operating Temperature Range Note 7 -Note 8 oC
XTALI/CLK_IN Pin Capacitance - 3 typ - pF Note 9
XTALO Pin Capacitance - 3 typ - pF Note 9
USB5744
XTALO
XTALI
Y1
C1C2
USB5744
DS00001855E-page 38 2015-2017 Microchip Technology Inc.
Note 7: 0 °C for commercial version, -40 °C for industrial version.
Note 8: +70 °C for commercial version, +85 °C for industrial version.
Note 9: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this
value. The XTALI/CLK_IN pin, XTALO pin and PCB capacitance values are required to accurately calcu-
late the value of the two external load capacitors. These two external load capacitors determine the accu-
racy of the 25.000 MHz frequency.
9.7.2 EXTERNAL REFERENCE CLOCK (CLK_IN)
When using an external reference clock, the following input clock specifications are suggested:
•25MHz
• 50% duty cycle ±10%, ±100 ppm
• Jitter < 100 ps RMS
2015-2017 Microchip Technology Inc. DS00001855E-page 39
USB5744
10.0 PACKAGE INFORMATION
10.1 Package Marking Information
*Standard device marking consists of Microchip part number, year code, week code and traceability code.
For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
Legend: iTemperature range designator (Blank = commercial, i = industrial)
R Product revision
nnn Internal code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
V Plant of assembly
COO Country of origin
YY Year code (last two digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
56-VQFN (7x7 mm)
PIN 1 USB5744i
Rnnn e3
VCOO
YYWWNNN
e3
USB5744
DS00001855E-page 40 2015-2017 Microchip Technology Inc.
10.2 Package Drawings
Note: For the most current package drawings, see the Microchip Packaging Specification at:
http://www.microchip.com/packaging.
FIGURE 10-1: 56-VQFN PACKAGE (DRAWING)
2015-2017 Microchip Technology Inc. DS00001855E-page 41
USB5744
FIGURE 10-2: 56-VQFN PACKAGE (DIMENSIONS)
USB5744
DS00001855E-page 42 2015-2017 Microchip Technology Inc.
FIGURE 10-3: 56-VQFN LAND PATTERN
2015-2017 Microchip Technology Inc. DS00001855E-page 43
USB5744
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1: REVISION HISTORY
Revision Level & Date Section/Figure/Entry Correction
DS00001855E (02-10-17) Tabl e 3 -1 Removed errant duplicate pin assignment
table.
Product Identification System on page
46
Added package with hub feature controller
disabled
DS00001855D (06-06-16) Section 10.0, Package Information Added top marking information and land pat-
tern drawing.
All Updated “SQFN” references to “VQFN”.
Name change only.
Section 8.4.2.1, Port Power Control
using USB Power Switch
Added additional information on overcurrent
detection methods.
Section 9.6.1, Power Supply and
RESET_N Sequence Timing
Added Power Supply and RESET_N
Sequence Timing section.
Section 9.6.5, I2C Timing “100kHz Standard Mode (Sm)” updated to
“400kHz Fast Mode (Fm)”, since the device
supports up to 400kHz I2C operation.
DS00001855C (06-22-15) All Updated “USB 3.0” references to “USB 3.1
Gen 1” throughout the document
Updated USB specification references
Misc. typos
DS00001855B (04-16-15) Features Changed Environmental feature bullet from
“4kV HBM JESD22-A114F ESD protection”
to
“3kV HBM JESD22-A114F ESD protection”
Section 9.2, Operating Conditions** Changed XTALI/CLK_IN Voltage to -0.3V to
+3.6V
Table 9-10, "Crystal Specifications" Total Allowable PPM budget changed to
100pm, removed notes under table regarding
“Frequency Tolerance” and “Frequency and
Transmitter Clock Frequency”
Section 9.7.2, External Reference
Clock (CLK_IN)
Changed +-350ppm t +-100 ppm
Figure 3-1, "56-VQFN Pin
Assignments"Table 3-1, "56-VQFN
Pin Assignments"
Modified pin 32 from “PRT_CTL4/
GANG_PWR” to “PRT_CTL4/GANG_PWR”
Table 3-4, "USB Port Control Pin
Descriptions"
Revised description of Pin 1, GANG_PWR
Table 1-1, "General Terms" and
throughout document
Replaced the term Hub Controller with Hub
Feature Controller, added definition in Tab l e 1 -
1, "General Terms".
Section 6.1.2, SMBus Accessible
Functions
Added web link to AN1903
Removed PortMap feature throughout docu-
ment.
Table 3-6, "Miscellaneous Pin
Descriptions"
Modified RESET_N pin description
USB5744
DS00001855E-page 44 2015-2017 Microchip Technology Inc.
Section 8.3, Link Power Management
(LPM)
Removed “per the USB 3.0 Specification” from
the first sentence. Removed last sentence
“For additional information, refer to the USB
3.0 Specification.”
Table 9-2, "MAXIMUM Power Dissipa-
tion"
Added Ta b le 9- 2 .
Section 9.7, "Clock
Specifications",Figure 9-6, Table 9-10,
"Crystal Specifications"
Updated these sections.
Section 9.7.2, External Reference
Clock (CLK_IN)
Oscillator changed from “35MHz” to “25 MHz”
Section 9.6.7, SPI Timing Removed SPI interface configure note
Section 9.1, Absolute Maximum Rat-
ings*
Added “Positive voltage on USB 3.0 USB3UP-
_xxxx and USB3DN_xxxx signal pins, with
respect to ground...1.32 V
Changed XTALI positive voltage from 2.1V to
3.63V.
Changed “USB 3.0 DP/DM Signal Pins Volt-
age” to “USB 3.0 USB3UP_xxxx and
USB3DN_xxxx Signal Pins Voltage”
Section 8.4.2, "Port Connection in
Combined Mode," on page 26
Added note under Section 8.4.2
Product Identification System on page
46
Updated ordering information
Section 9.1, "Absolute Maximum Rat-
ings*," on page 30
Updated +1.2V supply voltage absolute max
value. Added HBM ESD performance specifi-
cation.
Table 9-1, “Package Thermal Parame-
ters,” on page 31
Added package thermal parameters.
Worldwide Sales and Service Updated Worldwide Sales Listing
Table 9-4, “I/O DC Electrical Charac-
teristics,” on page 33
Updated I buffer type high input level max.
Added IS buffer type Schmitt trigger hystere-
sis values.
Cover, All Updated document title to “4-Port SS/HS Con-
troller Hub”
Removed PortMap references.
Removed sentence: ”These circuits are used
to detect the attachment and type of a USB
charger and provide an interrupt output to indi-
cate charger information is available to be
read from the device’s status registers via the
serial interface.“
FIGURE 3-1: 56-VQFN Pin Assign-
ments on page 8
Added configuration strap note under figure.
DS00001855A (12-15-14) All Initial Release
TABLE A-1: REVISION HISTORY (CONTINUED)
Revision Level & Date Section/Figure/Entry Correction
2015-2017 Microchip Technology Inc. DS00001855E-page 45
USB5744
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
•Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
•General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
•Business of Mic r oc hi p – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://www.microchip.com/support
USB5744
DS00001855E-page 46 2015-2017 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: USB5744
Tape and Reel
Option: Blank = Standard packaging (tray)
T = Tape and Reel (Note 1)
Temperature
Range: Blank = 0C to +70C (Commercial)
I= -40C to +85C (Industrial)
Package: 2G = 56-pin VQFN
Configuration
Option: Blank = Standard Configuration
X01 = Hub Feature Controller disabled
Examples:
a) USB5744/2G
Tray, Commercial temp., 56-pin VQFN
b) USB5744-I/2G
Tray, Industrial temp., 56-pin VQFN
c) USB5744T-I/2G
Tape & reel, Industrial temp., 56-pin VQFN
d) USB5744T/2G
Tape & reel, Commercial temp., 56-pin VQFN
e) USB5744/2GX01
Tray, Commercial temp., 56-pin VQFN
Hub Feature Controller disabled
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office for
package availability with the Tape and Reel
option.
PART NO.
Device Tape & Reel
[X]
Option Temperature
Range
[-X]
/
XX
Package
XXX
Config.
Option
2015-2017 Microchip Technology Inc. DS00001855E-page 47
USB5744
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be super-
seded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REP-
RESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR,
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision
Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2015-2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781522413714
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, micro perip hera ls, nonvolat ile memor y and
analog products . I n additio n, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
2015-2017 Microchip Technology Inc. DS00001855E-page 48
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Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
France - Saint Cloud
Tel: 33-1-30-60-70-00
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7289-7561
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
11/07/16
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Microchip:
USB5744/2G USB5744-I/2G USB5744T/2G USB5744T-I/2G