BS616LV2010-70 - Brilliance Semiconductor, Inc.

Revision 2.2

Nov. 2002

R0201-BS616LV2010

Very Low Power/Voltage CMOS SRAM

128K X 16 bit

• Very low operation voltage : 2.7 ~ 3.6V

• Very low power consumption :

Vcc = 3.0V C-grade: 25mA (Max.) operating current

I-grade: 30mA (Max.) operating current

0.15uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc = 3.0V

-10 100ns (Max.) at Vcc = 3.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

• I/O Configuration x8/x16 selectable by LB and UB pin

The BS616LV2010 is a high performance, very low power CMOS Static

Random Access Memory organized as 131,072 words by 16 bits and

operates from a wide range of 2.7V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current

of 0.15uA and maximum access time of 70ns in 3V operation.

Easy memory expansion is provided by active LOW chip enable(CE)

, active LOW output enable(OE) and three-state output drivers.

The BS616LV2010 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS616LV2010 is available in 44L-TSOP2 and 48-ball BGA package.

DESCRIPTION

FEATURES

Row

Decoder

Memory Array

1024 x 2048

Column I/O

Write Driver

Sense Amp

Column Decoder

Data

Buffer

Output

A3 A2 A1

Data

Buffer

Input

Control

Gnd

Vcc

DQ15

DQ0

A16

A15

A13

128

2048

BLOCK DIAGRAM

1024

A14

A12

A11

Address

Input

Buffer

A10

Address Input Buffer

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

BS616LV2010

BSI

POWER DISSIPATION

SPEED

( ns ) STANDBY

( ICCSB1 , Max ) Operating

( ICC, Max )

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

Vcc=3.0V Vcc=3.0V Vcc=3.0V

PKG TYPE

BS616LV2010EC TSOP2-44

BS616LV2010AC +0 O C to +70O C 2.7V ~ 3.6V 70 / 100 8uA 25mA BGA-48-0608

BS616LV2010EI TSOP2-44

BS616LV2010AI -40O C to +85O C 2.7V ~ 3.6V 70 / 100 12uA 30mA BGA-48-0608

A9A8

D15

D14

VSS

D13

A12

A14

D12

D11

D10 A5

A11A10

A13

A15

A16

A1 A2

N.C.

VCC VSS

VCC

N.C.

48-ball BGA top view

DQ0

DQ1

DQ2

DQ3

VCC

GND

DQ4

DQ5

DQ6

DQ7

A16

A15

A14

A13

A12

DQ15

DQ14

DQ13

DQ12

GND

VCC

DQ11

DQ10

DQ9

DQ8

A10

A11

BS616LV2010EC

BS616LV2010EI

Revision 2.2

Nov. 2002

R0201-BS616LV2010

Name Function

A0-A16 Address Input These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.

CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins.

DQ0 - DQ15 Data Input/Output

Ports

These 16 bi-directional ports are used to read data from or write data into the RAM.

Vcc Power Supply

Gnd Ground

TRUTH TABLE

PIN DESCRIPTIONS

BSI BS616LV2010

MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT

Not selected

(Power Down) H X X X X High Z High Z ICCSB, ICCSB1

Output Disabled L H H X X High Z High Z ICC

L L Dout Dout ICC

H L High Z Dout ICC

Read L H L

L H Dout High Z ICC

LL Din Din I

HL X Din I

Write L L X

LH Din X I

Revision 2.2

Nov. 2002

PARAMETER

NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS

VIL Guaranteed Input Low

Voltage(2) Vcc=3.0V -0.5 -- 0.8 V

VIH Guaranteed Input High

Voltage(2) Vcc=3.0V 2.0 -- Vcc+0.2 V

IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA

ILO Output Leakage Current Vcc = Max, CE = VIH, or OE = VIH,

VI/O = 0V to Vcc -- -- 1 uA

VOL Output Low Voltage Vcc = Max, IOL = 2mA Vcc=3.0V -- -- 0.4 V

VOH Output High Voltage Vcc = Min, IOH = -1mA Vcc=3.0V 2.4 -- -- V

ICC Operating Power Supply

Current CE = VIL, IDQ = 0mA, F = Fmax(3) Vcc=3.0V -- -- 25 mA

ICCSB Standby Current-TTL CE = VIH, IDQ = 0mA Vcc=3.0V -- -- 1 mA

ICCSB1 Standby Current-CMOS

CE ≧ Vcc-0.2V,

VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V Vcc=3.0V -- 0.15 8 uA

R0201-BS616LV2010

SYMBOL PAR AMETER TEST CONDITIONS MIN. TYP.

(1) MAX. UNITS

VDR Vcc for Data Retention CE ≧ Vcc - 0.2V

VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V

ICCDR Data Retention Current CE ≧ Vcc - 0.2V

VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.1 5 uA

tCDR

Chip Deselect to Data

Retention Time 0---- ns

tROperation Recovery Time

See Retention Waveform

TRC (2) -- -- ns

SYMBOL PARAMETER CONDITIONS MAX. UNIT

CIN Input

Capacitance VIN=0V 6 pF

CDQ Input/Output

Capacitance VI/O=0V 8 pF

RANGE AMBIENT

TEMPERATURE Vcc

Commercial 0 O C to +70 O C2.7V ~ 3.6V

Industrial -40 O C to +85 O C2.7V ~ 3.6V

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/tRC .

DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )

1. Vcc = 1.5V, TA= + 25OC

2. tRC = Read Cycle Time

ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE

CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

1. This parameter is guaranteed and not 100% tested.

DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )

SYMBOL PARAMETER RATING UNITS

TERM Terminal Voltage with

Respect to GND

-0.5 to

Vcc+0.5 V

BIAS Temperature Under Bias -40 to +125 O C

STG Storage Temperature -60 to +150 O C

TPower Dissipation 1.0 W

OUT DC Output Current 20 mA

BSI BS616LV2010

Revision 2.2

Nov. 2002

R0201-BS616LV2010

JEDEC

PARAMETER

NAME

PARAMETER

NAME DESCRIPTION BS616LV2010-70

MIN. TYP. MAX.

BS616LV2010-10

MIN. TYP. MAX. UNIT

tAVAX tRC Read Cycle Time 70 -- -- 100 -- -- ns

tAVQV tAA Address Access Time -- -- 70 -- -- 100 ns

tELQV tACS Chip Select Access Time (CE) -- -- 70 -- -- 100 ns

tBA tBA Data Byte Control Access Time (LB,UB)----40----50 ns

tGLQV tOE Output Enable to Output Valid -- -- 50 -- -- 60 ns

tE1LQX tCLZ Chip Select to Output Low Z (CE) 10 -- -- 15 -- -- ns

tBE tBE Data Byte Control to Output Low Z (LB,UB) 10 -- -- 15 -- -- ns

tGLQX tOLZ Output Enable to Output in Low Z 10 -- -- 15 -- -- ns

tEHQZ tCHZ Chip Deselect to Output in High Z (CE) 0 -- 35 0 -- 40 ns

tBDO tBDO Data Byte Control to Output High Z (LB,UB) 0 -- 30 0 -- 35 ns

tGHQZ tOHZ Output Disable to Output in High Z 0 -- 30 0 -- 35 ns

tAXOX tOH Output Disable to Address Change 10 -- -- 15 -- -- ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output

Timing Reference Level

Vcc/0V

1V/ns

0.5Vcc

AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )

READ CYCLE

AC TEST CONDITIONS

AC TEST LOADS AND WAVEFORMS

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE

STEADY

MAY CHANGE

FROM H TO L

DON T CARE:

ANY CHANGE

PERMITTED

DOES NOT

APPLY

MUST BE

STEADY

WILL BE

CHANGE

FROM H TO L

CHANGE :

STATE

UNKNOWN

CENTER

LINE IS HIGH

IMPEDANCE

”OFF ”STATE

MAY CHANGE

FROM L TO H

WILL BE

CHANGE

FROM L TO H

LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

Vcc

tCDR

Vcc

VIHVIH

Vcc VDR 1.5V

≥

CE Vcc - 0.2V

≥

BSI BS616LV2010

Ω667

THEVENIN EQUIVALENT

ALL INPUT PULSES

→

10%

←

90%

Vcc

GND →←5ns

90% 10%

1.73V

OUTPUT

FIGURE 2

3.3V

OUTPUT

INCLUDING

JIG AND

SCOPE

Ω

1269

Ω

1404

5PF

FIGURE 1B

3.3V

INCLUDING

JIG AND

SCOPE

Ω

1269

Ω

100PF

FIGURE 1A

1404

OUTPUT

Revision 2.2

Nov. 2002

R0201-BS616LV2010

NOTES:

1. WE is high for read Cycle.

2. Device is continuously selected when CE = VIL.

3. Address valid prior to or coincident with CE transition low.

4. OE = VIL .

5. Transition is measured 500mV from steady state with CL= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

BSI BS616LV2010

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1 (1,2,4)

t RC

t OH

t AA

DOUT

ADDRESS

t OH

READ CYCLE3 (1,4)

tRC

t OE

D OUT

LB,UB

ADDRESS

t CLZ

(5) tACS

t CHZ

(1,5)

t OHZ (5)

t OLZ

tAA

READ CYCLE2 (1,3,4)

tCLZ

tCHZ

(5)

D OUT

LB,UB

(5)

t BA

t ACS

t BE t BDO

t BDO

t BA

t BE

Revision 2.2

Nov. 2002

JEDEC

PARAMETER

NAME

PARAMETER

NAME DESCRIPTION BS616LV2010-70

MIN. TYP. MAX.

BS616LV2010-10

MIN. TYP. MAX. UNIT

tAVAX tWC Write Cycle Time 70 -- -- 100 -- -- ns

tE1LWH tCW Chip Select to End of Write 70 -- -- 100 -- -- ns

tAVWL tAS Address Setup Time 0 -- -- 0 -- -- ns

tAVWH tAW Address Valid to End of Write 70 -- -- 100 -- -- ns

tWLWH tWP Write Pulse Width 50 -- -- 70 -- -- ns

tWHAX tWR Write recovery Time (CE,WE) 0 -- -- 0 -- -- ns

tBW tBW Date Byte Control to End of Write (LB,UB)60----80---- ns

tWLQZ tWHZ Write to Output in High Z 0 -- 30 0 -- 40 ns

tDVWH tDW Data to Write Time Overlap 30 -- -- 40 -- -- ns

tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns

tGHQZ tOHZ Output Disable to Output in High Z 0 -- 30 0 -- 40 ns

tWHOX tOW End of Write to Output Active 5----10---- ns

R0201-BS616LV2010

AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )

WRITE CYCLE

BSI BS616LV2010

t WR

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1 (1)

t WC

(3)

t CW

(11)

t BW

(2)

t WP

t AW

t OHZ

(4,10)

t AS

(3)

t DH

t DW

DIN

D OUT

LB,UB

ADDRESS

(5)

Revision 2.2

Nov. 2002

R0201-BS616LV2010

BSI BS616LV2010

WRITE CYCLE2 (1,6)

t WC

t CW

(11)

(2)

t WP

t AW

t WHZ

(4,10)

t AS

t WR

(3)

t DH

t DW

DIN

D OUT

ADDRESS

(5)

t OW (7) (8)

(8,9)

t BW

LB,UB

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.

The data input setup and hold timing should be referenced to the second transition edge of

the signal that terminates the write.

3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = VIL ).

7. DOUT is the same phase of write data of this write cycle.

8. DOUT is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with CL= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

11. TCW is measured from the later of CE going low to the end of write.

Revision 2.2

Nov. 2002

R0201-BS616LV2010

PACKAGE

A: BGA - 48 Ball (6mm X 8mm)

E: TSOP2 - 44 PIN

ORDERING INFORMATION

BSI

BS616LV2010 X X -- Y Y

GRADE

C: +0oC ~ +70oC

I: -40oC ~ +85oC

SPEED

70: 70ns

10: 100ns

BS616LV2010

PACKAGE DIMENSIONS

48 mini-BGA (6 x 8)

VIEW A

1.4 Max.

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

BALL PITCH e = 0.75

8.0 6.0

48 3.75

E1D1

5.25

NOTES:

Revision 2.2

Nov. 2002

BSI BS616LV2010

PACKAGE DIMENSIONS

TSOP2-44

R0201-BS616LV2010