1. General description
The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 Vand 5 V environment. Schmitt-trigger action at the inp ut
makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the outpu t, preventing the damaging ba ckflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V).
24 mA output drive (VCC =3.0V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Unlimited rise and fall times
Input accepts voltages up to 5 V
Multiple package options
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A ex ce ed s 200 V.
Specified from 40 Cto+85C and 40 Cto+125C.
3. Applications
Wave and pulse shaper
Astable multivibrator
Monostable multivibrator
74LVC1G14
Single Schmitt-trigger inverter
Rev. 12 — 6 August 2012 Product data sheet
74LVC1G14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 6 August 2012 2 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
4. Ordering information
5. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
Table 1. Ordering information
Type number Package
Temperatu re range Name Description Version
74LVC1G14GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm SOT353-1
74LVC1G14GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753
74LVC1G14GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm SOT886
74LVC1G14GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 10.5 mm SOT891
74LVC1G14GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm SOT1115
74LVC1G14GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm SOT1202
74LVC1G14GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 0.8 0.35 mm
SOT1226
Table 2. Marking
Type number Marking code[1]
74LVC1G14GW VF
74LVC1G14GV V14
74LVC1G14GM VF
74LVC1G14GF VF
74LVC1G14GN VF
74LVC1G14GS VF
74LVC1G14GX VF
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram
mna023
AY
24
24
mna024
mna025
AY
74LVC1G14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 6 August 2012 3 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 4. Pin configu ration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886
74LVC1G14
n.c. VCC
A
GND Y
001aab655
1
2
3
5
4
74LVC1G14
A
001aab656
n.c.
GND
n.c.
V
CC
Y
Transparent top view
2
3
1
5
4
6
Fig 6. Pin configu ration SOT891, SOT1115 and
SOT1202 Fig 7. Pin configuration SOT1226 (X2S ON5)
74LVC1G14
A
001aae976
n.c.
GND
n.c.
VCC
Y
Transparent top view
2
3
1
5
4
6
n.c. VCC
GND
1
3
2
5
4
AY
aaa-003024
Transparent top view
74LVC1G14
Table 3. Pin description
Symbol Pin Description
TSSOP5 and X2SON5 XSON6
n.c. 1 1 not conn ected
A 2 2 data i np ut
GND 3 3 ground (0 V)
Y 4 4 data o utput
n.c. - 5 not conn ected
VCC 5 6 supply voltage
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Product data sheet Rev. 12 — 6 August 2012 4 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
8. Functional description
[1] H = HIGH voltage level; L = LOW voltage level
9. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 4. Function table[1]
Input Output
A Y
LH
HL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
VIinput voltage [1] 0.5 +6.5 V
VOoutput voltage Active mode [1][2] 0.5 VCC +0.5 V
Power-down mode [1][2] 0.5 +6.5 V
IIK input clamping current VI<0V 50 - mA
IOK output clamping current VO>V
CC or VO<0V - 50 mA
IOoutput curren t VO=0 VtoV
CC -50 mA
ICC supply current - +100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[3] - 250 mW
Table 6. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage Active mo de 0 - VCC V
Power-down mode; VCC =0V 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
74LVC1G14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 6 August 2012 5 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
11. Static characteristics
[1] All typical values are measured at maximum VCC and Tamb = 25 C.
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VOH HIGH-level
output voltage VI= VT+ or VT
IO = 100 A;
VCC = 1.65 V to 5.5 V VCC 0.1 - - VCC 0.1 - V
IO = 4 mA; VCC = 1.65 V 1.2 1.54 - 0.95 - V
IO = 8 mA; VCC = 2.3 V 1.9 2.15 - 1.7 - V
IO = 12 mA; VCC = 2.7 V 2.2 2.50 - 1.9 - V
IO = 24 mA; VCC = 3.0 V 2.3 2.62 - 2.0 - V
IO = 32 mA; VCC = 4.5 V 3.8 4.11 - 3.4 - V
VOL LOW-level
output voltage VI= VT+ or VT
IO = 100 A;
VCC = 1.65 V to 5.5 V - - 0.10 - 0.10 V
IO = 4 mA; VCC = 1.65 V - 0.07 0.45 - 0.70 V
IO = 8 mA; VCC = 2.3 V - 0.12 0.30 - 0.45 V
IO = 12 mA; VCC = 2.7 V - 0.17 0.40 - 0.60 V
IO = 24 mA; VCC = 3.0 V - 0.33 0.55 - 0.80 V
IO = 32 mA; VCC = 4.5 V - 0.39 0.55 - 0.80 V
IIinput leakage
current VI = 5.5 V or GND;
VCC =0Vto5.5V -0.1 5-100 A
IOFF power-off
leakage
current
VI or VO = 5.5 V; VCC = 0 V - 0.1 10 - 200 A
ICC supply current VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V - 0.1 10 - 200 A
ICC additional
supply current VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V - 5 500 - 5000 A
CIinput
capacitance VCC = 3.3 V; VI=GNDtoV
CC -5.0- - -pF
Table 8. Transfer characteristics
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VT+ positive-going
threshold voltage see Figure 10 and Figure 11
VCC = 1.8 V 0.82 1.0 1.14 0.79 1.14 V
VCC = 2.3 V 1.03 1.2 1.40 1.00 1.40 V
VCC = 3.0 V 1.29 1.5 1.71 1.26 1.71 V
VCC = 4.5 V 1.84 2.1 2.36 1.81 2.36 V
VCC = 5.5 V 2.19 2.5 2.79 2.16 2.79 V
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Product data sheet Rev. 12 — 6 August 2012 6 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
[1] All typical values are measured at Tamb = 25 C
12. Dynamic characteristics
[1] Typical values are measured at Tamb =25C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fi+(C
LVCC2fo)where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V.
VTnegative-going
threshold voltage see Figure 10 and Figure 11
VCC = 1.8 V 0.46 0.6 0.75 0.46 0.78 V
VCC = 2.3 V 0.65 0.8 0.96 0.65 0.99 V
VCC = 3.0 V 0.88 1.0 1.24 0.88 1.27 V
VCC = 4.5 V 1.32 1.5 1.84 1.32 1.87 V
VCC = 5.5 V 1.58 1.8 2.24 1.58 2.27 V
VHhysteresis voltag e (VT+ VT); see Figure 10,
Figure 11 and Figure 12
VCC = 1.8 V 0.26 0.4 0.51 0.19 0.51 V
VCC = 2.3 V 0.28 0.4 0.57 0.22 0.57 V
VCC = 3.0 V 0.31 0.5 0.64 0.25 0.64 V
VCC = 4.5 V 0.40 0.6 0.77 0.34 0.77 V
VCC = 5.5 V 0.47 0.6 0.88 0.41 0.88 V
Table 8. Transfer characteristics …continued
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay A to Y; see Figure 8 [2]
VCC = 1.65 V to 1.95 V 1.0 4.1 11.0 1.0 14.0 ns
VCC = 2.3 V to 2.7 V 0.7 2.8 6.5 0.7 8.5 ns
VCC = 2.7 V 0.7 3.2 6.5 0.7 8.5 ns
VCC = 3.0 V to 3.6 V 0.7 3.0 5.5 0.7 7.0 ns
VCC = 4.5 V to 5.5 V 0.7 2.2 5.0 0.7 6.5 ns
CPD power dissipation
capacitance VCC = 3.3 V; VI = GND to VCC [3] - 15.4 - - - pF
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Product data sheet Rev. 12 — 6 August 2012 7 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
13. Waveforms
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The data input (A) to output (Y) propagation delays
mna640
tPHL tPLH
VM
VM
A input
Y output
GND
VI
VOH
VOL
Table 10. Measurement points
Supply voltage Input Output
VCC VMVM
1.65 V to 1.95 V 0.5 VCC 0.5 VCC
2.3 V to 2.7 V 0.5 VCC 0.5 VCC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5 V 0.5 VCC 0.5 VCC
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Test circuit for measuring switching times
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
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Product data sheet Rev. 12 — 6 August 2012 8 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
14. Waveforms transfer characteristics
Table 11. Test data
Supply voltage Input Load VEXT
VCC VItr=t
fCLRLtPLH, tPHL
1.65 V to 1.95 V VCC 2.0ns 30pF 1kopen
2.3 V to 2.7 V VCC 2.0ns 30pF 500open
2.7V 2.7V 2.5ns 50pF 500open
3.0V to 3.6V 2.7V 2.5ns 50pF 500open
4.5 V to 5.5 V VCC 2.5ns 50pF 500open
VT+ and VT limits at 70 % and 20 %.
Fig 10. Transfer characteristic Fig 11. Definition of VT+, VT and VH
mna207
VO
VI
VHVT+
VT−
mna208
V
O
V
I
V
H
V
T+
V
T−
VCC = 3.0 V.
Fig 12. Typical transfer characteristics
03
V
I
(V)
I
CC
(mA)
10
0
2
mna641
4
6
8
12
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Product data sheet Rev. 12 — 6 August 2012 9 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd =f
i(trICC(AV) +t
fICC(AV))VCC where:
Padd = additional power dissipation (W);
fi= input frequency (MHz);
tr= input rise time (ns); 10 % to 90 %;
tf= input fall time (ns); 90 % to 10 %;
ICC(AV) = average additional supply current (A).
Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 13.
An example of a relaxation circuit using the 74LVC1G14 is shown in Figure 14.
Linear change of VI between 0.8 V to 2.0 V.
All values given are typical unless otherwise specifie d.
Fig 13. Average additional supply current as a function of supply voltage
02 6
12
0
8
6
4
2
10
mna642
4VCC (V)
average
ICC
(mA)
negative-going
edge
positive-going
edge
Fig 14. Relaxation oscillator
mna035
R
C
f1
T
---1
0.5 RC
---------------------
=
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Product data sheet Rev. 12 — 6 August 2012 10 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
16. Package outline
Fig 15. Package outline SOT353-1 (TSSOP5)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.1
01.0
0.8 0.30
0.15 0.25
0.08 2.25
1.85 1.35
1.15 0.65
e1
1.3 2.25
2.0 0.60
0.15 7°
0°
0.1 0.10.30.425
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.46
0.21
SOT353-1 MO-203 SC-88A 00-09-01
03-02-19
wM
bp
D
Z
e
e1
0.15
13
54
θ
A
A2
A1
Lp
(A3)
detail X
L
HE
E
c
vMA
X
A
y
1.5 3 mm0
scale
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1
1.1
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Product data sheet Rev. 12 — 6 August 2012 11 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
Fig 16. Package outline SOT753 (SC-74A)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT753 SC-74A
wBM
bp
D
e
A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
45
Plastic surface-mounted package; 5 leads SOT753
UNIT A1bpcDEHELpQywv
mm 0.100
0.013 0.40
0.25 3.1
2.7
0.26
0.10 1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2 0.33
0.23
A
1.1
0.9
02-04-16
06-03-16
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Product data sheet Rev. 12 — 6 August 2012 12 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
Fig 17. Package outline SOT886 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT886 MO-252
sot886_po
04-07-22
12-01-05
Unit
mm max
nom
min
0.5 0.04 1.50
1.45
1.40
1.05
1.00
0.95
0.35
0.30
0.27
0.40
0.35
0.32
0.6
A(1)
Dimensions (mm are the original dimensions)
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886
A1b
0.25
0.20
0.17
DEee
1
0.5
LL
1
terminal 1
index area
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
1
6
2
5
3
4
6x
(2)
4x
(2)
A
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Product data sheet Rev. 12 — 6 August 2012 13 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
Fig 18. Package outline SOT891 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT891
SOT891
05-04-06
07-05-15
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm 0.20
0.12 1.05
0.95 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.350.55
A
max
0.5 0.04
1
6
2
5
3
4
A
6×
(1)
4×
(1)
Note
1. Can be visible in some manufacturing processes.
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Product data sheet Rev. 12 — 6 August 2012 14 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
Fig 19. Package outline SOT1115 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1115
sot1115_po
10-04-02
10-04-07
Unit
mm max
nom
min
0.35 0.04 0.95
0.90
0.85
1.05
1.00
0.95 0.55 0.3 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
L1
b
321
6 5 4
(6×)(2) A1A
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Product data sheet Rev. 12 — 6 August 2012 15 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
Fig 20. Package outline SOT1202 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1202
sot1202_po
10-04-02
10-04-06
Unit
mm max
nom
min
0.35 0.04 1.05
1.00
0.95
1.05
1.00
0.95 0.55 0.35 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
b
123
L1
6 5 4
(6×)(2)
A
A1
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Product data sheet Rev. 12 — 6 August 2012 16 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
Fig 21. Package outline SOT1226 (X2SON5)
References
Outline
version European
projection Issue date
IEC JEDEC EIAJ
SOT1226
sot1226_po
12-04-10
12-04-25
Unit
mm max
nom
min
0.35 0.85
0.80
0.75
0.04 0.30
0.25
0.20
0.85
0.80
0.75
0.27
0.22
0.17 0.05
A(1)
Dimensions
Note
1. Dimension A is including plating thickness.
2. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
SOT1226
A1A3
0.128
0.040
DD
hEbe
0.48
kLv
0.1
wy
0.05 0.05
scale
01 mm
X
terminal 1
index area
D
E
AB
detail X
A
A1A3
C
y
C
y1
54
terminal 1
index area
Dh
L
b
k
eAC B
vCw
21
0.20
0.27
0.22
0.17
y1
X2SON5: plastic thermal enhanced extremely thin small outline package; no leads;
5 terminals; body 0.8 x 0.8 x 0.35 mm
3
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Product data sheet Rev. 12 — 6 August 2012 17 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
17. Abbreviations
18. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
TTL Transistor-Transistor Logic
HBM Human Body Model
ESD ElectroSt atic Discharge
MM Machine Model
DUT Device Under Test
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC1G14 v.12 20120806 Product data sheet - 74LVC1G14 v.11
Modifications: •Package outli n e drawing of SOT1226 (Figure 21) modified.
74LVC1G14 v.11 20120412 Product data sheet - 74LVC1G14 v.10
Modifications: •Added type number 74LVC1G14GX (SOT1226)
•Package outli n e drawing of SOT886 (Figure 17) modified.
74LVC1G14 v.10 20111206 Product data sheet - 74LVC1G14 v.9
Modifications: •Legal pages updated.
74LVC1G14 v.9 20110922 Product data sheet - 74LVC1 G14 v.8
74LVC1G14 v.8 20101110 Product data sheet - 74LVC1G14 v.7
74LVC1G14 v.7 20070718 Product data sheet - 74LVC1G14 v.6
74LVC1G14 v.6 20060615 Product data sheet - 74LVC1G14 v.5
74LVC1G14 v.5 20040910 Product specification - 74LVC1G14 v.4
74LVC1G14 v.4 20021119 Product specification - 74LVC1G14 v.3
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74LVC1G14 v.2 20010406 Product specification - 74LVC1G14 v.1
74LVC1G14 v.1 20001212 Product specification - -
74LVC1G14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 6 August 2012 18 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
19. Legal information
19.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short dat a sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors product s are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cu stomer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property right s.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specificatio n.
74LVC1G14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 6 August 2012 19 of 20
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applicati ons.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ pro duct specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
19.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC1G14
Single Schmitt-trigger inverter
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 August 2012
Document identifier: 74LVC1G14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
21. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Functional description . . . . . . . . . . . . . . . . . . . 4
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
10 Recommended operating conditions. . . . . . . . 4
11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
12 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
14 Waveforms transfer cha racteristics. . . . . . . . . 8
15 Application information. . . . . . . . . . . . . . . . . . . 9
16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
19.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
20 Contact information. . . . . . . . . . . . . . . . . . . . . 19
21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
