DATA SH EET
Product specification
Supersedes data of 2000 Jan 04
File under Integrated Circuits, IC01
2001 Mar 27
INTEGRATED CIRCUITS
UDA1328T
Multi-channel filter DAC
2001 Mar 27 2
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
CONTENTS
1 FEATURES
1.1 General
1.2 Multiple format input interface
1.3 Multi-channel DAC
1.4 Advanced audio configuration
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 QUICK REFERENCE DATA
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION
8.1 System clock
8.2 Application modes
8.3 Interpolation filter (DAC)
8.4 Digital silence detection
8.5 Noise shaper
8.6 Filter stream DAC
8.7 Static mode
8.7.1 System clock setting
8.7.2 De-emphasis control
8.7.3 Digital interface formats
8.8 L3 mode
8.8.1 Digital interface formats
8.8.2 L3 address
9 L3 INTERFACE DESCRIPTION
9.1 Address mode
9.2 Data transfer mode
9.2.1 Programming the sound processing and other
features
9.2.2 Reset bit
9.2.3 System clock frequency
9.2.4 Data input format
9.2.5 Quick mute
9.2.6 Power control
9.3 Feature settings
9.3.1 Channel selection mode
9.3.2 Volume control
9.3.3 Sub volume control
9.3.4 Mute
9.3.5 Digital silence mode
9.3.6 De-emphasis
9.3.7 Output polarity control
10 LIMITING VALUES
11 HANDLING
12 THERMAL CHARACTERISTICS
13 QUALITY SPECIFICATION
14 DC CHARACTERISTICS
15 AC CHARACTERISTICS (ANALOG)
16 AC CHARACTERISTICS (DIGITAL)
17 APPLICATION INFORMATION
18 PACKAGE OUTLINE
19 SOLDERING
19.1 Introduction to soldering surface mount
packages
19.2 Reflow soldering
19.3 Wave soldering
19.4 Manual soldering
19.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
20 DATA SHEET STATUS
21 DEFINITIONS
22 DISCLAIMERS
2001 Mar 27 3
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
1 FEATURES
1.1 General
•2.7 to 3.6 V power supply
•5 V tolerant TTL compatible inputs
•Selectable control via L3 microcontroller interface or via
static pin control
•Multi-channel integrated digital filter plus non-inverting
Digital-to-Analog Converter (DAC)
•Supports sample frequencies between 5 and 100 kHz
•Digital silence detection (output)
•Slave mode only applications
•No analog post filtering required for DAC
•Easy application.
1.2 Multiple format input interface
•I2S-bus, MSB-justified and LSB-justified format
compatible (in L3 mode)
•I2S-bus and LSB-justified format compatible
•1fs input format data rate.
1.3 Multi-channel DAC
•6-channel DAC with power on/off control
•Digital logarithmic volume control via L3; volume can be
set for each of the channels individually
•Digital de-emphasis for 32, 44.1, 48 and 96 kHz fs via
L3 and, for 32, 44.1 and 48 kHz in static mode
•Soft or quick mute via L3
•Output signal polarity control via L3 microcontroller
interface.
1.4 Advanced audio configuration
•6-channel line output (under L3 volume control)
•Astereodifferentialoutput(channel 1andchannel 2)for
improved performance
•High linearity, wide dynamic range, low distortion.
2 APPLICATIONS
This multi-channel DAC is eminently suitable for DVD-like
applications in which 5.1 channel encoded signals are
used.
3 GENERAL DESCRIPTION
The UDA1328 is a single-chip 6-channel DAC employing
bitstreamconversiontechniques,whichcanbeusedeither
in L3 microcontroller mode or in static pin mode.
The UDA1328 supports the I2S-bus data format with word
lengths of up to 24 bits, the MSB-justified data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 18, 20 and 24 bits.
Alldigitalsound processingfeaturescan becontrolledwith
the L3 interface e.g. volume control, selecting digital
silence type, output polarity control and mute. Also system
features such as power control, digital silence detection
mode and output polarity control.
Under static pin control, via static pins, the system clock
can be set to either 256fsor 384fs support, digital
de-emphasis can be set, there is digital mute and the
digital input formats can also be set.
4 ORDERING INFORMATION
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
UDA1328T SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1
2001 Mar 27 4
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
5 QUICK REFERENCE DATA
Notes
1. The output voltage scales proportionally with the power supply voltage.
2. In this case the two outputs per channel (for channels 1 and 2) are combined.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDDA analog supply voltage 2.7 3.3 3.6 V
VDDD digital supply voltage 2.7 3.3 3.6 V
IDDA analog supply current 6 channels active −28 −mA
IDDD digital supply current −11 −mA
Tamb ambient temperature −40 −+85 °C
DAC: channels 1 and 2 differential
Vo(rms) output voltage (RMS value) notes 1 and 2 −2−V
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio at 0 dB
fs=48kHz −−95 −88 dB
fs=96kHz −−90 −dB
at −60 dB; A-weighted
fs=48kHz −−46 −dB
fs=96kHz −−44 −dB
S/N signal-to-noise ratio code = 0; A-weighted
fs=48kHz −106 −dB
fs=96kHz −104 −dB
DAC: channels 3 to 6 (channels 1 and 2 non-differential)
Vo(rms) output voltage (RMS value) note 1 −1−V
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio at 0 dB
fs=48kHz −−90 −83 dB
fs=96kHz −−85 −dB
at −60 dB; A-weighted
fs=48kHz −−43 −dB
fs=96kHz −−41 −dB
S/N signal-to-noise ratio code = 0; A-weighted
fs=48kHz −103 −dB
fs=96kHz −101 −dB
αcs channel separation −100 −dB
2001 Mar 27 5
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
6 BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MGR979
STATIC
9
DS
26
MUTE
23
DEEM1
24
DEEM0
25
18
19
17
10
11
12
13
14
TEST3
8
TEST2
22
TEST1 27
VOUT3 1
4
SYSCLK 16
CONTROL
INTERFACE
DIGITAL
INTERFACE
VOLUME/MUTE/DE-EMPHASIS
UDA1328T
DAC
INTERPOLATION FILTER
6-CHANNEL NOISE SHAPER
DAC
DAC DAC
DAC
DAC
VOUT1N 29
6
VOUT1P 28
VOUT5
VOUT4
2
5
VOUT2N
31 VOUT2P
32
VOUT6
VDDA
7, 15
n.c.
3
VSSA
30
Vref
21 20
BCK
WS
DATAI12
DATAI34
DATAI56
L3DATA
L3CLOCK
L3MODE
VDDD VSSD
2001 Mar 27 6
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
7 PINNING
SYMBOL PIN DESCRIPTION
VOUT3 1 channel 3 analog output
VOUT4 2 channel 4 analog output
VSSA 3 analog ground
VOUT5 4 channel 5 analog output
VOUT6 5 channel 6 analog output
VDDA 6 analog supply voltage
n.c. 7 not connected (reserved)
TEST3 8 test output 3
STATIC 9 static mode/L3 mode switch input
BCK 10 bit clock input
WS 11 word select input
DATAI12 12 data input channel 1 and 2
DATAI34 13 data input channel 3 and 4
DATAI56 14 data input channel 5 and 6
n.c. 15 not connected (reserved)
SYSCLK 16 system clock: 256fs, 384fs,
512fsand 768fs
L3MODE 17 L3 mode selection input
L3CLOCK 18 L3 clock input
L3DATA 19 L3 data input
VSSD 20 digital ground
VDDD 21 digital supply voltage
TEST2 22 test output 2
MUTE 23 static mute control input
DEEM1 24 DEEM control 1 input
(static mode)
DEEM0 25 L3 address select
(L3 mode)/DEEM control 0 input
(static mode)
DS 26 digital silence detect output
TEST1 27 test input 1
VOUT1P 28 channel 1 analog output P
VOUT1N 29 channel 1 analog output N
Vref 30 DAC reference voltage
VOUT2N 31 channel 2 analog output N
VOUT2P 32 channel 2 analog output P Fig.2 Pin configuration.
handbook, halfpage
UDA1328T
MGR980
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VOUT3
VOUT4
VSSA
VOUT5
VOUT6
VDDA
n.c.
TEST3
STATIC
BCK
WS
DATAI12
DATAI34
DATAI56
VOUT2P
VOUT2N
Vref
VOUT1N
TEST1
DS
VOUT1P
DEEM0
DEEM1
MUTE
TEST2
VDDD
VSSD
L3DATA
n.c.
SYSCLK
L3CLOCK
L3MODE
2001 Mar 27 7
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
8 FUNCTIONAL DESCRIPTION
8.1 System clock
The UDA1328 operates in slave mode only, this means
that in all applications the system must provide the system
clock.Thesystem frequencyisselectable. Theoptionsare
256fs, 384fs, 512fsand 768fsfor the L3 mode and 256fsor
384fs for the static mode. The system clock must be
frequency-locked to the digital interface signals.
It should be noted that the UDA1328 can operate from
5 to 100 kHz sampling frequency (fs). However in 768fs
mode the sampling frequency must be limited to 55 kHz.
8.2 Application modes
Operating mode can be set with the STATIC pin, either to
L3 mode (STATIC = LOW) or to the static mode
(STATIC = HIGH). See Table 1 for pin functions in the
static mode.
Table 1 Mode selection in the static mode
Notes
1. SF1 and SF0 are the Serial Format inputs (2-bit).
2. X means that the pin has no function in this mode and
can best be connected to ground.
8.3 Interpolation filter (DAC)
The digital filter interpolates from 1 to 128fs by cascading
a half-band filter and a FIR filter, see Table 2. The overall
filter characteristic of the digital filters is illustrated in Fig.3,
andthe pass-band rippleis illustratedin Fig.4.Bothfigures
are with a 44.1 kHz sampling frequency.
Table 2 Interpolation filter characteristics
8.4 Digital silence detection
The UDA1328 can detect digital silence conditions in
channels 1 to 6, and report this via the output pin DS. This
function is implemented to allow for external manipulation
of the audio signal in the absence of program material,
such as muting or recorder control.
An active LOW output is produced at the DS pin if the
channels selected via L3 or for all channels in static mode,
carries all zeroes for at least 9600 consecutive audio
samples (equals 200 ms for fs= 48 kHz). The DS pin is
also active LOW when the output is digitally muted either
via the L3 interface or via the STATIC pin.
In static mode all channels participate in the digital silence
detection. In L3 mode control each channel can be set,
either to participate in the digital silence detection or not.
8.5 Noise shaper
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream DAC (FSDAC).
8.6 Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. No post-filter is needed due to
the inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
8.7 Static mode
The UDA1328 is set to static mode by setting the STATIC
pin HIGH. The function of 6 pins of the device now get
another function as can be seen in Table 1.
8.7.1 SYSTEM CLOCK SETTING
In static mode pin 18 (L3CLOCK) is used to select the
system clock setting. When pin 18 is LOW, the device is in
256fs mode, when pin 18 is HIGH the device is in 384fs
mode.
PIN L3 MODE STATIC MODE
L3CLOCK L3CLOCK clock select
L3MODE L3MODE SF1(1)
L3DATA L3DATA SF0(1)
MUTE X(2) MUTE
DEEM1 X(2) DEEM1
DEEM0 L3ADR DEEM0
ITEM CONDITION VALUE (dB)
Pass-band ripple 0 to 0.45fs±0.02
Stop band >0.55fs−55
Dynamic range 0 to 0.45fs>114
DC gain −−3.5
2001 Mar 27 8
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
8.7.2 DE-EMPHASIS CONTROL
Instaticpin modethepins DEEM0 and DEEM1controlthe
de-emphasis mode; see Table 3.
Table 3 De-emphasis control
8.7.3 DIGITAL INTERFACE FORMATS
Instaticpin modethedigital audiointerfaceformats canbe
selected via pin 17 (SF1) and 19 (SF0). The following
interface formats can be selected (see also Table 4):
•I2S-bus with data word length of up to 24 bits
•LSB-justified format with data word length of
16, 20 or 24 bits.
Table 4 Input format selection in the static mode
It should be noted that the digital audio interface holds that
the BCK frequency can be 64 times the WS maximum
frequency, or fBCK ≤64 ×fWS
DEEM MODE DEEM1 DEEM0
No de-emphasis 0 0
32 kHz de-emphasis 0 1
44.1 kHz de-emphasis 1 0
48 kHz de-emphasis 1 1
INPUT FORMAT SF1 SF0
I2S-bus 0 0
LSB-justified 16 bits 0 1
LSB-justified 20 bits 1 0
LSB-justified 24 bits 1 1
8.8 L3 mode
The device is set to L3 mode by setting the STATIC pin to
LOW. The device can then be controlled via the L3
microcontroller interface (see Chapter 9).
8.8.1 DIGITAL INTERFACE FORMATS
The following interface formats can be selected in the
L3 mode:
•I2S-bus with data word length of up to 24 bits
•MSB-justified with data word length of up to 24 bits
•LSB-justified format with data word length of 16, 18,
20 or 24 bits.
8.8.2 L3 ADDRESS
TheUDA1328canbeaddressedvia theL3microcontroller
interface using one of two addresses. This is done in order
to individually control the UDA1328 and other Philips
DACs or CODECs via the same L3 bus.
The address can be selected using pin 25 (DEEM0) in
L3 mode.When pin 25 is set LOW, the address is 000100.
When pin 25 is set HIGH the address is 000101.
2001 Mar 27 9
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
Fig.3 Overall frequency characteristics.
fs= 6.14400 MHz
handbook, halfpage
0 200
0
−100
−80
MGR981
−60
−40
−20
40 80 120 160
volume
(dB)
f (kHz)
Fig.4 Pass-band ripple of all filters.
fs= 6.14400 MHz
handbook, halfpage
0 102030
−3.45
−3.47
−3.49
−3.51
−3.53
MGR982
Vo
(dB)
f (kHz)
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2001 Mar 27 10
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
a
ndbook, full pagewidth
MGR751
16
B5 B6 B7 B8 B9 B10
LEFT
LSB-JUSTIFIED FORMAT 24 BITS
WS
BCK
DATA
RIGHT
1518 1720 1922 212324 2 1
B3 B4
MSB B2 B23 LSB
16
B5 B6 B7 B8 B9 B10
1518 1720 1922 212324 21
B3 B4
MSB B2 B23 LSB
16
MSB B2 B3 B4 B5 B6
LEFT
LSB-JUSTIFIED FORMAT 20 BITS
WS
BCK
DATA
RIGHT
1518 1720 19 2 1
B19 LSB
16
MSB B2 B3 B4 B5 B6
1518 1720 19 2 1
B19 LSB
16
MSB B2 B3 B4
LEFT
LSB-JUSTIFIED FORMAT 18 BITS
WS
BCK
DATA
RIGHT
1518 17 2 1
MSB B2 B3 B4
B17 LSB
16 1518 17 2 1
B17 LSB
16
MSB B2
LEFT
LSB-JUSTIFIED FORMAT 16 BITS
WS
BCK
DATA
RIGHT
15 2 1
B15 LSB
16
MSB B2
15 2 1
B15 LSB
MSB MSBB2
21> = 812 3
LEFT
INPUT FORMAT I2S-BUS
WS
BCK
DATA
RIGHT
3> = 8
MSB B2
Fig.5 Serial interface; input formats.
2001 Mar 27 11
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
9 L3 INTERFACE DESCRIPTION
The following system and digital sound processing
features can be controlled in the microcontroller mode of
the UDA1328:
•Data input format
•De-emphasis for 32, 44.1, 48 and 96 kHz
•Volume control: master and for individual channels
•Soft or quick mute: master and for individual channels
•Output polarity control: master and for individual
channels
•Digital silence control: master and for individual
channels
•Power-down mode.
Theexchange of data and control information betweenthe
microcontroller and the UDA1328 is accomplished via a
serial hardware interface comprising the following pins:
L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK: microcontroller interface clock line.
Information transfer via the microcontroller bus is
organized LSB first and is in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished. The address mode and data transfer
mode are illustrated in Figs 6 and 7.
The address mode is required to select a device
communicating via the L3-bus and to define the
destination registers for the data transfer mode. Data
transfer for the UDA1328 can only be in one direction;
inputtothe UDA1328to programits soundprocessingand
other functional features.
9.1 Address mode
The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits. The fundamental timing is
shown in Fig.6. Data bits 0 and 1 indicate the type of
subsequent data transfer as given in Table 5.
Table 5 Selection of data transfer
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1328 is 000100 (bit 7 to bit 2) when L3ADR
(DEEM0) = LOW or 000101 when L3ADR = HIGH. In the
eventthat theUDA1328 receives adifferent address,it will
deselect its microcontroller interface logic.
9.2 Data transfer mode
The selection preformed in the address mode remains
active during subsequent data transfers, until the
UDA1328 receives a new address command. The
fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.6. The
maximuminputclockanddatarateis 64fs. All transfersare
byte wise, i.e. they are based on groups of 8 bits. Data will
be stored in the UDA1328 after the eighth bit of a byte has
been received. A multibyte transfer is illustrated in Fig.8.
9.2.1 PROGRAMMING THE SOUND PROCESSING AND
OTHER FEATURES
The sound processing and other feature values are stored
inindependentregisters. Thefirstselection oftheregisters
is achieved by the choice of data type that is transferred.
This is performed in the address mode, bit 1 and bit 0
(see Table 5). The second selection is performed by the
2 MSBs of the data byte (bit 7 and bit 6). The other bits in
thedata byte(bit 5 to bit 0) isthe value thatis placedin the
selected registers.
When the data transfer of type ‘data’ is selected, the
features volume, sub volume, de-emphasis, mute, digital
silence settings, output polarity control and channel
selection can be controlled. When the data transfer of type
‘status’ is selected, the features system clock frequency,
data input format, mute mode and power control can be
controlled.
BIT 1 BIT 0 TRANSFER
0 0 data (volume, de-emphasis, mute,
digital silence mode, polarity control)
0 1 not used
1 0 status (system clock frequency,
data input format, mute mode,
power control)
1 1 not used
2001 Mar 27 12
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
Fig.6 Timing address mode.
handbook, full pagewidth
th(L3)A
th(L3)DA
tsu(L3)DA
Tcy(CLK)(L3)
BIT 0
L3MODE
L3CLOCK
L3DATA BIT 7
MGL723
tCLK(L3)H
tCLK(L3)L
tsu(L3)A
tsu(L3)A
th(L3)A
handbook, full pagewidth
tstp(L3) tstp(L3)
tsu(L3)D
tsu(L3)DA th(L3)DA
th(L3)D
MGL882
Tcy(CLK)L3
L3MODE
L3CLOCK
tCLK(L3)H
tCLK(L3)L
BIT 0
L3DATA
WRITE BIT 7
Fig.7 Timing for data transfer mode.
2001 Mar 27 13
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
Fig.8 Multibyte transfer.
handbook, full pagewidth
tstp(L3)
address
L3DATA
L3CLOCK
L3MODE
addressdata byte #1 data byte #2
MGL725
Table 6 Data transfer of type ‘status’
Table 7 Data transfer of type ‘data’
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED
0 RST SC1 SC0 IF2 IF1 IF0 0 ReSeT
System Clock frequency (1 and 0)
data Input Format (2 to 0)
100000QMPCQuick/soft Mute
Power Control
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED
0 0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 to 0)
010000VQ1VQ00.25 dB step sub volume (1 and 0)
1 0 DE2 DE1 DE0 MT DSM PLC DE-emphasis (2 to 0)
MuTe
Digital Silence Mode
PoLarity Control
1100ACHCH2CH1CH0All CHannels select
CHannel select (2 to 0)
2001 Mar 27 14
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
9.2.2 RESET BIT
A 1-bit value to initialize the L3 registers with the default
settings (except the system clock setting and the data
input format setting) by writing a logic 1 to RST
(see Table 6).
The default settings after reset are as follows:
•Mute mode: soft mute
•Power: on
•Volume: 0 dB
•Sub volume: 0 dB
•De-emphasis: off
•Mute: off
•Silence detect mode: detect
•Polarity: non-inverting.
9.2.3 SYSTEM CLOCK FREQUENCY
A 2-bit value (SC1 and SC0) to select the used external
clock frequency (see Table 8).
Table 8 System clock frequency settings
9.2.4 DATA INPUT FORMAT
A 3-bit value (IF2 to IF0) to select the used data format
(see Table 9).
Table 9 Data input format settings
SC1 SC0 FUNCTION
0 0 512fs
0 1 384fs
1 0 256fs
1 1 768fs
IF2 IF1 IF0 FUNCTION
000I
2
S-bus
0 0 1 LSB-justified; 16 bits
0 1 0 LSB-justified; 18 bits
0 1 1 LSB-justified; 20 bits
1 0 0 MSB-justified
1 0 1 LSB-justified; 24 bits
1 1 0 reserved
1 1 1 reserved
9.2.5 QUICK MUTE
A 1-bit value to set the mute mode to either soft mute (via
cosine roll-off), quick or hard mute.
Table 10 Quick mute
9.2.6 POWER CONTROL
A 1-bit value to disable the ADC and/or DAC to reduce
power consumption.
Table 11 Power control settings
9.3 Feature settings
In the UDA1328 there are features that can be controlled
either per-channel or all at the same time. These features
are:
•Volume control
•Sub volume control
•Mute
•Output polarity control
•Digital silence detect.
Whena‘per-channel’ settingisrequired forthesefeatures,
the ACH bit (see Table 7) must be set to logic 0 before
writing a new value to one of the features. Once this has
been performed a channel is selected via the CH2 to CH0
bits.Thefeaturesforthischannelcanbecontrolledwithout
sending the same channel address again (low
microcontroller mode).
When the ACH bit is set to logic 1, which means ‘all
channels select’, all channels will be set to the same value
of the feature sent afterwards.
For the digital silence detector it holds that the DS pin is
either active on the selected channel when bit ACH is set
to logic 0 before writing the DSM bit, or the DS pin is active
on all channels when the ACH bit is set to logic 1.
QM FUNCTION
0 soft mute mode
1 quick mute mode
PC FUNCTION
0 all channels off
1 all channels on
2001 Mar 27 15
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
9.3.1 CHANNEL SELECTION MODE
A 1-bit value to set the selection mode (either individually
or per-channel) for the volume, mute, polarity control and
silence detect is given in Table 12. The 3-bit value is given
in Table 13.
Table 12 1-bit selection
Note
1. For setting the de-emphasis mode, the ACH bit must
be set to logic 1 before setting the de-emphasis.
Table 13 3-bit selection
9.3.2 VOLUME CONTROL
A 6-bit value to program the channel volume attenuation
(VC5 to VC0). The range is 0 dB to −∞ dB in steps of 1 dB
(see Table 14).
Table 14 Volume settings
ACH(1) FUNCTION
0 individual channel select; use CH(2 : 0)
1 all channels selected
CH2 CH1 CH0 FUNCTION
0 0 0 channel 1 selected
0 0 1 channel 2 selected
0 1 0 channel 3 selected
0 1 1 channel 4 selected
1 0 0 channel 5 selected
1 0 1 channel 6 selected
1 1 0 not used
1 1 1 not used
VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)
000000 0
000001 0
000010 −1
000011 −2
:::::: :
111011 −58
111100 −59
111101 −60
111110 −∞
111111 −∞
9.3.3 SUB VOLUME CONTROL
A 2-bit value to program the channel volume attenuation
with a 0.25 dB step (VQ1 and VQ0). To validate the sub
volume settings in these registers, the volume control
registers of corresponding channels must be updated one
after the other.
Table 15 Sub volume settings
9.3.4 MUTE
A 1-bit value to enable the digital mute (the type of mute is
set via the QM bit in the status register).
Table 16 Mute
9.3.5 DIGITAL SILENCE MODE
A 1-bit value to set the digital silence mode. This bit is set
together with the channel address CH2 to CH0 and the
ACH bit.
When the ACH bit is set to logic 0, each channel can be
selected for digital silence detection. When the ACH bit is
set to logic 1 all channels are selected.
Table 17 Digital silence mode
VQ1 VQ0 VOLUME (dB)
0 0 0.00
01−0.25
10−0.50
11−0.75
MT FUNCTION
0 no muting
1 muting
DSM FUNCTION
0 no participation
1 participates
2001 Mar 27 16
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
9.3.6 DE-EMPHASIS
A 2-bit value to enable the digital de-emphasis filter.
Table 18 De-emphasis settings
9.3.7 OUTPUT POLARITY CONTROL
A 1-bit value to program the output polarity of the output
signal.This bit mustbe usedtogether withtheCH2 to CH0
bits and the ACH bit to either select the polarity for all
channels or to set for each channel individually.
Table 19 Output polarity control
DE2 DE1 DE0 FUNCTION
0 0 0 no de-emphasis
0 0 1 de-emphasis; 32 kHz
0 1 0 de-emphasis; 44.1 kHz
0 1 1 de-emphasis; 48 kHz
1 0 0 de-emphasis; 96 kHz
PLC FUNCTION
0 non-inverting
1 inverting
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Notes
1. All supply connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, expect pin 19 (L3DATA) which can
withstand ESD pulses of −2500 to +2500 V.
3. Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor.
4. DAC operation cannot be guaranteed after a short-circuit has occurred.
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDD digital supply voltage note 1 −5.0 V
VDDA analog supply voltage note 1 −5.0 V
Txtal(max) maximum crystal temperature −150 °C
Tstg storage temperature −65 +125 °C
Tamb ambient temperature −40 +85 °C
Ves electrostatic handling note 2 −3000 +3000 V
note 3 −250 +250 V
Ilu(prot) latch-up protection current Tamb = 125 °C; VDD = 3.6 V −200 mA
Isc(DAC) DAC short-circuit current: Tamb =0°C; VDD = 3.0 V;
note 4
output short-circuited to VSSA(DAC) −482 mA
output short-circuited to VDDA(DAC) −346 mA
2001 Mar 27 17
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
12 THERMAL CHARACTERISTICS
13 QUALITY SPECIFICATION
In accordance with
“SNW-FQ-611-E”
.
14 DC CHARACTERISTICS
VDDD =V
DDA = 3.3 V; Tamb =25°C; RL=5kΩ. All voltages referenced to ground (pins 3 and 20); unless otherwise
specified.
Notes
1. All supply connections must be made to the same external power supply unit.
2. When the DAC drives a capacitive load above 50 pF, a series resistor of 100 Ωmust be used to prevent oscillations
in the output operational amplifier.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air 58 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDDA analog supply voltage note 1 2.7 3.3 3.6 V
VDDD digital supply voltage note 1 2.7 3.3 3.6 V
IDDA analog supply current all channels active;
operating mode −28 −mA
IDDD digital supply current operating mode −11 −mA
Digital input pins: 5 V tolerant TTL compatible
VIH HIGH-level input voltage 2.0 −−V
V
IL LOW-level input voltage −−0.8 V
VIL(th) LOW-level threshold input voltage;
falling edge 0.9 −1.45 V
VIH(th) HIGH-level threshold input
voltage; rising edge 1.4 −1.9 V
Vhyst Schmitt trigger hysteresis voltage 0.4 −0.7 V
ILIinput leakage current −−1µA
C
iinput capacitance −−10 pF
Digital output pin
VOH HIGH-level output voltage IOH =−2 mA 0.85VDDD −−V
V
OL LOW-level output voltage IOL =2mA −−0.4 V
DAC
Vref reference voltage referenced to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V
Io(max) maximum output current (THD + N)/S < 0.1% −0.22 −mA
RLload resistance 3 −−kΩ
C
Lload capacitance note 2 −−50 pF
2001 Mar 27 18
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
15 AC CHARACTERISTICS (ANALOG)
VDDD =V
DDA = 3.3 V; fi= 1 kHz; Tamb =25°C; RL=5kΩ. All voltages referenced to ground (pins 3 and 20); unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
DAC: channels 1 and 2 in differential mode
Vo(rms) output voltage (RMS value) −2−V
∆Vounbalance between channels −0.1 −dB
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio fs= 48 kHz; at 0 dB −−95 −88 dB
fs= 48 kHz; at −60 dB; A-weighted −−46 −dB
fs= 96 kHz; at 0 dB −−90 −dB
fs= 96 kHz; at −60 dB; A-weighted −−44 −dB
S/N signal-to-noise ratio fs= 48 kHz; code = 0; A-weighted −106 −dB
fs= 96 kHz; code = 0; A-weighted −104 −dB
DAC: channels 3 to 6
Vo(rms) output voltage (RMS value) −1−V
∆Vounbalance between channels −0.1 −dB
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio fs= 48 kHz; at 0 dB −−90 −83 dB
fs= 48 kHz; at −60 dB; A-weighted −−43 −dB
fs= 96 kHz; at 0 dB −−85 −dB
fs= 96 kHz; at −60 dB; A-weighted −−41 −dB
S/N signal-to-noise ratio fs= 48 kHz; code = 0; A-weighted −103 −dB
fs= 96 kHz; code = 0; A-weighted −101 −dB
PSRR power supply rejection ratio fripple = 1 kHz; Vripple(p-p) = 100 mV −50 −dB
2001 Mar 27 19
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
16 AC CHARACTERISTICS (DIGITAL)
VDDD =V
DDA = 2.7 to 3.6 V; Tamb =−20 to +85 °C; RL=5kΩ. All voltages referenced to ground (pins 3 and 20); unless
otherwise specified. The typical timing is specified at 44.1 kHz sampling frequency.
Note
1. In the 768fs clock mode, the sampling frequency must be limited to 55 kHz.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Tsys system clock cycle fsys = 256fs35 88 780 ns
fsys = 384fs23 59 520 ns
fsys = 512fs20 44 390 ns
fsys = 768fs; note 1 20 30 260 ns
tCWL LOW-level system clock pulse
width fsys < 19.2 MHz 30 −70 %Tsys
fsys ≥19.2 MHz 40 −60 %Tsys
tCWH HIGH-level system clock pulse
width fsys < 19.2 MHz 30 −70 %Tsys
fsys ≥19.2 MHz 40 −60 %Tsys
trrise time −−20 ns
tffall time −−20 ns
Serial input data timing (see Fig.9)
Tcy(CLK)(bit) bit clock period 140 −−ns
tCLKH(bit) bit clock HIGH time 60 −−ns
tCLKL(bit) bit clock LOW time 60 −−ns
trrise time −−20 ns
tffall time −−20 ns
tsu(i)(D) data input set-up time 20 −−ns
th(i)(D) data input hold time 0 −−ns
tsu(WS) word selection set-up time 20 −−ns
th(WS) word selection hold time 10 −−ns
Microcontroller interface timing (see Figs 6,7 and 8)
Tcy(CLK)(L3) L3CLOCK time 500 −−ns
tCLK(L3)H L3CLOCK HIGH time 250 −−ns
tCLK(L3)L L3CLOCK LOW time 250 −−ns
tsu(L3)A L3MODE set-up time addressing mode 190 −−ns
th(L3)A L3MODE hold time addressing mode 190 −−ns
tsu(L3)D L3MODE set-up time data transfer mode 190 −−ns
th(L3)D L3MODE hold time data transfer mode 190 −−ns
tsu(L3)DA L3DATA set-up time data transfer and addressing mode 190 −−ns
th(L3)DA L3DATA hold time data transfer and addressing mode 30 −−ns
tstp(L3) L3MODE halt time 190 −−ns
2001 Mar 27 20
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
Fig.9 Serial interface timing.
handbook, full pagewidth
MGL721
tf
th(WS)
tsu(WS)
tsu(i)(D) th(i)(D)
tCLKH(bit)
tCLKL(bit)
Tcy(CLK)(bit)
tr
WS
BCK
DATAI
Fig.10 System clock timing.
handbook, full pagewidth
MGR984
Tsys
tCWH
tCWL
2001 Mar 27 21
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
17 APPLICATION INFORMATION
Fig.11 Application diagram.
handbook, full pagewidth
MGR983
UDA1328T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
2
31
28
27
26
25
24
23
22
21
20
19
18
17
VOUT3
AGND
AGND
AGND
AGND
DGND
VOUT4
VSSA
VOUT5
VOUT6
VOUT3
VOUT4
VOUT5
VOUT6
VDDA
VDDA
n.c.
TEST3
STATIC
STATIC/L3
BCK
WS
DATAI12
DATAI34
DATAI56
VOUT2P
VOUT2N VOUT2
Vref
VOUT1N
VOUT1P
TEST1
DS
VOUT1
DEEM0
DEEM1
MUTE
TEST2
VDDD VDDD
VSSD
L3DATA
n.c.
SYSCLK
SYSCLK
L3CLOCK
L3MODE
R13 100 Ω
R14 10 kΩ
C7 47 µF
(16 V)
C8 47 µF
(16 V)
C9 47 µF
(16 V)
C10 47 µF
(16 V)
R15 100 Ω
R16 10 kΩ
R17 100 Ω
R18 10 kΩ
AGND
R19 100 Ω
1 Ω
47 Ω
R20 10 kΩ100 nF
100 µF
(16 V)
1 Ω
100
nF 100 µF
(16 V)
DGNDAGND
ground
AGND
C14
100 nF
100 pF
100 pF
C13
47 µF
(16 V)
47 µF
47 µF
(16 V)
(16 V)
AGND
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ10 kΩ
10 kΩ
10 kΩ
10 kΩ
100 Ω
5
67100 Ω
AGND
AGND
AGND
1/2
NE5532
1/2
NE5532
DGND
VDDD
VDDA
100 µF
(16 V)
100 µF
(16 V)
3.3 V
AGND
BLM32A07
2001 Mar 27 22
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
18 PACKAGE OUTLINE
UNIT A
max. A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
inches
2.65
0.10
0.25
0.01
1.4
0.055
0.3
0.1 2.45
2.25 0.49
0.36 0.27
0.18 20.7
20.3 7.6
7.4 1.27 10.65
10.00 1.2
1.0 0.95
0.55 8
0
o
o
0.25 0.1
0.004
0.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.1
0.4
SOT287-1 MO-119
(1)
0.012
0.004 0.096
0.089 0.02
0.01 0.050 0.047
0.039
0.419
0.394
0.30
0.29
0.81
0.80
0.011
0.007 0.037
0.022
0.010.01
0.043
0.016
wM
bp
D
HE
Z
e
c
vMA
X
A
y
32 17
16
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
E
pin 1 index
0 5 10 mm
scale
SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1
99-12-27
00-08-17
2001 Mar 27 23
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
19 SOLDERING
19.1 Introduction to soldering surface mount
packages
Thistextgives averybrief insighttoa complextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs, butitisnot suitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
19.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuitboard byscreen printing,stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
19.3 Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices (SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleads onfoursides,the footprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
19.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2001 Mar 27 24
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
19.5 Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE SOLDERING METHOD
WAVE REFLOW(1)
BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
2001 Mar 27 25
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
20 DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DATA SHEET STATUS(1) PRODUCT
STATUS(2) DEFINITIONS
Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
21 DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor atany otherconditionsabove thosegiven in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuch applicationswillbe
suitable for the specified use without further testing or
modification.
22 DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofany oftheseproducts,conveys nolicenceortitle
under any patent, copyright, or mask work right to these
products,and makesno representations orwarranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
2001 Mar 27 26
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
NOTES
2001 Mar 27 27
Philips Semiconductors Product specification
Multi-channel filter DAC UDA1328T
NOTES
© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
2001 72
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Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
Printed in The Netherlands 753503/03/pp28 Date of release: 2001 Mar 27 Document order number: 9397 750 08101
