STPC-CONSUMER - STMicroelectronics



STPC CONSUMER

PC Compatible Embeded Microprocessor

1/518/2/00 Issue 1.2

Figure 1. Logic Diagram

■POWERFUL X86 PROCESSOR

■64-BIT BUS ARCHITECTURE

■64-BIT DRAM CONTROLLER

■SVGA GRAPHICS CONTROLLER

■UMA ARCHITECTURE

■VIDEO SCALER

■DIGITAL PAL/NTSC ENCODER

■VIDEO INPUT PORT

■CRTCONTROLLER

■135MHz RAMDAC

■3 LINE FLICKER FILTER

■SCAN CONVERTER

■PCI MASTER / SLAVE / ARBITER CTRL

■ISA MASTER/SLAVE INTERFACE

■IDE CONTROLLER

■DMA CONTROLLER

■INTERRUPT CONTROLLER

■TIMER / COUNTERS

■POWER MANAGEMENT

STPC CONSUMER OVERVIEW

The STPC Consumer integrates a standard 5th

generation x86 core, a DRAM controller, a graph-

ics subsystem, a video pipeline and support logic

including PCI,ISA andIDE controllers toprovide a

single Consumer orientated PC compatible sub-

system on a single device.

The device is based on a tightly coupled Unified

Memory Architecture (UMA), sharing the same

memory array between the CPU main memory

and the graphics and video frame buffers.

Extra facilities are implemented to handle video

streams. Features include smooth scaling and

color space conversion of the video input stream

and mixing with graphics data. The chip also in-

cludes abuilt-in digital TV encoder andanti-flicker

filters that allow stable, high-quality display on

standard PAL or NTSC television sets without ad-

ditional components.

The STPC Consumer is packaged in a 388 Plastic

Ball Grid Array (PBGA).

PBGA388

x86

Core

Host I/F

DRAM

CTRL

VIP

PCI

m/s

PCIBUS

ISA

m/s

EIDE

PCI

m/s

ISABUS

CRTC HW Cursor

Monitor

TVOutput

SYNCOutput

Color Space

Converter

Color

Key

Chroma

Key

Video

pipeline

CCIRInput

EIDE

SVGA

AntiFlicker

IPC

Digital

PAL/

NTSC

STPC CONSUMER

2/51 Issue 1.2

■X86 Processor core

■Fully static 32-bit 5-stage pipeline, x86

processor fully PC compatible.

■Can access up to 4GBytes of external

memory.

■8KByte unified instruction and data cache

with write back and write through capability.

■Parallel processingintegral floating point unit,

with automatic power down.

■Clock core speeds up to of 100 MHz.

■Fully static design for dynamic clock control.

■Low power and system management modes.

■Optimized design for3.3V operation.

■DRAM Controller

■Integrated system memory andgraphic frame

memory.

■Supports up to 128 MBytes system memory

in 4 banks and down to as little as 2Mbytes.

■Supports 4MB, 8MB, 16MB, 32MB single-

sided and double-sided DRAM SIMMs.

■Four quad-word write buffersfor CPU to

DRAM and PCI to DRAM cycles.

■Four 4-word read buffers for PCI masters.

■Supports Fast Page Mode & EDO DRAM.

■Programmable timing for DRAM parameters

including CAS pulse width, CAS pre-charge

time and RAS to CAS delay.

■60, 70, 80 & 100ns DRAM speeds.

■Memory hole between 1 MByte & 8 MByte

supported for PCI/ISA busses.

■Hidden refresh.

To check if your memory device is supported by

the STPC, please refer to Table 9-3 in the

Programming Manual.

■Graphics Engine

■64-bit windows accelerator.

■Backward compatibility to SVGA standards.

■Hardware acceleration for text, bitblts,

transparent bltsand fills.

■Up to64 x 64 bit graphics hardware cursor.

■Up to 4MB long linear frame buffer.

■8-, 16-, and 24-bit pixels.

■Drivers for Windows and other operating

systems.

■VGA Controller

■Integrated 135MHz triple RAMDAC allowing

for 1280 x 1024 x 75Hz display.

■Requires external frequency synthesizer and

reference sources.

■8-, 16-, 24-bit pixels.

■Interlaced or non-interlaced output.

■Video Input port

■Accepts video inputs in CCIR 601/656 or

ITU-R 601/656, and stream decoding.

■Optional 2:1 decimator

■Stores captured video in off setting area of

the onboard frame buffer.

■Video pass through to the onboard PAL/

NTSC encoder for full screen video images.

■HSYNC and B/T generation or lock onto

external video timing source.

■Video Pipeline

■Two-tap interpolative horizontal filter.

■Two-tap interpolative vertical filter.

■Color space conversion (RGB to YUV and

YUV to RGB).

■Programmable window size.

■Chroma and color keyingfor integrated video

overlay.

■Programmable two tap filter with gamma

correction or three tap flicker filter.

■Progressive to interlaced scan converter.

■Digital NTSC/PAL encoder

■NTSC-M, PAL-M,PAL-B,D,G,H,I,PAL-N easy

programmable video outputs.

■CCIR601 encoding with programmable color

subcarrier frequencies.

■Line skip/insert capability

■Interlaced or non-interlaced operation mode.

■625 lines/50Hz or 525 lines/60Hz 8 bit

multiplexedCB-Y-CR digital input.

■CVBS and R,G,B simultaneous analog

outputs through 10-bit DACs.

■Cross colorreduction by specific trap filtering

on luma within CVBS flow.

■Power down mode available on each DAC.

STPC CONSUMER

3/51

Issue 1.2

■PCI Controller

■Fully compliant with PCI 2.1 specification.

■Integrated PCI arbitration interface. Up to 3

masters can connect directly. External PAL

allows forgreater than 3 masters.

■Translation of PCI cycles to ISA bus.

■Translation of ISA master initiated cycle to

PCI.

■Support forburst read/write from PCI master.

■

0.33X and 0.5X CPU clock PCI clock.

■ISA master/slave Interface

■Generates the ISA clock from either

14.318MHz oscillator clock or PCI clock

■Supports programmable extra wait state for

ISA cycles

■Supports I/O recovery time for back to back

I/O cycles.

■Fast Gate A20 and Fast reset.

■

Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

■Supports flash ROM.

■Supports ISA hidden refresh.

■Buffered DMA & ISA master cycles to reduce

bandwidth utilization ofthe PCI and Host bus.

NSP compliant.

■IDE Interface

■Supports PIO

■

Supports up to Mode 5 Timings

■TransferRates to 22 MBytes/sec

■Supports up to 4 IDE devices

■Concurrent channel operation(PIO modes) -

4 x 32-Bit Buffer FIFOs per channel

■Support for PIO mode 3 & 4.

■Support for 11.1/16.6 MB/s, I/O Channel

Ready PIO data transfers.

■Individual drive timing for all four IDE devices

■Supports both legacy & native IDE modes

■Supports hard drives larger than 528MB

■Support for CD-ROM and tape peripherals

■Backward compatibility with IDE (ATA-1).

■Drivers for Windows and other Operating

Systems

■Integrated peripheral controller

■2X8237/AT compatible 7-channel DMA

controller.

■2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

■Three 8254 compatible Timer/Counters.

■Co-processor error support logic.

■Power Management

■Four power saving modes: On, Doze,

Standby, Suspend.

■Programmable system activity detector

■Supports SMM and APM.

■Supports STOPCLK.

■Supports IO trap & restart.

■Independent peripheral time-out timer to

monitor hard disk, serial & parallel ports.

■Supports RTC, interrupts and DMAs wake-up

STPC CONSUMER

4/51 Issue 1.2

UPDATE HISTORY FOR OVERVIEW.

5/51

Issue 1.2

0.1 UPDATE HISTORY FOR OVERVIEW.

The following changes have been made to the Electrical Specification Chapter on the 02/02/2000.

Section Change Text

Added To check if your memory device is supported by the STPC, please refer to

Table 9-3 Host Address to MA Bus Mappingin the Programming Manual.

GENERAL DESCRIPTION

6/51 Issue 1.2

1. GENERAL DESCRIPTION

At the heart of the STPC Consumer is an ad-

vanced processor block, dubbed the 5ST86. The

5ST86 includes a powerful x86 processor core

along with a 64-bit DRAM controller, advanced

64bit accelerated graphics and video controller, a

high speed PCI local-bus controller and Industry

standard PC chip set functions (Interrupt control-

ler, DMA Controller, Interval timer and ISA bus)

and EIDE controller.

The STPC Consumer has in addition to the

5ST86, a Video subsystem and high quality digital

Television output.

The STMicroelectronics x86 processorcore is em-

bedded with standard and application specific pe-

ripheral modules on the same silicon die. The core

has all the functionality of the STMicroelectronics

standard x86 processor products, including the

low power System Management Mode (SMM).

System Management Mode (SMM) provides an

additional interrupt and address space that canbe

used for system power management or software

transparent emulation of peripherals. While run-

ning in isolated SMM address space, the SMM in-

terrupt routine can execute without interfering with

the operating system or application programs.

Further power management facilities include a

suspend mode that can be initiated from either

hardware or software. Because of the static nature

of the core, no internal data is lost.

The STPC Consumer makes use of a tightly cou-

pled Unified Memory Architecture (UMA), where

the same memory array is used for CPU main

memory and graphics frame-buffer. This signifi-

cantly reduces total system memory with system

performances equal to that of a comparable solu-

tion with separate frame buffer and system mem-

ory. Inaddition, memory bandwidth is improvedby

attaching the graphics engine directly to the 64-bit

processor host interface running at the speed of

the processor bus rather than the traditional PCI

bus.

The 64-bit wide memory array provides the sys-

tem with 320MB/s peak bandwidth, double that of

an equivalent system using 32 bits. This allows for

higher screen resolutions and greater color depth.

The processor bus runs at the speed of the proc-

essor (DX devices) or half the speed (DX2 devic-

es).

The ‘standard’ PC chipset functions (DMA, inter-

rupt controller, timers, power management logic)

are integrated with the x86 processor core.

The PCI bus is the main data communication link

to the STPC Consumer chip. The STPC Consum-

er translates appropriate host bus I/O and Memory

cycles onto the PCI bus. It also supports the gen-

eration of Configuration cycles on the PCI bus.

The STPC Consumer, as a PCI bus agent (host

bridge class), fully complies with PCI specification

2.1. The chip-set also implements the PCI manda-

tory header registers in Type 0 PCI configuration

space for easy porting of PCI aware system BI-

OS. The device contains a PCI arbitration function

for three external PCI devices.

The STPC Consumer integrates an ISA bus con-

troller. Peripheral modules such as parallel and

serial communications ports, keyboard controllers

and additional ISA devices can be accessed by

the STPC Consumer chip set through this bus.

An industry standard EIDE (ATA 2) controller is

built in to the STPC Consumer and connected in-

ternally via the PCI bus.

Graphics functions are controlled by the on-chip

SVGA controller and the monitor display is man-

aged by the 2D graphics display engine.

This Graphics Engine is tuned to work with the

host CPU to provide a balanced graphics system

with a low silicon area cost. It performs limited

graphics drawing operations, which include hard-

ware acceleration of text, bitblts, transparent blts

and fills. These operations can act on off-screen

or on-screen areas. The frame buffer size ranges

up to 4 Mbytes anywhere in the physical main

memory.

The graphics resolution supported is a maximum

of 1280x1024 in 65536 colours at 75Hz refresh

rate and is VGA and SVGA compatible. Horizontal

timing fields are VGA compatible while the vertical

fields are extended by onebit to accommodate the

above display resolution.

STPC Consumer providesseveral additional func-

tions to handle MPEG or similar video streams.

The Video Input Port accepts an encoded digital

video stream in one of a number of industry stand-

ard formats, decodes it, optionally decimates it by

a factor of 2:1, and deposits it into an off screen

area of the frame buffer. An interrupt request can

be generated when an entire field or frame has

been captured.

GENERAL DESCRIPTION

7/51

Issue 1.2

The video output pipeline incorporates a video-

scaler and color space converter function and pro-

visions in the CRT controller to display a video

window. While repainting the screen the CRT con-

troller fetchesboth the video as well as the normal

non-video frame buffer in two separate internal

FIFOs (256-Bytes each). The video stream can be

color-space converted (optionally) and smooth

scaled. Smooth interpolative scaling in both hori-

zontal and vertical directions are implemented.

Color and Chroma key functions are also imple-

mented to allow mixing video stream with non-vid-

eo frame buffer.

The video output passes directly to the RAMDAC

for monitor output or through another optional

color spaceconverter (RGB to 4:2:2 YCrCb) to the

programmable anti-flicker filter. The flicker filter is

configured as either a two line filter with gamma

correction (primarily designed for DOS type text)

or a 3 line flicker filter (primarily designed for Win-

dows type displays). The flicker filter is optional

and canbe software disabled for use withvideo on

large screen areas.

The Video output pipeline of the STPC Consumer

interfaces directly to the internal digital TV encod-

er. It takes a 24 bit RGB non-interlaced pixel

stream and converts to a multiplexed 4:2:2 YCrCb

8 bit output stream, the logic includes a progres-

sive to interlaced scan converter and logic to in-

sert appropriate CCIR656 timing reference codes

into the output stream. It facilitates the high quality

display of VGA or full screen video streams re-

ceived via the Video input port to standard NTSC

or PAL televisions.

The STPC Consumer core is compliant with the

Advanced Power Management (APM) specifica-

tion to provide a standard method by which the

BIOS can control the power used by personal

computers. The Power Management Unit module

(PMU) controls the power consumption by provid-

ing a comprehensive set of features that control

the power usage and supports compliance with

the United States EnvironmentalProtection Agen-

cy’s Energy Star Computer Program. The PMU

provides following hardware structures to assist

the software in managing the power consumption

by the system.

- System Activity Detection.

- 3 power-down timers detecting system inactivity:

- Doze timer (short durations).

- Stand-by timer (medium durations).

- Suspend timer (long durations).

- House-keeping activity detection.

- House-keeping timer to cope with short bursts of

house-keeping activity while dozing or in stand-by

state.

- Peripheral activity detection.

- Peripheral timer detecting peripheralinactivity

- SUSP# modulation to adjust the system perform-

ance in various power down states of the system

including full power on state.

- Power control outputs to disable power from dif-

ferent planes of the board.

Lack of system activity for progressively longer

period of times is detected by the three power

down timers. These timers can generate SMI in-

terrupts to CPU so that the SMM software can put

the system in decreasing states of power con-

sumption. Alternatively, system activity in a power

down state can generate SMI interrupt to allow the

software to bring the system back up to full power

on state. The chip-set supports up to three power

down states: Doze state, Stand-by state and Sus-

pend mode. These correspond to decreasing lev-

els of power savings.

Power down puts the STPC Consumer into sus-

pend mode. The processor completes execution

of thecurrent instruction, any pending decoded in-

structions and associated bus cycles. During the

suspend mode, internal clocks are stopped. Re-

moving power down, the processor resumes in-

struction fetching and begins execution in the in-

struction stream at the point it had stopped.

A reference design for the STPC Consumer is

available including the schematics and layout

files, the design isa PC ATX motherboard design.

The design is available as a demonstration board

for application and systemdevelopment.

The STPC Consumer is supported by several

BIOS vendors, including the super I/O device

used in the reference design. Drivers for 2D accel-

erator, video features and EIDE are availaible on

various operating systems.

The STPC Consumer has been designed using

modern reusable modular design techniques, it is

possible to add or remove the standard features of

the STPC Consumer or other variants of the

5ST86 family. Contact your local STMicroelecton-

ics sales office for further information.

GENERAL DESCRIPTION

8/51 Issue 1.2

Figure 1-1 Functionnal description

x86

Core

Host I/F

DRAM

SVGA

VIP

PCI m/s PCI BUS

ISA

EIDE

PCI m/s

ISA BUS

CRTC HW Cursor

Monitor

TV Output

SYNC Output

IPC

Anti-Flicker

Color Space

Color

Key

Chroma

Video

pipeline

CCIR Input

EIDE

Digital

PAL/

GENERAL DESCRIPTION

9/51

Issue 1.2

Figure 1-2 Typical Application

STPC Consumer

ISA

PCI

4x 16-bit EDO DRAMs

Super I/O

2x EIDE

Flash

Keyboard / Mouse

Serial Ports

Parallel Port

Floppy

Monitor

Video

SVGA

CCIR601

CCIR656

S-VHS

RGB

PAL

NTSC

IRQ

DMA.REQ

DMA.ACK

DMUX

MUX

RTC

PIN DESCRIPTION

10/51 Issue 1.2

2. PIN DESCRIPTION

2.1 INTRODUCTION

The STPC Consumer integrates most of the func-

tionalities ofthe PC architecture. As aresult, many

of the traditional interconnections between the

host PC microprocessor and the peripheral devic-

es aretotally internal to the STPC Consumer. This

offers improved performance due to the tight cou-

pling of the processor core and these peripherals.

As a result many of the external pin connections

are made directly to the on-chip peripheral func-

tions.

Figure2-1 shows the STPC Consumer’s external

interfaces. It defines the main busses and their

function. Table 2-1 describes the physical imple-

mentation listing signal types and their functional-

ities. Table 2-2 provides a full pin listing and de-

scription. Table 2-3 provides a full listing of the

STPC Consumer pin locations of package by

physical connection. Please refer to thepin alloca-

tion drawing for reference. Note: Several interface pins are multiplexed with

other functions, refer to the Pin Description sec-

tion for further details

Table 2-1. Signal Description

Group name Qty

Basic Clocks reset & Xtal(SYS) 12

DRAM Controller 89

PCI interface (PCI) 58

ISA / IDE / IPC combined interface 88

Video Input (VIP) 9

TV Output 10

VGA Monitor interface 10

Grounds 69

VDD 26

Analog specific VCC/VDD 12

Reserved 5

Total Pin Count 388

Figure 2-1. STPC Consumer External Interfaces

SOUTHNORTH PCI

x86

DRAM VGA VIP TV SYS ISA/IDE IPC

89 10 9 10 58 13 77 11

STPC Consumer

PIN DESCRIPTION

11/51

Issue 1.2

Table 2-2. Definition of Signal Pins

Signal Name Dir Description Qty

BASIC CLOCKS AND RESETS

SYSRSTI# I System Reset / Power good 1

XTALI I 14.3MHz Crystal Input 1

XTALO I/O 14.3MHz Crystal Output - External Oscillator Input 1

HCLK O Host Clock (Test) 1

DEV_CLK O 24MHz Peripheral Clock (floppy drive) 1

GCLK2X I/O 80MHz Graphics Clock 1

DCLK I/O 135MHz Dot Clock 1

PCI_CLKI I 33MHz PCI Input Clock 1

PCI_CLKO O 33MHz PCI Output Clock (from internal PLL) 1

SYSRSTO# O Reset Output to System 1

ISA_CLK O ISA Clock Output - Multiplexer Select Line For IPC 1

ISA_CLK2X O ISA Clock x 2 Output - Multiplexer Select Line For IPC 1

MEMORY INTERFACE

MA[11:0] I/O Memory Address 12

RAS#[3:0] O Row Address Strobe 4

CAS#[7:0] O Column Address Strobe 8

MWE# O Write Enable 1

MD[63:0] I/O Memory Data 64

PCI INTERFACE

AD[31:0] I/O PCI Address / Data 32

CBE[3:0] I/O Bus Commands / Byte Enables 4

FRAME# I/O Cycle Frame 1

TRDY# I/O Target Ready 1

IRDY# I/O Initiator Ready 1

STOP# I/O Stop Transaction 1

DEVSEL# I/O Device Select 1

PAR I/O Parity Signal Transactions 1

SERR# O System Error 1

LOCK# I PCI Lock 1

PCIREQ#[2:0] I PCI Request 3

PCIGNT#[2:0] O PCI Grant 3

PCI_INT[3:0] I PCI Interrupt Request 4

VDD5 I 5V Power Supply for PCI ESD protection 4

ISA AND IDE COMBINED ADDRESS/DATA

LA[23:22] / SCS3#,SCS1# I/O Unlatched Address (ISA) / Secondary Chip Select (IDE) 2

LA[21:20] / PCS3#,PCS1# I/O Unlatched Address (ISA) / Primary Chip Select (IDE) 2

LA[19:17] / DA[2:0] O Unlatched Address (ISA) / Address (IDE) 3

RMRTCCS# / DD[15] I/O ROM/RTC Chip Select / Data Bus bit 15 (IDE) 1

KBCS# / DD[14] I/O Keyboard Chip Select / Data Bus bit 14 (IDE) 1

RTCRW# / DD[13] I/O RTC Read/Write / Data Bus bit 13 (IDE) 1

RTCDS# / DD[12] I/O RTC Data Strobe / Data Bus bit 12 (IDE) 1

SA[19:8] / DD[11:0] I/O Latched Address (ISA) / Data Bus (IDE) 16

SA[7:0] I/O Latched Address (IDE) 4

SD[15:0] I/O Data Bus (ISA) 16

PIN DESCRIPTION

12/51 Issue 1.2

ISA/IDE COMBINED CONTROL

IOCHRDY / DIORDY I/O I/O Channel Ready (ISA) - Busy/Ready (IDE) 1

ISA CONTROL

OSC14M O ISA bus synchronisation clock 1

ALE O Address Latch Enable 1

BHE# I/O System Bus High Enable 1

MEMR#, MEMW# I/O Memory Read and Memory Write 2

SMEMR#, SMEMW# O System Memory Read and Memory Write 2

IOR#, IOW# I/O I/O Read and Write 2

MASTER# I Add On Card Owns Bus 1

MCS16#, IOCS16# I Memory/IO Chip Select16 2

REF# O Refresh Cycle. 1

AEN O Address Enable 1

ZWS# I Zero Wait State 1

IOCHCK# I I/O Channel Check. 1

ISAOE# O Bidirectional OE Control 1

RTCAS# O Real Time Clock Address Strobe 1

GPIOCS# I/O General Purpose Chip Select 1

IDE CONTROL

PIRQ I Primary Interrupt Request 1

SIRQ I Secondary Interrupt Request 1

PDRQ I Primary DMA Request 1

SDRQ I Secondary DMA Request 1

PDACK# O Primary DMA Acknowledge 1

SDACK# O Secondary DMA Acknowledge 1

PIOR# I/O Primary I/O Read 1

PIOW# O Primary I/O Write 1

SIOR# I/O Secondary I/O Read 1

SIOW# O Secondary I/O Write 1

IPC

IRQ_MUX[3:0] I Multiplexed Interrupt Request 4

DREQ_MUX[1:0] I Multiplexed DMA Request 2

DACK_ENC[2:0] O DMA Acknowledge 3

TC O ISA Terminal Count 1

MONITOR INTERFACE

RED, GREEN, BLUE O Red, Green, Blue 3

VSYNC O Vertical Sync 1

HSYNC O Horizontal Sync 1

VREF_DAC I DAC Voltage reference 1

RSET I Resistor Set 1

COMP I Compensation 1

DDC[1:0] I/O Display Data Channel Serial Link 2

SCL / D DC[1] I/O I C Inte rface - Clock / Can be used for VG A DDC[1] signal 1

Table 2-2. Definition of Signal Pins

Signal Name Dir Description Qty

PIN DESCRIPTION

13/51

Issue 1.2

SDA / D DC[0] I/O I C Inte rface - Data / Can be used for V GA D DC[0] signal 1

COL_CMP O Color Compare Output.

VIDEO INPUT

VCLK I Pixel Clock 1

VIN I YUV Video Data Input CCIR 601 or 656 8

DIGITAL TV OUTPUT

RED_TV, GREEN_TV, BLUE_TV O Analog video outputs synchronized with CVBS 3

VCS O Composite Synch or Horizontal line SYNC output 1

ODD_EVEN O Frame Synchronisation 1

CVBS O Analog video composite output (luminance / chrominance) 1

IREF1_TV I Reference current of 9bit DAC for CVBS 1

VREF1_TV I Reference voltage of 9bit DAC for CVBS 1

IREF2_TV I Reference current of 8bit DAC for R,G,B 1

VREF2_TV I Reference voltage of 8bit DAC for R,G,B 1

VSSA_TV I Analog Vss for DAC 1

VDDA_TV I Analog Vdd for DAC 1

MISCELLANEOUS

SPKRD O Speaker Device Output 1

SCAN_ENABLE I Reserved (Test pin) 1

Table 2-2. Definition of Signal Pins

Signal Name Dir Description Qty

PIN DESCRIPTION

14/51 Issue 1.2

2.2 SIGNAL DESCRIPTIONS

2.2.1 BASIC CLOCKS AND RESETS

SYSRSTI

System Reset/Powergood.

This input is

low when the reset switch is depressed. Other-

wise, it reflects the power supply’s power good

signal. SYSRSTI is asynchronous to all clocks,

and acts as a negative active reset. The reset cir-

cuit initiates a hard reset on the rising edge of

SYSRSTI.

SYSRSTO#

Reset Output to System.

This is the

system reset signal and is used to reset the rest of

the components (not on Host bus) in the system.

The ISA bus reset is an externally inverted buff-

ered version of this output and the PCI bus reset is

an externally buffered version of this output.

XTALI

14.3MHz Crystal Input

XTALO

14.3MHz Crystal Output.

These pins are

the 14.318MHz crystalinput; This clock isused as

the reference clock for the internal frequency syn-

thesizer to generate the HCLK, CLK24M,

GCLK2X and DCLK clocks.

A 14.318 MHz Series Cut Quartz Crystal should

be connected between these two pins. Balance

capacitors of 15 pF should also be added. In the

event ofan external oscillatorproviding the master

clock signal to the STPC Consumer device, the

TTL signal should be provided on XTALO.

HCLK

Host Clock.

This is the host 1X clock. Its

frequency can vary from 25 to 75 MHz. All host

transactions and PCI transactions are synchro-

nized to this clock. The DRAM controller to exe-

cute the host transactions is also driven by this

clock. In normal mode, this output clock is gener-

ated by the internal pll.

GCLK2X

80MHz Graphics Clock.

This is the

Graphics 2X clock, which drives the graphics en-

gine and the DRAM controller to execute the

graphics and display cycles.

Normally GCLK2X is generated by the internal fre-

quency synthesizer, and this pin is an output. By

setting a bit in Strap Register 2, this pin can be

made an input so that an external clock can re-

place the internal frequency synthesizer.

PCI_CLKI

33MHz PCI Input Clock

This signal is the PCI bus clock input and should

be driven from the PCI_CLKO pin.

PCI_CLKO

33MHz PCI Output Clock.

This is the

master PCI bus clock output.

DCLK

135MHz Dot Clock.

This is the dot clock,

which drivesgraphics display cycles.Its frequency

can go from 8MHz (using internal PLL) up to 135

MHz, and it is required to have a worst case duty

cycle of 60-40.

This signal is either driven by the internal pll (VGA)

or an external 27MHz oscillator (when the com-

posite video output is enabled). The direction can

be controlled by a strap option or an internal regis-

ter bit.

ISA_CLK

ISA Clock Output (also Multiplexer Se-

lect Line For IPC).

This pin produces the Clock

signal for the ISA bus. It is also used with

ISA_CLK2X asthe multiplexorcontrol lines for the

Interrupt Controller Interrupt input lines. This is a

divided down version of either the PCICLK or

OSC14M.

ISA_CLKX2

ISA Clock Output (also Multiplexer

Select Line For IPC).

This pin produces a signal

that is twice the frequency of the ISA bus Clock

signal. It is also used with ISA_CLK as the multi-

plexor control lines for the Interrupt Controller in-

put lines.

DEV_CLK

24MHz Peripheral Clock Output.

This

24MHZ signal is provided as a convenience for

the system integration of a Floppy Disk driver

function in an external chip.

OSC14M

ISA bus synchronisation clock Output.

This is the buffered 14.318 Mhz clock to the ISA

bus.

2.2.2 MEMORY INTERFACE

MA[11:0]

Memory Address Output.

These 12 mul-

tiplexed memory address pins support external

DRAM with up to 4K refresh. These include all

16M x N and some 4M x N DRAM modules. The

address signals must be externally buffered to

support more than 16 DRAM chips. The timing of

these signals can be adjusted by software to

match the timings of most DRAM modules.

PIN DESCRIPTION

15/51

Issue 1.2

MD[63:0]

Memory Data I/O.

This is the 64-bit

memory data bus. If only half of a bank is populat-

ed, MD63-32 is pulled high, data is on MD31-0.

MD[40-0] are read by the device strap option reg-

isters during rising edge of SYSRSTI.

RAS#[3:0]

Row Address Strobe Output.

There

are 4 active low row address strobe outputs, one

for each bank of the memory. Each bank contains

4 or 8-Bytes of data. The memory controllerallows

half of a bank (4-bytes) to be populated to enable

memory upgrade at finer granularity.

The RAS# signals drive the SIMMs directly with-

out any external buffering. These pins are always

outputs, but they can also simultaneously be in-

puts, toallow the memory controller to monitor the

value of the RAS# signals at the pins.

CAS#[7:0]

Column Address Strobe Output.

There

are 8 active low column address strobe outputs,

one each for each byte of the memory.

The CAS# signals drive the SIMMs either directly

or through external buffers.

These pins are always outputs, but they can also

simultaneously be inputs, to allow the memory

controller to monitor the value of the CAS# signals

at the pins.

MWE#

Write Enable Output.

Write enable speci-

fies whether the memory access is a read (MWE#

= H) or a write (MWE# = L). This single write ena-

ble controls all the DRAM. It can be externally

buffered to boost the maximum number of loads

(DRAM chips) supported.

The MWE# signals drive the SIMMs directly with-

out any external buffering.

2.2.3 VIDEO INTERFACE

VCLK

Pixel Clock Input.

VIN[7:0]

YUV Video DataInput CCIR 601 or 656.

Time multiplexed 4:2:2 luminance and chromi-

nance data as defined in ITU-R Rec601-2 and

Rec656 (except for TTL input levels). This bus in-

terfaces with an MPEG video decoder output port

and typically carries a stream of Cb,Y,Cr,Y digital

video at VCLK frequency, clocked on the rising

edge (by default) of VCLK. A 54-Mbit/s ‘double’

Cb, Y,Cr, Y input multiplex issupported for double

encoding application (rising and falling edge of

CKREF are operating).

2.2.4 TV OUTPUT

RED_TV / C_TV

Analog video outputs synchro-

nized withCVBS.

This output is current-driven and

must be connected to analog ground over a load

resistor (RLOAD). Following the load resistor, a

simple analog low pass filter is recommended. In

S-VHS mode, this is the Chrominance Output.

GREEN_TV / Y_TV

Analog video outputs syn-

chronized with CVBS.

This output is current-driv-

en and must be connected to analog ground over

a load resistor (RLOAD). Following the load resis-

tor, a simple analog low pass filter is recommend-

ed. In S-VHS mode, this is the Luminance Output.

BLUE_TV / CVBS

Analog video outputs synchro-

nized withCVBS.

This outputis current-driven and

must be connected to analog ground over a load

resistor (RLOAD). Following the load resistor, a

simple analog low pass filter is recommended. In

S-VHS mode, this is a second composite output.

VCS

Line synchronisation Output.

This pin is an

input in ODDEV+HSYNC or VSYNC + HSYNC or

VSYNC slave modes and an output in all other

modes (master/slave)

The signal is synchronous to rising edge of CK-

REF. The default polarity uses a negative pulse

ODD_EVEN

Frame Synchronisation Ourput.

This

pin supports the Frame synchronisation signal. It

is an input in slave modes, except when sync is

extracted from YCrCb data, and an output in mas-

ter mode and when sync is extracted from YCrCb

data

The signal is synchronous to rising edge of DCLK.

The default polarity for this pin is:

- odd (not-top) field : LOW level

- even (bottom) field : HIGH level

IREF1_TV

Ref. current

for CVBS 10-bit DAC.

VREF1_TV

Ref. voltage

for CVBS 10-bit DAC.

IREF2_TV

Reference current

for RGB 9-bit DAC.

VREF2_TV

Reference voltage

forRGB 9-bit DAC.

VSSA_TV

Analog V

for DAC

VDDA_TV

Analog V

for DAC

CVBS

Analog videocomposite output (luminance/

chrominance).

CVBS is current-driven and must

be connected to analog ground over a load resis-

tor (RLOAD). Following the load resistor, a simple

analog low pass filter is recommended.

2.2.5 PCI INTERFACE

AD[31:0]

PCI Address/Data.

This is the 32-bit

multiplexed address and data bus of the PCI. This

bus is driven by the master during the address

phase and data phase of write transactions. It is

PIN DESCRIPTION

16/51 Issue 1.2

driven by the target during data phase of read

transactions.

CBE#[3:0]

Bus Commands/Byte Enables.

These

are the multiplexed command and byte enable

signals of the PCI bus. During the address phase

they define the command and during the data

phase they carry the byte enable information.

These pins are inputs when a PCI master other

than the STPC Consumer owns the bus and out-

puts when the STPC Consumer owns the bus.

FRAME#

Cycle Frame.

This is the frame signal of

the PCIbus. Itis aninput when aPCI master owns

the bus and is an output when STPC Consumer

owns the PCI bus.

TRDY#

Target Ready.

This is the target ready sig-

nal of the PCI bus. It is driven as an output when

the STPC Consumer is the target of the current

bus transaction. It is used as an input when STPC

Consumer initiates a cycle on the PCI bus.

IRDY#

Initiator Ready.

This is the initiator ready

signal of the PCI bus. It is used as an output when

the STPC Consumer initiates a bus cycle on the

PCI bus. It is used as an input during the PCI cy-

cles targeted to the STPC Consumer to determine

when the current PCI master is ready to complete

the current transaction.

STOP#

Stop Transaction.

Stop is used to imple-

ment the disconnect, retry and abort protocol of

the PCI bus. It is used as an input for the bus cy-

cles initiated by the STPC Consumer and is used

as an output when a PCI master cycle is targeted

to the STPC Consumer.

DEVSEL#

I/O Device Select.

This signal is used

as an input when the STPC Consumer initiates a

bus cycle on the PCI bus to determine if a PCI

slave device has decoded itself to be the target of

the current transaction. It is asserted as an output

either when the STPC Consumer is the target of

the current PCI transaction or when no other de-

vice asserts DEVSEL# prior to the subtractive de-

code phase of the current PCI transaction.

PAR

Parity Signal Transactions.

This is the parity

signal of the PCI bus. This signal is used to guar-

antee even parity across AD[31:0], CBE#[3:0],

and PAR. This signal is driven by the master dur-

ing the address phase and data phase of write

transactions. It is driven by the target during data

phase of read transactions. (Its assertion is identi-

cal to that of theAD busdelayed byone PCI clock

cycle)

SERR#

System Error.

This is the system error sig-

nal of the PCI bus. It may, if enabled, be asserted

for one PCI clock cycle if target aborts a STPC

Consumer initiated PCI transaction. Its assertion

by either the STPC Consumer or by another PCI

bus agent will trigger the assertion of NMI to the

host CPU. This is an open drain output.

LOCK#

PCI Lock.

This is the lock signalof the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.

PCIREQ#[2:0]

PCI Request.

This pin are the

three external PCI master requestpins. They indi-

cates to the PCI arbiter that the external agents

desire use of the bus.

PCIGNT#[2:0]

PCI Grant.

These pins indicate that

the PCI bus has been granted to the master re-

questing it on its PCIREQ#.

2.2.6 ISA/IDE COMBINED ADDRESS/DATA

LA[23]/SCS3#

Unlatched Address (ISA)/Second-

ary Chip Select (IDE).

This pin has two functions,

depending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 23 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high secondary slave IDE chip select

signal. This signal is to be externally NANDed with

the ISAOE#signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

PIN DESCRIPTION

17/51

Issue 1.2

LA[22]/SCS1#

Unlatched Address (ISA)/Second-

ary Chip Select (IDE)

This pin has two functions, depending on whether

the ISA bus is active or the IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 22 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high secondary slave IDE chip select

signal. This signal is to be externally ANDed with

the ISAOE#signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

LA[21]/PCS3#

Unlatched Address (ISA)/Primary

Chip Select (IDE).

This pin has two functions, de-

pending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 21 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA-

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high primary slave IDE chip select sig-

nal. This signal is to be externally NANDed with

the ISAOE#signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

LA[20]/PCS1#

Unlatched Address (ISA)/Primary

Chip Select (IDE).

This pin has two functions, de-

pending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 20 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high primary slave IDE chip select sig-

nal. This signal is to be externally NANDed with

the ISAOE#signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

LA[19:17]/DA[2:0]

Unlatched Address (ISA)/Ad-

dress (IDE).

These pins are multi-function pins.

They are used as the ISA bus unlatched address

bits [19:17] for ISA bus or the three address bits

for the IDE bus devices.

When used by the ISA bus, these pins are ISA

Bus unlatched address bits 19-17 on 16-bit devic-

es. When ISA bus is accessed by any cycle initiat-

ed from the PCI bus, these pins are in output

mode. When an ISA bus master owns the bus,

these pins are tristated.

For IDE devices, these signals are used as the

DA[2:0] and are connected to DA[2:0] of IDE de-

vices directly or through a buffer. If the toggling of

signals are to be masked during ISA bus cycles,

they can be externally ORed before being con-

nected to the IDE devices.

SA[19:8]/DD[11:0]

Unlatched Address (ISA)/Data

Bus (IDE).

These aremultifunction pins. When the

ISA bus is active, they are used as the ISA bus

system address bits 19-8. When the IDE bus isac-

tive, they serve as IDE signals DD[11:0].

These pins are used as an input when an ISA bus

master owns the bus and are outputs at all other

times.

IDE devices areconnected to SA[19:8] directlyand

ISA bus is connected to these pins through two

LS245 transceivers. The OE of the transceivers

are connected toISAOE#and DIR is connected to

MASTER#. A bus signals of the transceivers are

connected to CPC and IDE DDbus and B bus sig-

nals are connected to ISA SA bus.

DD[15:12]

Databus (IDE).

The high 4 bits of the

IDE databus are combined with several of the X-

bus lines. Refer to the following section for X-bus

pins for further information.

SA[7:0]

ISA Bus address bits [7:0].

These are the

8 low bits of the system address bus of ISA on 8-

bit slot. These pins are used as an input when an

ISA bus master owns the bus and are outputs at

all other times.

SD[15:0]

I/O Data Bus (ISA).

These pins are the

external databus to the ISA bus.

PIN DESCRIPTION

18/51 Issue 1.2

2.2.7 ISA/IDE COMBINED CONTROL

IOCHRDY/DIORDY

Channel Ready (ISA)/Busy/

Ready (IDE).

This is a multi-function pin. When

the ISA bus is active, this pin is IOCHRDY. When

the IDE bus is active, this serves as IDE signal DI-

ORDY.

IOCHRDY is the IO channel ready signal of the

ISA bus and is driven as an output in response to

an ISA mastercycle targeted to the host bus or an

internal register of the STPC Consumer. The

STPC Consumer monitors this signal as an input

when performing an ISA cycle on behalf of the

host CPU, DMA master or refresh.

ISA masters which do not monitor IOCHRDY are

not guaranteed to work with the STPC Consumer

since the access to the system memory can be

considerably delayed due to CRT refresh or a

write back cycle.

2.2.8 ISA CONTROL

ALE

Address Latch Enable.

This is the address

latch enable output of the ISA bus and is asserted

by the STPC Consumer to indicate that LA23-17,

SA19-0, AEN and SBHE# signals are valid. The

ALE is driven high during refresh, DMA master or

an ISA master cycles by the STPC Consumer.

ALE is driven low after reset.

BHE#

System Bus High Enable.

This signal, when

asserted, indicates that a data byte is being trans-

ferred on SD15-8 lines. It is used asan input when

an ISA master owns thebus andis an output at all

other times.

MEMR#

Memory Read.

This is the memory read

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

The MEMR# signal is active during refresh.

MEMW#

Memory Write.

This is the memory write

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

SMEMR#

System Memory Read.

The STPC Con-

sumer generates SMEMR# signal of the ISA bus

only when the address is below one megabyte or

the cycle is a refresh cycle.

SMEMW#

System Memory Write.

The STPC Con-

sumer generates SMEMW# signal of the ISA bus

only when the address is below one megabyte.

This signal is multiplexed with COL_CMP on the

VGA Interface. The signal is selected by setting

Strap Option MD[0] as described in Section 3.

IOR#

I/O Read.

This is the IO read command sig-

nal ofthe ISA bus. Itis an input when anISA mas-

ter owns the bus and is an output at all other

times.

IOW#

I/O Write.

This is theIO write commandsig-

nal ofthe ISA bus. Itis an input when anISA mas-

ter owns the bus and is an output at all other

times.

MASTER#

Add On Card Owns Bus.

This signal is

active when an ISA device has been granted bus

ownership.

MCS16#

Memory Chip Select16.

This is the de-

code of LA23-17 address pins of the ISA address

bus without any qualification of the command sig-

nal lines. MCS16# is always an input. The STPC

Consumer ignores this signal during IO and re-

fresh cycles.

IOCS16#

IO Chip Select16.

This signal is the de-

code of SA15-0 address pins of the ISA address

bus without any qualification of the command sig-

nals. The STPC Consumer does not drive

IOCS16# (similar to PC-AT design). An ISA mas-

ter accessto aninternal register of the STPC Con-

sumer is executed as an extended 8-bit IO cycle.

REF#

Refresh Cycle.

This is the refresh command

signal of the ISA bus. It is driven as an output

when the STPC Consumer performs a refresh cy-

cle on the ISA bus. It is used as an input when an

ISA master owns the bus and is used to trigger a

refresh cycle.

The STPC Consumer performs a pseudo hidden

refresh. It requests the host bus for two host

clocks to drive the refresh address and capture it

in external buffers. The host bus is then relin-

quished while the refresh cycle continues on the

ISA bus.

AEN

Address Enable.

Address Enable is enabled

when the DMA controller is the bus owner to indi-

cate that a DMA transfer will occur. The enabling

of the signal indicates to IO devices to ignore the

IOR#/IOW# signal during DMA transfers.

ZWS#

Zero Wait State.

This signal, when assert-

ed by addressed device, indicates that current cy-

cle can be shortened.

IOCHCK#

IO Channel Check.

IO Channel Check

is enabled by any ISA device to signal an error

condition that can not be corrected. NMI signal be-

comes active upon seeing IOCHCK# active if the

corresponding bit in Port B is enabled.

PIN DESCRIPTION

19/51

Issue 1.2

ISAOE#

Bidirectional OE Control.

This signal con-

trols the OE signal of the external transceiver that

connects the IDE DD bus and ISA SA bus.

GPIOCS#

I/O General Purpose Chip Select 1.

This output signal is used by the external latch on

ISA bus to latch the data on the SD[7:0] bus. The

latch can be use by PMU unit to control the exter-

nal peripheral devices to powerdown or any other

desired function.

This pin is also serves as a strap input during re-

set.

2.2.9 IDE CONTROL

PIRQ

Primary Interrupt Request.

Interrupt request

from primary IDE channel.

SIRQ

Secondary Interrupt Request.

Interrupt re-

quest from secondary IDE channel.

PDRQ

Primary DMA Request.

DMA request from

primary IDE channel.

SDRQ

Secondary DMA Request.

DMA request

from secondary IDE channel.

PDACK#

Primary DMA Acknowledge.

DMA ack-

noledge to primary IDE channel.

SDACK#

Secondary DMA Acknowledge.

DMA

acknoledge to secondary IDE channel.

PIOR#

Primary I/O Read.

Primary channel read.

Active low output.

PIOW#

Primary I/O Write

. Primary channel write.

Active low output.

SIOR#

Secondary I/O Read

Secondary channel

read. Active low output.

SIOW#

Secondary I/O Write

Secondary channel

write. Active low output.

2.2.10 IPC

IRQ_MUX[3:0]

Multiplexed Interrupt Request.

These are the ISA bus interrupt signals. They are

to be encoded before connection to the STPC

Consumer using ISACLK and ISACLKX2 as the

input selection strobes.

Note that IRQ8B, which by convention is connect-

ed to the RTC, is inverted before being sent to the

interrupt controller, so thatit may beconnected di-

rectly to the IRQ pin of the RTC.

PCI_INT[3:0]

PCI Interrupt Request.

These are

the PCI bus interrupt signals. They are to be en-

coded before connection to the STPC Consumer

using ISACLK and ISACLKX2 as the input selec-

tion strobes.

DREQ_MUX[1:0]

ISA Bus Multiplexed DMA Re-

quest.

These are the ISA bus DMA request sig-

nals. Theyare to be encoded before connection to

the STPC Consumer using ISACLK and

ISACLKX2 as the input selection strobes.

DACK_ENC[2:0]

DMA Acknowledge.

These are

the ISA bus DMA acknowledge signals. They are

encoded by the STPC Consumer before output

and should be decoded externally using ISACLK

and ISACLKX2 as the control strobes.

ISA Terminal Count.

This is the terminal count

output of the DMA controller and is connected to

the TCline of the ISA bus. Itis asserted during the

last DMA transfer, when the byte count expires.

SPKRD

Speaker Drive.

This the output to the

speaker and is AND of the counter 2 output with

bit 1 of Port 61, and drives an external speaker

driver. This output should be connected to 7407

type high voltage driver.

2.2.11 X-Bus Interface pins / IDE Data

RMRTCCS# / DD[15]

ROM/Real Time clock chip

select.

This pin is a multi-function pin. When

ISAOE# is active, this signal is used as RM-

RTCCS#. This signal is asserted if a ROM access

is decoded during a memory cycle. It should be

combined with MEMR# or MEMW# signals to

properly access the ROM. During a IO cycle, this

signal is asserted if access to the Real Time Clock

(RTC) is decoded. It should be combined with IOR

or IOW# signals to properly access the real time

clock.

When ISAOE# is inactive, this signal is used as

IDE DD[15] signal.

This signal must be ORed externally with ISAOE#

and is then connected to ROM and RTC. An

LS244 or equivalent function canbe used if OE# is

connected to ISAOE# and the output is provided

with a weak pull-up resistor.

KBCS# / DD[14]

Keyboard Chip Select.

This pin

is a multi-function pin. When ISAOE# is active,

this signal isused as KBCS#. Thissignal isassert-

ed if a keyboard access is decoded during a I/O

cycle.

When ISAOE# is inactive, this signal is used as

IDE DD[14] signal.

This signal must be ORed externally with ISAOE#

and is then connected to keyboard. An LS244 or

equivalent function can be used if OE# is connect-

PIN DESCRIPTION

20/51 Issue 1.2

ed to ISAOE# and the output is provided with a

weak pull-up resistor.

RTCRW# / DD[13]

Real Time Clock RW.

This pin

is a multi-function pin. When ISAOE# is active,

this signal is used as RTCRW#. This signal is as-

serted for any I/O write to port 71H.

When ISAOE# is inactive, this signal is used as

IDE DD[13] signal.

This signal must be ORed externally with ISAOE#

and then connected to the RTC. An LS244 or

equivalent function can be used if OE is connect-

ed to ISAOE# and the output is provided with a

weak pull-up resistor.

RTCDS# /DD[12]

Real Time Clock DS

. This pin is

a multi-function pin. When ISAOE# is active, this

signal is used as RTCDS. This signal is asserted

for any I/O read to port 71H.

When ISAOE# is inactive, this signal is used as

IDE DD[12] signal.

This signal must be ORed externally with ISAOE#

and is then connected to RTC. An LS244 or equiv-

alent function can be used if OE# is connected to

ISAOE# and the output is provided with a weak

pull-up resistor.

RTCAS#

Real timeclock addressstrobe.

This sig-

nal is asserted for any I/O write to port 70H.

2.2.12 Monitor Interface

RED, GREEN, BLUE

RGB Video Outputs.

These

are the 3 analog color outputs from the RAMDACs

VSYNC

Vertical Synchronisation Pulse.

This is

the vertical synchronization signal from the VGA

controller.

HSYNC

Horizontal Synchronisation Pulse.

This is

the horizontal synchronization signal from the

VGA controller.

VREF_DAC

DAC Voltage reference.

An external

voltage reference is connected to this pin to bias

the DAC.

RSET

Resistor Current Set.

This is reference cur-

rent input to the RAMDAC is used to set the full-

scale output of the RAMDAC.

COMP

Compensation.

This is the RAMDAC com-

pensation pin. Normally, an external capacitor

(typically 10nF) is connected between this pin and

VDD to damp oscillations.

DDC[1:0]

Direct Data Channel Serial Link.

These

bidirectional pins are connected to CRTC register

3Fh to implementDDC capabilities. They conform

to I2C electrical specifications, they have open-

collector output drivers which are internally con-

nected to VDD through pull-up resistors.

They can instead be used for accessing I C devic-

es on board. DDC1 and DDC0 correspond toSCL

and SDA respectively.

COL_CMP

Color Compare Output

. Allows access

to the video signal which flags when there is a

color compare hit. This signal is multiplexed with

SMEMEW# onthe ISA Bus. The signal is selected

by setting Strap Option MD[0] asdescribed in Sec-

tion3.

2.2.13 MISCELLANEOUS

SCAN_ENABLE

Reserved

. The pins are re-

served for Test and Miscellaneous functions)

PIN DESCRIPTION

21/51

Issue 1.2

Table 2-3. Pinout.

Pin # Pin name

AF3 SYSRSTI

A3 XTALI

C4 XTALO

G23 HCLK

F25 DEV_CLK

AF15 GCLK2X

AF9 DCLK

AD15 MA[0]

AF16 MA[1]

AC15 MA[2]

AE17 MA[3]

AD16 MA[4]

AF17 MA[5]

AC17 MA[6]

AE18 MA[7]

AD17 MA[8]

AF18 MA[9]

AE19 MA[10]

AF19 MA[11]

AD18 RAS#[0]

AE20 RAS#[1]

AC19 RAS#[2]

AF20 RAS#[3]

AE21 CAS#[0]

AC20 CAS#[1]

AF21 CAS#[2]

AD20 CAS#[3]

AE22 CAS#[4]

AF22 CAS#[5]

AD21 CAS#[6]

AE23 CAS#[7]

AC22 MWE#

AF23 MD[0]

AE24 MD[1]

AF24 MD[2]

AD25 MD[3]

AC25 MD[4]

AC26 MD[5]

AB24 MD[6]

AA25 MD[7]

AA24 MD[8]

Y25 MD[9]

Y24 MD[10]

V23 MD[11]

W24 MD[12]

V26 MD[13]

V24 MD[14]

U23 MD[15]

U24 MD[16]

R26 MD[17]

P25 MD[18]

P26 MD[19]

N25 MD[20]

N26 MD[21]

M25 MD[22]

M26 MD[23]

M24 MD[24]

M23 MD[25]

L24 MD[26]

J25 MD[27]

J26 MD[28]

H26 MD[29]

G25 MD[30]

G26 MD[31]

AD22 MD[32]

AD23 MD[33]

AE26 MD[34]

AD26 MD[35]

AC24 MD[36]

AB25 MD[37]

AB26 MD[38]

Y23 MD[39]

AA26 MD[40]

Y26 MD[41]

W25 MD[42]

W26 MD[43]

V25 MD[44]

U25 MD[45]

U26 MD[46]

T25 MD[47]

R25 MD[48]

T24 MD[49]

R23 MD[50]

R24 MD[51]

N23 MD[52]

P24 MD[53]

N24 MD[54]

L25 MD[55]

L26 MD[56]

K25 MD[57]

K26 MD[58]

K24 MD[59]

H25 MD[60]

J24 MD[61]

H23 MD[62]

H24 MD[63]

F24 PCI_CLKI

Pin # Pin name D25 PCI_CLKO

A20 AD[0]

C20 AD[1]

B19 AD[2]

A19 AD[3]

C19 AD[4]

B18 AD[5]

A18 AD[6]

B17 AD[7]

C18 AD[8]

A17 AD[9]

D17 AD[10]

B16 AD[11]

C17 AD[12]

B15 AD[13]

A15 AD[14]

C16 AD[15]

D15 AD[16]

A14 AD[17]

C15 AD[18]

B13 AD[19]

D13 AD[20]

A13 AD[21]

C14 AD[22]

C13 AD[23]

A12 AD[24]

B11 AD[25]

C12 AD[26]

A11 AD[27]

D12 AD[28]

B10 AD[29]

C11 AD[30]

A10 AD[31]

D10 CBE[0]

C10 CBE[1]

A9 CBE[2]

B8 CBE[3]

A8 FRAME#

B7 TRDY#

D8 IRDY#

A7 STOP#

C8 DEVSEL#

B6 PAR

D7 SERR#

A6 LOCK#

C21 PCI_REQ#[0]

A21 PCI_REQ#[1]

B20 PCI_REQ#[2]

C22 PCI_GNT#[0]

Pin # Pin name

PIN DESCRIPTION

22/51 Issue 1.2

B21 PCI_GNT#[1]

D20 PCI_GNT#[2]

A5 PCI_INT[0]

C6 PCI_INT[1]

B4 PCI_INT[2]

D5 PCI_INT[3]

F2 LA[17]/DA[0]

G4 LA[18]/DA[1]

F3 LA[19]/DA[2]

F1 LA[20]/PCS1#

G2 LA[21]/PCS3#

G3 LA[22]/SCS1#

H2 LA[23]/SCS3#

J4 SA[0]

H1 SA[1]

H3 SA[2]

J2 SA[3]

J1 SA[4]

K2 SA[5]

J3 SA[6]

K1 SA[7]

K4 SA[8]/DD[0]

L2 SA[9]/DD[1]

K3 SA[10]/DD[2]

L1 SA[11]/DD[3]

M2 SA[12] / DD[4]

M1 SA[13] / DD[5]

L3 SA[14] / DD[6]

N2 SA[15] / DD[7]

M4 SA[16] / DD[8]

N1 SA[17] / DD[9]

M3 SA[18] / DD[10]

P4 SA[19] / DD[11]

P3 RTCDS / DD[12]

R2 RTCRW# / DD[13]

N3 KBCS# / DD[14]

P1 RMRTCCS# / DD[15]

R1 SD[0]

T2 SD[1]

R3 SD[2]

T1 SD[3]

R4 SD[4]

U2 SD[5]

T3 SD[6]

U1 SD[7]

U4 SD[8]

V2 SD[9]

U3 SD[10]

Pin # Pin name V1 SD[11]

W2 SD[12]

W1 SD[13]

V3 SD[14]

Y2 SD[15]

Y1 IOCHRDY

AE4 SYSRSTO#

AD4 ISA_CLK

AE5 ISA_CLK2X

AF8 OSC14M

W3 ALE

AC9 ZWS#

AA2 BHE#

Y4 MEMR#

AA1 MEMW#

Y3 SMEMR#

AB2 SMEMW#/COL_CMP

AA3 IOR#

AC2 IOW#

AB4 MASTER#

AC1 MCS16#

AB3 IOCS16#

AD2 REF#

AC3 AEN

AD1 IOCHCK#

AF2 ISAOE#

A4 RTCAS#

AE3 GPIOCS#

B1 PIRQ

C2 SIRQ

C1 PDRQ

D2 SDRQ

D3 PDACK#

D1 SDACK#

E2 PIOR#

E4 PIOW#

E3 SIOR#

E1 SIOW#

E23 IRQ_MUX[0]

D26 IRQ_MUX[1]

E24 IRQ_MUX[2]

C25 IRQ_MUX[3]

A24 DREQ_MUX[0]

B23 DREQ_MUX[1]

C23 DACK_ENC[0]

Pin # Pin name A23 DACK_ENC[1]

B22 DACK_ENC[2]

D22 TC

C5 SPKRD

AE6 RED

AD6 GREEN

AF6 BLUE

AD5 VSYNC

AC5 HSYNC

AD7 VREF_DAC

AE8 RSET

AF5 COMP

C7 SDA / DDC[0]

B5 SCL / DDC[1]

AC12 VCLK

AE13 VIN[0]

AD14 VIN[1]

AD12 VIN[2]

AE14 VIN[3]

AC14 VIN[4]

AF14 VIN[5]

AD13 VIN[6]

AE15 VIN[7]

AF10 RED_TV

AC10 GREEN_TV

AF11 BLUE_TV

AE10 VCS

AD9 ODD_EVEN

AD11 CVBS

AD8 IREF1_TV

AE9 VREF1_TV

AE11 IREF2_TV

AD10 VREF2_TV

B3 SCAN_ENABLE

AF12 VDDA_TV

AC7 VDD_DAC1

AF4 VDD_DAC2

AD19 VDD_GCLK_PLL

AF13 VDD_DCLK_PLL

F26 VDD_HCLK_PLL

G24 VDD_DEVCLK_PLL

A16 VDD5

B12 VDD5

B9 VDD5

Pin # Pin name

PIN DESCRIPTION

23/51

Issue 1.2

D18 VDD5

A22 VDD

B14 VDD

C9 VDD

D6 VDD

D11 VDD

D16 VDD

D21 VDD

F4 VDD

F23 VDD

G1 VDD

K23 VDD

L4 VDD

L23 VDD

P2 VDD

T4 VDD

T23 VDD

T26 VDD

W4 VDD

AA4 VDD

AA23 VDD

AB1 VDD

AB23 VDD

AC6 VDD

AC11 VDD

AC16 VDD

AC21 VDD

AE12 VSSA_TV

AE7 VSS_DAC1

AF7 VSS_DAC2

E25 VSS_DLL

E26 VSS_DLL

A1:2 VSS

A26 VSS

B2 VSS

B25:26 VSS

C3 VSS

C24 VSS

D4 VSS

D9 VSS

D14 VSS

D19 VSS

D23 VSS

H4 VSS

J23 VSS

L11:16 VSS

M11:16 VSS

N4 VSS

Pin # Pin name N11:16 VSS

P11:16 VSS

P23 VSS

R11:16 VSS

T11:16 VSS

V4 VSS

W23 VSS

AC4 VSS

AC8 VSS

AC13 VSS

AC18 VSS

AC23 VSS

AD3 VSS

AD24 VSS

AE1:2 VSS

AE16 VSS

AE25 VSS

AF1 VSS

AF25 VSS

AF26 VSS

C26 RESERVED

D24 RESERVED

B24 RESERVED

A25 RESERVED

Pin # Pin name

PIN DESCRIPTION

24/51 Issue 1.2

Update History for Pin Description chapter

25/51

Issue 1.2

2.4 Update History for Pin Description chapter

The following changes have been made to the Pin Description Chapter on 08/02/2000

The following changes have been made to the Pin Description Chapter on 13/01/2000

Section Change Text

2.2 Added Color Compare Signal

Section Change Text

2.2 Added “to a minimum of 8MHz”

Update History for Pin Description chapter

26/51 Issue 1.2

STRAP OPTION

27/51

Issue 1.2

3. STRAP OPTION

This chapter defines the STPC Consumer Strap

Options and their location

Memory

Data

Lines Note Refer to Designation Location Actual

Settings Set to ’0’ Set to ’1’

MD0 1 Index 4A, Bit 0 User defined COLOR_KEY SMEMW#

MD1 - Reserved - - - -

MD2 2 DRAM Bank 1 Speed Index 4A, bit 2 User defined 70 ns 60 ns

MD3 2 Speed Index 4A, bit 3 Pull up

MD4 2 Type Index 4A,bit 4 User defined EDO FPM

MD5 2 DRAM Bank 0 Speed Index 4A,bit 5 User defined 70 ns 60 ns

MD6 2 Speed Index 4A,bit 6 Pull up - -

MD7 2 Type Index 4A, bit 7 User defined EDO FPM

MD8 2 - Reserved Index4B,bit0 Pull up - -

MD9 2 - Reserved Index4B,bit1 - - -

MD10 2 DRAM Bank 3 Speed Index 4B,bit 2 User defined 70 ns 60 ns

MD11 2 Speed Index 4B,bit 3 Pull up - -

MD12 2 Type Index 4B,bit 4 User defined EDO FPM

MD13 2 DRAM Bank 2 Speed Index 4B,bit 5 User defined 70 ns 60 ns

MD14 2 Speed Index 4B, bit 6 Pull up - -

MD15 2 Type Index 4B,bit 7 User defined EDO FPM

MD16 - Reserved Index 4C,bit 0 Pull up - -

MD17 PCI Clock PCI_CLKO Divisor Index 4C,bit 1 User defined HCLK / 2 HCLK / 3

MD18 - Reserved Index 4C,bit 2 Pull up - -

MD19 - Reserved Index 4C,bit 3 Pull up - -

MD20 - Reserved Index 4C, bit4 Pull up - -

MD21 - Reserved Index 5F, bit 0 Pull up - -

MD22 - Reserved Index 5F, bit 1 Pull up - -

MD23 - Reserved Index 5F,bit 2 Pull up - -

MD24 HCLK HCLK PLL Speed Index 5F,bit 3 User defined 000 25 MHz

MD25 Index 5F,bit 4 User defined 001 33 MHz

MD26 Index 5F,bit 5 User defined 010 40 MHz

User defined 011 50 MHz

User defined 100 60 MHz

User defined 101 66 MHz

User defined 110 75 MHz

User defined 111 80 MHz

MD27 - Reserved - Pull down - -

MD28 - Reserved - Pull down - -

MD29 - Reserved - Pull down - -

MD30 - Reserved - Pull down - -

MD31 - Reserved - Pull down - -

MD32 - Reserved - Pull down - -

MD33 - Reserved - Pull down - -

MD34 - Reserved - Pull down - -

MD35 - Reserved - Pull down - -

MD36 - Reserved - Pull up - -

MD37 - Reserved - Pull up - -

STRAP OPTION

28/51 Issue 1.2

Note;

1) This Strap Option selects between two different

functional blocks, the first is the ISA (SMEMW#)

and the other is the VGA block (Color_Key).

2) Setting of Strap Options MD [2:15] have no ef-

fect on the DRAM Controller but are purely meant

for software issues. i.e. Readable in a register.

3.1 STRAP REGISTER DESCRIPTION

3.1.1 STRAP REGISTER 0 INDEX 4AH

(STRAP0)

Bits 7-0 of this register reflect the status of pins

MD[7:0] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Note that the SIMM speed and type information

read here is meant only for the software and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[7:0] pins after reset.

3.1.2 STRAP REGISTER 1 INDEX 4BH

(STRAP1)

Bits 7-0 of this register reflect the status of pins

MD[15:8] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Note that the SIMM speed and type information

read here is meant only for thesoftware and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[15:8] pins after reset.

3.1.3 STRAP REGISTER 2 INDEX 4CH

(STRAP2)

Bits 4-0 of this register reflect the status of pins

MD[20:16] respectively. Bit 5 of this register reflect

the status of pin MD[23]. Bit 4 is writeable, writes

to other bits in this register have no effect.

They are use by the chip as follows:

Bit 4-2; Reserved

MD38 - Reserved - Pull up - -

MD39 - Reserved - Pull up - -

MD40 CPU CPU Mode User defined DX1 DX2

MD41 - Reserved - Pull down - -

MD42 - Reserved - Pull up - -

MD43 - Reserved - Pull down - -

Memory

Data

Lines Note Refer to Designation Location Actual

Settings Set to ’0’ Set to ’1’

Bit Sampled Description

Bit 7 SIMM 0 dram type

Bits 6-5 SIMM 0 speed

Bit 4 SIMM 1 dram type

Bits 3-2 SIMM 1 speed

Bits 1-0 Reserved

Bit Sampled Description

Bit 7 SIMM 2 dram type

Bits 6-5 SIMM 2 speed

Bit 4 SIMM 3 dram type

Bits 3-2 SIMM 3 speed

STRAP OPTION

29/51

Issue 1.2

Bit 1 This bit reflects the value sampled on

MD[17] pin and controls the PCI clock output as

follows:

0: PCI clock output = HCLK / 2

1: PCI clock output = HCLK / 3

Bit 0; Reserved

This register defaults to the values sampled on

MD[23] & MD[20:16] pins after reset.

3.1.4 HCLK PLL STRAP REGISTER 0 INDEX

5FH (HCLK_STRAP0)

Bits 5-0 of this register reflect the status of pins

MD[26:21] respectively. They are use by the chip

as follows:

Bits 5-3; These pins reflect the value sampled on

MD[26:24] pins respectively and control the Host

clock frequency synthesizer.

Bit 2-0; Reserved

This register defaults to the values sampled on

above pins after reset.

Strap Options [39:27] are reserved.

3.1.5 486 CLOCK PROGRAMMING (486_CLK)

The bit MD[40] is used to set the clock multiplica-

tion factor of the 486 core. With the MD[40] pin

pulled low the 486 will run in DX (x1) mode, while

with the MD[40] pin pulled high the 486 will run in

DX2 (x2) mode. The default value of the resistor

on this strap input should be a resister to ground

(DX mode).

Strap options MD[43:41] are reserved.

ELECTRICAL SPECIFICATIONS

30/51 Issue 1.2

4. ELECTRICAL SPECIFICATIONS

4.1 Introduction

The electrical specifications in this chapterare val-

id for the STPC Consumer.

4.2 Electrical Connections

4.2.1 Power/Ground Connections/Decoupling

Due to the high frequency of operation of the

STPC Consumer, it is necessary to install and test

this device using standard high frequency tech-

niques. The high clock frequencies used in the

STPC Consumer and its output buffer circuits can

cause transient power surges whenseveral output

buffers switch outputlevels simultaneously. These

effects can be minimized by filtering the DC power

leads with low-inductance decoupling capacitors,

using low impedance wiring, and by utilizing all of

the VSS and VDD pins.

4.2.2 Unused Input Pins

All inputs not used by the designer and not listed

in the table of pin connections in Chapter 3 should

be connected either to VDD or to VSS. Connect

active-high inputs to VDD through a20 kΩ(±10%)

pull-down resistor and active-low inputs to VSS

and connect active-low inputs to VCC through a

20 kΩ(±10%) pull-up resistor to prevent spurious

operation.

4.2.3 Reserved Designated Pins

Pins designated reserved should be left discon-

nected. Connecting a reserved pin to a pull-up re-

sistor, pull-down resistor, or an active signal could

cause unexpected results and possible circuit

malfunctions.

4.3 Absolute Maximum Ratings

The following table lists the absolute maximum

ratings for the STPC Consumer device. Stresses

beyond those listed under Table 4-1 limits may

cause permanent damage to the device. These

are stress ratings only and do not imply that oper-

ation under any conditions other thanthose spec-

ified in section ”Operating Conditions”.

Exposure to conditions beyond Table 4-1 may (1)

reduce device reliability and (2) result in prema-

ture failure even when there is no immediately ap-

parent sign offailure. Prolonged exposure to con-

ditions at or near the absolute maximum ratings

(Table 4-1) may also result in reduced useful life

and reliability.

Table 4-1. Absolute Maximum Ratings

Symbol Parameter Value Units

VDDx DC Supply Voltage -0.3, 4.0 V

VI,V

ODigital Input and Output Voltage -0.3, VDD + 0.3 V

TSTG Storage Temperature -40, +150 °C

TOPER Operating Temperature 0, +70 °C

PTOT Total Power Dissipation 4.8 W

ELECTRICAL SPECIFICATIONS

31/51

Issue 1.2

4.4 DC Characteristics

Notes:

1. MHz ratings refer to CPU clock frequency.

2. Not 100% tested.

4.5 AC Characteristics

Table 4-4 through Table 4-9 list the AC character-

istics including output delays, input setup require-

ments, input hold requirements and output float

delays. These measurements are based on the

measurement points identified in Figure 4-1 . The

rising clock edge reference level VREF , and other

reference levels are shown in Table 4-3 below for

the STPC Consumer.Input or output signals must

cross these levels during testing.

Figure 4-1 shows output delay(A and B) and input

setup and hold times (C and D). Input setup and

hold times (C and D) are specified minimums, de-

fining the smallest acceptable sampling window a

synchronous input signal must be stable for cor-

rect operation.

Note: Refer to Figure 4-1.

Table 4-2. DC Characteristics

Recommended Operating conditions : VDD = 3.3V ±0.3V, Tcase = 0 to 100°C unless otherwise specified

Symbol Parameter Test conditions Min Typ Max Unit

VDD Operating Voltage 3.0 3.3 3.6 V

PDD Supply Power VDD = 3.3V, HCLK = 66Mhz 3.2 3.9 W

HCLK Internal Clock (Note 1) 75 Mhz

VREF_D

AC DAC Voltage Reference 1.215 1.235 1.255 V

VOL Output Low Voltage ILoad =1.5 to 8mA depending of the pin 0.5 V

VOH Output High Voltage ILoad =-0.5 to -8mA depending of the pin 2.4 V

VIL Input Low Voltage Except XTALI -0.3 0.8 V

XTALI -0.3 0.9 V

VIH Input High Voltage Except XTALI 2.1 VDD+0.3 V

XTALI 2.35 VDD+0.3 V

ILK Input Leakage Current Input, I/O -5 5 µA

CIN Input Capacitance (Note 2) pF

COUT Output Capacitance (Note 2) pF

CCLK Clock Capacitance (Note 2) pF

Table 4-3. Drive Level and Measurement Points for Switching Characteristics

Symbol Value Units

VREF 1.5 V

VIHD 3.0 V

VILD 0.0 V

ELECTRICAL SPECIFICATIONS

32/51 Issue 1.2

Figure 4-1 DriveLevel and Measurement Points for Switching Characteristics

Figure 4-2 CLK Timing Measurement Points

Note; The above timings are generic timings and are not specific to the interfaces defined below

CLK:

Ref

ILD

IHD

LEGEND: A - Maximum Output Delay Specification

B - Minimum Output Delay Specification

C - Minimum Input Setup Specification

D - Minimum Input Hold Specification

Ref

Valid

OUTPUTS:

INPUTS:

Output n Output n+1

Input

MAX

MIN

Ref

ILD

IHD

CLK

T5 T4T3

Ref

IL (MAX)

IH (MIN)

LEGEND: T1 - One Clock Cycle

T2 - Minimum Time at V

T3 - Minimum Time at V

T4 - Clock Fall Time

T5 - Clock Rise Time

NOTE; All sIgnals are sampled on the rising edge of the CLK.

ELECTRICAL SPECIFICATIONS

33/51

Issue 1.2

4.5.1 AC Timing parameters

Table 4-4. PCI Bus AC Timing

Name Parameter Min Max Unit

t1 PCI_CLKI to AD[31:0] valid 2 11 ns

t2 PCI_CLKI to FRAME# valid 2 11 ns

t3 PCI_CLKI to CBE#[3:0] valid 2 11 ns

t4 PCI_CLKI to PAR valid 2 11 ns

t5 PCI_CLKI to TRDY# valid 2 11 ns

T6 PCI_CLKI to IRDY# valid 2 11 ns

T7 PCI_CLKI to STOP# valid 2 11 ns

T8 PCI_CLKI to DEVSEL# valid 2 11 ns

T9 PCI_CLKI to PCI_GNT# valid 2 12 ns

t10 AD[31:0] bus setup to PCI_CLKI 7 ns

t11 AD[31:0] bus hold from PCI_CLKI 0 ns

t12 PCI_REQ#[2:0] setup to PCI_CLKI 7 ns

t13 PCI_REQ#[2:0] hold from PCI_CLKI 4 ns

t14 CBE#[3:0] setup to PCI_CLKI 7 ns

t15 CBE#[3:0] hold to PCI_CLKI 0 ns

t16 IRDY# setup to PCI_CLKI 7 ns

t17 IRDY# hold to PCI_CLKI 0 ns

t18 FRAME# setup to PCI_CLKI 7 ns

t19 FRAME# hold from PCI_CLKI 0 ns

Table 4-5. DRAM Bus AC Timing

Name Parameter Min Max Unit

t22 HCLK to RAS#[3:0] valid 19 ns

t23 HCLK to CAS#[7:0] bus valid 19 ns

t24 HCLK to MA[11:0] bus valid 19 ns

t25 HCLK to MWE# valid 17 ns

t26 HCLK to MD[63:0] bus valid 20 ns

t27 MD[63:0] Generic setup 13 ns

t28 GCLK2X to RAS#[3:0] valid 19 ns

t29 GCLK2X to CAS#[7:0] valid 19 ns

t30 GCLK2X to MA[11:0] bus valid 19 ns

t31 GCLK2X to MWE# valid 17 ns

t32 GCLK2X to MD[63:0] bus valid 20 ns

t33 MD[63:0] Generic hold 0 ns

Table 4-6. IDE Bus AC Timing

Name Parameter Min Max Unit

t20 DD[15:0] setup to PIOR#/SIOR#falling 15 ns

t21 DD[15:0} hold to PIOR#/SIOR# falling 0 ns

ELECTRICAL SPECIFICATIONS

34/51 Issue 1.2

Table 4-7. Video Input AC Timing

Name Parameter Min Max Unit

t35 VIN[7:0] setup to VCLK 5 ns

t36 VIN[7:0] hold from VCLK 4 ns

t37 VCLK to ODD_EVEN valid 15 ns

t38 VCLK to VCS valid 15 ns

t39 ODD_EVEN setup to VCLK 10 ns

t40 ODD_EVEN hold from VCLK 5 ns

t41 VCS setup to VCLK 10 ns

t42 VCS hold from VCLK 5 ns

Table 4-8. Graphics Adapter (VGA) AC Timing

Name Parameter Min Max Unit

t43 DCLK to VSYNC valid 30 ns

t44 DCLK to HSYNC valid 30 ns

Table 4-9. ISA Bus AC Timing

Name Parameter Min Max Unit

t45 XTALO to LA[23:17] bus active 60 ns

t46 XTALO to SA[19:0] bus active 60 ns

t47 XTALO to BHE# valid 62 ns

t48 XTALO to SD[15:0] bus active 35 ns

t49 PCI_CLKI to ISAOE# valid 28 ns

t50 XTALO to GPIOCS# valid 60 ns

t51 XTALO to ALE valid 62 ns

t52 XTALO to MEMW# valid 50 ns

t53 XTALO to MEMR# valid 50 ns

t54 XTALO to SMEMW# valid 50 ns

t55 XTALO to SMEMR# valid 50 ns

t56 XTALO to IOR# valid 50 ns

t57 XTALO to IOW# valid 50 ns

Update History for Electrical Specification chapter

35/51

Issue 1.2

4.10 Update History for Electrical Specification chapter

The following changes have been made to the Electrical Specification Chapter on the 07/02/2000.

The following changes have been made to the Electrical Specification Chapter on the 20/10/99.

The following changes have been made to the Electrical Specification Chapter on the 16/08/99.

Section Change Text

4.5 Revued Timings t35 - t42

Section Change Text

4.5 Revued Timings T1-10, T12, T14, T16, T18, T26, T32, T35, T39-42 &T54

Section Change Text

18 Removed Figure 4-2 CLK Timing Measurement Points.

Update History for Electrical Specification chapter

36/51

MECHANICAL DATA

37/51

Issue 1.2

5. MECHANICAL DATA

5.1 388-Pin Package Dimension

The pin numbering for the STPC 388-pin Plastic

BGA package is shown in Figure 5-1.

Dimensions are shown in Figure 5-2, Table 5-1

and Figure 5-3, Table5-2.

Figure 5-1. 388-Pin PBGA Package - Top View

1 3 5 7 9 11 13 15 17 19 21 23 25

2468101214161820222426

1 3 5 7 9 1113151719212325

2468101214161820222426

MECHANICAL DATA

38/51 Issue 1.2

Figure 5-2. 388-pin PBGA Package - PCB Dimensions

Table 5-1. 388-pin PBGA Package - PCB Dimensions

Symbols mm inches

Min Typ Max Min Typ Max

A 34.95 35.00 35.05 1.375 1.378 1.380

B 1.22 1.27 1.32 0.048 0.050 0.052

C 0.58 0.63 0.68 0.023 0.025 0.027

D 1.57 1.62 1.67 0.062 0.064 0.066

E 0.15 0.20 0.25 0.006 0.008 0.001

F 0.05 0.10 0.15 0.002 0.004 0.006

G 0.75 0.80 0.85 0.030 0.032 0.034

Detail

A1 Ball Pad Corner

MECHANICAL DATA

39/51

Issue 1.2

Figure 5-3. 388-pin PBGA Package - Dimensions

Table 5-2. 388-pin PBGA Package - Dimensions

Symbols mm inches

Min Typ Max Min Typ Max

A 0.50 0.56 0.62 0.020 0.022 0.024

B 1.12 1.17 1.22 0.044 0.046 0.048

C 0.60 0.76 0.92 0.024 0.030 0.036

D 0.52 0.53 0.54 0.020 0.021 0.022

E 0.63 0.78 0.93 0.025 0.031 0.037

F 0.60 0.63 0.66 0.024 0.025 0.026

G 30.0 11.8

Solderball Solderball after collapse

MECHANICAL DATA

40/51 Issue 1.2

5.2 388-Pin Package thermal data

388-pin PBGA package has a Power Dissipation

Capability of 4.5W which increases to 6W when

used with a Heatsink.

Structure in shown in Figure 5-4.

Thermal dissipation options are illustrated in Fig-

ure 5-5 and Figure 5-6.

Figure 5-4. 388-Pin PBGA structure

Thermal balls

Power & Ground layersSignal layers

Figure 5-5. Thermal dissipation without heatsink

Ambient

Board

Case

Junction

Board

Ambient

Case

Junction

Board

Rca

Rjc

Rjb

Rba

1258.5

Rja = 13 °C/W

Airflow = 0

Board dimensions:

The PBGA is centered on board

Copper thickness:

-17

m for internal layers

-34

m for external layers

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)

There are no other devices

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

Board temperature taken at the center balls

MECHANICAL DATA

41/51

Issue 1.2

Figure 5-6. Thermal dissipation with heatsink

Board

Ambient

Case

Junction

Board

Ambient

Case

Junction

Board

Rca

Rjc

Rjb

Rba

508.5

Rja = 9.5 °C/W

Airflow = 0

Board dimensions:

The PBGA is centered on board

Copper thickness:

-17

m for internal layers

-34

m for external layers

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)

There are no other devices

Heat sink is 11.1

C/W

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

Board temperature taken at the center balls

MECHANICAL DATA

42/51 Issue 1.2

BOARD LAYOUT

43/51

Issue 1.2

6. BOARD LAYOUT

6.1 THERMAL DISSIPATION

Thermal dissipation of the STPC depends mainly

on supply voltage. As a result, when the system

does not need to workat 3.3V, it may be to reduce

the voltage to 3.15V for example. This may save

few 100’s of mW.

The second area that can be concidered is un-

used interfaces and functions. Depending on the

application, some input signals can be grounded,

and some blocks not powered or shutdown. Clock

speed dynamic adjustment is also a solution that

can be usedalong withthe integrated power man-

agement unit.

The standard way to route thermal balls to internal

ground layerimplements only one viapad foreach

ball pad, connected using a 8-mil wire.

With such configuration thePlastic BGA 388 pack-

agedissipates 90%of the heat through theground

balls, and especially the central thermal balls

which are directly connected to the die, the re-

maining 10% is dissipated through the case. Add-

ing a heat sink reduces this value to 85%.

As a result, some basic rules have to be applied

when routing the STPC in order to avoid thermal

problems.

First of all, the whole ground layer acts as a heat

sink and ground balls must be directly connected

to it as illustrated in Figure 6-1.

If one ground layer is not enough, a second

ground plane may be added on the solder side.

Figure 6-1. Ground routing

Pad for ground ball

Thru hole to ground layer

TopLayer:S

ignals

roundlayer

erlayer

ttomLayer:sig

ls+localgro

undlayer(ifneeded

)

Note: For better visibility, ground balls are not all routed.

BOARD LAYOUT

44/51 Issue 1.2

When considering thermal dissipation, the most

important - and not the more obvious - part of the

layout is the connection between the ground balls

and the ground layer.

A 1-wire connection is shown in Figure 6-2. The

use of a 8-mil wire results in a thermal resistance

of 105°C/W assuming copper is used (418 W/

m.°K). This high value is due to the thickness (34

µm) of the copper on theexternal side of the PCB.

Considering only the central matrix of 36 thermal

balls and one via for each ball, the global thermal

resistance is 2.9°C/W. This can be easily im-

proved by using four 10 milwires to connect to the

four vias around the ground pad link as in Figure

6-3. This gives a total of 49 viasand a global resis-

tance for the 36 thermal balls of 0.6°C/W.

The use of a ground plane like in Figure 6-4 is

even better.

To avoid solder wickingover to the via padsduring

soldering, it is important to have a solder mask of

4 mil around the pad (NSMD pad), this gives a di-

ameter of 33mil for a 25 mil ground pad.

To obtain the optimum ground layout, place the

vias directly under the ball pads. In this case no lo-

cal boar d distortion is tolerated.

The thickness of the copper on PCB layers is typ-

ically 34 µm for external layers and 17 µm forinter-

nal layers. This means thermal dissipation is not

good and temperature of the board is concentrat-

ed around the devices and falls quickly with in-

creased distance.

When it is possible to place a metal layer inside

the PCB, this improves dramatically the heat

spreading and hence thermal dissipation of the

board.

Figure 6-2. Recommended 1-wire ground pad layout

Figure 6-3. Recommended 4-wire ground pad layout

Solder Mask (4 mil)

Pad for ground ball (diameter= 25 mil)

Hole to ground layer (diameter = 12 mil)

Connection Wire (width = 10 mil)

Via (diameter = 24 mil)

34.5 mil

1 mil = 0.0254 mm

4 via pads for each ground ball

BOARD LAYOUT

45/51

Issue 1.2

The PBGA Package also dissipates heat through

peripheral ground balls. When a heat sink is

placed on the device, heat is more uniformely

spread throughout the moulding increasing heat

dissipation through the peripheral ground balls.

The more via pads are connected to each ground

ball, the more heat is dissipated . The only limita-

tion is the risk of lossing routing channels.

Figure 6-5 shows a routing with a good trade off

between thermal dissipation and number of rout-

ing channels.

Figure 6-4. Optimum layout for central ground ball

Via to Ground layer

Pad for ground ball

Clearance = 6mil

diameter = 25 mil

hole diameter = 14 mil

Solder mask

diameter = 33 mil

External diameter = 37 mil

connections = 10 mil

Figure 6-5. Global ground layout for good thermal dissipation

Ground pad

Via to ground layer

BOARD LAYOUT

46/51 Issue 1.2

A local ground plane on opposite side of the board

as shown in Figure 6-6 improves thermal dissipa-

tion. It is used toconnect decoupling capacitances

but can also be used for connection to a heat sink

or to the system’s metal box for better dissipation.

This possibility ofusing the whole system’s box for

thermal dissipation is very usefull in case of high

temperature inside the system and low tempera-

ture outside. In that case, both sides of the PBGA

should be thermally connected to the metal chas-

sis in order to propagate the heat through the met-

al. Figure 6-7 illustrates such an implementation.

Figure 6-6. Bottom side layout and decoupling

Ground plane for thermal dissipation

Via to ground layer

Figure 6-7. Use of metal plate for thermal dissipation

Metal planes Thermal conductor

Board

Die

BOARD LAYOUT

47/51

Issue 1.2

6.2 HIGH SPEED SIGNALS

Some Interfaces of the STPC run at high speed

and have to be carefully routed or even shielded.

Here is the list of these interfaces, in decreasing

speed order:

- Memory Interface.

- Graphics and video interfaces

- PCI bus

- 14MHz oscillator stage

All the clocks have to be routed first and shielded

for speeds of 27MHz or more. The high speed sig-

nals have the same contrainsts as some of the

memory interface control signals.

The next interfaces to be routed are Memory, Vid-

eo/graphics, and PCI.

All the analog noise sensitive signals have to be

routed in a separate area and hence can be rout-

ed indepedently.

Figure 6-8. Shielding signals

ground ring

ground pad

shielded signal line

ground pad shielded signal lines

ORDERING DATA

48/51 Issue 1.2

7. ORDERING DATA

7.1 OrderingCodes

ST PC C01 66 BT C 3

STMicroelectronics

Prefix

Product Family

PC: PC Compatible

Product ID

C01: Consumer

Core Speed

66: 66MHz

75: 75MHz

80: 80MHz

10: 100MHz

Package

BT: 388 Overmoulded BGA

Temperature Range

C: Commercial

0to+70°C

Tcase = 0 to +100°C

I: Industrial

-40 to +85°C

Tcase = -40 to +100°C

Operating Voltage

3 : 3.3V ±0.3V

ORDERING DATA

49/51

Issue 1.2

7.2 Available Part Numbers

Part Number Core Frequency

(MHz) CPU Mode Tcase Range

(V)

STPCC0166BTC3 66 DX 0°C to +100°C3.3V ±0.3V

STPCC0180BTC3 80 DX

STPCC0110BTC3 100 DX2

STPCC0166BTI3 66 DX -40°C to +100°C

STPCC0180BTI3 80 DX

ORDERING DATA

50/51 Issue 1.2

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of useof such information nor forany infringement ofpatents or otherrights of third parties which may result from itsuse. No license isgranted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.

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Issue 1.2