73M1866B/73M1966B MicroDAATM with PCM Highway DATA SHEET Simplifying System IntegrationTM DS_1x66B_001 DESCRIPTION The 73M1866B and 73M1966B use the Teridian patented Data Access Arrangement function (R) (MicroDAA ) designed exclusively for ForeignExchange-Office (FXO) in Voice-over-IP (VoIP) applications. These devices provide much of the circuitry required to connect PCM formatted voice channels to a PSTN via a two-wire twisted pair interface. The package options provide the necessary functional programmability and protection required for easy worldwide homologation. The family of devices consists of the 73M1866B and the 73M1966B. The 73M1866B MicroDAA is the world's first single-package silicon Data Access Arrangement (DAA). Suitable applications for the 73M1866B and 73M1966B devices include VoIP equipment that must provide connectivity to the PSTN for purposes of guaranteeing emergency service calling, redundancy for supplementary connectivity for voice, and maintenance services. The 73M1966B device set consists of the 73M1906B Host-Side Device that provides digital data, control interfaces and power to the 73M1916 Line-Side Device. These devices are based on an innovative and patented technology, which sets new standards in reliability and cost. A small pulse transformer forms a digital isolation barrier, transferring both power and data to the PSTN line-side components. This method results in reliable operation in the presence of EMI and a tolerance to line voltage variations by providing power to the Line-Side Device across the barrier. The devices also support the ability to provide up to an additional +6 dB of analog gain to the lineside transmit and +3 dB in the receive signal paths. The device supports transmit and receive digital gain ranging from -18 dB to +7.375 dB by increments of 0.125 dB. April 2010 Through its PCM interface, the 73M1966B can be connected to other PCM enabled devices such as POTS codecs, ISDN codecs, E1/T1 framers, etc. Additional DAA functions supported by the 73M1x66B devices include a call progress monitor, Caller ID Type I and II, ring detection, pulse dialing, billing tone detection and polarity reversal detection. APPLICATIONS * * * * * * Computer Telephony VOIP Equipment PBX Systems Internet Appliances Voicemail Systems POTS Termination Equipment FEATURES * * * * * * * * * * * * * * * * * * * PCM highway data interface supporting both slave and master modes PCM highway interface supporting both E-1 and T-1 SPI control interface, with daisy chain support for up to 16 devices Designed to meet global DAA compliance FCC, ETSI ES 203 021-2, JATE and other PTT standards. 8 kHz and 16 kHz sample rates 16-bit linear mode TX and RX gains adjustable in 0.125 dB increments -Law, A-law ITU-T Recommendation G.711 compliant compander operation Automatic clock rate detection Low power modes Polarity Reversal detection GPIO for user-configurable I/O ports Call Progress Monitor Isolation up to 6 kV THD -80 dB 5 V tolerant I/O on selected pins 3.0 V - 3.6 V operating voltage Industrial temperature range (-40 C to +85 C) 5x5 mm 32-pin QFN or 20-pin TSSOP packages RoHS compliant (6/6) lead-free package The digital side provides a PCM highway interface with automatic clock rate detection. With an 8-kHz sampling rate, the devices include an ITU-T G.711 compliant codec with selectable -law and A-law companding modes. The devices also provide a 16-bit linear mode, which * is suitable for interfacing with wide band codecs, as well as 16 kHz sampling rate. Device control is performed over an SPI interface. The SPI supports daisy chain operation. Rev. 1.6 (c) 2010 Teridian Semiconductor Corporation 1 73M1866B/73M1966B Data Sheet DS_1x66B_001 Table of Contents 1 Introduction ................................................................................................................................... 6 2 Pinout ............................................................................................................................................. 8 2.1 73M1906B 20-Pin TSSOP Pinout............................................................................................ 8 2.2 73M1916 20-Pin TSSOP Pinout .............................................................................................. 9 2.3 73M1906B 32-Pin QFN Pinout .............................................................................................. 10 2.4 73M1916 32-Pin QFN Pinout ................................................................................................ 12 2.5 73M1866B Pinout ................................................................................................................. 14 2.6 Requisite Use of Exposed Bottom Pad on 73M1866B and 73M1966B QFN Packages .......... 15 Electrical Characteristics and Specifications............................................................................. 16 3.1 Isolation Barrier Characteristics ............................................................................................. 16 3.2 Electrical Specifications......................................................................................................... 16 3.2.1 Absolute Maximum Ratings ....................................................................................... 16 3.2.2 Recommended Operating Conditions ........................................................................ 16 3.2.3 DC Characteristics..................................................................................................... 17 3.3 Interface Timing Specification................................................................................................ 18 3.3.1 SPI Interface ............................................................................................................. 18 3.3.2 PCM Highway Interface ............................................................................................. 19 3.4 Analog Specifications ............................................................................................................ 20 3.4.1 DC Specifications ...................................................................................................... 20 3.4.2 Call Progress Monitor ................................................................................................ 21 3.5 73M1x66B Line-Side Electrical Specifications (73M1916)...................................................... 22 3.6 Reference and Regulation ..................................................................................................... 23 3.7 DC Transfer Characteristics .................................................................................................. 23 3.8 Transmit Path ....................................................................................................................... 24 3.9 Receive Path ........................................................................................................................ 25 3.10 Transmit Hybrid Cancellation ................................................................................................ 26 3.11 Receive Notch Filter .............................................................................................................. 26 3.12 Detectors .............................................................................................................................. 27 3.12.1 Over-Voltage Detector ............................................................................................... 27 3.12.2 Over-Current Detector ............................................................................................... 27 3.12.3 Under-Voltage Detector ............................................................................................. 27 3.12.4 Over-Load Detector ................................................................................................... 27 3 4 Applications Information ............................................................................................................. 28 4.1 Example Schematic of the 73M1966B and 73M1866B .......................................................... 28 4.2 Bill of Materials...................................................................................................................... 30 4.3 Over-Voltage and EMI Protection .......................................................................................... 31 4.4 Isolation Barrier Pulse Transformer ....................................................................................... 32 5 SPI Interface................................................................................................................................. 33 6 Control and Status Registers ...................................................................................................... 37 7 Hardware Control Functions ....................................................................................................... 41 7.1 Device Revision .................................................................................................................... 41 7.2 Interrupt Control .................................................................................................................... 41 7.3 Power Management .............................................................................................................. 42 7.4 Device Clock Management.................................................................................................... 42 7.5 GPIO Registers ..................................................................................................................... 43 7.6 Call Progress Monitor ............................................................................................................ 44 7.7 16 kHz Operation of Call Progress Monitor ............................................................................ 44 7.8 Device Reset ........................................................................................................................ 44 PCM Highway Interface and Signal Processing ......................................................................... 45 8.1 PCM Highway Interface Timing ............................................................................................. 45 8.2 PCM Clock Frequencies........................................................................................................ 47 8.3 Master Mode ......................................................................................................................... 47 8.4 A-law / -law Compander ...................................................................................................... 47 8 2 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 8.5 9 10 11 12 13 Transmit and Receive Levels ................................................................................................ 48 8.5.1 A-Law........................................................................................................................ 48 8.5.2 -Law ........................................................................................................................ 48 8.5.3 Transmit and Receive Level Control .......................................................................... 48 8.6 Transmit Path Signal Processing........................................................................................... 49 8.6.1 General Description ................................................................................................... 49 8.6.2 Total Transmit Path Response................................................................................... 49 8.6.3 73M1x66B Transmit Spectrum................................................................................... 50 8.7 Receive Path Signal Processing............................................................................................ 50 8.7.1 General Description ................................................................................................... 50 8.7.2 Total Receive Path Response.................................................................................... 51 8.7.3 Receiver DC Offset Subtraction ................................................................................. 51 8.8 PCM Control Functions ......................................................................................................... 52 8.8.1 Transmit and Receive Level Control .......................................................................... 57 8.8.2 Time Slot Assignment Example ................................................................................. 59 Barrier Information ...................................................................................................................... 60 9.1 Isolation Barrier ..................................................................................................................... 60 9.2 Barrier Powered Options ....................................................................................................... 60 9.2.1 Barrier Powered Operation ........................................................................................ 60 9.2.2 Line Powered Operation ............................................................................................ 60 9.3 Synchronization of the Barrier ............................................................................................... 60 9.4 Auto-Poll ............................................................................................................................... 61 9.5 Barrier Control Functions ...................................................................................................... 61 9.6 Line-Side Device Operating Modes ....................................................................................... 63 9.7 Fail-Safe Operation of Line-Side Device ................................................................................ 63 Configurable Direct Access Arrangement (DAA) ....................................................................... 64 10.1 Pulse Dialing ......................................................................................................................... 64 10.2 DC Termination ..................................................................................................................... 64 10.3 AC Termination ..................................................................................................................... 66 10.4 Billing Tone Rejection ........................................................................................................... 67 10.5 Trans-Hybrid Cancellation ..................................................................................................... 68 10.6 Direct Access Arrangement Control Functions....................................................................... 68 10.7 International Register Settings Table for DC and AC Terminations ........................................ 72 Line Sensing and Status ............................................................................................................. 73 11.1 Auxiliary A/D Converter ......................................................................................................... 73 11.2 Ring Detection ...................................................................................................................... 73 11.3 Line In Use Detection (LIU) ................................................................................................... 73 11.4 Parallel Pick Up (PPU) .......................................................................................................... 73 11.5 Polarity Reversal Detection ................................................................................................... 73 11.6 Off-hook Detection of Caller ID Type II .................................................................................. 73 11.7 Voltage and Current Detection .............................................................................................. 74 11.8 Under Voltage Detection (UVD)............................................................................................. 74 11.9 Over Voltage Detection (OVD) .............................................................................................. 74 11.10 AC Signal Overload Detection ............................................................................................. 74 11.11 Over Current Detection (OID).............................................................................................. 74 11.12 Line Sensing Control Functions........................................................................................... 75 Loopback and Testing Modes ..................................................................................................... 78 14 Performance ................................................................................................................................ 80 13.1 Transmit................................................................................................................................ 80 13.2 Receive................................................................................................................................. 82 Package Layout ........................................................................................................................... 85 15 Ordering Information ................................................................................................................... 87 16 Contact Information..................................................................................................................... 87 Revision History .................................................................................................................................. 88 Rev. 1.6 3 73M1866B/73M1966B Data Sheet DS_1x66B_001 Figures Figure 1: Simple 73M1x66B Reference Block Diagram ............................................................................ 6 Figure 2: 73M1906B 20-Pin TSSOP Pinout.............................................................................................. 8 Figure 3: 73M1916 20-Pin TSSOP Pinout ................................................................................................ 9 Figure 4: 73M1906B 32-Pin QFN Pinout ................................................................................................ 10 Figure 5: 73M1916 32-Pin QFN Pinout .................................................................................................. 12 Figure 6: 73M1866B 42-Pin Pinout ........................................................................................................ 14 Figure 7: SPI Timing Diagram ................................................................................................................ 18 Figure 8: PCM Timing Diagram for Positive Edge Transmit Mode and Negative Edge Receive Mode ..... 19 Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode ..... 20 Figure 10: Frequency Response of the Call Progress Monitor Filter ....................................................... 21 Figure 11: Demo Board Circuit Connecting AOUT to a Speaker ............................................................. 21 Figure 12: Recommended Circuit for the 73M1966B .............................................................................. 28 Figure 13: Recommended Circuit for the 73M1866B .............................................................................. 29 Figure 14: Suggested Over-Voltage Protection and EMI Suppression Circuit ......................................... 31 Figure 15: Daisy-Chain Configuration .................................................................................................... 34 Figure 16: SPI Write Operation - 8-bit Mode .......................................................................................... 34 Figure 17: SPI Read Transaction - 8-bit Mode....................................................................................... 35 Figure 18: SPI Write Transaction - 16-bit Mode ..................................................................................... 35 Figure 19: SPI Read Transaction - 16-bit Mode..................................................................................... 35 Figure 20: 8-bit Transmission Example .................................................................................................. 45 Figure 21: 16-bit Transmission Example ................................................................................................ 46 Figure 22: Example of PCM Highway Interconnect................................................................................. 46 Figure 23: Example of PCM Highway Interconnect for Typical Large Systems ....................................... 46 Figure 24: Mapping of A-law Code to 16-bit Code .................................................................................. 48 Figure 25: Mapping of -law Code to 16-bit Code .................................................................................. 48 Figure 26: Transmit Path Overall Frequency Response to Fs of 8 kHz ................................................... 49 Figure 27: Transmit Path Passband Response for an 8 kHz Sample Rate.............................................. 49 Figure 28: Transmit Spectrum to 32 kHz for an 8 kHz Sample Rate ....................................................... 50 Figure 29: Overall Frequency Response of the Receive Path ................................................................. 51 Figure 30: Pass-band Response of the Overall Receive Path................................................................. 51 Figure 31: Timing Relationships with Various TTS, TCS, TPOL, and RTS, RCS, RPOL Settings............ 59 Figure 32: Line-Side Device AC and DC Circuits.................................................................................... 63 Figure 33: DC-IV Characteristics............................................................................................................ 64 Figure 34: Tip-Ring Voltage versus Current Using Different DCIV Settings............................................. 65 Figure 35: Voltage versus Current in the Seize Mode is the Same for All DCIV Settings ......................... 66 Figure 36: Magnitude Response of Impedance Matching Filter, ACZ (3:0)=0010 (ES 203 021-2) ........... 67 Figure 37: Magnitude Response of Billing Tone Notch Filter .................................................................. 67 Figure 38: Trans-hybrid Cancellation ..................................................................................................... 68 Figure 39: Loopback Modes Highlighted ................................................................................................ 78 Figure 40: Variation of Transmit Gain Digital Input to Analog Output at the Line ..................................... 80 Figure 41: Gain versus Frequency for Digital Input to Analog Output at the Line..................................... 81 Figure 42: Signal to Total Distortion versus Input Level for Digital Input to Analog Output to the Line...... 81 Figure 43: Variation of Receiver Analog Gain at the Line to the Digital DX Output .................................. 82 Figure 44: Gain versus Frequency for Analog Input at the Line to the Digital DX Output ......................... 83 Figure 45: Signal to Total Distortion versus Input Level for Analog at the Line to the Digital DX Output... 83 Figure 46: Return Loss, @ 80 mA .......................................................................................................... 84 Figure 47: 20-Pin TSSOP Package Dimensions..................................................................................... 85 Figure 48: 32-Pin QFN Package Dimensions ......................................................................................... 85 Figure 49: 42-Pin QFN Package Dimensions ......................................................................................... 86 4 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet Tables Table 1: 73M1906B 20-Pin TSSOP Pin Definitions .................................................................................. 8 Table 2: 73M1916 20-Pin TSSOP Pin Definitions ..................................................................................... 9 Table 3: 73M1906B 32-Pin QFN Pin Definitions ..................................................................................... 10 Table 4: 73M1916 32-Pin QFN Pin Definitions ....................................................................................... 12 Table 5: 73M1866B Pin Definitions ........................................................................................................ 14 Table 6: Isolation Barrier Characteristics ................................................................................................ 16 Table 7: Absolute Maximum Device Ratings .......................................................................................... 16 Table 8: Recommended Operating Conditions ....................................................................................... 16 Table 9: DC Characteristics ................................................................................................................... 17 Table 10: SPI Interface Switching Characteristics .................................................................................. 18 Table 11: Switching Characteristics - PCM Interface (Slave Mode) ........................................................ 19 Table 12: Switching Characteristics - PCM Interface (Master Mode) ...................................................... 19 Table 13: Reference Voltage Specifications ........................................................................................... 20 Table 14: Component Values for the Speaker Driver .............................................................................. 21 Table 15: Call Progress Monitor Specification ........................................................................................ 22 Table 16: Line-Side Absolute Maximum Ratings .................................................................................... 22 Table 17: VBG Specifications ................................................................................................................ 23 Table 18: Maximum DC Transmit Levels ................................................................................................ 23 Table 19: Transmit Path......................................................................................................................... 24 Table 20: Receive Path ......................................................................................................................... 25 Table 21: Transmit Hybrid Cancellation Characteristics .......................................................................... 26 Table 22: Receive Notch Filter ............................................................................................................... 26 Table 23: Over-voltage Detector ............................................................................................................ 27 Table 24: Over-current Detector............................................................................................................. 27 Table 25: Under-voltage Detector .......................................................................................................... 27 Table 26: Over-load Detector ................................................................................................................. 27 Table 27: Reference Bill of Materials for 73M1x66B ............................................................................... 30 Table 28: Reference Bill of Materials for Figure 14 ................................................................................. 31 Table 29: Compatible Pulse Transformer Sources ................................................................................. 32 Table 30: Pulse Transformer Electrical Characteristics ........................................................................... 32 Table 31: Control and Status Register Map ............................................................................................ 37 Table 32: Alphabetical Bit Map .............................................................................................................. 38 Table 33: PCM Control Functions .......................................................................................................... 52 Table 34: Transmit Gain Control ............................................................................................................ 57 Table 35: Recommended Gain Setting................................................................................................... 57 Table 36: Receive Gain Control ............................................................................................................. 59 Table 37: Barrier Control Functions........................................................................................................ 61 Table 38: DAA Control Functions ........................................................................................................... 68 Table 39: Recommended Register Settings for International Compatibility ............................................. 72 Table 40: Line Sensing Control Functions .............................................................................................. 75 Table 41: Loopback Modes.................................................................................................................... 78 Table 42: Loopback Modes Summary .................................................................................................... 79 Table 43: Order Numbers and Packaging Marks .................................................................................... 87 Rev. 1.6 5 73M1866B/73M1966B Data Sheet DS_1x66B_001 1 Introduction The 73M1966B is a two-device chip set that provides embedded FXO functionality by connecting a PCM interface to a voice-band PSTN. The device set supports ITU-T Recommendation G.711 -law and A-law companding, and also a 16-bit linear mode. High-voltage isolation is provided by the physical separation of the Host-Side (73M19106) and Line-Side (73M1916) Devices. The Host-Side and the Line-Side Devices communicate with each other using a single pulse transformer. A few low-cost components complete the DAA interface to the network. The pulse transformer transmits encoded digital data rather than analog signals as with other transformer designs. Data is transmitted and received without the usual degradation from common mode noise and magnetic coupling typical of other capacitive and voice-band transformer techniques. The data stream passed between the Host-Side and Line-Side Devices includes the media stream data, control, status, and clocking information. This data sheet describes both the 73M1966B and 73M1866B, which will be collectively referred to as the 73M1x66B in this document. A unique capability of the 73M1x66B Host Side device (73M1906B) is its ability to provide power to the 73M1x66B Line Side device (73M1916) via the pulse transformer. The 73M1906B exchanges control and status information with the host using the SPI interface, while the PCM encoded media streams connect with other PCM-enabled devices using the PCM highway bus interface. Figure 1 shows a reference block diagram of the 73M1x66B connected by a pulse transformer and example external line interface circuitry shown for clarification. Host -Side Device Line-Side Device 73M1906B 73M1916 SPI SPI Interface Aux A/D Tip PRP Transmit Interpolation Filter PCM PCM Interface Receive Decimation Filter SCP Line Side Barrier Interface (LSBI) Host Side Barrier Interface (HSBI) PRM SCM Digital Sigma Delta Modulator Transmit Analog Front End SinC3 Filter Receive Analog Front End (with Sigma Delta Modulator) TxA Off-Chip LIC (OffLIC) On-Chip LIC (OnLIC) Call Progress Monitor Audio Out RxA Ring Figure 1: Simple 73M1x66B Reference Block Diagram The Host-Side Device (73M1906B) consists of: 1. 2. 3. 4. 5. 6 PCM Interface Block (PCM) SPI Interface Block (SPI) Transmit Interpolation Filter Receive Decimation Filter Host-Side Barrier Interface Circuit (HSBI) Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet The Line-Side Device (73M1916) consists of: 1. 2. 3. 4. 5. 6. Digital Sigma Delta Modulator Transmit Analog Front End Receive Analog Front End including Sigma Delta Modulator 3 Sinc Filter (Sinc3) On-chip Line Interface Circuit Line-Side Barrier Interface Circuit (LSBI) Received data from a host connected to the PCM bus is interpolated from the sampling frequency of 8 kHz or 16 kHz (for PCM encoded streams) to twice the sampling frequency. The control information is multiplexed with the audio stream signals and transmitted across the isolation barrier to the Line-Side Device. In the Line-Side Device, the two streams are separated and the audio signal is converted to analog for transmission to the line. An audio stream received at the analog line input pins is converted to a serialized data stream and, along with status information such as line condition from the Auxiliary Analog to Digital Converter, is transmitted over the isolation barrier using the pulse transformer. The data is extracted with status information being transmitted on the SPI. The audio stream is sent to a host using the PCM bus. The 73M1x66B is an enhanced version of the 73M1966 that includes the additional functionality of finer resolution of transmit and receive gain, receiver DC offset subtraction and support for T-1 PCLK frequencies. Rev. 1.6 7 73M1866B/73M1966B Data Sheet DS_1x66B_001 2 Pinout The 73M1906B and the 73M1916 are supplied as 20-pin TSSOP packages and as 32-pin QFN packages. 2.1 73M1906B 20-Pin TSSOP Pinout Figure 2 shows the 73M1906B 20-pin TSSOP pinout. CS 1 20 SCLK VPD 2 19 INT DR 3 18 SDO DX 4 17 SDI FS 5 16 SDIT PCLKO 6 15 RST PCLKI 7 14 VPT VNA/VND 8 13 PRP AOUT 9 12 PRM VPA 10 11 VNT 73M1906B Figure 2: 73M1906B 20-Pin TSSOP Pinout Table 1 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins. Table 1: 73M1906B 20-Pin TSSOP Pin Definitions Pin Number Pin Name Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CS VPD DR DX FS PCLKO PCLKI VNA/VND AOUT VPA VNT PRM PRP VPT RST SDIT SDI SDO INT SCLK I PWRI I O I/O O I GND O PWRI GND I/O I/O PWRI I O I O O I 8 Description SPI chip select (active low) Positive digital supply PCM transmit data sent to the D to A PCM received data from the A to D PCM frame synchronization PCM clock output PCM clock in Negative analog/digital ground Audio output - must be buffered for speaker Positive analog supply Negative transformer supply Transformer primary minus Transformer primary plus Positive transformer supply Hardware reset (active low) SPI data out for daisy chain mode SPI data in SPI data out Interrupt / ring detect (active low - open drain) SPI clock Rev. 1.6 DS_1x66B_001 2.2 73M1866B/73M1966B Data Sheet 73M1916 20-Pin TSSOP Pinout Figure 3 shows the 73M1916 20-pin TSSOP pinout. DCI 1 20 DCG RGN 2 19 DCS RGP 3 18 DCD OFH 4 17 TXM VNX 5 16 RXM SCP 6 15 RXP MID 7 14 VPS VPX 8 13 VNS SRE 9 12 ACS SRB 10 11 VBG 73M1916 Figure 3: 73M1916 20-Pin TSSOP Pinout Table 2 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins. Table 2: 73M1916 20-Pin TSSOP Pin Definitions Pin Number Pin Name Type Description 1 2 3 4 5 6 7 8 9 10 11 12 13 DCI RGN RGP OFH VNX SCP MID VPX SRE SRB VBG ACS VNS I I I O GND I/O I/O PWR I O O I GND DC loop input Ring detect negative voltage input Ring detect positive voltage input Off-hook control Negative supply voltage (line side of the barrier) Positive side of the secondary pulse transformer winding Charge pump midpoint Supply from the barrier Voltage regulator sense Voltage regulator drive VBG bypass, connect to 0.1 F capacitor to VNS AC current sense Analog negative supply voltage 14 VPS PWRO 15 16 17 18 19 20 RXP RXM TXM DCD DCS DCG I I O O I O Rev. 1.6 Analog positive supply voltage (output) Receive plus - signal input Receive minus - signal input Transmit minus - transhybrid cancellation output DC loop output DC loop current sense DC loop control 9 73M1866B/73M1966B Data Sheet 2.3 DS_1x66B_001 73M1906B 32-Pin QFN Pinout GPIO6 DR VPD CS SCLK INT VND GPIO5 32 31 30 29 28 27 26 25 Figure 4 shows the 73M1906B 32-pin QFN pinout. GPIO7 1 24 SDO TSC 2 23 SDI DX 3 22 SDIT VPD 4 21 RST 20 VPD FS 73M1906B 5 14 15 16 N/C N/C PRM VNT 17 13 8 N/C VND 12 PRP VPA / VPPLL 18 11 7 AOUT PCLKI 10 VPT VBG 19 9 6 VNA / VNPLL PCLKO Figure 4: 73M1906B 32-Pin QFN Pinout Table 3 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins. Table 3: 73M1906B 32-Pin QFN Pin Definitions Pin Number 1 2 3 4 5 6 7 Pin Name Description FS PCLKO PCLKI I/O O O PWR I/O O I Configurable input/output pin PCM time slot control (active low) PCM received data from the A to D Positive digital supply PCM frame synchronization PCM clock output PCM clock in 8 9 VND VNA/VNPLL GND GND Negative digital ground Negative analog/PLL ground 10 11 12 13 14 15 16 VBG AOUT VPA/VPPLL N/C VNT N/C N/C O O PWR - GND - - Band gap voltage reference monitor Audio output - must be buffered for speaker Positive analog/PLL supply No connect Negative transformer supply No connect No connect 10 GPIO7 TSC DX VPD Type Rev. 1.6 DS_1x66B_001 Pin Number 17 18 19 20 21 22 23 24 PRM PRP VPT VPD RST SDIT SDI SDO 25 26 27 28 29 30 31 32 Rev. 1.6 Pin Name 73M1866B/73M1966B Data Sheet Type Description GPIO5 VND I/O I/O PWR PWR I O I O I/O GND Transformer primary minus Transformer primary plus Positive transformer supply Positive digital supply Hardware reset (active low) SPI data out for daisy-chain mode SPI data in SPI data out Configurable input/output pin Negative digital ground INT SCLK CS VPD DR GPIO6 O I I PWR I I/O Interrupt / ring detect (active low - open drain) SPI clock SPI chip select (active low) Positive digital supply PCM transmit data sent to the D to A Configurable input/output pin 11 73M1866B/73M1966B Data Sheet 2.4 DS_1x66B_001 73M1916 32-Pin QFN Pinout GPO GPI VNS/VND RGP RGN DCI DCG DCS 32 31 30 29 28 27 26 25 Figure 5 shows the 73M1916 32-pin QFN pinout. CKO 1 24 DCD OFH 2 23 RST CKI 3 22 TST VNX 4 21 TXM SCP 5 20 SACIN MID 6 19 RXM SCM 7 18 RXP VPX 8 17 16 VNS 13 VNS 15 12 SRB ACS 11 SRE 14 10 BYP VBG 9 RCT 73M1916 VPS Figure 5: 73M1916 32-Pin QFN Pinout Table 4 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins. Table 4: 73M1916 32-Pin QFN Pin Definitions Pin Number 1 2 3 4 5 6 7 8 9 Pin Name CKO OFH CKI VNX SCP MID SCM VPX RCT 10 11 12 13 14 15 BYP SRE SRB VNS VBG ACS 12 Type O O I GND I/O I/O I/O PWR I I I O GND O I Description Test point for recovered clock Off-hook control Test input for clock Negative supply voltage Positive side of the secondary pulse transformer winding Charge pump midpoint Negative side of the secondary pulse transformer winding Supply from the barrier External rectification - disables internal rectifier when low, leave open Test pin, leave open Voltage regulator sense Voltage regulator drive Digital negative supply voltage VBG bypass, connect to 0.1F capacitor to VNS AC current sense Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet Pin Number 16 17 18 Pin Name VNS VPS RXP GND PWRO I 19 20 RXM SACIN I I Receive minus - signal input Caller ID mode AC impedance connection 21 22 23 TXM O I I Transmit Minus - transhybrid cancellation output Factory test mode, leave open Resets the control registers to default - weakly pulled high 24 25 26 27 28 29 30 31 32 Rev. 1.6 TST RST DCD DCS DCG DCI RGN RGP VNS GPI GPO Type O I O I I I GND I O Description Analog negative supply voltage Analog positive supply voltage (output) Receive plus - signal input DC loop output DC loop current sense DC loop control DC loop input Ring detect negative voltage input Ring detect positive voltage input Negative supply voltage (line side of the barrier) General purpose input (test pin) General purpose output (test pin) 13 73M1866B/73M1966B Data Sheet 2.5 DS_1x66B_001 73M1866B Pinout RGP RGN DCI DCG DCS 36 35 34 33 32 OFH M20PB 38 37 VNX 39 SCP MID 41 40 VPX 42 Figure 6 shows the 73M1866B 42-pin pinout. 31 DCD 30 TXM 29 RXM DX 1 28 RXP VPD 2 27 VPS FS 3 26 VNS PCLKO 4 25 ACS VNA 5 24 VBG PCLKI 6 23 SRB AOUT 7 22 SRE VPA 8 VNT 9 21 DR 18 INT 20 17 VND CS 16 SDO 19 15 SDI SCLK 14 SDIT 13 12 VPT RST 11 10 PRP PRM 73M1866B Figure 6: 73M1866B 42-Pin Pinout Table 5 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins. Table 5: 73M1866B Pin Definitions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 14 Pin Name Type DX O PWR I/O O GND I O PWR GND I/O I/O PWR I O I O VPD FS PCLKO VNA PCLKI AOUT VPA VNT PRM PRP VPT RST SDIT SDI SDO Description PCM received data from the A to D Positive digital supply PCM frame synchronization PCM clock output Negative analog ground PCM clock in Audio output - must be buffered for speaker Positive analog supply Negative transformer supply Transformer primary minus Transformer primary plus Positive transformer supply Hardware reset (active low) SPI data out for daisy-chain mode SPI data in SPI data out Rev. 1.6 DS_1x66B_001 Pin Number 17 18 19 20 Pin Name Type VND GND O I INT SCLK CS 21 22 23 24 25 26 DR 27 28 29 30 31 32 33 34 35 36 37 VPS 38 39 40 41 42 M20PB 2.6 73M1866B/73M1966B Data Sheet SRE SRB VBG ACS VNS RXP RXM TXM DCD DCS DCG DCI RGN RGP OFH VNX SCP MID VPX Description Negative digital ground Interrupt / ring detect (active low - open drain) SPI clock I I SPI chip select (active low) PCM transmit data sent to the D to A I O O Voltage regulator sense Voltage regulator drive VBG bypass, connect to 0.1F capacitor to VNS I GND PWRO I I O O I O I I I O I GND I/O I/O PWR AC current sense Analog negative supply voltage Analog positive supply voltage (output) Receive plus - signal input Receive minus - signal input Transmit Minus - transhybrid cancellation output DC loop output DC loop current sense DC loop control DC loop input Ring detect negative voltage input Ring detect positive voltage input Off-hook control Test pin. Connect to VNX. Negative supply voltage Positive side of the secondary pulse transformer winding Charge pump midpoint Supply from the barrier Requisite Use of Exposed Bottom Pad on 73M1866B and 73M1966B QFN Packages The exposed bottom pad is not intended for thermal relief (heat dissipation) and should not be soldered to the PCB. Soldering of the exposed pad could also compromise electrical isolation/insulation requirements for proper voltage isolation. Avoid any PCB traces or through-hole vias on the PCB beneath the exposed pad area. Rev. 1.6 15 73M1866B/73M1966B Data Sheet DS_1x66B_001 3 Electrical Characteristics and Specifications 3.1 Isolation Barrier Characteristics Table 6 provides the characteristics of the 73M1x66B Isolation Barrier. Table 6: Isolation Barrier Characteristics Parameter Barrier frequency Data transfer rate across the barrier for the sampling rate of 8 kHz Rating 768 kHz 1.536 Mbps When 16 kHz sampling rate is selected, the frequency and data transfer rates are twice those shown above. 3.2 Electrical Specifications This section provides the absolute maximum ratings, the recommended operating conditions and the DC characteristics. 3.2.1 Absolute Maximum Ratings Table 7 lists the maximum operating conditions for the 73M1x66B. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. Table 7: Absolute Maximum Device Ratings Parameter Supply voltage Pin input voltage (except OSCIN) Pin input voltage (OSCIN) Min -0.5 -0.5 -0.5 to VDD Max 4.0 6.0 0.5 Unit V V V 3.2.2 Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 8. Table 8: Recommended Operating Conditions Parameter Supply voltage (VDD) with respect to VSS Operating temperature 16 Min 3.0 -40 Max 3.6 85 Unit V C Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 3.2.3 DC Characteristics Table 9 lists the 73M1x66B DC characteristics. Table 9: DC Characteristics Parameter Input low voltage Input high voltage Output low voltage Output low voltage FSB,SCLK, Output high voltage Output high voltage FSB, FSBD, SCLK Input low leakage current Input high leakage current Active digital current Active PLL current Active analog current IDD total current* IDD total current* IDD current PWDN=1 IDD current SLEEP=1 (Ext Ref Clk) IDD current ENFEH=0 (Ext Ref Clk) VIL VIH1 VOL VOL Condition - - IOL=4 mA IOL=1 mA Min -0.5 0.7 VDD - - Nom - - - - VOH VOH IOH=-4 mA IOH=-1 mA IIL1 IIH1 VDD - 0.45 VDD - 0.45 - - VSS < Vin < VIL1 10 - 40 A VIH1 < Vin < 5.5 - - 1 A 1.5 1.5 17 20 30 5 mA mA mA mA mA A IDD current at 3.0 V - 3.6 V Nominal at 3.3 V - - IDD1dig 1.0 - - IDD1pll 1.0 - - IDD1ana 12 - - IDD1 15 - - IDD2 20 - - IDD3 1.0 Max 0.2 VDD 5.5 0.45 0.45 Unit V V V V V V IDD4 - - 0.5 1.0 mA IDD6 - - 1.0 1.5 mA *Note: IDD1 is with the secondary of the barrier left open. IDD2 is with the secondary of the barrier connected to 73M1916 fully powered. Rev. 1.6 17 73M1866B/73M1966B Data Sheet 3.3 DS_1x66B_001 Interface Timing Specification There are three interfaces associated with the 73M1x66B: the SPI interface, the PCM highway interface and the line interface. This section provides the timing specification for the SPI interface and the PCM highway interface. 3.3.1 SPI Interface Table 10 lists the characteristics for the SPI interface. Table 10: SPI Interface Switching Characteristics Parameter SCLK cycle time1 SCLK rise time SCLK fall time CS setup time CS hold time SDI setup time SDI hold time SDO turn on delay SDO turn off delay SDO hold time SDI to SDITHRU propagation delay Symbol tscy tscr tscf tics tich tids tidh todd todo todh tidt Min 62.5 - - 25 20 25 20 - - - - Typ - - - - - - - - - - 6 Max - 25 25 - - - - 20 20 20 - Unit ns ns ns ns ns ns ns ns ns ns ns Note1: The minimal value of this parameter is for the case where only one 73M1906B is connected to the host. If the daisy chain mode is used, the minimum SCLK cycle time increases according to the number of slaves in the chain. SCLK tscy tics tich CS tids tidh SDI todd todh todo SDO Figure 7: SPI Timing Diagram 18 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 3.3.2 PCM Highway Interface Table 11: Switching Characteristics - PCM Interface (Slave Mode) Parameter PCLK_IN cycle time PCLK_IN rise time PCLK_IN fall time FS setup time FS hold time FS cycle time DR setup time DR hold time DX turn on delay DX turn off delay DX hold time Symbol tpcy tpcr tpcf tifs tifh tifc tids tidh todd todo todh Min 122 - - 25 20 - 25 20 - - - Typ - - - - - 125 - - - - - Max 3906 25 25 - - - - - 20 20 20 Unit ns ns ns ns ns s ns ns ns ns ns Table 12: Switching Characteristics - PCM Interface (Master Mode) Parameter PCLK_OUT cycle time PCLK_OUT rise time PCLK_OUT fall time FS setup time FS hold time FS cycle time DR setup time DR hold time DX turn on delay DX turn off delay DX hold time Symbol tpcy tpcr tpcf tifs tifh tifc tids tidh todd todo todh Min - - - 50 50 - 25 20 - - - Typ 488 - - - - 125 - - - - - Max - 25 25 - - - - - 20 20 20 Unit ns ns ns ns ns s ns ns ns ns ns tifc PCLK tifs tifh tpcy FS tird tids tidh DR todd todh todo DX Figure 8: PCM Timing Diagram for Positive Edge Transmit Mode and Negative Edge Receive Mode Rev. 1.6 19 73M1866B/73M1966B Data Sheet DS_1x66B_001 PCLK tifh tifs tpcy FS tird tids tidh DR todh todd todo DX Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode 3.4 Analog Specifications This section provides the electrical characterizations of the 73M1x66B analog circuitry. 3.4.1 DC Specifications VBG is to be connected to an external bypass capacitor with a minimum value of 0.1 F. This pin is not intended for any other external use. Table 13: Reference Voltage Specifications Parameter VBG VBG Noise VBG PSRR 20 Test Condition VDD=3.0 V - 3.6 V 300 Hz - 3.3 kHz 300 Hz - 30 kHz Min 0.9 - 40 Nom 1.19 -86 - Max 1.4 -80 - Units V dBm600 dB Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 3.4.2 Call Progress Monitor The Call Progress Monitor monitors activities on the line. The audio output contains both transmit and receive data with a configurable level individually set by Register 10h. Figure 10 shows the frequency response of the Call Progress Monitor Filter based upon the characteristics of the device plus the external circuitry as shown. Figure 10: Frequency Response of the Call Progress Monitor Filter C1 0.1uF R1 120K R2 120K -VIN CD VOUT1 VOUT2 LS1 AOUT VCC R3 120K 4 1 2 3 + C2 2.2uF C4 1uF VREF1 VREF2 U1 V+ GND 5 8 AT-2308 INTERVOX VCC 6 7 C3 NJM2135 1uF Figure 11: Demo Board Circuit Connecting AOUT to a Speaker Table 14: Component Values for the Speaker Driver Quantity 1 1 2 1 3 1 Reference C1 C2 C3, C4 LS1 R1, R2, R3 U1 Part Description Ceramic capacitor Ceramic capacitor Ceramic capacitor Sound transducer 1/8 W resistor 0603 Audio amplifier Part 0.1 F 2.2 F (optional) 1 F Speaker (Intervox) 120 k NJM2135 (New Japan Radio) All measurements are at the AOUT pin with CMVSEL=0. Note that when CMVSEL=1, the peak signal at AOUT is increased to approximately 1.11 Vpk. Rev. 1.6 21 73M1866B/73M1966B Data Sheet DS_1x66B_001 Table 15: Call Progress Monitor Specification Parameter AOUT for transmit AOUT transmit THD AOUT for receive AOUT receive THD AOUT output impedance 3.5 Test Condition 1 kHz full swing code (ATX) CMRXG=11 (Mute) Observe AOUT pin CMTXG=00 CMTXG=01 relative to CMTXG=00 CMTXG=10 relative to CMTXG=00 CMTXG=11 (Mute) CMTXG=00 1.0 Vpk, 1 kHz at the line or 0.5 Vpk at RXP/RXM with RXG=10 CMTXG=11 (Mute) Observe AOUT pin CMRXG=00 CMRXG=01 relative to CMRXG=00 CMRXG=10 relative to CMRXG=00 CMRXG=11 (Mute) CMRXG=00 Min - Nom - Max - Units - - - 0.98 -6 - - Vpk dB - -12 - dB - - - Mute 40 - - - - dB dB - - - 0.96 -6 - - Vpk dB - -12 - dB - - - Mute 40 10 - - - dB dB k 73M1x66B Line-Side Electrical Specifications (73M1916) Table 16 lists the absolute maximum ratings for the line side. Operation outside these rating limits may cause permanent damage to this device. Table 16: Line-Side Absolute Maximum Ratings Parameter Pin input voltage from VPX to VNX Pin input voltage (all other pins) to VNS 22 Min -0.5 -0.5 Max 6.0 4.0 Unit V V Rev. 1.6 DS_1x66B_001 3.6 73M1866B/73M1966B Data Sheet Reference and Regulation Table 17 lists the VBG specifications. VBG should be connected to an external bypass capacitor with a minimum value of 0.1 F. This pin is not intended for any other external use. The following conditions apply: VPX=5 V; Barrier Powered Mode; Barrier Data Rate across the Barrier=1.5 Mbps; VBG connected to 0.1 F external cap. Table 17: VBG Specifications Parameter VBG VBG noise VBG PSRR VPS VPS PSRR 3.7 Test Condition See conditions above. 300 Hz - 3.3 kHz 300 Hz - 30 kHz VPX=5.5 V VPX=4.5 V to 5.5 V Min - - 40 - - Nom 1.19 -86* - 3.15 40 Max - -80 - - - Units V dBm600 dB V dB DC Transfer Characteristics Table 18 lists the maximum DC transmit levels. All tests are driven at pin DCI and measured at pin DCS. DCEN=1. ILM=1. Table 18: Maximum DC Transmit Levels Parameter VDCON (DC "On" Voltage) With ENAC=0 DC Gain IDCI before ILIM IDCI after ILIM Delta VDCS Delta IDCI *Noise Rev. 1.6 Test Condition DCIV=00 DCIV=01 DCIV=10 DCIV=11 DCIV=XX VDCON<VDCI<0.4V+VDCON ILM=1 VDCI=0.28V+VDCON ILM=1 VDCI=0.44V+VDCON 8.245mA< VDCS < 8.260mA At the line with 300 (ac) (0.15 - 4.0 kHz) Min 0.62 0.83 1.08 1.32 0.20 -0.30 - 20 Nom 0.69 0.92 1.16 1.42 0.26 0 .0 - - Max 0.78 1.00 1.24 1.53 0.30 +0.25 10 - Units V V V V V dB A A - 0.85 - mA/V - -85 -80 dBm 23 73M1866B/73M1966B Data Sheet 3.8 DS_1x66B_001 Transmit Path Table 19 list the transmit path characteristics. A pattern for a sinusoid of 1 kHz, full scale (code word of +/- 32,767) from the 73M1x66B is forced and ACS is measured with R10=174 . Unless stated otherwise, test conditions are: ACZ=0000 (600 termination), THEN=1, ATEN=1, DAA=01, TXBST=0, sample rate=8kHz. Table 19: Transmit Path Parameter Offset voltage 8 and 16 kHz sample rate Tx gain, relative to DAA[1:0]=01 AC swing (1 kHz sinusoid) 8 and 16 kHz sample rate Idle noise THD Intermod distortion 1.0 kHz and 1.2 kHz summed Passband ripple Aliased image 24 Test Condition 50% 1's density relative to 1.4 V common mode. DAA=00 DAA=01 DAA=10 DAA=11 DAA=01 DAA=00 TXBST=1, DAA=xx ACZ=0001 ACZ=0010 ACZ=0011 ACZ=0100 ACZ=0101 ACZ=0110 ACZ=0111 ACZ=1000 ACZ=1001 ACZ=1010 ACZ=1011 ACZ=1100 ACZ=1101 ACZ=1110 ACZ=1111 300 Hz - 4 kHz 300 Hz - 4 kHz 300 Hz - 4 kHz 150 Hz - 3.3 kHz Gain relative to 1 kHz 0.5 kHz 1.0 kHz 2.0 kHz 3.3 kHz Fs +/- 1 kHz, relative to 1 kHz Min Nom Max Units - 25 - mV 2.5 -0.5 -4.5 -8.5 - - - - - - - - - - - - - - - - - - - - +3 0 -4 -8 0.317 0.447 0.634 0.211 0.211 0.200 0.254 0.220 0.171 0.194 0.222 0.205 0.223 0.313 0.208 0.211 0.285 0.235 -80 -80 3.5 0.5 -3.5 -7.5 - - - - - - - - - - - - - - - - - - - - dB dB dB dB Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk Vpk dBm dB - -85 - dB -0.125 - - - - - - - - 0.17 0 0.193 -0.12 -75 +0.125 - - - - - - dB dB dB dB dB dB dB Rev. 1.6 DS_1x66B_001 3.9 73M1866B/73M1966B Data Sheet Receive Path Table 20 lists the receive path characteristics. All test inputs are driven through an AC coupling network shown in Figure 29. The receive bit stream is measured at the DX pin. RXEN=1. Table 20: Receive Path Parameter Differential input resistance Input level Input level Overall sigma-delta ADC modulation gain inclusive of 73M1906B processing Offset voltage Rx gain (See Note 1.) Overall receive frequency response inclusive of 73M1906B processing Idle noise THD Intermod Dist 1.0 kHz and 1.2 kHz summed Crosstalk CMRR PSRR On-Hook AC Impedance Test Condition Min Nom Max Units RXP/RXM - 1000 - k Differential, RXP/RXM Common mode, RXP/RXM Normalized to VBG=1.19 V. RXG=00 Divide Vrxp/m by PCM Output R6=17.4 k, R8=52.3 k, R9=21 k. See Figure 12. RXG=00 RXG=01 RXG=10 RXG=11 RXBST=1, RXG=00 Relative to 1 kHz 0.3 kHz - 3.3 kHz - - 1.1 1.37 1.16 - Vpk V - 47.3 - V/bit - 0 +/- 30 mV -0.5 2.5 5.5 8.5 18.3 - -0.25 0 3 6 9 19.3 - 0 0.5 3.5 6.5 9.5 20.3 - +0.25 dB dB dB dB dB - dB Fs (8 kHz) - -75 - dB 300 Hz - 4 kHz RXG=00 RXBST=1 - - - -80 -85 -60 - - - dBm dB 300 Hz - 4 kHz - -85 - dB - -90 - dBm 40 - - dB - - 40* dB - 2 - M 1 Vpk 1 kHz sine wave at TXP; FFT on Rx ADC samples, first four harmonics reflected to the line. RXP=RXM 1 Vpk -30 dBm signal at VPX in Barrier Powered Mode; 300 Hz - 30 kHz. 300 Hz - 4 kHz, without EMI caps. Note 1: RXG controls the amount of gain or attenuation of the receiver analog gain element as specified in Table 20. The overall receiver channel gain has 6 dB of attenuation and the net effect of the RXG bits on the receiver channel gain is defined in Table 36. Rev. 1.6 25 73M1866B/73M1966B Data Sheet DS_1x66B_001 3.10 Transmit Hybrid Cancellation Table 21 lists the transmit hybrid cancellation characteristics. Unless stated otherwise, test conditions are: ACZ[3:0]=0000 (600 termination), THEN=1, ATEN=1, DAA[1:0]=01, TXBST=0. TXM is externally fed back into the 73M1916 to effect cancellation of transmit signal. Table 21: Transmit Hybrid Cancellation Characteristics Parameter Transmit hybrid cancellation Offset voltage AC swing Idle noise Test Condition Measure in 73M1906B 50% 1's density 1 kHz sinusoid 300 Hz - 4 kHz Min Nom Max Units - 20 - dB - 1.00 - 0 1.05 -80 25 1.10 - mV Vpk dBm 3.11 Receive Notch Filter Table 22 lists the receive notch filter characteristics. All measurements taken with RLPNEN=1, TXEN=0, RXG=00, ATEN=1. RXP is driven with 1 Vpk signal. Table 22: Receive Notch Filter Parameter Magnitude response Delay Magnitude response Delay 26 Test Condition Min Nom RLPNH=0 (12 kHz Notch) - 300 Hz 0.0 - 1 kHz +0.03 - 3 kHz +0.04 12 kHz -30 -50 - Passband Ripple (0.3 kHz - 3.4 kHz) +/- 0.15 - 28.8 - 300 Hz 28.93 - 1 kHz 30.25 - 3 kHz 41.62 - 12 kHz 9.95 RLPNH=1 (16 kHz Notch) - 300 Hz 0.0 - 1 kHz +0.04 3 kHz - +0.11 16 kHz -30 -50 - Passband Ripple (0.3 kHz - 3.4 kHz) +/- 0.15 - 30.53 - 300 Hz 30.66 - 1 kHz 31.93 - 3 kHz 42.26 - 16 kHz 4.74 Max Unit - - - - - - - - - - dB dB dB dB dB s s s s s - - - - - - - - - - dB dB dB dB dB s s s s s Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 3.12 Detectors This section provides electrical characteristics for the following detectors: * * * * Over-Voltage. Over-Current. Under-Voltage. Over-Load. 3.12.1 Over-Voltage Detector The values in Table 23 were measured between RGP and RGN. Table 23: Over-voltage Detector Parameter Over voltage levels Test Condition OVDTH=0 OVDTH=1 Min 0.52 0.59 Nom 0.6 0.7 Max 0.68 0.77 Unit V V Nom 1.025 Max 1.20 Unit V 3.12.2 Over-Current Detector The values in Table 24 were measured in Barrier Powered Mode. Table 24: Over-current Detector Parameter Over current level Test Condition Measured at DCS. Min 0.90 3.12.3 Under-Voltage Detector The values in Table 25 were measured in Barrier Powered Mode. In the recommended schematic (see Figure 12), disconnect Q5 collector and connect to an external power supply, VPE, through a 600 resistor. Table 25: Under-voltage Detector Parameter Under voltage detect Test Condition Measure VPE when UVD is detected as VPE is decreased. Min - Nom 7.5 Max - Unit V Nom 0.75 Max 0.9 Unit Vpk 3.12.4 Over-Load Detector The values in Table 26 were measured in Barrier Powered Mode. Table 26: Over-load Detector Parameter Over load level Rev. 1.6 Test Condition Measured at DCI with 1 kHz. Min 0.6 27 73M1866B/73M1966B Data Sheet DS_1x66B_001 4 Applications Information This section provides general usage information for the design and implementation of the 73M1x66B. 4.1 Example Schematic of the 73M1966B and 73M1866B Figure 12 shows a typical application schematic for the implementation of the 73M1966B. Figure 13 shows a typical application schematic for the implementation of the 73M1866B. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information. For more information about schematic and layout design, see the 73M1866B/73M1966B Schematic and Layout Guidelines. C1 0.022uF, 200V C3 0.022uF, 200V R5 8.2, 0805 2 4 2 DR DX FSIO CLKO CLKI AUDIO CS VPD DR DX FS PCLKO PCLKI VNA/VND AOUT VPA U2 SCLK INT SDO SDI SDIT RST VPT PRP PRM VNT 20 19 18 17 16 15 14 13 12 11 T1 1 4 C14 15pF 2 3 SCP C10 0.22uF C26 1nF C13 15pF DCG DCS DCD TXM RXM RXP VPS VNS ACS VBG DCI RGN RGP OFH VNX SCP MID VPX SRE SRB U1 240 5.1K MMBTA42 1 Q3 R2 10M, 0805 TIP RING L2 2K Ohms @ 100 MHz R3 412K, 1% R69 100K* R65 200 73M1916-20 C48 0.1uF R6 17.4K, 1% R4 100K, 1% NOTE: GND for C35 and C36 should be on the host side of the barrier 3 R11 3K C49 100pF SRB 1 C45 + 3.3uF Q5 2 C31 0.1uF R12 C20 1nF VCC E1 P3100SBRP TISP4290T3BJ Q4 MMBTA92 1 73M1906B-20 C9 0.22uF C33 1nF 20 19 18 17 16 15 14 13 12 11 C41 220pF, 300V 3 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 - 2 2 R58 10uF CS\ F1 TRF600-150 BR1 HD04 1 + Q6 BCP-56 3 0.1uF 1 + 3 1nF C4 2 C17 3 C30 L1 2K Ohms @ 100 MHz Q7 MMBTA42 VPS C21 3.3uF 1 1 VCC + TP14 OFH R66 1M, 0805 4 R68 1M, 0805 3 RST\ SDITHRU SDI SDO INT\ SCLK SRE 1 MMBTA06 R8 52.3K, 1% TP15 VPS R9 21K, 1% C7 4.7uF, 25V C37 0.01uF C12 0.1uF R10 C8 + 174, 1% C38 0.1uF C43 1nF D1 MMSZ4710T1* 4.7uF C24 ISOLATION BARRIER C39 5.6nF C36 220pF, 3KV C35 220pF, 3KV NC (TBD as needed, 3KV) Figure 12: Recommended Circuit for the 73M1966B 28 Rev. 1.6 73M1866B/73M1966B Data Sheet 3 DS_1x66B_001 2 Q5 MMBTA06 R8 52.3K, 1% 1 C37 0.01uF C7 4.7uF, 25V D1 MMSZ4710T1* R9 21K, 1% R6 17.4K, 1% L1 R66 1M, 0805 2 kOhm@100MHz C1 0.022uF, 200V VNS R10 174, 1% C41 C12 0.1uF C38 0.1uF C8 4.7uF R68 1M, 0805 C43 1nF 220pF, 300V C3 0.022uF, 200V C35 + VNS 22 23 24 25 26 27 28 29 30 31 BR1 C45 + C33 3.3uF 0.1uF 2 32 33 34 35 36 37 38 39 40 41 42 Q4 MMBTA92 3 R2 10M C36 3 Q3 MMBTA42 3 1 R12 5.1K 1 C4 C20 1nF C9 0.22uF 10uF + RING 220pF, 3kV R3 412K, 1% R5 8.2 C48 R11 3K R65 200 R4 100K, 1% C39 5.6nF C49 100pF L2 2 kOhm@100MHz 0.1uF VNS U1 VNS C26 1nF 10 9 8 7 6 5 4 3 2 1 1nF C31 73M1866B TIP HD04 DCS DCG DCI RGN RGP OFH M20PB VNX SCP MID VPX 3 SPI OUT SPI IN SDITHRU RSTB VCC DR CS SCLK INT VND SDO SDI SDIT RST VPT PRP - 2 2 21 20 19 18 17 16 15 14 13 12 11 E1 P3100SBRP 1 + PRM VNT VPA AOUT PCLKI VNA PCLKO FS VPD DX PCM TX SPI CSB SPI CLK INTB R69 100K* SRE SRB VBG ACS VNS VPS RXP RXM TXM DCD Maintain 2.5 mm Spacing Between Line and Host Side Components F1 TRF600-150 4 220pF, 3kV C10 0.22uF Q7 1 NOTE: GND for C35 and C36 should be on the host side of the barrier 2 MMBTA42 4 R58 2 4 1 C13 15pF PCM FS PCM RX AOUT 240 PCM CLKIN PCM CLKO C14 15pF 3 T1 Pulse Transf ormer C24 NC (as needed, 3KV) 3 1 2 Q6 BCP56 Isolation Barrier VCC C21 + 3.3uF C17 0.1uF C30 1nF Figure 13: Recommended Circuit for the 73M1866B Rev. 1.6 29 73M1866B/73M1966B Data Sheet 4.2 DS_1x66B_001 Bill of Materials Table 27 provides the 73M1x66 bill of materials for the reference schematics provided in Figure 12 and Figure 13. Table 27: Reference Bill of Materials for 73M1x66B Qty Reference 1 2 1 1 1 2 2 1 1 1 1 BR1 C1, C3 C4 C7 C8 C9, C10 C12,C17,C31, C38, C48 C13, C14 C20, C26, C30, C33, C43 C21, C45 C37 C39 C49 D1 1 Q5 1 Q4 2 Q3, Q7 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 Q6 R2 R3 R4 R5 R6 R8 R9 R10 R11 R12 R58 R65 R66, R68 R69* T1 4 2 5 Part Description Source Example MFR P/N HD04 rectifier bridge, 0.8A, 400V 0.022F 200V, X7R, 1206 10F 6.3V, tantalum, 0805 4.7F 25V, X5R, 0805 4.7uF 6.3V, tantalum, 0805 0.22F 16V, X7R, ceramic, 0603 0.1F 16V, X7R, ceramic, 0603 Diodes Inc. Panasonic AVX, Panasonic AVX, Panasonic Rohm Panasonic HD04-T ECJ-3FB2D223K TCP0J106M8RA 08053D475KAT2A TCP0J475M8R C0603C224K8RACTU Panasonic, Kemet C0603C104K8RACTU 15pF 50V, ceramic, 0603 1nF 10V, X7R, ceramic, 0603 Panasonic Panasonic ECJ-1VC1H150J C0603C102K8RACTU 3.3F 6.3V, tantalum, 0805 0.01F 50V, X7R, ceramic, 0603 5.6nF 50V, X7R, 10% ceramic, 0603 100pF 50V, ceramic, 0603 25V, 500mW Zener diode MMBTA06, NPN 80 V transistor SOT23 MMBTA92, PNP 300 V transistor SOT23 MMBTA42, NPN 300 V transistor SOT23 NPN 80 V transistor SOT223 10M, 5%, 1/8W resistor 0805 412K, 1%, 1/10W resistor 0603 100K, 1%, 1/10W resistor 0603 8.2, 5%, 1/8W resistor 0805 17.4K, 1%, 1/10W resistor 0603 52.3K, 1%, 1/10W resistor 0603 21K, 1%, 1/10W resistor 0603 174, 1%, 1/10W resistor 0603 3K, 5%, 1/10W resistor 0603 5.1 K, 5%, 1/10W resistor 0603 240, 5%, 1/10W resistor 0603 200, 5%, 1/10W resistor 0603 1 M, 5%, 1/8W resistor 0805 100K typ. 5%, 1/10W resistor 0603 Pulse transformer Rohm AVX, Panasonic Panasonic Taiyo Yuden ON Semi Diodes, Fairchild, Central, On Semi Diodes, Fairchild, Central, On Semi Diodes, Fairchild, Central, On Semi Fairchild, On Semi Yageo Yageo Yageo Yageo Yageo Yageo Yageo Yageo Yageo Yageo Yageo Yageo Yageo Yageo See Table 29. TCP0J335M8R 06035C103KAT2A ECJ-1VB1H562K UMK107CH101JZ-T MMSZ4710T1, MMBTA06LT1G MMBTA92LT1G MMBTA42LT1G BCP56 RC0805JR-0710ML RC0603FR-07412KL RC0603FR-07100KL RC0805JR-078R2L RC0603FR-0717K4L RC0603FR-0752K3L RC0603FR-0721KL RC0603FR-07174RL RC0603JR-073K0L RC0603JR-075K1L RC0603JR-07240RL RC0603JR-07200RL RC0603JR-071ML RC0603JR-07100KL * Optional - see the 73M1866B/1966B Schematics and Layout Guidelines for details. 30 Rev. 1.6 DS_1x66B_001 4.3 73M1866B/73M1966B Data Sheet Over-Voltage and EMI Protection Over-voltage protection is required to meet worst-case conditions for target countries. UL1950, EN60950, IEC 60950, ITU-T K.20/K.21 and GR-1089-CORE specifications define the protection requirements for many countries. A single design can be implemented to meet all these requirements. Figure 14 shows a recommended protection circuit topology. Fuse (F1) should be rated appropriately for the country of operation, and the bidirectional thyristor (E1) should have a minimum break-over of 220 V, a maximum break-over of 275 V and be able to survive a 100 A fast transient. In addition to over-voltage and current protection, the 73M1x66B should make provisions to prevent EMI emissions and EMC susceptibility. Figure 14 also illustrates how L1, L2, C35, C36 and C41can provide this suppression. The ferrite beads, L1 and L2, should be capable of passing 150 mA and have an impedance of 2K at 100 MHz. C35, C36 and C41 should be between 47pF and 220nF, and rated for a breakdown voltage greater than the highest isolation voltage or line voltage that is required for country compatibility. C35 and C36 should be returned to an earth ground. EMI suppression is highly dependent on the physical design of the overall circuit and not all the suppression components may be needed in every design and application. L1 2K Ohm @ 100MHz F1 TR600-150 T C41 220pF, 300V E1 P3100SBRP L2 2K Ohm @ 100MHz or equiv . J1 6 5 4 3 2 1 RJ-11 R C36 220pF, 3kV C35 220pF, 3kV Figure 14: Suggested Over-Voltage Protection and EMI Suppression Circuit Table 28: Reference Bill of Materials for Figure 14 Reference Part Description Source Example MFR P/N E1 Bidirectional Thyristor Diodes Inc., Bourns TB3100H-13-H, TISP4290T3BJR-S F1 PPTC Fuse Tyco, Bourns MF-R015/600 or equiv. L1,L2 2 K @ 100 MHz, 150 mA min, 0805 Steward, TDK MPZ2012S601A C35, C36 220 pF, 3000 V TDK C4532COG3F221K C41 220 pF, 300 V Vishay VJ1206Y221KXEAT5Z Rev. 1.6 31 73M1866B/73M1966B Data Sheet 4.4 DS_1x66B_001 Isolation Barrier Pulse Transformer The isolation element used by the 73M1x66B is a standard digital pulse transformer. Several vendors supply compatible transformers with up to 6000 V ratings. Since the transformer is the only component crossing the isolation barrier other than EMI capacitors that may be required, it solely determines the isolation between the PSTN and the FXO's digital interface. This method of isolation is significantly superior to other isolation techniques with major advantages in high common mode voltage operation, lower radiated noise (EMI) and improved operation in noisy environments. Table 29 lists some pulse transformers compatible with the 73M1x66B. The table also includes low-voltage transformers that offer low-cost alternatives if such voltages are sufficient. Table 29: Compatible Pulse Transformer Sources Company Sumida Wurth Electronics Midcom Inc. UMEC Datatronics AAsupreme Number ESMIT 4180 ESMIT 4181 750110001 TG-UTB01543S PT79280 P950003 Table 30 lists some of the typical pulse transformer specifications used by the 73M1x66B. Contact the manufacturer directly for product information. Table 30: Pulse Transformer Electrical Characteristics Parameter Inductance Interwinding Capacitance Turn Ratio DC Resistance Dielectric Breakdown Voltage ET Constant Surge Test Operating Temperature 32 Test Condition 100 kHz, 10 mVAC, 1-2, Ls. - Min 54 - Nom 60 - Max 200 6 Tolerance - - Unit H pF - Primary Secondary 1 sec - - - 2000 1:1 - - 3750 - 0.25 0.25 - 2 % - - - N/A Vrms - 1.2 x 50 s - - 2800 -40 1.2 6000 - - - - - Vs V C 85 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 5 SPI Interface The host accesses the 73M1x66B using an SPI interface to write to control registers and read status registers. The host is the master of the transaction. Four pins orchestrate the communication between the host and the SPI, and a fifth pin is dedicated to support the daisy-chain mode. The signals are as follows: * * * * * SDI SDO SCLK CS SDIT Serial data input driven by the host. Serial data output driven by the 73M1x66B. Clock input driven by the host. Chip select input driven by the host. Serial data output for daisy-chain mode. The SPI implemented by the 73M1x66B has the following key features: * * * * Support for 8-bit and 16-bit mode operations. Support for daisy-chain operations. Support for both continuously active SCLK or SCLK active during transfers only. Support for broadcast mode. Transactions between the host and the 73M1x66B require three bytes. All bytes are transmitted most significant byte first. The first is the control byte, the second the address byte and the third is the data byte. The control byte is structured as follows: Bit 7 BRCT Bit 6 R/W Bit 5 X Bit 4 X Bit 3 CID[0] Bit 2 CID[1] Bit 1 CID[2] Bit 0 CID[3] The value of CID[0:3] determines which 73M1x66B in the daisy chain should execute the read or write operation requested by the host. Up to 16 devices in the daisy chain can be supported. The daisy chain organization is shown in Figure 15. The control byte is submitted to the first 73M1x66B in the daisy chain. If the value of CID[0:3] is different from zero, the SPI of that device decreases the value of CID[0:3] by one and passes the new value through SDIT to the next 73M1x66B in the chain. This process continues until CID[0:3] is zero, thus stopping at the device designated to execute the operation. The value of CID will be the position in the daisy chain for the device being addressed minus one. If the host is controlling only one 73M1x66B, CID[0:3] must be set to 0. The BRCT bit overrides the chip addressing driven by CID[0:3]. The host asserts BRCT for all write operations that must be executed by all 73M1x66B devices in the chain. At that time, whatever comes in SDI comes out through SDIT. BRCT does not affect read operations. Rev. 1.6 33 73M1866B/73M1966B Data Sheet DS_1x66B_001 CIDin SDI SDO SCLK HOST SCLK CS CS SDI SDO 73M1906B Channel 0 SDITHRU CID=CIDin-1 SDI SCLK CS 73M1906B Channel 1 SDO SDITHRU CID=CIDin-2 ... CID=000 (target) SDI SCLK CS 73M1906B Channel 15 SDO SDITHRU Figure 15: Daisy-Chain Configuration The R/W bit determines whether the host requests a read (1) or a write (0) operation. The second byte of the SPI transaction is the address byte. The address byte simply contains the 8-bit value for the register targeted by the operation. For the 73M1x66B, only six bits of the address are relevant for the register space, and the two most-significant bits of the address byte are always set to 0. The third byte of the SPI transaction is the data byte. It contains the data to write to the addressed 73M1x66B registers or the data read from the addressed 73M1x66B register. In the 8-bit mode, the three bytes are exchanged over three frames, as directed by CS. Figure 16 and Figure 17 show a write and read transaction between the 73M1x66B and the host in 8-bit mode. CS SCLK SDI CONTROL ADDRESS DATA [7:0] HI-Z SDO Figure 16: SPI Write Operation - 8-bit Mode 34 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet CS SCLK SDI CONTROL ADDRESS DATA [7:0] HI-Z SDO DATA [7:0] Figure 17: SPI Read Transaction - 8-bit Mode In 16-bit mode, the first frame of 16 bits contains both the control and address bytes, and the second frame contains the data bytes. Note that the second part of the second frame is irrelevant. Figure 18 and Figure 19 show the write and read transactions in 16-bit mode. CS SCLK SDI CONTROL ADDRESS DATA[7:0] XXXXXXXX HI-Z SDO Figure 18: SPI Write Transaction - 16-bit Mode CS SCLK SDI SDO CONTROL ADDRESS XXXXXXXX XXXXXXXX DATA[15:8] DATA[7:0] HI-Z Figure 19: SPI Read Transaction - 16-bit Mode The transaction diagrams show the case where SCLK is only active during the transaction frames. The same transaction remains valid even if SCLK runs continuously, regardless of frame boundaries. The SPI state machine resets when the host sends a frame containing a number of SCLK periods different from a multiple of eight: Rev. 1.6 35 73M1866B/73M1966B Data Sheet * * 36 DS_1x66B_001 In 8-bit mode, if either the control or the address frames do not correspond to a multiple of eight SCLK cycles, the SPI state machine resets and the transaction is aborted. If the data frame is shorter than eight SCLK cycles, the state machine resets and the transaction is aborted. If the data frame is longer than eight SCLK cycles, while not being a multiple of eight cycles, the write/read transaction is performed and the state machine resets. In 16-bit mode, if the control/address frame does not contain a multiple of eight SCLK cycles, the SPI state machine resets and the transaction is aborted. If the data frame is shorter than eight SCLK cycles, the state machine resets and the transaction is aborted. If the data frame is longer than eight SCLK cycles, while not being a multiple of eight cycles, the write/read transaction is performed and the state machine resets. This scheme can be used to reset the SPI if one looses track of frames. Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 6 Control and Status Registers Table 31 shows the 73M1x66B register map of addressable registers. The shaded cells indicate read-only bits and cannot be modified. Reserved bits should be left in their default state. Accessing unspecified registers should be avoided. Each register and bit is described in detail in the following sections. For registers 0x12 through 0x1F, which are located in the Line-Side Device, there is a minimum time between consecutive write transactions of 300 s when using an 8 kHz sample rate. Table 31: Control and Status Register Map Address (hex) Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 02 10h TMEN Reserved Reserved Reserved Reserved ENLPW Reserved Reserved 03 E0h GPIO7 GPIO6 GPIO5 PCLKDT RGMON DET SYNL RGDT 04 E4h DIR7 DIR6 DIR5 Reserved REVHSD3 REVHSD2 REVHSD1 REVHSD0 05 1Bh ENGPIO7 ENGPIO6 ENGPIO5 ENPCLKDT ENAPOL ENDET ENSYNL ENRGDT 06 00h POL7 POL6 POL5 Reserved Reserved Reserved Reserved Reserved 07 00h Reserved Reserved Reserved Reserved Reserved Reserved DTST1 DTST0 08 00h TXDG -12 TXDG -6 TXDG +3.5 TXDG +2 TXDG +1 TXDG +0.5 TXDG +0.25 TXDG +0.125 09 00h RXDG -12 RXDG -6 RXDG +3.5 RXDG +2 RXDG +1 RXDG +0.5 RXDG +0.25 RXDG +0.125 0D 40h LOKDET SLHS Reserved Reserved RSTLSBI Reserved 0E 00h FRCVCO Reserved Reserved Reserved Reserved Reserved RGTH1 RGTH0 0F 80h ENFEH PWDN SLEEP Reserved Reserved Reserved Reserved Reserved 10 00h Reserved Reserved Reserved CMVSEL CMTXG1 CMTXG0 CMRXG1 CMRXG0 12 00h OFH ENDC ENAC ENSHL ENLVD ENFEL ENDT ENNOM 13 00h DCIV1 DCIV0 ILM Reserved PLDM OVDTH IDISPD SEL16K 14 00h TXBST DAA1 DAA0 Reserved RXBST RLPNH RXG1 RXG0 15 00h ENOLD DISNTR Reserved CIDM THEN ENUVD ENOVD ENOID 16 00h TXEN RXEN RLPNEN ATEN ACZ3 ACZ2 ACZ1 ACZ0 17 00h Reserved Reserved RXOCEN Reserved Reserved Reserved Reserved Reserved 18 01h TEST3 TEST2 TEST1 TEST0 Reserved Reserved Reserved Reserved Reserved Reserved 19 00h POLL MATCH Reserved Reserved INDX3 INDX2 INDX1 INDX0 1A 00h RNG7 RNG6 RNG5 RNG4 RNG3 RNG2 RNG1 RNG0 1B 00h LV7 LV6 LV5 LV4 LV3 LV2 LV1 Reserved 1C 00h LC6 LC5 LC4 LC3 LC2 LC1 LC0 Reserved 1D 00h REVLSD3 REVLSD2 REVLSD1 REVLSD0 Reserved Reserved Reserved Reserved 1E 00h ILMON UVDET OVDET OIDET OLDET SLLS Reserved Reserved 1F 00h POLVAL7 POLVAL6 POLVAL5 POLVAL4 POLVAL3 POLVAL2 POLVAL1 POLVAL0 20 00h TPOL TTS6 TTS5 TTS4 TTS3 TTS2 TTS1 TTS0 21 00h RPOL RTS6 RTS5 RTS4 RTS3 RTS2 RTS1 RTS0 22 00h SR ADJ RCS2 RCS1 RCS0 TCS2 TCS1 TCS0 23 00h PCMEN MASTER PCODE3 PCODE2 PCODE1 PCODE0 LIN LAW 24 00h Reserved Reserved Reserved Reserved Reserved Reserved Reserved LB 25 00h RXOM7 RXOM6 RXOM5 RXOM4 RXOM3 RXOM2 RXOM1 RXOM0 Rev. 1.6 37 73M1866B/73M1966B Data Sheet DS_1x66B_001 Throughout this document, type W is read/write, type WO is write only and type R is read only. Registers and bits are defined as 0x16[3:0], where 0x16 is the register address and the numbers in square brackets specify the address bits. The bit order is [msb - lsb] for a field. For example, [3:0] means bits 3 through 0 of a particular field. Table 32: Alphabetical Bit Map Bit Name ACZ ADJ ATEN CIDM CMRXG1/0 CMTXG1/0 CMVSEL DAA1/0 DCIV1/0 DET DIR5 DIR6 DIR7 DISNTR DTST1/0 ENAC ENAPOL ENDC ENDET ENDT ENFEH ENFEL ENGPIO7 ENGPIO6 ENGPIO5 ENLPW ENLVD ENNOM ENOID ENOLD ENOVD ENPCLKDT ENRGDT ENSHL ENSYNL ENUVD FRCVCO GPIO5 GPIO6 GPIO7 IDISPD ILM ILMON INDX LAW LB LC LIN LOKDET 38 Register 0x16[3:0] 0x22[6] 0x16[4] 0x15[4] 0x10[1:0] 0x10[3:2] 0x10[4] 0x14[6:5] 0x13[7:6] 0x03[2] 0x04[5] 0x04[6] 0x04[7] 0x15[6] 0x07[1:0] 0x12[5] 0x05[3] 0x12[6] 0x05[2] 0x12[1] 0x0F[7] 0x12[2] 0x05[7] 0x05[6] 0x05[5] 0x02[2] 0x12[3] 0x12[0] 0x15[0] 0x15[7] 0x15[1] 0x05[4] 0x05[0] 0x12[4] 0x05[1] 0x15[2] 0x0E[7] 0x03[5] 0x03[6] 0x03[7] 0x13[1] 0x13[5] 0x1E[7] 0x19[3:0] 0x23[0] 0x24[0] 0x1C[7:1] 0x23[1] 0x0D[7] Page 68 52 69 75 44 44 44 52 69 76 43 43 43 61 79 69 61 69 76 76 42 70 43 43 43 61 70 70 77 77 77 52 75 70 61 76 42 43 43 43 69 70 70 40 52 79 76 52 42 Default 0000 0 0 0 00 00 0 00 00 0 1 1 1 0 00 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 Type W W W W W W W WO WO R W W W WO W WO W WO W WO W WO W W W W WO WO WO WO WO W W WO W WO W W W W WO WO R W W W R R/W R Category DAA Control Function PCM Control Function DAA Control Function DAA Control Function Call Progress Monitor Call Progress Monitor Call Progress Monitor PCM Control Function DAA Control Function Line Sensing Control GPIO Control GPIO Control GPIO Control Barrier Control Function Loopback Control DAA Control Function Barrier Control Function DAA Control Function Line Sensing Control Line Sensing Control Power Management Current Limiting Detection Control and Status GPIO Control GPIO Control GPIO Control Barrier Control Function Current Limiting Detection Control and Status DAA Control Function Over-Current Detection Control and Status Over-Load Detection Control and Status Over-Voltage Detection Control and Status PCM Control Function Ring Detection Function Current Limiting Detection Control and Status Barrier Control Function Under-Voltage Detection Control and Status Device Clock Management GPIO Control GPIO Control GPIO Control DAA Control Function Current Limiting Detection Control and Status Current Limiting Detection Control and Status Line-Side Device Register Polling PCM Control Function Loopback Control Function Auxiliary A/D Converter Status PCM Control Function Device Clock Management Rev. 1.6 DS_1x66B_001 Bit Name LV MASTER MATCH OFH OIDET OLDET OVDET OVDTH PCLKDT PCMEN PCODE PLDM POL7 POL6 POL5 POLL POLVAL PWDN RCS REVHSD REVLSD RGDT RGMON RGTH1/0 RLPNEN RLPNH RNG RPOL RSTLSBI RTS RXBST RXDG RXEN RXG0 RXG1 RXOCEN RXOM SLEEP SLHS SLLS SR SYNL TCS THEN TMEN TPOL TEST TTS TXBST TXDG TXEN UVDET Rev. 1.6 Register 0x1B[7:1] 0x23[6] 0x19[6] 0x12[7] 0x1E[4] 0x1E[3] 0x1E[5] 0x13[2] 0x03[4] 0x23[7] 0x23[5:2] 0x13[3] 0x06[7] 0x06[6] 0x06[5] 0x19[7] 0x1F[7:0] 0x0F[6] 0x22[5:3] 0x04[3:0] 0x1D[7:4] 0x03[0] 0x03[3] 0x0E[1:0] 0x16[5] 0x14[2] 0x1A[7:0] 0x21[7] 0x0D[3] 0x21[6:0] 0x14[3] 0x09[7:0] 0x16[6] 0x14[0] 0x14[1] 0x17[5] 0x25[7:0] 0x0F[5] 0x0D[6] 0x1E[2] 0x22[7] 0x03[1] 0x22[2:0] 0x15[3] 0x02[7] 0x20[7] 0x18[7:4] 0x20[6:0] 0x14[7] 0x08[7:0] 0x16[7] 0x1E[6] 73M1866B/73M1966B Data Sheet Page 76 52 41 70 77 77 77 77 52 52 53 70 43 43 43 40 40 42 53 41 41 78 78 75 71 71 76 53 62 53 75 54 54 54 54 54 54 42 62 62 55 62 55 71 79 55 79 55 55 56 56 76 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0100 0 0 0 0 0 0 0 0 0 0000000 0 00000000 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0000000 0 00000000 0 0 Type R W R WO R R R WO R W W WO W W W W R W W R R R R W W W R W W W WO WO WO WO WO W W W R R W R W W W W W W WO WO WO R Category Auxiliary A/D Converter Status PCM Control Function Line-Side Device Register Polling DAA Control Function Over-Current Detection Control and Status Over-Load Detection Control and Status Over-Voltage Detection Control and Status Over-Voltage Detection Control and Status PCM Control Function PCM Control Function PCM Control Function DAA Control Function GPIO Control Function GPIO Control Function GPIO Control Function Line-Side Device Register Polling Line-Side Device Register Polling Power Management PCM Control Function Device Revision Device Revision Ring Detection Function Ring Detection Function Ring Detection Function DAA Control Function DAA Control Function Auxiliary A/D Converter Status PCM Control Function Barrier Control Function PCM Control Function PCM Control Function PCM Control Function PCM Control Function PCM Control Function PCM Control Function PCM Control Function PCM Control Function Power Management Barrier Control Function Barrier Control Function PCM Control Function Barrier Control Function PCM Control Function DAA Control Function Loopback Control Function PCM Control Function Loopback Control Function PCM Control Function PCM Control Function PCM Control Function PCM Control Function Under-Voltage Detection Control and Status 39 73M1866B/73M1966B Data Sheet DS_1x66B_001 While all registers may be read or written to via an SPI operation without error, some registers react differently to read and write operations, as follows: * Read/Write (W) registers change in response to an SPI write transaction and report their correct current value for a read SPI transaction. * Read Only (R) registers do not change in response to an SPI write transaction but report their correct current value for a read SPI transaction. * Write Only (WO) registers are shadow registers to corresponding registers on the Line-Side Device (0x12-0x18) that are written to during the barrier communications, and so are written to indirectly. The true contents of these Line-Side registers cannot be read directly from the shadow registers representing them, but these Line-Side registers can be read using the polling register described in 6.1. Certain events, such as lightning or voltage surges, could corrupt the contents of the Line-Side registers, so to verify their contents, the polling registers (0x19 and 0x1F) must be used. 6.1 Line-Side Device Register Polling The Register Map as read from a 73M1x66B Host-Side Device consists of two groups. The first is the Host-Side Device registers (0x00 through 0x10 and 0x20 through 0x24) and the second is a copy of the Line-Side Device registers (0x12 through 0x1F). As an extra degree of integrity, the 73M1x66B supports the ability to manually monitor the registers of its Line-Side Device. This is achieved by using the Manual Poll Function. The Line-Side registers that can be polled are 0x12 through 0x18 (index values 0x0-0x6 respectively). The method is to write the offset address of the Line-Side Device register to be read into the INDX field. The value of this is the offset index from 0x12; that is, Register 0x12 is 0x0, 0x13 is 0x1, etc. The next step is to set the POLL bit, which causes the device to read the requested register from the Line-Side Device. The value of the requested Line-Side Device register is written by the Line-Side Device into POLVAL (0x1F). This value is compared with that of the Host-Side copy and, if they are the same, the MATCH bit is set to 1. The values presented at MATCH and POLVAL are valid approximately 600 s after a poll request, and are valid only after the POLL bit has been reset by the Host-Side Device. Function Mnemonic INDX Register Location 0x19[3:0] MATCH 0x19[6] R POLL 0x19[7] W POLVAL 0x1F[7:0] R 40 Type Description W Index Address of the register to be manually polled with the results placed in POLVAL. This address should be cleared after the poll. Default = 0. Polling Match 0 = No match. (Default) 1 = This read-only bit indicates that there is match with the corresponding polled register in the Host-Side Device. The result of the polling function can be read only after the POLL bit is reset to zero by the 73M1x66B. Polling Enable 0 = Polling disabled. (Default) 1 = Manually polls the control register in the Line-Side Device whose address is given by INDX. The Poll bit remains high until the MATCH result is available at which time it will be reset to 0 and the MATCH bit status can be read. Polling Value When 73M1x66B is polled, the content of the Line-Side Device Register given by the offset address in INDX is placed in this register. Default = 0. This register can be read after the POLL bit has been reset to zero, indicating the result is ready. Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 7 Hardware Control Functions This section describes the 73M1x66B capabilities with respect to its configuration and hardware pin control. These include features such as Device Revision, Interrupt Management, Power Management, Clock Control, General Purpose Input/Output (GPIO) and control of the Call Progress Monitor. 7.1 Device Revision The 73M1x66B provides the device revision number for the Host-Side Device and the Line-Side Device. For the 73M1x66B: * * Revision for the Host-Side Device is: 0100. Revision for the Line-Side Device is: 1101. Function Mnemonic REVHSD Register Location 0x04[3:0] REVLSD 0x1D[7:4] 7.2 Type Description R Host-Side Device Revision These read only status bits indicate the revision of the 73M1x66B Host-Side Device (73M1906B). Line-Side Device Revision These read-only status bits provide the Device ID for the 73M1x66B Line-Side Device (73M1916). When barrier is synchronized, REV has the value of 1101. When barrier is not synchronized, the value of the field is 0000. R Interrupt Control The 73M1x66B supports a single interrupt that can be asserted under several configurable conditions. These include status of GPIOs, PCLKDT, RGMON, DET, SYNL and RGDT. All interrupt sources that are enabled are ORed together to create the INT output signal. GPIO ports that are configured to be output will not generate interrupts. When the INT pin goes active (low), the host should read the interrupt source Register 0x03, which is then automatically cleared after the read operation. An interrupt during wake-on-ring should be interpreted as the detection of a valid ring signal. Address 0x03 Reset State E0h Bit 7 GPIO7 Rev. 1.6 Bit 6 GPIO6 Bit 5 GPIO5 Bit 4 PCLKDT Bit 3 RGMON Bit 2 DET Bit 1 SYNL Bit 0 RGDT 41 73M1866B/73M1966B Data Sheet 7.3 DS_1x66B_001 Power Management The 73M1x66B supports three modes of power control for the device. Normal mode ENFEH = 0 Sleep mode Power Down The 73M1x66B operates normally. In this mode the Host Side of the Barrier interface is disabled and the line side device is disabled. The Host side continues to operate normally. The device PLL is turned off and PCLK is propagated on the clock tree. The PCM DX and TSC outputs are tri-stated. Control and status registers of the Host side maintain their content. The device is shut down altogether. The registers remain accessible through the SPI. Control and status registers of the Host side maintain their content. To restart the PCM operations, the PCODE register must be set for the appropriate PCLK frequency value. In all reduced power modes of operation the SPI interface remains active. Function Mnemonic ENFEH Register Location 0x0F[7] PWDN 0x0F[6] W SLEEP 0x0F[5] W 7.4 W Description Enable Front End Host 1 = Enable Front End of the 73M1906B Host-Side Device. (Default) 0 = Disable Front End of the 73M1906B Host-Side Device. Power Down Mode 0 = Disable Power Down Mode. (Default) 1 = Enable Power Down Mode. Sleep Mode 0 = Disable Sleep Mode. (Default) 1 = Enable Sleep Mode. Device Clock Management Function Mnemonic FRCVCO Register Location 0x0E[7] LOKDET 0x0D[7] 42 Type Type W R Description Force VCO 0 = The system clock is the same as PCLK. (Default) 1 = The system clock is derived from locked PLL. This is set to 0 upon reset, Sleep or Power Down mode enabled. Phase Locked Loop Lock Detect 0 = PLL is not locked. (Default) 1 = PLL is locked to PCLK. Rev. 1.6 DS_1x66B_001 7.5 73M1866B/73M1966B Data Sheet GPIO Registers Three user-defined I/O pins are provided in the 32-pin QFN package of the 73M1966B only. The pins are GPIO7, GPIO6 and GPIO5. GPIO pins are not available on the 20-pin package of the 73M1966B. GPIO pins are not available on the 42-pin package of the 73M1866B. Each pin can be configured independently as either an input or an output by writing to the corresponding I/O Direction (DIR) register. At power on and after a reset, the GPIO pins are initialized to a high impedance state to avoid unwanted current contention and consumption. The input structures are protected from floating inputs, and no output levels are driven by any of the GPIO pins. The mapping of GPIO pins is designed to correspond to the bit location in their control and status registers. The 73M1x66B supports the ability to generate an interrupt on the INT pin. The source can be configured to generate on a rising or a trailing edge. Only GPIO ports that are configured as inputs can be used to generate interrupts. Function Mnemonic DIR Register Location 0x04[7:5] GPIOn 0x03[7:5] W ENGPIOn 0x05[7:5] W POLn 0x06[7:5] W Rev. 1.6 Type Description W GPIO Input/Output Select These control bits are used to designate the GPIO pins as either inputs or outputs. 0 = GPIO pin is defined as an output. 1 = GPIO pin is defined as an input. (Default) GPIO State These bits reflect the status of the GPIO7, GPIO6 and GPIO5 pins. If the DIR bit is reset, reading this field returns the logical value of the appropriate GPIOn pin as an input. If the DIR bit is set, the pins output the logical value as written. GPIO Enable Each of the GPIO enable bits in this register enables the corresponding GPIO bit as an edge-triggered interrupt source. If a GPIO bit is set to one, an edge (which edge depends on the value in the GIP register) of the corresponding GPIO pin will cause the INT pin to go active low, and the edge detectors will be rearmed when the GPIO data register is read. GPIO Interrupt Edge Selection Defines the interrupt source as being either on a rising or a falling edge of the corresponding GPIO pin. 0 = A rising edge will trigger an interrupt from the corresponding pin. (Default) 1 = A falling edge will trigger an interrupt from the corresponding pin. 43 73M1866B/73M1966B Data Sheet 7.6 DS_1x66B_001 Call Progress Monitor For the purpose of monitoring activities on the line, a Call Progress Monitor is provided in the 73M1x66B. This audio output contains both transmit and receive data with configurable levels. Function Mnemonic CMRXG Register Location 0x10[1:0] Type W Description Receive Path Gain Setting 00 01 10 11 CMTXG 0x10[3:2] W Transmit Path Gain Setting 00 01 10 11 CMVSEL 7.7 0x10[4] W 0 dB (for full swing, AOUT=1.08 Vpk) (Default) -6 dB -12 dB MUTE 0 dB (for full swing, AOUT=1.08 Vpk) (Default) -6 dB -12 dB MUTE Call Progress Monitor Voltage Reference Select Quiescent DC voltage select at AOUT. 0 = 1.5 Vdc. (Default) 1 = VCC/2 Vdc. 16 kHz Operation of Call Progress Monitor After switching from 8 kHz sampling rate to 16 kHz sampling rate, the SLEEP bit must be enabled then disabled if the Call Progress Monitor function is used. After cycling the SLEEP bit, the Line-Side Device registers (Registers 0x12 to 0x18) must be reconfigured. 7.8 Device Reset For a correct reset of the 73M1x66B, the RST signal must be asserted for a minimum period of 1 ms. PCLK must be active for a minimum of 8 clock cycles before the RST signal can be de-asserted. The PLL locks to the PCLK after 20 PCM frames as defined by the occurrence of the Frame Sync Signal (FS). This gives a minimum period of 3.5 ms from the assertion of RST until the PLL is locked and normal operations may occur, including access to all device registers and the transmission and reception of PCM data samples. If PCLK changes frequency, then the PLL will lose lock so a stable clock must be used during this reset period. If a PCLK frequency change is required after the reset, the user should implement the procedure described for PCODE (Register 0x23 bits 2 to 5). 44 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 8 PCM Highway Interface and Signal Processing The PCM highway is the method by which the 73M1x66B exchanges PCM data with the host or other PCM-enabled devices. The PCM data can be in either 8-bit compressed mode or in 16-bit linear mode. Compression of the received signals from the PSTN line interface is selectable A-law or -law, as specified by ITU-T Recommendation G.711. The 73M1x66B is configurable with respect to tuning the clock and time slot relationships. See Section 8.1 for details. The PCM interface provided by the 73M1x66B consists of the following signals: * * * * PCLK FS DX DR The frequency at which bits are driven on the PCM highway. (Goes to the PCLKI pin.) PCM frame synchronization pulse. PCM data transmitted to the PCM highway. PCM data received from the PCM highway. The basic timing relationship of PCM highway interface signals is shown in Figure 20. FS PCLK DX MSB LSB Figure 20: 8-bit Transmission Example 8.1 PCM Highway Interface Timing Signal FS defines the frame boundaries by being asserted at a rate of 8 kHz. The duration of FS is defined by the setup and hold times around the falling edge of PCLK and can be extended to multiple PCLK cycles. The timing relationship between FS and PCLK is determined by the rising edge of FS and the first falling edge of PCLK that follows the FS rising edge. PCLK and FS are common to all devices connected to the PCM highway. The ratio of PCLK frequency to FS frequency determines the number of bit slots available during a frame, i.e., the number of bits per frame. The number of bit slots divided by 8 is the number of 8-bit time slots available during the frame. PCLK Frequency FS Frequency (8 kHz) = Bits per Frame Bits per Frame 8-bits per Time Slot = Number of Time Slots per Frame Refined granularity to the time slot can be achieved by programming the clock slot offset. The clock slot defines an offset in terms of the number of bits from the start of the time slot. The combination of the transmit and receive time slot and clock slot registers determines the bit slot at which the 73M1x66B begins transmitting or receiving a data sample. Adjustments of a half clock period can be made using these controls in conjunction with TPOL and RPOL. The 73M1x66B supports a 16-bit linear transmission and receive mode. The transmission and reception of the data samples consumes two adjacent 8-bit time slots each on the PCM highway. The 16-bit data sample is transmitted most significant bit first starting at the bit slot defined by the TTS and TCS controls. The transmission lasts for 16 consecutive bit slots, as illustrated in Figure 21. Rev. 1.6 45 73M1866B/73M1966B Data Sheet DS_1x66B_001 FS PCLK DX MSB LSB Figure 21: 16-bit Transmission Example Similarly, the 16-bit data sample is received most significant bit first, beginning at the bit slot defined by the RTS and RCS control registers. The reception lasts for 16 consecutive bit slots. SR selects between 8 kHz and 16 kHz sampling rates. However, FS remains constant at 8 kHz. Therefore, in 16 kHz sampling mode, two data samples are transmitted to (or received from) the PCM highway starting at the bit slot dictated by the time and clock slot registers. In 16 kHz mode, either two or four adjacent 8-bit time slots are used for two compressed 8-bit data samples or two linear 16-bit data samples, respectively. The 16 kHz mode is enabled by setting SR=1 followed by SEL16K=1. When switching to 16 kHz sampling rate and if the Call Progress Monitor function is being used, the Line-Side Device needs to be reconfigured. See Section 7.7. PCM highway interfaces are designed such that a device can transmit and receive to other devices on the PCM highway. For example, Codec A will use a time slot assignment for its transmit to the PCM highway and Codec B will assign its receiver to the same time slot. The time slot assignment is such that if Codec A wants to transmit its data sample to Codec B, then Codec A transmit time/clock slot value is identical to the Codec B receive time/clock slot value. The 73M1x66B uses the DX signal pin to transmit to the PCM highway and the DR signal pin to receive from the PCM highway. Figure 22 illustrates a typical example. DR DR DR Codec A Codec B Codec N TSC DX DX TSC TSC DX PCM Highway To System Figure 22: Example of PCM Highway Interconnect Larger systems may use buffers to interconnect multiple segments of the PCM highway (across line cards for instance). In the 73M1x66B, Control TSC is used to control the tri-state mode of the transmit side of the PCM highway as shown in Figure 23. TSC is asserted (active low) for the duration of the time slot during which the 73M1x66B is transmitting to the PCM highway. Receive PCM Highway From System DR DR DR Codec A Codec B Codec N DX TSC DX TSC DX TSC TSC Tri-State Control Transmit PCM Highway To System Figure 23: Example of PCM Highway Interconnect for Typical Large Systems 46 Rev. 1.6 DS_1x66B_001 8.2 73M1866B/73M1966B Data Sheet PCM Clock Frequencies The 73M1x66B supports the following PCLK input frequencies: * * * * * * * * * * * 256 kHz 512 kHz 768 kHz 1.024 MHz 1.536 MHz 1.544 MHz 2.048 MHz 3.088 MHz 4.096 MHz 6.176 MHz 8.192 MHz The 73M1x66B automatically detects the frequency of PCLK and adjusts its internal PLL parameters accordingly. At startup, the first eight frames are discarded. The next eight frames are used to count the number of PCLK cycles during each frame. If the count differs among these eight frames or if the count is a non-supported value, then a PCLKDT interrupt is asserted. If PCLK is set at a frequency different from the above list, the PLL will be set for a PCLK of 2.048 MHz. Since there will be a discrepancy between the frequency of PCLK and the frequency considered for PLL settings, a PCLKDT interrupt may occur if required. It takes about 20 PCM frames before PLL is locked, which is shown through the assertion of the FRCVCO status bit. PCLK must be running for several cycles when reset is de-asserted. After that point, SPI transactions can start. 8.3 Master Mode The default mode of operation for the PCM highway in the 73M1x66B is the slave mode i.e., FS and PCLK are inputs to the device. The 73M1x66B offers a master mode by which a 4.096 MHz clock is applied to the PCLKI pin. The master clock is divided by two to generate a 2.048 MHz clock that is connected to the PCM highway via the PCLKO pin. Similarly, FS of one 2.048 MHz period long is generated and driven to the PCM highway. The master mode is set by setting the MASTER bit. 8.4 A-law / -law Compander The 73M1x66B may be programmed for compressed A-law mode, compressed -law mode, or linear mode. Compression schemes are used to minimize the bandwidth required for exchanging data samples on the PCM highway. For instance, when PCLK is 8.192 MHz there are 128 8-bit time slots available. The density of the overall system is halved when working in linear mode, which requires 16-bit time slots. The 73M1x66B fully complies with the A-law and -law companding specifications defined in the ITU-T Recommendation G.711. Rev. 1.6 47 73M1866B/73M1966B Data Sheet 8.5 DS_1x66B_001 Transmit and Receive Levels 8.5.1 A-Law According to the ITU-T Recommendation G.711, A-law assumes +4096 (in sign plus 12 bit) to represent 3.14 dBm. That is, a sinusoid having a peak value of +4095 to correspond to +3.14 dBm or 1.1119 Vrms or 1.5725 Vpk or 3.145 Vpp. Figure 24 shows the mapping implied in the ITU-T Recommendation G.711. Therefore, one least significant bit in 16-bit code is equivalent to: LSB = 1.5725V = 48.0 V / bit 215 - 8 A-Law (Sign + 12 bits) 0 1 1 1 11 1 1 1 1 1 1 1 0 1 1 1 11 1 1 1 1 1 1 1 0 0 0 16 bits Linear Figure 24: Mapping of A-law Code to 16-bit Code For A-law, 0 dBm=774.6 mVrms=1.095 Vp (sinusoid) implies a peak code of 22,821=5925h. 8.5.2 -Law Similarly, -Law assumes +8159 (in sign plus 13 bit) to represent 3.17 dBm. That is, a sinusoid having a peak value of +8159 to correspond to +3.17 dBm or 1.1157 Vrms or 1.578 Vpk or 3.156 Vpp. Figure 25 shows the mapping implied in the ITU-T Recommendation G.711. Therefore, one least significant bit in 16-bit code is equivalent to: LSB = 1.578V = 48.35V / bit 32636 u-Law (Sign + 13 bits) 16 bits Linear 0 1 1 1 1 1 1 1 0 1 1 1 11 0 1 1 1 11 1 1 0 1 1 1 1 1 0 0 Figure 25: Mapping of -law Code to 16-bit Code For -law, 0 dBm=774.6 mVrms=1.095 Vp (sinusoid) implies a peak code of 22,647=5876h. 8.5.3 Transmit and Receive Level Control The 73M1x66B provides digital and analog control over the gains of transmit and receive signal. The overall transmit gain adjustment is +13.4 dB to -26 dB and the range of the receiver gain is +10.4 dB to -24 dB. Both gain adjustments are in steps of 0.125 dB. Optimal performance on how the overall gain is to be achieved requires the appropriate management of the gain elements in the signal paths. 48 Rev. 1.6 DS_1x66B_001 8.6 73M1866B/73M1966B Data Sheet Transmit Path Signal Processing 8.6.1 General Description In the transmit path, data is first sent by the host DSP through a serial interface to the 73M1x66B then interpolated by an interpolation filter, serialized and transmitted across barrier interface to the Line-Side Device, which is floating relative to the Host-Side Device earth ground. The data received on the Line-Side Device is then de-serialized and digitally sigma-delta modulated to a one-bit data stream of 1.536 Mbps for a sample frequency of 8 kHz or 3.072 Mbps for a sample frequency of 16 kHz. The signal is further filtered first by a switched capacitor filter and then a continuous time anti-aliasing circuit. * * The 0.2 dB pass-band ripple frequency is from dc to 3.422 kHz for an 8 kHz sample rate or 6.844 kHz for a 16 kHz sample rate. The 3 dB bandwidth is 3.65 kHz for an 8 kHz sample rate or 7.299 kHz for a 16 kHz sample rate. 8.6.2 Total Transmit Path Response Figure 26 and Figure 27 show the transmit path frequency response. The response shape is the same, but the frequencies double for a 16 kHz sample rate. 10 Transmit Path Overall Frequency Response 10 0 10 20 Gain (dB) 30 composite( x) com 40 50 60 iplo 70 xou 80 - 100 xou 90 100 0 1 2 3 4 5 6 7 x 16 0 8 8 Freq(kHz) Figure 26: Transmit Path Overall Frequency Response to Fs of 8 kHz 1. Transmit Passband Response 1 0.8 0.6 Gain (dB) 0.4 0.2 comp osite( x) 0 0.2 0.4 0.6 0.8 - 1.0 1 0 0 0.5 1 1.5 2 2.5 3 3.5 x 16 4 4 Freq(kHz) Figure 27: Transmit Path Passband Response for an 8 kHz Sample Rate Rev. 1.6 49 73M1866B/73M1966B Data Sheet DS_1x66B_001 8.6.3 73M1x66B Transmit Spectrum Figure 28 shows the transmit spectrum observed on the line from dc to 32 kHz for a sample frequency (Fs) of 8 kHz. The transmit signal is band-limited (by default) to Fs/2=4 kHz and is flat (with 0.2 dB ripple) to 3.65 kHz and is marked as Txdb(x) in the figure. All frequencies double for a 16 kHz sample rate Also shown, and marked as signaldb(x), is the baseband signal from 1 kHz to 2 kHz for an 8 kHz sample rate (2 kHz to 4 for a 16 kHz sample rate). The aliases of signaldb(x) are shown as aliasdb(x) and are attenuated significantly with better than 80 dB attenuation at 8 kHz, better than 60 dB at 16 kHz, better than 100 dB at 24 kHz, etc for an 8 kHz sample rate and the frequencies double for a 16 kHz sample rate. 20 Transmit Spectrum 20 Spectrum (dB) 0 signaldb( x) aliasdb( x) 20 40 60 Txdb( x) 80 100 - 140 120 140 0 4 8 0 12 16 20 24 28 32 32 16x Freq Figure 28: Transmit Spectrum to 32 kHz for an 8 kHz Sample Rate 8.7 Receive Path Signal Processing 8.7.1 General Description In the receive path, the signal from the telephone line is input to the anti-aliasing filter and passed through a selectable low pass (notch) filter, which can be used to attenuate in-band Billing Tones. The analog signal is digitized by a sigma-delta analog to digital converter. The resulting high frequency one-bit data stream is decimated and sent to the Host-Side Device via the barrier. Another decimation FIR filter in the Host-Side Device filters the received data and sends it to the host DSP for processing. The response of the receive path, in conjunction with the decimation filter in the Host-Side Device, provides a flat pass-band response to 3.342 kHz at an 8 kHz sample rate or 6.744 kHz with a 16 kHz sample rate with 0.2 dB ripple. The 3 dB bandwidth is 3.58 kHz at 8kHz sample rate or 7.226 kHz at a 16 kHz sample rate. . The one-bit data stream is 1.536 Mbps for an 8 kHz sample rate or 3.072 Mbps with a 16 kHz sample rate. 50 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 8.7.2 Total Receive Path Response Figure 29: Overall Frequency Response of the Receive Path Figure 30: Pass-band Response of the Overall Receive Path 8.7.3 Receiver DC Offset Subtraction The 73M1x66B provides a method to improve audio quality by reducing unwanted DC offset from the receiver signal path in A-law or -law compression modes. This method requires that a signal path calibration be performed. This calibration is benign to the performance of the device and is only required after an initialization or device reset sequence. Receiver DC offset calibration can only be executed when the device is on-hook and not in linear mode, otherwise the process will disturb signal quality. See the 73M1866B/73M1966B Implementer's Guide for the steps to enable the calibration of receive DC offset. Rev. 1.6 51 73M1866B/73M1966B Data Sheet 8.8 DS_1x66B_001 PCM Control Functions Table 33: PCM Control Functions Function Mnemonic ADJ Register Location 0x22[6] DAA 0x14[6:5] W ENPCLKDT 0x05[4] W LAW 0x23[0] W LIN 0x23[1] W MASTER 0x23[6] W PCLKDT 0x03[4] R PCMEN 0x23[7] W Type Description W Adjacent Time Slot Driver Control Allows LSB of the PCM frame (DX) to be tri-stated during the second half of the clock cycle. This feature allows adjacent time slots to be used by different devices without risking a contention at the time slot boundary. 0 = Drives DX during the entire bit time. (Default) 1 = Drives DX only during the first half of bit time. DAA Transmit Gain Used in conjunction with TXBST to manage transmit level. See Section 8.8.1. Enable PCLK Error Detection Interrupt 0 = Disables this function. 1 = Enables the detection of an interrupt resulting from an incoherency in the PCLK count during the second set of eight frames received after power up. (Default) Law Compression Mode Selects the PCM compression mode. 0 = Selects the A-law compression mode. (Default) 1 = Selects the -law compression mode. Linear Mode Enable 0 = The compression modes of either A-law or -law are enabled. (Default.) See the LAW bit. 1 = 16-bit linear mode. Master/Slave Mode The 73M1x66B is in Slave Mode by default. See Section 8.3 for details of master and slave operation. 0 = Enables Slave Mode. (Default) 1 = Enables Master Mode. PCLK Detect Error PCLKDT is an interrupt resulting from the detection of two possible events: 1. The number of PCLK periods per frame is not consistent among the second set of eight frames after power up. 2. The number of PCLK periods per frame does not equate to any of the acceptable PCLK frequencies. This is a maskable interrupt. It is enabled by the ENPCLKDT bit. See Section 7.2. PCM Transmit Enable Controls DX and TSC. This bit must be set on completion of all configuration changes to enable transmission on to the PCM highway. When powered up, the 73M1x66B PCM outputs are tri-stated. The host must set PCMEN after setting the time/clock slot control bits to avoid contention on the PCM highway. 52 Rev. 1.6 DS_1x66B_001 Function Mnemonic PCODE Register Location 0x23[5:2] 73M1866B/73M1966B Data Sheet Type W Description PCM Clock Code The default state of PCODE out of reset is 0000. In PCM Slave Mode at reset, the device will attempt to automatically detect the correct frequency of PCLK. If the PCLK frequency is different from those listed in the table below or an incorrect PCODE value is written, the PLL will not lock (LOCKDET 0x0D[7] == 0). To modify the value of PCODE, first write a value of 0000 and then write the required PCODE value. Toggling of the MASTER bit 0x23[6] (0 1 0) with a PCODE of 0000 will also restart the automatic PCLK frequency detection function. PCLK Frequency 256 kHz 512 kHz 768 kHz 1.024 MHz 1.536 MHz 1.544 MHz 2.048 MHz 3.088 MHz 4.096 MHz 6.176 MHz 8.192 MHz RCS 0x22[5:3] W RPOL 0x21[7] W RTS 0x21[6:0] W Rev. 1.6 PCODE [3:0] 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Receive Clock Slot These bits control the starting clock of the receive channel. The clock slot value allows the adding of an offset of up to 7 (111) bits to the time slot value. A value of 000 is zero offset. Receive Polarity 0 = The receive PCM data is to be sampled on the falling edge of PCLK. (Default) 1 = The receive PCM data is to be sampled on the rising edge of PCLK. Receive Time Slot Selects the time slot number on the PCM highway for the receiver. The maximum number of 8-bit time slots is 128 (with a PCLK frequency of 8.192 MHz). A value of 0000000 is time slot zero and 1111111 is time slot 128. The default is 0000000. 53 73M1866B/73M1966B Data Sheet RXEN 0x16[6] W RXG 0x14[1:0] W RXOCEN 0x17[5] W RXOM 54 0x25[7:0] W RXDG +0.5dB RXDG +0.25dB RXDG +0.125dB Receiver Digital Gain These bits controls the value of the digital gain section of the 73M1x66B receive path. Each bit indicates either a gain or attenuation value. The net value of the gain setting is the linear sum of each attributed value. Reading the RXDG register returns all zeros, regardless of what was written to them. RXDG +1dB WO RXDG +2dB Description RXDG +3.5dB Type RXDG -6dB Register Location 0x09[7:0] RXDG -12dB Function Mnemonic RXDG DS_1x66B_001 0 0 0 0 0 0 0 0 0dB (default) 1 0 0 0 0 0 0 0 -12 dB 0 1 0 0 0 0 0 0 -6 dB 0 0 1 0 0 0 0 0 +3.5 dB 0 0 0 1 0 0 0 0 +2 dB 0 0 0 0 1 0 0 0 +1 dB 0 0 0 0 0 1 0 0 +0.5 dB 0 0 0 0 0 0 1 0 +0.25 dB 0 0 0 0 0 0 0 1 +0.125 dB Gain/Attenuate Examples: 10000000 -12dB 00100000 +3.5dB 00010011 +2 + 0.25 + 0.125 =2.375dB 01001000 -6 + 1 = -5dB Receive Path Enable 1 = Enable Receive Path. 0 = Disable Receive Path. (Default) Receive Gain Sets the receive path gain/attenuation. See Table 36. Rx DC Offset Calibrate Enable When RXOCEN is set to 1 and OFH, ENDC and ENNOM are reset to 0, the receiver dc offset calibration process is enabled. RXOCEN must be reset to 0 before OFH, ENDC and ENNOM are set to 1 in order for the calibration to operate correctly. RXOCEN should not be used in linear mode. Default value is 0. RX Offset Measurement Stores the result of the receive offset measurement. See Section 8.8.3. Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet Function Mnemonic SEL16K Register Location 0x13[0] SR 0x22[7] W TCS 0x22[2:0] W TPOL 0x20[7] W TTS 0x20[6:0] W TXBST 0x14[7] Rev. 1.6 Type W WO Description Sample Rate Mode Configuration Select Configures the 16 kHz mode of operation. See also SR. 0 = 8 kHz sampling rate. (Default) 1 = 16 kHz sampling rate. The 16 kHz mode is enabled by setting SR=1 followed by SEL16K=1. Sampling Rate Mode Enables the 16 kHz mode of operation. See also SEL16K. 0 = 8 kHz sampling rate. (Default) 1 = 16 kHz sampling rate. The 16 kHz mode is enabled by setting SR=1 followed by SEL16K=1. Transmit Clock Slot Controls the starting clock of the transmit channel. The clock slot value allows the adding of an offset of up to 7 (111) bits to the time slot value. A value of 000 is zero offset. Transmit Polarity 0 = The transmit PCM data is to be transmitted based on the falling edge of PCLK. (Default) 1 = The transmit PCM data is to be transmitted based on the rising edge of PCLK. Transmit Time Slot Selects the time slot number on the PCM highway for the transmitter. The maximum number of 8-bit time slots is 128 (with a PCLK frequency of 8.192 MHz). A value of 0000000 is time slot zero and 1111111 is time slot 128. The default is 0000000. Transmit Boost Used in conjunction with DAA to manage transmit level. See Section 8.8.1. 55 73M1866B/73M1966B Data Sheet Examples: 10000000 00100000 00010011 01001000 TXEN 56 0x16[7] WO TXDG +0.5dB TXDG +0.25dB TXDG +0.125dB Transmitter Digital Gain These bits control the value of the digital gain section of the 73M1x66B transmit path. Each bit indicates either a gain or attenuation value. The net value of the gain setting is the linear sum of each attributed value. Reading the TXDG register returns all zeros, regardless of what was written to them. TXDG +1dB WO TXDG +2dB Description TXDG +3.5dB Type TXDG -6dB Register Location 0x08[7:0] TXDG -12dB Function Mnemonic TXDG DS_1x66B_001 Gain/Attenuate 0 0 0 0 0 0 0 0 0 dB (default) 1 0 0 0 0 0 0 0 -12 dB 0 1 0 0 0 0 0 0 -6 dB 0 0 1 0 0 0 0 0 +3.5 dB 0 0 0 1 0 0 0 0 +2 dB 0 0 0 0 1 0 0 0 +1 dB 0 0 0 0 0 1 0 0 +0.5 dB 0 0 0 0 0 0 1 0 +0.25 dB 0 0 0 0 0 0 0 1 +0.125 dB -12dB +3.5dB +2 + 0.25 + 0.125 =2.375dB -6 + 1 = -5dB Transmit Path Enable 1 = Enable Transmit Path. 0 = Disable Transmit Path. (Default) Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 8.8.1 Transmit and Receive Level Control Refer to Section 8.5 for information about 73M1x66B levels. 8.8.1.1 Transmit Gain Scaling The first gain stage in the transmit signal path is the digital gain whose value is controlled by writing to Register 0x08 (TXDG). The second gain stages are the analog gains that are controlled by Register 0x14[7] (TXBST) and Register 0x14[6:5] (DAA). As a general rule to prevent clipping of the analog gain stages, it is important to choose a value of the digital gain such that the transmit data after multiplied by TXDG does not exceed +1.25 dBm. So for correct use of the gain controls the appropriate mix of digital and analog settings must be used. Generally speaking, for best S/N performance, it is advisable to make the digital words, after digital gain scaling, as large as possible without going over the +1.25 dBm limit. Example: If +2 dBm transmit level is desired for the case where the maximum input is 0 dBm: Set analog gain to +3 dB (i.e. TXBST and DAA = 0) add attenuation of -1 dB by setting TXDG to 01101100 (-6 + 3.5 + 1 + 0.5 = -1); therefore, +3 - 1 = +2. Note in this case any digital gain could cause clipping at high input levels in the analog circuitry. Table 34 lists transmit level analog gain adjustment settings based upon the values of TXBST and DAA. Table 34: Transmit Gain Control TXBST 0x14[7] 0 0 0 0 1 1 1 1 DAA1 0x14[6] 0 0 1 1 0 0 1 1 DAA0 Gain, 0x14[5] Nom. (dB) 0 +3.0 1 0.0 0 -4.0 1 -8.0 0 +6.0 1 +6.0 0 +2.0 1 -2.0 Table 35 shows a recommended gain settings for various transmit levels. With 0 dBm of Tx Data and default setting of DAA1:0 = 01, Txbst=0, TXDG=00h, the transmit level is slightly off at -0.25 dBm. TXDG=00000010 is required to achieve 0 dBm transmit level. For Tx level > 6 dBm, Tx Data is assumed less than 0 dBm such that the product of Tx Data and TXDG is less than 1.25 dBm. Table 35: Recommended Gain Setting TX Level Analog Gain dBm TxBst DAA1 DAA0 -26 0 1 1 -25 0 1 1 -24 0 1 1 -23 0 1 1 -22 0 1 1 -21 0 1 1 -20 0 1 1 -19 0 1 1 -18 0 1 1 Rev. 1.6 dB -8 -8 -8 -8 -8 -8 -8 -8 -8 Digital Gain Ana+Dig TXDG dB dB 1100_0010 -17.75 -25.75 1100_1010 -16.75 -24.75 1101_0010 -15.75 -23.75 1101_1010 -14.75 -22.75 1110_0110 -13.75 -21.75 1110_1110 -12.75 -20.75 1000_0010 -11.75 -19.75 1000_1010 -10.75 -18.75 1001_0010 -9.75 -17.75 57 73M1866B/73M1966B Data Sheet TX Level Analog Gain dBm TxBst DAA1 DAA0 -17 0 1 1 -16 0 1 1 -15 0 1 1 -14 0 1 1 -13 0 1 1 -12 0 1 1 -11 0 1 1 -10 0 1 1 -9 0 1 1 -8 0 1 1 -7 0 1 1 -6 0 1 0 -5 0 1 0 -4 0 1 0 -3 0 1 0 -2 1 1 1 -1 0 0 1 0 0 0 1 1 0 0 1 2 1 1 0 3 0 0 0 4 0 0 0 5 1 0 0 6 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 DS_1x66B_001 dB -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -4 -4 -4 -4 -2 0 0 0 2 3 3 6 6 6 6 6 6 6 6 Digital Gain TXDG dB 1001_1010 -8.75 1010_0110 -7.75 1010_1110 -6.75 0100_0010 -5.75 0100_1010 -4.75 0101_0010 -3.75 0101_1010 -2.75 0110_0110 -1.75 0110_1110 -0.75 0000_0010 0.25 0000_1010 1.25 0110_0110 -1.75 0110_1110 -0.75 0000_0010 0.25 0000_1010 1.25 0000_0010 0.25 0110_1110 -0.75 0000_0010 0.25 0000_1010 1.25 0000_0010 0.25 0000_0010 0.25 0000_1010 1.25 0110_1110 -0.75 0000_0010 0.25 0000_1010 1.25 0001_0010 2.25 0001_1010 3.25 0010_0110 4.25 0010_1110 5.25 0011_0110 6.25 Ana+Dig dB -16.75 -15.75 -14.75 -13.75 -12.75 -11.75 -10.75 -9.75 -8.75 -7.75 -6.75 -5.75 -4.75 -3.75 -2.75 -1.75 -0.75 0.25 1.25 2.25 3.25 4.25 5.25 6.25 7.25 8.25 9.25 10.25 11.25 12.25 Note 1. Tx Data is assumed small enough that the combination of Tx Data and TXDG is less than 1.25 dBm. 8.8.1.2 Receive Gain Scaling On the receive side, a 0 dBm receive signal on the line results in ~0 dBm at the PCM interface. Means is provided to adjust receive signal path gain by use of a digital gain stage. This gain value is controlled by Register 0x09[7:0] (RXDG). The gain values are explained in Table 33. The two RXG bits (Register 0x14[1:0]) control the value of the receiver analog gain. The RXG bits must be set to 10 to enable 0 dB gain in the receive path. For the best S/N performance it is recommended to use a gain value up front in the analog domain. The digital control should be used to fine-tune the receiver signal path gain. When the received line signal exceeds a voltage level greater than specified by ITU-T Recommendation G.711, the receive gain must be reduced to prevent saturation and clipping within the receive signal processing path. 58 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet Table 36 lists the value of Receive Gain for each value of RXG. Table 36: Receive Gain Control RXG1 0x14[1] 0 0 1 1 RXG0 0x14[0] 0 1 0 1 Gain Nom (dB) -6.0 -3.0 0.0 +3.0 The precise values of the digital gain settings are: Bit Gain Gain / Attenuation 7 0.25 -12.04dB 6 0.5 -6.02dB 5 1.5 3.52dB 4 1.25 1.94dB 3 1.125 1.02dB 2 1.0625 0.53dB 0 1 1.015625 1.03125 0.13dB 0.27dB 8.8.1.3 Maximum Levels The 73M1x66B is capable of providing gain attenuation in both the digital and analog domain. It is important to note that for optimum performance the transmitter output and receiver input should not exceed more than +7.25 dBm. Signal levels that are greater than this will cause distortion and reduced performance. This implies that the maximum input signal capable by the transmitter, if adjusted for unity gain, is the +7.25 dBm, e.g. digital gain of -6.0 dB (ensures analog input is less than +1.25 dBm) and analog gain of +6 dB gives +7.25 dBm. 8.8.2 Time Slot Assignment Example Figure 31 shows an example of the timing of transmit and receive time slots with changes in the time slot, clock slot and edge controls. Refer to Section 8.8, PCM Control Functions. To program the first transmit time slot after FS, TTC=31, TCS=7 and TPOL=1: * * The first receive time slot after FS would be RTS=31, RCS=7 and RPOL=0. Adjustments of 1/2 clock period can be made using these registers. DX DX TTS, TCS = 31, 7 TPOL=0 TTS, TCS = 0, 0 TPOL=0 TTS, TCS = 31, 7 TPOL=1 TTS, TCS = 0, 0 TPOL=1 PCLK FS DR DR RTS, RCS = 31, 7 RPOL=0 RTS, RCS = 31, 7 RPOL=1 RTS, RCS = 0, 0 RPOL=0 RTS, RCS = 0, 0 RPOL=1 Figure 31: Timing Relationships with Various TTS, TCS, TPOL, and RTS, RCS, RPOL Settings Rev. 1.6 59 73M1866B/73M1966B Data Sheet DS_1x66B_001 9 Barrier Information 9.1 Isolation Barrier The 73M1x66B uses the Teridian MicroDAA proprietary isolation method based upon low-cost pulse transformer coupling. This technique provides several advantages over other methods, including: * * * * Lower BOM cost. Reduced component count. Lower radiated noise (EMI). Improved operation in noisy environments. The MicroDAA has additional and enhanced functionality such as the support of powering the Line-Side DAA circuit from the Host-Side Device. This allows operation on leased lines circuits and on low current conditions commonly encountered in long loops. The MicroDAA can also operate entirely from line power when sufficient loop current is available. Since the transformer is the only component crossing the isolation barrier, it solely determines the isolation between the PSTN and the FXO's digital interface. Several vendors can supply compatible transformers with ratings up to 6000 V. Communication of PCM data, control data and status data is performed in the digital domain and is bidirectional at a rate of 1.536 Mbps. 9.2 Barrier Powered Options The 73M1x66B has the ability to be used either in a Line Powered Mode or one where the Line-Side Device can be powered across the barrier from the Host-Side Device. The power-on default for the 73M1x66B is Barrier Powered Mode. 9.2.1 Barrier Powered Operation In this default mode of operation, the 73M1x66B Host-Side Device drives the pulse transformer in such a way that power pulses are time division multiplexed into the transmit bit stream (half the time) that is rectified by circuitry in the Line-Side Device and uses this energy to power itself. 9.2.2 Line Powered Operation If there is sufficient current available from the PSTN line, the 73M1x66B can be programmed to use line power instead of power from across the barrier. 9.3 Synchronization of the Barrier Since the communication across the barrier is digital, synchronization of data across the barrier is of absolute importance. To that end, the devices implement special procedures to ensure reliability across the barrier. When loss of synchronization is detected, the SLHS bit is set to 1 and likewise SYNL is also set to 1 and initiates an interrupt to the host. Once the SYNL bit is asserted a new barrier synchronization sequence will automatically begin. Once read, the SLHS bit is reset, but will be set again if the synchronization loss continues. 60 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet Upon power up, the following sequence should be used to ensure barrier synchronization: 1. The 73M1906B starts in Barrier Powered Mode and transmits a preamble to aid the PLL locking of the Line-Side Device. 2. When PLL Lock detect is achieved the Line-Side Device transmits status data to the Host-Side Device. 3. When the Line-Side status Data is detected by the Host-Side Device, the barrier is considered to be in synchronization by the Host-Side Device. 4. If the auto-poll mode is enabled, the Device ID is transmitted, which is followed by transmit data. 5. Upon detection of the Device ID, the Line-Side Device considers the barrier to be in synchronization in host-to-line side direction. 6. The Line-Side Device starts sending Receive Data. 7. If the Auto-Poll bit is enabled, the Host-Side Device will have polled the Device ID of the Line-Side Device. If the barrier is synchronized, then Register 1Dh, bits 7-4, will be 1101. If not synchronized, then 0000. 9.4 Auto-Poll Once the Barrier Interface acquires synchronization, the Barrier Interface state machine automatically sends a polling command to Line-Side Device requesting it to return its Device ID. This is provided in REV. Upon power up or loss of barrier synchronization, the contents of REV is cleared. After the auto-poll sequence, the host should read REV. A non-zero value indicates that synchronization is established. The auto-poll mechanism is disabled by resetting the ENAPOL control bit. 9.5 Barrier Control Functions Table 37: Barrier Control Functions Function Mnemonic DISNTR Register Location 0x15[6] ENAPOL 0x05[3] W ENLPW 0x02[2] W ENSYNL 0x05[1] W Rev. 1.6 Type Description WO Disable No-Transition Timer If enabled, the No-Transition Timer is a safety feature. If the barrier fails, i.e. no transition is detected for 400 s, the Line-Side Device resets itself and goes on hook to prevent line holding in a failure condition. 0 = Enables No-Transition Timer of 400 s. (Default) 1 = Disables No-Transition Timer. Enable Automatic Polling 0 = Disables automatic polling. 1 = Initiates automatic polling of the 73M1x66B Device ID upon the establishment of the barrier SYN. (Default) If SYN is lost, the Device ID will be reset to 0000. Enable Line Power 0 = Barrier Powered Mode is selected. (Default) 1 = Line Powered Mode is selected. Bit ENLVD must have the value of 0 before switching from Line Powered Mode to Barrier Powered Mode. Otherwise level detection is disabled and the transition to Barrier Powered Mode will not occur. Enable Synch Loss Detection Interrupt 0 = Disables Synch Loss Detection Interrupt. 1 = Enables Synch Loss Detection Interrupt. (Default) When the 73M1x66B detects a loss of synchronization in Host-Side Barrier Interface, SYNL 0x03[1] will be set and reset when read. 61 73M1866B/73M1966B Data Sheet Function Mnemonic RSTLSBI Register Location 0x0D[3] SLHS 0x0D[6] R SLLS 0x1E[2] R SYNL 0x03[1] R 62 DS_1x66B_001 Type Description W Reset Line-Side Barrier Interface To reset the Line-Side Barrier Interface, set this bit to 1. 1 = Resets the Line-Side Barrier Interface. The chip sets this bit back to 0 after it has completed resetting the Line-Side Barrier Interface. Synchronization Lost Host Side This bit indicates the status of the Barrier Interface as seen from the Host-Side. 0 = Host-Side Barrier Interface is synchronized. 1 = Host-Side Barrier Interface lost synchronization. Once read, the SLHS bit is reset, but will be set again if the synchronization loss continues. Synchronization Loss Line Side 0 = TXRDY will continuously be generated following Synchronization Loss so as to allow SLLS information to be transferred across the barrier. This causes an automatic transfer of 1Eh. (Default) 1 = Synchronization is lost in the Line-Side Device due to Header. Barrier Synchronization Loss 0 = Indicates synchronization of data across the barrier. 1 = Indicates a loss of synchronization of data across the barrier. This status bit is reset when read. This is a maskable interrupt. It is enabled by the ENSYNL bit. Rev. 1.6 DS_1x66B_001 9.6 73M1866B/73M1966B Data Sheet Line-Side Device Operating Modes The architecture of the 73M1x66B is unique in that the isolation barrier device, an inexpensive pulse transformer, is used to provide power and also bidirectional data between the Host-Side Device and the Line-Side Device. When the 73M1x66B is on hook, all the power for the Line-Side Device is provided over the barrier interface. After the Line-Side Device goes off hook, the telco line supplies approximately 8 mA to the Line-Side Device while the host provides the remainder across the barrier. It is also possible to power the Line-Side Device entirely from the line provided there is at least 17 mA of loop current available. Setting the ENLPW bit enables this mode and turns off the power supplied across the barrier. There is a penalty in using this mode in that the noise and dynamic range are about 6 dB worse than with the Barrier Powered Mode. It is therefore recommended that the Line Powered Mode be reserved for applications where the absolute minimum power from the host side is a priority and the reduction in performance can be tolerated. Figure 32 shows the AC and DC circuits of the Line-Side Device. TP14 OFH OHS 3 1 1 DCI 1 1 2 3 4 5 6 7 8 9 10 R58 + C4 10uF U2 DCI RGN RGP OFH VNX SCP MID VPX SRE SRB 20 DCG 19 DCS 18 DCD 17 TXM 16 RXM 15 RXP 14 VPS 13 VNS 12 ACS 11 VBG Q7 MMBTA42 2 2 4 240 3 Q6 BCP-56 2 1 DCD TXM RXM RXP R12 5.1K 3 3 1 MMBTA42 R65 200 Q3 Q4 MMBTA92 R3 412K, 1% 4 BR1 HD04 1+ - 2 2 3 73M1916-20 R11 5.1K R5 8.2 R4 100K, 1% 3 SRB 1 SRE Q5 MMBTA06 2 Figure 32: Line-Side Device AC and DC Circuits The DCIV bits control the voltage versus current characteristics of the 73M1x66B by monitoring the voltage at the line divided down by the ratios of (R3+R4)/R4 (5:1) measured at the DCI pin. This voltage does not include the voltage across the Q4 and the bridge. When both the ENAC and ENDC bits are set (the hold mode), the DCIV characteristics follow approximately a 50 load line offset by a factor determined by the DCIV bits. If ENDC=1 and ENAC=0, the 73M1x66B will go into the "Seize state mode" and the DC voltage load characteristic will be reduced to meet the Australian seize voltage requirements regardless of the setting of the DCIV bits. 9.7 Fail-Safe Operation of Line-Side Device The 73M1x66B provides additional protection against improper operation during error and harmful external events. These include power or communication failure with the Line-Side Device and the detection of abnormal voltages and currents on the line. The basis of this protection is to ensure that under these conditions the device is in the On-Hook state and the isolation is provided. The following events will cause the 73M1x66 Line-Side Device to go to the On-Hook state if it is Off-Hook: 1. A Power-On Reset occurs while Off-Hook. 2. The non-transition timer function (see DISNTR) is triggered by the absence of any signal transitions for more than 400 s on the barrier interface, indicating a problem with communications. 3. The power supply to the Line-Side Device is below normal operating levels. Rev. 1.6 63 73M1866B/73M1966B Data Sheet DS_1x66B_001 10 Configurable Direct Access Arrangement (DAA) The 73M1x66B Line-Side Device integrates most of the circuitry to implement a PSTN line interface or DAA that is capable of being globally compliant with a single bill of materials. The 73M1x66B supports the following DAA functions: * * * * * * * * Pulse dialing On and Off Hook switch control Loop current (DC-IV) regulation Line impedance matching Ring detection Tip and Ring voltage polarity reversal detection Billing tone rejection Trans-hybrid cancellation The device is able to support Barrier Powered Mode in which the PSTN loop current may be as low as 8 mA. 10.1 Pulse Dialing The 73M1x66B supports Pulse Dialing. See Section 10.6 for the descriptions of applicable control and status bits. 10.2 DC Termination DC Termination or Loop Current (DC-IV) regulation is managed by the 73M1x66B Line-Side Device by configuring the appropriate registers. No additional components are necessary. The 73M1x66B provides a DC transconductance circuit that regulates the tip to ring voltage depending on the DC current supplied by the line. There are four settings that can be used to set the voltage to current ratio. Figure 33 shows the DC-IV characteristics of the 73M1x66B with special regions of interest. V Current Limit Turned on 2.2 k 41 * Programmable Turn-on Voltage Given by DCIV Control Bits Seize Voltage I * ~50 with 8 fuse resistance Current Limit Turn-on=42 mA Figure 33: DC-IV Characteristics 64 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet The 73M1x66B can: * * Shift the characteristics by setting the turn-on voltage. Enable a current limit of 42 mA. The 73M1x66B meets a wide range of different countries' requirements under software control. See Section 10.7. There are two operating states for the DC-IV circuits: Hold and Seize. DCVI Performance 14 12 Tip/Ring Voltage 10 DCIV=00 8 DCIV=01 DCIV=10 6 DCIV=11 4 2 0 5 9 15 20 30 40 50 60 70 80 90 96 110 DC Current, mA Figure 34: Tip-Ring Voltage versus Current Using Different DCIV Settings The Hold state is the nominal operational point for the DC-IV circuits. The response shown in Figure 34 is for the Hold state (both DC and AC transconductance circuits are enabled). The slope of the DC-IV characteristics is approximately 50 when the series resistance of a typical PPTC resettable fuse is taken into account. The Seize state is a condition that is used by some central offices to determine an off-hook condition. In this state an additional load is added to the nominal operational DC-IV characteristics used during the Hold state In the Seize state (only the DC transconductance circuit is enabled), the turn-on voltage is reduced on the line independent of the DCIV control bits. See Figure 35 and the description of the DCIV bits in Section 10.6. Rev. 1.6 65 73M1866B/73M1966B Data Sheet DS_1x66B_001 An example of the use of the Seize state is for Australia, which requires this state for the first 300 ms immediately after going off hook. DCVI Performance 14 12 Australian Prohibited Region Tip/Ring Voltage 10 DCIV=xx 8 6 4 Australian Not Recommended Region 2 0 0 10 20 30 40 50 DC current, mA 60 70 80 90 100 Figure 35: Voltage versus Current in the Seize Mode is the Same for All DCIV Settings To facilitate the quick capture of the loop, the bandwidth of the DC loop is high upon power up. On the completion of DC loop capture, it should be lowered to avoid the interaction of DC and AC loops. See the description of the ENNOM bit in Section 10.6. 10.2.1 Current Limit Detection If the DAA Current Limiting feature is enabled and the device detects an I-limit condition, a status bit is set to report this event. 10.3 AC Termination The 73M1x66B supports 16 impedance configurations. This set of AC impedances has been selected to provide global coverage without the need for changing external components. The AC Termination function is controlled by an enable and a disable control bit and by writing the appropriate network configuration code to the device. The AC Terminations provided include ones suitable for ETSI ES 203 021-2, Australia, FCC and China, among others. See Section 10.7 on how to select a configuration. When using the 900 termination, an additional gain of 1.75 dB should be added to the transmitter path. Upon selection of a particular AC impedance configuration, the 73M1x66B monitors the line and controls the AC current back to the line, such that the desired impedance looking into the RXP pins is realized. The 73M1x66B provides an AC transconductance circuit that is used to modulate the AC signal onto the line as well as to regulate the current and provide the AC load in the AC signal path. Figure 36 shows the magnitude response of the impedance matching filter for the case of ES 203 021-2. 66 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet Freq Response of IPMF, AZ=01 10 10 9 8 7 F1db( f 1000) 6 5 4 3 2 0 1 0 0 0.5 1 1.5 2 0 2.5 3 3.5 4 4.5 f kHz 5 5 Figure 36: Magnitude Response of Impedance Matching Filter, ACZ (3:0)=0010 (ES 203 021-2) 10.4 Billing Tone Rejection Some countries use a large amplitude out-of-band tone to measure call duration and to allow remote central offices to determine the duration of a call for billing purposes. To avoid saturation and distortion of the input caused by these tones, it is important to be able to reject them. These frequencies are typically 12 kHz or 16 kHz. The 73M1x66B has an integrated notch filter that attenuates either of these tones. By enabling this filter and selecting the position of the notch frequency, such tones will be attenuated. Figure 37 shows the magnitude response of the filter with a notch at either 12 kHz (F1) or 16 kHz (F2). 10 10 0 10 F1db( f 1000) F2db( f 1000) 20 30 40 - 50 50 0 0 2 4 6 8 10 12 14 16 f Sp ans 20kHz 18 20 20 Figure 37: Magnitude Response of Billing Tone Notch Filter In addition to the notch filter, the 73M1x66B can indicate the presence of an overload condition when a line's AC voltage exceeds 3.5 Vpk. Rev. 1.6 67 73M1866B/73M1966B Data Sheet DS_1x66B_001 10.5 Trans-Hybrid Cancellation In order to improve performance, the Trans-hybrid Cancellation option allows a replica of the transmit signal to be created within the 73M1x66B and fed back to the RXM pin via an external circuit at the line interface. With a well matched AC impedance the amount of cancellation achieved is >26 dB. This function can be enabled or disabled. Tx Buf TXM 17.4 k - Rn RXM Rx Buf + Vin - 21 k Rp RXP From the Line Vin+ 52.3 k 4.7 uF Figure 38: Trans-hybrid Cancellation 10.6 Direct Access Arrangement Control Functions These Transmit Control Registers contain control information to set up the line side of the 73M1x66B. Included are DC-IV characteristics, off-hook control, etc. Table 38: DAA Control Functions Function Mnemonic ACZ Register Location 0x16[3:0] Type W Description Active Termination Loop Controls the selection of the active termination loops per the table shown below. ATEN must be set to 1 for selection to be enabled. ACZ Field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 68 Active Termination Loop Setting 600 900 270 + 750 || 150 nF and 275 + 780 || 150 nF (ETSI ES 203 021-2) 220 + 820 || 120 nF and 220 + 820 || 115 nF (Australia) 370 + 620 || 310 nF 320 + 1050 || 230 nF 370 + 820 || 110 nF 275 + 780 || 115 nF 120 + 820 || 110 nF 350 + 1000 || 210 nF 200 + 680 || 100 nF (China) 600 + 2.16 F 900 + 1 F 900 + 2.16 F 220 + 400 || 70 nF (China) 270 + 600 || 150 nF (Global Impedance) Rev. 1.6 DS_1x66B_001 Function Mnemonic ATEN Register Location 0x16[4] DCIV 0x13[7:6] 73M1866B/73M1966B Data Sheet Type W W ENAC 0x12[5] WO ENDC 0x12[6] WO ENFEL 0x12[2] WO Rev. 1.6 Description Active Termination Loop Enable Enables or disables Active Termination Loop. 0 = Disable. (Default) 1 = Enable Active Termination Loop. Note: normal operation requires this bit to be set to always enable a termination circuit. DC Current Voltage Characteristic Control Hold state with ENDC and ENAC=1, at 20 mA DC loop current measured at DCI. The Tip/Ring voltage assumes that there is a 5:1 attenuation of off-hook voltage at the DCI input pin. DCIV1 0 DCIV0 0 0 1 1 0 1 1 Description DC Loop On Voltage of 0.73 V (5.60 V at Tip/Ring assuming a 5:1 step down of off-hook voltage) DC Loop On Voltage of 0.977 V (6.75 V at Tip/Ring assuming a 5:1 step down of off-hook voltage) DC Loop On Voltage of 1.232 V (7.65 V at Tip/Ring assuming a 5:1 step down of off-hook voltage) DC Loop On Voltage of 1.488 V (9.35 V at Tip/Ring assuming a 5:1 step down of off-hook voltage) *Seize state with ENDC=1 and ENAC=0, 20 mA loop current. DCIV =xxProvides a DC Loop "On" Voltage of 0.281V (3.9 V at Tip/Ring assuming 5:1 step down of off-hook voltage) Enable AC Transconductance Circuit 0 = Shut Down AC Transconductance Circuit. Aux A/D input = Ring Detect Buffer (RGP/RGN) / Line Voltage (DCI). Seize state for going off hook. (Default) 1 = Enable AC Transconductance Circuit. Aux A/D input = Line Current (DCS) / Line Voltage (DCI). Enable DC Transconductance Circuit 0 = Shut down Transconductance Circuit. (Default) 1 = Enable Transconductance Circuit. Enable Front End Line-Side Circuit 0 = Power down Front End Line-Side circuits. (Default) 1 = Enable Front End blocks excluding DCGM, ACGM, shunt regulator. 69 73M1866B/73M1966B Data Sheet Function Mnemonic ENLVD Register Location 0x12[3] ENNOM 0x12[0] ENSHL IDISPD 0x12[4] 0x13[1] Type Description WO LeV Detection (OVDET, UVDET, OIDET monitors) 0 = Enable LeV detection. (Default) 1 = Disable LeV detection (used in line-powered mode to save power). This bit will be 0 when Line Powered Mode is detected (ENLPW is set in Register 0x02[2]) and set to 1 when an interrupt occurs within the 73M1916. This bit must be reset prior to switching back to Barrier Powered Mode. Enable Nominal Operation 0 = Speeds up the on and off hook transitions time by increasing the DC loop bandwidth of the DC transconductance circuit in the 73M1x66B. This should be used for pulse dialing, going on and off hook, etc. In addition, ENNOM=0 prevents the reset of all bits in Register 0x12. (Default) 1 = Enter Nominal Operation. Reduces the loop bandwidth of the DC transconductance circuit. Allows reset of Register 0x12 caused by bits UVDET, OVDET or OIDET. Enable Shunt Loading 0 = Disable shunt loading. (Default) 1 = Enable shunt loading of the line. Not used for most applications. Discharge and Pulse Dialing Controls the DC discharge current and how fast the loop turns off. Affects pulse dialing waveform. Controls the amount of discharge current during hook switch transitions. 0 = Minimum current. (Default) 1 = Maximum current. It is recommended to set IDISPD to 1 prior to hook switching operations. Current Limit Enable This control enables or disables loop current limit. 0 = No current limit. (Default) 1 = 42 mA current limit enabled. Current Limit Mode On This status bit is effective only when the ILM bit is set to 1. 0 = Loop current is lower than 42 mA. 1 = Loop current is higher than 42 mA and the current limiting mode is active. Off-Hook Enable This bit controls the state of the Hook signal. 0 = On-Hook. (Default) 1 = Off-Hook. Pulse Dialing Mode Enable Alleviates the strict timing requirements for the Host having to control ENDC and OFH during pulse dialing. With PLDM = 1, the Host only has to toggle OFH to perform pulse dialing. 0 = Pulse Dialing Mode is disabled. (Default) 1 = Pulse Dialing Mode is enabled. Receive Low Pass Notch Enable 0 = Billing Tone Receive Low Pass Notch (RLPN) filter bypassed. (Default) 1 = RLPN Filter Enabled. See RLPNH for notch frequency selection. WO WO WO ILM 0x13[5] WO ILMON 0x1E[7] R OFH 0x12[7] WO PLDM 0x13[3] WO RLPNEN 70 0x16[5] DS_1x66B_001 W Rev. 1.6 DS_1x66B_001 Function Mnemonic RLPNH THEN Rev. 1.6 Register Location 0x14[2] 0x15[3] 73M1866B/73M1966B Data Sheet Type W W Description Receive Low Pass Notch 0 = Selects Receive Low Pass Notch (RLPN) at 12 kHz. (Default) 1 = Selects RLPN at 16 kHz. See RLPNEN (Register 0x16[5]) to enable the filter. Enable Transhybrid Circuit The rejection of the transmit signal from the receive signal path. 0 = Transhybrid Circuit disabled. (Default) 1 = Transhybrid Circuit enabled. This bit should always be set for optimal performance. 71 73M1866B/73M1966B Data Sheet DS_1x66B_001 10.7 International Register Settings Table for DC and AC Terminations Table 39 lists the recommended ACZ and DCIV register settings for various countries. Other parameters can also be set in addition to the AC and DC termination. These settings along with the reference schematic (see Figure 12) can realize a single design for global usage without country-specific modifications. For more information on worldwide approvals, refer to the 73M1x66 Worldwide Design Guide Application Note. Table 39: Recommended Register Settings for International Compatibility Country ACZ(3:0) Argentina 0000 DCIV(1:0) Country 10 Hungary 2 1 ACZ(3:0) DCIV(1:0) Country ACZ(3:0) DCIV(1:0) 0010 10 Pakistan 0000 10 Australia 0011 11 Iceland 0010 10 Peru 0000 10 Austria1 0010 10 India 0000 10 Philippines 0000 10 Bahrain 0000 10 Indonesia 0000 10 Poland1 0010 10 Belgium1 0010 10 Ireland1 0010 10 Portugal1 0010 10 Bolivia 0000 10 Israel 0000 10 Romania 0010 10 1 1 Brazil 0000 10 Italy 0010 10 Russia 0000 10 Bulgaria1 0010 10 Japan 0000 00 Saudi Arabia 0000 10 Canada 0000 10 Jordan 0000 10 Singapore 0000 10 0000 10 0010 10 0010 10 Chile 0000 3 China 1110 10 10 Kuwait 1 0000 10 Croatia 0010 10 Cyprus1 0010 10 Columbia 1 Kazakhstan 0000 0010 10 Lebanon 0000 10 Leichtenstein2 0010 10 Latvia 1 0010 10 Denmark 0010 10 Ecuador 0000 10 Egypt 0000 10 El Salvador 0000 10 Estonia1 0010 10 1 0010 10 Morocco France 0010 10 Netherlands Germany1 0010 10 New Zealand3 Greece 0010 10 Guam 0000 10 Hong Kong 0000 10 Czech Rep 1 Finland 1 1 10 1 Slovakia 1 Slovenia 3 0011 10 South Korea 0000 10 Spain1 0010 10 South Africa 1 0010 10 Luxembourg 0010 10 Macao 0000 10 Malaysia 0000 10 Taiwan 0000 10 Malta 0010 10 ES 203 021-2 0010 10 Mexico 0000 10 Thailand 0000 10 0000 10 Turkey 0000 10 0010 10 UAE 0000 10 0100 10 UK1 0010 10 Nigeria 0000 10 Ukraine 0000 00 Norway2 0010 10 USA 0000 10 Oman 0000 10 Yemen 0000 10 Lithuania 1 1 1 0010 10 Switzerland 0010 10 Syria 0000 10 Sweden 2 1 These countries are members of the European Union, where there are no longer any regulatory requirements for AC impedance. The suggested setting complies with ETSI ES 203 021-2. Other settings can be used if desired. 2 These countries are members of the European Free Trade Association, and their regulations generally follow the European Union model. The suggested setting complies with ETSI ES 203 021-2. 3 72 These countries can use the suggested complex setting for voice or data products Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 11 Line Sensing and Status The 73M1x66 supports the means to implement several line status functions such as ring detection, Line In Use detection, parallel pickup detection, and line voltage polarity reversals. To support these functions, 73M1x66 is able to measure the line voltage and current characteristics. In conjunction with these measurements, procedures can be implemented in the host to fully support these capabilities in an application. 11.1 Auxiliary A/D Converter An 8-bit auxiliary A/D converter integrated in the 73M1x66B provides line monitoring and sensing capabilities. The A/D converter input signals are connected to the RGP and RGN pins of the device. It is possible to use this A/D converter to sample signals unrelated to PSTN DAA functions. However, in this application, it is necessary to isolate the input signal with optical or other means since the 73M1x66B is connected directly to the PSTN. Under normal conditions, RGP and RGN are AC coupled to the line through high voltage (250 V) capacitors. Through the use of this auxiliary A/D converter, the following line status sensing features are supported by the 73M1x66B: * * * * * Ring detection. PSTN line already in use detection. Off-hook detection that a parallel phone has been picked-up - parallel pick-up detection (PPU). On-hook detection of DC loop voltage polarity reversals. On-hook detection of Type II Caller ID. 11.2 Ring Detection Ring Detection is provided through circuitry connected to the device pins RGP and RGN. Any large voltage transition (ringing or line reversal) will be a source for the "Wake up" signal to the 73M1x66B. Upon reception of a wake-up signal, the 73M1x66B passes the detected signal to the host where it is to be qualified for frequency and cadence (on and off timing of the ring tone bursts) as a valid ring signal. 11.3 Line In Use Detection (LIU) If the 73M1x66B is preparing to go off-hook and dial, it is required to be aware whether the phone line is already in use by another device. If the 73M1x66B determines that the phone line is presently in use, it can avoid going off-hook and interrupting the call in progress. The timing of the FXO's off-hook transition can be delayed until the FXO determines that the phone line is available. LIU sensing is done at pin DCIN with the Aux A/D. 11.4 Parallel Pick Up (PPU) Parallel Pick Up is a means for the 73M1x66B to determine and notify a host in the case when the DAA is off-hook and a second or parallel-connected device during the course of a connection is also made to go off-hook. 11.5 Polarity Reversal Detection A third type of line sensing requirement is associated with Caller ID protocols found in Japan and some European countries. In these countries, the Caller ID signals are sent prior to the start of normal ringing. A polarity reversal is used to indicate to the FXO that transmission of Caller ID information is about to begin. The detection of a polarity reversal takes place while the FXO is in the on-hook state. 11.6 Off-hook Detection of Caller ID Type II It is also possible to receive Caller ID signals while the telephone is in use, referred to as Type II CID. This requires the 73M1916 to constantly monitor the line for signals, such as special in-band or CAS tones, while the FXO is in the off-hook state. This is done through the normal receive path. Rev. 1.6 73 73M1866B/73M1966B Data Sheet DS_1x66B_001 11.7 Voltage and Current Detection The 73M1x66B is capable of detecting the following circumstances: * * * Under voltage on the line. Over voltage on the line. Over current. These 73M1x66B built-in mechanisms provide protection to both the device itself and the external line circuitry. If enabled, Over Voltage and Over Current detection will cause the 73M1x66B to go on-hook without the intervention of the host. If configured in Line Powered Mode, the detection of an under-voltage condition causes the 73M1x66B to switch automatically to Barrier Powered Operation (see Section 9.2.1). This is done without the intervention of the host. For each of the detection functions there are enable control bits and detection status bits. For each function there is a master detection function enable bit that must be set in order for the functions to work. 11.8 Under Voltage Detection (UVD) Under Voltage Detection is an important feature of 73M1x66B. It determines if the phone line is not capable of supplying the current that the 73M1x66B requires from the line for proper operation. If this function is enabled and if the line is not capable of providing this current, the UVD condition will be asserted and can become a source of interrupt from the 73M1x66B to its connected host. 11.9 Over Voltage Detection (OVD) If enabled, Over Voltage Detection is indicated if the device senses that the line voltage exceeds a defined threshold. The device allows the selection of choice of either 60 Vpk or 70 Vpk (depending upon the attenuation ratio, typically this is 100:1). If enabled, the 73M1x66B will automatically go on-hook if over voltage is detected. 11.10 AC Signal Overload Detection This is the same feature as used for the detection of billing tones (see Section 10.4). In this most generic sense, this detector provides an indicator that the AC signal on the line exceeds a value of 3.5 Vpk. 11.11 Over Current Detection (OID) When the line current exceeds the safe operating range of the 73M1x66B or the external transistors, the device indicates this condition. If enabled, the 73M1x66B will automatically go on-hook if an over current event is detected. 74 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 11.12 Line Sensing Control Functions These registers contain control information to set up and use the 73M1x66B line sensing functions. Table 40: Line Sensing Control Functions Function Mnemonic CIDM Register Location 0x15[4] RXBST 0x14[3] Type Description W Caller ID Mode 0 = Disable Caller ID Mode. (Default) 1 = Enables Caller ID Mode by coupling the signal from the RGN/RGP pins to the PCM DX pins in the appropriate PCM codec format. A 20 dB gain boost is included in the signal path. The RXBST bit should also be set to allow the total nominal gain of 40 dB in the Caller ID path. The normal signal path is disconnected. Received Boost If set to 1, Receive signal is increased by 20 dB. Default is 0. This is used to amplify signals that are passed through the auxiliary A/D when On-Hook. Ring Detection Status Bits Enable Ring Detection Interrupt This control bit enables the ring detection interrupt. 0 = Ring Detection Interrupt Disabled. 1 = Ring Detection Interrupt Enabled. (Default) When 73M1922 detects an incoming ring signal, this bit will be set, if enabled, and reset when read. Ring or Line Reversal Detection Voltage greater than the Ring Detect Threshold was detected at RGP/RGN. This value is latched upon the event and cleared on read. The threshold is determined by RGTH. This is a maskable interrupt. It is enabled by the ENRGDT bit. 0 = No Latched Ring or Line Reversal Detection event. (Default) 1 = A Latched Ring or Line Reversal Detection event. Ringing Monitor Bit 3 monitors the activity of Ringing for further cadence check by the host: 0 = Silent 1 = Ringing This bit is not latched. This status bit is reset when read. Ring Detect Threshold Controls the Ring Detect Threshold assuming a 100:1 reduction of Ring Voltage into the RGP/RGN pins. WO ENRGDT 0x05[0] W RGDT 0x03[0] R RGMON 0x03[3] R 0x0E[1:0] W RGTH Rev. 1.6 RGTH1 RGTH0 Description 0 0 0 1 1 0 1 1 Ring Detect disabled. For ring detection to occur, these bits must be programmed to a nonzero state. 0.15 Vpk equivalent to 15 Vpk at Auxiliary A/D input. 0.30 Vpk equivalent to 30 Vpk at Auxiliary A/D input. 0.45 Vpk equivalent to 45 Vpk at Auxiliary A/D input. 75 73M1866B/73M1966B Data Sheet Function Mnemonic Register Location Type DS_1x66B_001 Description Auxiliary A/D Converter Status Bits LC 0x1C[7:1] R LV 0x1B[7:1] R Loop Current In DC Path Result of Auxiliary A/D measuring the Loop Current (7-bit resolution, least significant bits only). Note: LC0=1 lsb=1.31/128=~10.23 mV=1.25 mA; magnitude only. The value of the resistor between the rectifier bridge and the DCS pin is assumed to be 8.2 . Example: 0000011 30.7 mV/RE=3.74 mA; 0010000 20 mA Note: The AC path also has ~7 mA of loop current that should be added to get the total loop current provided by the line. Line Voltage On and Off Hook Contains the seven most significant bits of an 8-bit A/D representation of the voltage of the input of pin DCI. The voltage at the DCI pin is equal to the decimal value of LV bits [7:1] x 11 mV. For example, if the value of 0100000x is read from LV bits [7:1], this has a decimal value of 64, therefore DCI voltage equals 64 x 11 = 704 mV. RNG 0x1A[7:0] R DET 0x03[2] R ENDET 0x05[2] W ENDT 0x12[1] WO Note that the voltage at the DCI pin is the voltage divided by 5 (off hook) or 100 (on hook). When offhook the diode bridge, switch saturation voltage, etc. should also be added to calculate the voltage at tip and ring. Result of Auxiliary A/D measuring the attenuated ring voltage. Note: 1 lsb=1.31/128=~10.23 mV; 1's compliment. Example: 00100000 327 mV or Ring Voltage=32.7 V Line Sensing Control Detection of Voltage or Current Fault 0 = None of the three conditions is detected. 1 = Indicates the detection of one of three conditions: Under Voltage, Over Voltage and Over Current. This status bit is reset when read. This is a maskable interrupt. It is enabled by the ENDET bit. Enables Line Sensing Interrupt On Host-Side Device This bit controls whether an interrupt is generated based upon the detection of Under Voltage, Over Voltage and Over Current. 0 = Disable detector interrupt (Default) 1 = Enable detector interrupt. Enable Detectors On Line-Side Device 0 = UVD, OVD and OID conditions are ignored. (Default) 1 = Enables UVD, OVD and OID in the Line-Side Device and allows them to be used in the Host-Side Device. Under-Voltage Detection Control and Status ENUVD 0x15[2] WO UVDET 0x1E[6] R 76 Enable Under Voltage Detector On Line-Side Device 0 = Under Voltage Detector not enabled. 1 = Under Voltage Detector enabled. When enabled, the ENNOM bit is temporarily set to the wide bandwidth mode if an under-voltage condition detected to allow fast reacquisition of the line. Under-Voltage Detector On Line-Side Device 0 = Under Voltage condition is not detected at VPS. 1 = Under Voltage condition is detected at VPS. Rev. 1.6 DS_1x66B_001 Function Mnemonic Register Location 73M1866B/73M1966B Data Sheet Type Description Over-Voltage Detection Control and Status ENOVD 0x15[1] OVDET 0x1E[5] OVDTH 0x13[2] ENOLD 0x15[7] OLDET 0x1E[3] ENOID 0x15[0] OIDET 0x1E[4] Rev. 1.6 WO Enable Over-Voltage Detector On Line-Side Device 0 = Over Voltage Detector not enabled. 1 = Over Voltage Detector enabled (not latched). Over voltage detector is enabled if ENOVD, ENFEL and ENNOM all equal 1. R Over-Voltage Detector On Line-Side Device 0 = Over Voltage condition is not detected at RGP/RGN inputs. 1 = Over Voltage Condition is detected at RGP/RGN inputs. WO Over-Voltage Threshold Setting 0 = Over Voltage Threshold is 0.6 Vpk at the chip or 60 Vp on the line. 1 = Over Voltage Threshold is 0.7 Vpk at the chip or 70 Vp on the line. Over-Load Detection Control and Status WO Enable Over-Load Detector 0 = Over Load Detector is not enabled. 1 = Over Load Detector is enabled (not latched). R Over-Load Detector 0 = Over-Load condition is not detected. 1 = Over-Load condition detected. Asserted when the line voltage exceeds 3.5 Vpk typically. OLDET is performed partially in analog domain and partially in digital domain. OLDET is asserted when the delta from aux A/D between two consecutive DCI samples is greater than 76. Over-Current Detection Control and Status WO Enable Over-Current Detector On Line-Side Device 0 = Over-Current Detector is not enabled. (Default) 1 = Over-Current Detector is enabled. R Over-Current (I) Detector On Line-Side Device 0 = Over-Current (I) condition is not detected. 1 = Over-Current (I) condition is detected at the DCS pin when Loop Current is > 125 mA if ILM=0, or > 55 mA if ILM=1. 77 73M1866B/73M1966B Data Sheet 12 DS_1x66B_001 Loopback and Testing Modes Figure 39 shows the six loop back modes available within the 73M1x66B. 73M1916 73M1906B CTL SPI Interface STA Aux A/D STA Tip Interp. Filter PRP TxD SCP LSBI MSBI DSDM Onchip LIC TBS TxAFE TxA TxData PCMLB RxData PCM Interface DIGLB1 DIGLB2 INTLB1 Decim. Filter RxD PRM SCM SinC3 Filter External LIC ALB INTLB2 RxAFE RBS RxA Ring Figure 39: Loopback Modes Highlighted Table 41 describes how the above control bits interact to provide each of the six loopback modes. Table 41: Loopback Modes TEST TMEN DTST LB 0000 0 00 0 0000 0 00 1 0000 0000 0001 0010 0011 78 1 1 0 0 0 10 11 00 00 00 0 0 0 0 0 Loopback Mode Normal Mode. (Default) Mnemonic No Loops Loopback between PCM Compander and FXO core. Digital Loopback Mode Interpolated TxData (TxD) is looped back to the Decimated RxData input (RxD). Remote Analog Loopback Received RxD is looped back as TxD and transmitted back to the 73M1x66B Line-Side Device; RxD is D/A converted to yield the analog transmit signal (TxA). Digital Loopback Mode DR Transmit Bit Stream (TBS) is looped back to receive digital channel and received at DX (DIGLB2). Remote Analog Loopback Receive analog signal is converted to Received Bit Stream (RBS) and is looped back to TBS and the analog transmit channel (INTLB2). Analog Loopback The transmit DR data is connected to the receiver at the analog interface and received at the DX pin (ALB). PCMLB DIGLB1 INTLB1 DIGLB2 INTLB2 ALB Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 12.1 Loopback Controls Table 42 describes the registers used for loopback control. Table 42: Loopback Controls Function Mnemonic TMEN DTST Register Location 0x02[7] 0x07[1:0] Type W W Description Test Mode Enable Used to enable the activation of the test loops controlled by the DTST bits (DIGLB1 and INTLB1). 0 = Disables DTST loops. 1 = Enables DTST loops. TMEN has to be set to 1 before the setting of the DTST bits. Digital Test Mode Select These control bits enable DIGLB1 and INTLB1. Prior to writing to these bits, TMEN must be set to 1. DTST1 0 1 1 LB 0x24[0] W TEST 0x18[7:4] W DTST0 0 0 1 Selected Test Mode Normal (Default) DIGLB1 INTLB1 Loopback 0 = Disables PCM Loopback. 1 = Enables PCM Loopback within the Host-Side Device. This four-bit field is used to enable the loopback mode per the following table: TEST Loopback Mode 0000 Normal Mode. (Default) Transmit and receive channels are independent. 0001 Digital Loopback Mode. DR Transmit Bit Stream (TBS) is looped back to receive digital channel and received at DX (DIGLB2). 0010 Remote Analog Loopback. Receive analog signal is converted to Received Bit Stream (RBS) and is looped back to TBS and the analog transmit channel (INTLB2). 0011 Analog Loopback. The transmit DR data is connected to the receiver at the analog interface and received at the DX pin (ALB). Rev. 1.6 79 73M1866B/73M1966B Data Sheet DS_1x66B_001 13 Performance This section provides an overview of typical performance characteristics measured using 73M1x66B production devices on a Teridian Reference Board. The measurements were made using a Wandel and Goltermann PCM-4 test unit. The tests conform to ITU-T Recommendation G.712 (2001). For more information, see the 73M1966B Performance Characterization. 13.1 Transmit Figure 40 provides performance characteristics for transmit gain tracking. Figure 40: Variation of Transmit Gain Digital Input to Analog Output at the Line 80 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet Figure 41 provides performance characteristics for receive gain variation against frequency. Figure 41: Gain versus Frequency for Digital Input to Analog Output at the Line Figure 42 provides performance characteristics for distortion in the direction of the digital port to analog port. Figure 42: Signal to Total Distortion versus Input Level for Digital Input to Analog Output to the Line Rev. 1.6 81 73M1866B/73M1966B Data Sheet DS_1x66B_001 13.2 Receive Figure 43 provides performance characteristics for receive gain tracking. Figure 43: Variation of Receiver Analog Gain at the Line to the Digital DX Output 82 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet Figure 44 provides performance characteristics for gain variation against frequency. Figure 44: Gain versus Frequency for Analog Input at the Line to the Digital DX Output Figure 45 provides performance characteristics for distortion in the direction of the analog port to digital port. Figure 45: Signal to Total Distortion versus Input Level for Analog at the Line to the Digital DX Output Rev. 1.6 83 73M1866B/73M1966B Data Sheet DS_1x66B_001 Figure 46: Return Loss, @ 80 mA 84 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 14 Package Layout Figure 47: 20-Pin TSSOP Package Dimensions 0.85 NOM./ 0.9MAX. 5 0.00 / 0.005 2.5 0.20 REF. 1 2.5 2 3 5 SEATING PLANE TOP VIEW SIDE VIEW 0.35 / 0.45 3.0 / 3.75 CHAMFERED 0.30 0.18 / 0.3 1.5 / 1.875 1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.5 0.2 MIN. 0.35 / 0.45 0.5 0.25 BOTTOM VIEW Figure 48: 32-Pin QFN Package Dimensions Rev. 1.6 85 73M1866B/73M1966B Data Sheet DS_1x66B_001 Figure 49: 42-Pin QFN Package Dimensions 86 Rev. 1.6 DS_1x66B_001 73M1866B/73M1966B Data Sheet 15 Ordering Information Table 43 lists the order numbers and packaging marks used to identify 73M1x66B products. Table 43: Order Numbers and Packaging Marks Part Description 73M1966B 32-Pin QFN, Lead free Order Number 73M1966B-IM/F 73M1966B 32-Pin QFN, Lead free, Tape and Reel 73M1966B 20-Pin TSSOP, Lead free 73M1966B-IMR/F 73M1966B 20-Pin TSSOP, Lead free, Tape and Reel 73M1866B 42-Pin QFN, Lead free 73M1866B 42-Pin QFN, Lead free, Tape and Reel 73M1966B-IVT/F 73M1966B-IVTR/F 73M1866B-IM/F 73M1866B-IMR/F Packaging Mark 73M1916A-M 73M1906B 73M1916A-M 73M1906B 73M1916AVT 73M1906BVT 73M1916AVT 73M1906BVT 73M1866B-IM 73M1866B-IM Host/Line Line-Side IC Host-Side IC Line-Side IC Host-Side IC Line-Side IC Host -Side IC Line-Side IC Host -Side IC 16 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73M1966B, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: fxo.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com. Rev. 1.6 87 73M1866B/73M1966B Data Sheet DS_1x66B_001 Revision History Revision Date 1.0 11/7/2007 1.1 1.2 1.3 1.4 5/13/2008 7/30/2008 11/17/2008 7/21/2009 1.5 1.6 10/16/2009 4/2/2010 Description First publication. Replaced Table 16 with a new table. Replaced the schematics in Figure 12 and Figure 13 with new schematics. Moved the steps to enable the calibration of receive DC offset from Section 8.8.3 to the 73M1866B/73M1966B Implementer's Guide. Corrected the Types (R, W, WO) in Table 32. Rewrote the description of the ADJ bit. Added clarification to the description of the PLDM bit. Added clarification to the description of the RGDT bit. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. MicroDAA is a registered trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company's warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com 88 Rev. 1.6