73M1866B/73M1966B
MicroDAA™ with PCM Highway
Simplifying System Integration™ D ATA SHEET
DS_1x66B_001 April 2010
Rev. 1.6 © 2010 Teridi an Semiconduct or C or por ati on 1
DESCRIPTION
The 73M1866B and 73M1966B use the Teridian
pat ented Data Ac cess Arrangem ent function
(MicroDAA®) designed exclusivel y for Foreign-
Exchange-Office (F XO) in Voice-over-IP (VoIP)
applications. These devices provide much of the
circ uitry required t o connect PCM formatted
voi ce c hannel s t o a PSTN via a t wo-wire twisted
pair i nterface. The package options provide the
necessary func ti onal pr ogr am mab ility and
protection r equi r ed for easy worldwide
homologation.
The fami l y of d evices cons i sts of the 73M1866B
and the 73M1966B. The 73M1866B MicroDAA
is the world’s first s ing le-package silicon Data
Access Arran gement (DAA). Suitable
applications for the 73M1866B and 73M1966B
devices inc lu de VoIP equip ment that must
provide connect ivity to t he PSTN for purpos es of
guarant eeing emer gency servic e calling,
redundancy for s uppl ement ar y connect ivity for
voi ce, and m aint enance ser vices.
The 73M1966B devic e set consis ts of the
73M1906B Host-Side D evice t hat provides digital
dat a, c ontrol interfaces and power to the
73M1916 Li ne -Sid e D evice.
These de vices are based on an i nnovative an d
patented technology, which sets new standards
in reliability an d cost . A small pu lse transformer
forms a di git al isol ati on barr ier, t r ansf er r in g both
power and data to th e PSTN li ne-side
components. This method r esults in r eliable
operation in the presence of EMI and a tolerance
t o l ine voltage variation s by p r oviding power to
the Line-Side Device acr oss the barr i er . The
devices also support the ability to provide up to
an additional +6 dB of analog gain to the line-
si de transmit and +3 dB i n the receive si gnal
pat hs. The device suppor ts transmi t and receive
digital gai n r angi ng from –18 dB to +7.375 dB by
increments of 0.125 dB.
The digital side provides a PCM highway
interface with aut omat i c c l ock r ate detection.
With an 8-kH z sam pl ing rate, the devices include
an ITU-T G.711 c om pl iant codec with selectable
µ-law and A-law companding modes. The
devices also provide a 16-bit linear mode, which
is suitab le for int erfacing with wide band codecs,
as w ell as 16 kHz sam pl ing rate. D evice control
is per formed over an SPI interfac e. The SPI
suppor ts dai sy chain oper ation.
Through i ts PCM int er face, the 73M1966B c an
be connect ed to other PCM enabl ed devices
such as POTS codecs, ISDN codecs, E1/T 1
framers, etc .
A ddit i onal DAA fun ct ions supported by t he
73M1x66B devices include a call progress
monitor, Caller ID Type I and II, rin g detection,
pulse dialing, billing tone detection and polarity
reversal detect i on.
APPLICATIONS
• Computer Telephony
• VOIP Equipm ent
• PBX System s
• Internet Appliances
• V oicemail Systems
• P OTS Termi nation Equi pment
FEATURES
• P CM highway data interfac e supporting both
sl ave and mast er m odes
• PCM highway interface supporting both E-1
and T-1
• S PI c ontrol interface, wit h daisy chain
support for up to 16 devices
• Des igned to meet gl obal DAA compli ance
FCC, ETSI ES 203 021-2, JATE and other
PTT standards.
• 8 kH z and 16 kHz sam pl e r ates
• 16-bit linear mode
• TX and RX gains adjustable in 0.125 dB
increments
• μ-La w, A-law ITU-T R ecom mend ati o n G. 7 11
compliant compander operation
• A utomati c clock rate det ect ion
• Low power modes
• P olarity Reversal det ect ion
• GPIO fo r user -configurable I/O ports
• Call P r ogr ess M oni tor
• I solation up to 6 kV
• THD -80 dB
• 5 V toleran t I/O on selected pins
• 3. 0 V – 3.6 V operating voltage
• I ndust r ial temperature range ( -40 °C to +85 °C)
• 5 x5 mm 32-p in Q FN or 20-pin TSSOP
packages
• RoHS compliant (6 /6) lead-free pack age
73M1866B/73M1966B Data Sheet DS_1x66B_001
2 Rev. 1.6
Table of Contents
1 Introduction ................................................................................................................................... 6
2 Pinout ............................................................................................................................................. 8
2.1 73M1906B 20-Pi n T SSO P Pi no ut ............................................................................................ 8
2.2 73M 19 16 2 0-Pin TSSOP Pinout .............................................................................................. 9
2.3 73M1906B 32-Pin QFN Pinout .............................................................................................. 10
2.4 73M19 16 3 2-Pin QFN Pinout ................................................................................................ 12
2.5 73M1866B Pinout ................................................................................................................. 14
2.6 Req ui site Use of E xposed Bottom Pad on 73M1866B and 73M1966B QFN P ack ages .......... 15
3 Electrical Characteristics and Specifications............................................................................. 16
3.1 Is ol ati on Barr ier Characterist ics ............................................................................................. 16
3.2 Electrical Specifications......................................................................................................... 16
3.2.1 Ab solute Maximum Ratings ....................................................................................... 16
3.2.2 Recommended Operating Condit i ons ........................................................................ 16
3.2.3 DC Characterist ic s ..................................................................................................... 17
3.3 Interface Timing Specification................................................................................................ 18
3.3.1 SP I Int er face ............................................................................................................. 18
3.3.2 PCM H ig hway Interface ............................................................................................. 19
3.4 Analog Specificat i ons ............................................................................................................ 20
3.4.1 DC Specifications ...................................................................................................... 20
3.4.2 Cal l Pr ogress M oni tor ................................................................................................ 21
3.5 73M1x66B Line-Side El ectrical Spec i fi cat ions ( 73M 1916) ...................................................... 22
3.6 Refer ence and Regulati on ..................................................................................................... 23
3.7 DC Tran sfer Characteri st ics .................................................................................................. 23
3.8 T ransmit Path ....................................................................................................................... 24
3.9 Receive Pat h ........................................................................................................................ 25
3.10 Transmit Hybrid Can c ellation ................................................................................................ 26
3.11 Receive Not ch Fi lt er .............................................................................................................. 26
3.12 Detectors .............................................................................................................................. 27
3.12.1 Over-Voltage D etec tor ............................................................................................... 27
3.12.2 Over-Cu r rent D etect or ............................................................................................... 27
3.12.3 Under-Vol tage D etec tor ............................................................................................. 27
3.12.4 Over-Load D etec tor ................................................................................................... 27
4 Appl ications Information ............................................................................................................. 28
4.1 Example Sc hem atic of t he 73M 1966B and 73M1866B .......................................................... 28
4.2 Bill of Materials...................................................................................................................... 30
4.3 Over-Voltage and EMI Protecti on .......................................................................................... 31
4.4 Is ol ati on Barr ier Puls e Trans former ....................................................................................... 32
5 SPI Inte rface ................................................................................................................................. 33
6 Contr ol and Status Regi sters ...................................................................................................... 37
7 Hardw are Control Functions ....................................................................................................... 41
7.1 Dev ic e Re vision .................................................................................................................... 41
7.2 Interrupt Control .................................................................................................................... 41
7.3 Power M anagement .............................................................................................................. 42
7.4 Device Cl ock M anagement.................................................................................................... 42
7.5 GPIO Registers ..................................................................................................................... 43
7.6 Call Progr ess M onit or ............................................................................................................ 44
7.7 16 kHz Operation of C all Progress M oni tor ............................................................................ 44
7.8 Device Reset ........................................................................................................................ 44
8 PCM Highway Inter face and S ignal Processing ......................................................................... 45
8.1 PCM Highway Interface Timing ............................................................................................. 45
8.2 PCM Cloc k Fr equencies ........................................................................................................ 47
8.3 Master Mode ......................................................................................................................... 47
8.4 A-law / μ-law C ompander ...................................................................................................... 47
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 3
8.5 Transmit and R eceive Levels ................................................................................................ 48
8.5.1 A-Law........................................................................................................................ 48
8.5.2 μ-Law ........................................................................................................................ 48
8.5.3 Transmit and Receive Level Control .......................................................................... 48
8.6 T ransmit Path Signal Processing ........................................................................................... 49
8.6.1 G ener al Descripti on ................................................................................................... 49
8.6.2 Total Trans mit P ath R esponse................................................................................... 49
8.6.3 73M1x66B Transmit Spec trum ................................................................................... 50
8.7 Receive Pat h Si gnal Pr ocessing ............................................................................................ 50
8.7.1 G ener al Descripti on ................................................................................................... 50
8.7.2 Total R eceive Pat h R esponse.................................................................................... 51
8.7.3 Receive r D C O ffset Subtrac ti on ................................................................................. 51
8.8 PCM Cont r ol Functions ......................................................................................................... 52
8.8.1 Tr ansmit and Receive Level Control .......................................................................... 57
8.8.2 Time Slot A ss i gnment Example ................................................................................. 59
9 Barri er Informa tion ...................................................................................................................... 60
9.1 Is ol ati on Barr ier ..................................................................................................................... 60
9.2 Barr i er Pow er ed Options ....................................................................................................... 60
9.2.1 Barri er Power ed Operati on ........................................................................................ 60
9.2.2 Line Powered Operation ............................................................................................ 60
9.3 Syn chronization of t he Barr ier ............................................................................................... 60
9.4 Auto-Poll ............................................................................................................................... 61
9.5 Barr i er Cont r ol Funct i ons ...................................................................................................... 61
9.6 Line-Side D evice O per ati ng Modes ....................................................................................... 63
9.7 Fail-Safe Operation of Line-Side Device ................................................................................ 63
10 Configurable Direct Access Arrangement (DAA) ....................................................................... 64
10.1 Pu ls e Dialing ......................................................................................................................... 64
10.2 DC Termin at ion ..................................................................................................................... 64
10.3 AC Termi nati on ..................................................................................................................... 66
10.4 Billin g Tone Rejection ........................................................................................................... 67
10.5 Trans-Hyb rid Cancellation ..................................................................................................... 68
10.6 Direct Access Arr angem ent Control Functions ....................................................................... 68
10.7 International R egister Settings Table for DC and A C Term in ati ons ........................................ 72
11 Line Sensing and Status ............................................................................................................. 73
11.1 Au xiliary A/D Converter ......................................................................................................... 73
11.2 Ring Detection ...................................................................................................................... 73
11.3 Line In U se Detec tion ( LIU ) ................................................................................................... 73
11.4 Parallel Pic k Up (PPU) .......................................................................................................... 73
11.5 Pol ar ity Re versal D etec tion ................................................................................................... 73
11.6 Off-hook Det ect ion of Caller ID Type II .................................................................................. 73
11.7 Vol tage and Cur r ent D etec ti on .............................................................................................. 74
11.8 Under Voltage Detec tion ( UV D) ............................................................................................. 74
11.9 Over Voltage Detec tion ( OVD) .............................................................................................. 74
11.10 A C S ignal Overload Detec tion ............................................................................................. 74
11.11 Over Current D etection (OID) .............................................................................................. 74
11.12 Line Sensing Control Functi ons........................................................................................... 75
12 Loopback and Testing Modes ..................................................................................................... 78
13 Performance ................................................................................................................................ 80
13.1 Transmit................................................................................................................................ 80
13.2 Receive................................................................................................................................. 82
14 Package Layout ........................................................................................................................... 85
15 Order i ng Information ................................................................................................................... 87
16 Contact Informa tion ..................................................................................................................... 87
Revisi on H istor y .................................................................................................................................. 88
73M1866B/73M1966B Data Sheet DS_1x66B_001
4 Rev. 1.6
Figures
Figure 1: Simple 73M1x66B Reference Block Diagram ............................................................................ 6
Figure 2: 73M1906B 20-Pin TSSOP Pinout .............................................................................................. 8
Figure 3: 73M1916 20-Pi n T SS OP Pi no u t ................................................................................................ 9
Figure 4: 73M1906B 32-Pin QFN Pinout ................................................................................................ 10
Figure 5: 73M1916 32-Pin QFN Pinout .................................................................................................. 12
Figure 6: 73M1866B 42-Pin Pinout ........................................................................................................ 14
Fig ure 7: SPI Timing Diagram ................................................................................................................ 18
Fi gur e 8: PCM Timing Diagr am for Positive Ed ge Trans mit Mode and Negative Edge Receiv e M ode ..... 19
Fi gur e 9: PCM Timing Diagr am for Neg ative Edge Transmit Mode and Posit i ve Edge Rec eiv e M ode ..... 20
Fi gur e 10: Fr equency Response of the Call Pr ogr ess M oni tor Fil ter ....................................................... 21
Fi gur e 11: Dem o Board Circuit Connect i ng AOUT t o a Speaker ............................................................. 21
Fi gur e 12: Recommended C irc ui t for the 73M1966B .............................................................................. 28
Fi gur e 13: Recommended C irc ui t for the 73M1866B .............................................................................. 29
Fi gur e 14: Suggest ed Over-Volt age Protect i on and EMI Suppression Circuit ......................................... 31
Fi gur e 15: Dai sy-Chain Con figuration .................................................................................................... 34
Figure 16: SPI Write Operation – 8-bit Mode .......................................................................................... 34
Figure 17: SPI Read Transact ion – 8-bit Mode ....................................................................................... 35
Figure 18: SPI Write T ransaction – 16-bit Mode ..................................................................................... 35
Fi gur e 19: SPI Read Transaction – 16-bit Mode ..................................................................................... 35
Fi gur e 20: 8-b i t Transmis sion Example .................................................................................................. 45
Fi gur e 21: 16-bit Tr ansmission Ex ample ................................................................................................ 46
Fi gur e 22: Example of PCM H ighway Interc onnect ................................................................................. 46
Fi gur e 23: Example of PCM H ighway Int er connect for T ypical Large Systems ....................................... 46
Fi gur e 24: Mappi ng of A-law C ode to 16-bit Code .................................................................................. 48
Figure 25: Mapping of μ-law Cod e to 16-b it Code .................................................................................. 48
Figure 26: Transmit Pat h Overall Frequenc y Respon se to Fs of 8 kHz ................................................... 49
Fi gur e 27: Tran smi t Path P ass band R esponse for an 8 kHz Sampl e R ate .............................................. 49
Fi gur e 28: Tran smi t Spec trum to 32 kHz for an 8 kH z Sam pl e R ate ....................................................... 50
Fi gur e 29: Overall Frequenc y Respon se of t he R eceive Pat h ................................................................. 51
Figure 30: Pass-band Response of the Overall R eceive Pat h ................................................................. 51
Fig ure 31: Timing Relations hip s wit h V arious TTS , TCS, TPOL, and RTS, RCS, RPOL Settings ............ 59
Fi gur e 32: Line-S ide Device AC and DC Circuit s .................................................................................... 63
Figure 33: DC-IV C har act er istics ............................................................................................................ 64
Figure 34: Tip-Ring Voltage versus Cur r ent Using D i fferent DC IV Settings ............................................. 65
Fi gur e 35: Vol tage vers us Curr ent in the Seize Mode is th e Same for A ll DCI V Sett in gs ......................... 66
Fi gur e 36: Magni tude Response of Impedanc e M atching F i lt er , ACZ (3:0)= 0010 (ES 203 021-2) ........... 67
Fi gur e 37: Magni tude Response of Billing Tone Notch Fil ter .................................................................. 67
Figure 38: Trans-hybrid Cancellation ..................................................................................................... 68
Fi gur e 39: Loopback M odes Hi ghlighted ................................................................................................ 78
Fi gur e 40: Var i ati on of Tr ansmi t G ai n Digital Input t o Anal og Output at the Li ne ..................................... 80
Figure 41: Gain versus Frequency for Digital Input to Analog Output at the Line ..................................... 81
Figure 42: Signal to Total Distortion versus Input Level for Digital Input to Analog Output to the Line ...... 81
Fi gur e 43: Var i ati on of Receiver Analog Gain at the Line to the Digit al DX Output .................................. 82
Figure 44: Gain versus Frequency for Analog Input at the Line to the Digital DX Output ......................... 83
Fi gur e 45: Si gnal t o Tot al Dis tortion versu s Input Level for Analog at the Li ne to the D i gi tal D X Output ... 83
Figure 46: Return Loss, @ 80 mA .......................................................................................................... 84
Fi gur e 47: 20-Pin TS SOP Package D i mensi ons ..................................................................................... 85
Fi gur e 48: 32-Pin QFN P ack age D imens i ons ......................................................................................... 85
Fi gur e 49: 42-Pi n QF N P ack age D imensions ......................................................................................... 86
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 5
Tables
Table 1: 73M1906B 20-Pin TSSOP Pin Definitions .................................................................................. 8
Table 2: 73M1916 20-Pin TSSOP Pin Definit ion s ..................................................................................... 9
Table 3: 73M1906B 32-Pin QFN Pin Definition s ..................................................................................... 10
Table 4: 73M1916 32-Pin QFN Pin Definitions ....................................................................................... 12
Table 5: 73M1866B Pin Definitions ........................................................................................................ 14
Tabl e 6: Isolat i on Barr ier Char act er istics ................................................................................................ 16
Tabl e 7: Absolut e M aximum Devic e Rat i ngs .......................................................................................... 16
Tabl e 8: Recommended Operating C ondit i ons ....................................................................................... 16
Tabl e 9: DC Charact er istics ................................................................................................................... 17
Table 10: S PI Int er face S witchin g Charac teri stic s .................................................................................. 18
Tabl e 11: Switching C har act er istics – PC M Interface ( Sl ave Mode) ........................................................ 19
Tabl e 12: Switching C har act er istics – PC M Interface ( Master M ode) ...................................................... 19
Tabl e 13: Reference Voltage S pecifications ........................................................................................... 20
Tabl e 14: Component Values for the S peaker D r i ver .............................................................................. 21
Tabl e 15: Cal l P r ogr ess M oni tor Specificat i on ........................................................................................ 22
Table 16: Line-Side Abs olu te Maximum Ratings .................................................................................... 22
Tabl e 17: VBG Specificat i ons ................................................................................................................ 23
Table 18: Maximum DC Tran smit Levels ................................................................................................ 23
Tabl e 19: Tran smi t Path ......................................................................................................................... 24
Tabl e 20: Receive P ath ......................................................................................................................... 25
Tab le 21: Tran s mit Hybrid Cancellation Characteristics .......................................................................... 26
Tabl e 22: Receive Notch Fil ter ............................................................................................................... 26
Tabl e 23: Over-voltage D etector ............................................................................................................ 27
Tabl e 24: Over-current Detec tor ............................................................................................................. 27
Tabl e 25: Under -v ol tage D etec tor .......................................................................................................... 27
Tabl e 26: Over-l oad D etect or ................................................................................................................. 27
Tabl e 27: Reference Bill of Mat er ials for 73M1x66B ............................................................................... 30
Tabl e 28: Reference Bill of Mat er ials for Figure 14 ................................................................................. 31
Tabl e 29: Compat ib le P ul se Tran sformer Sour ces ................................................................................. 32
Tabl e 30: Pulse Transformer El ectrical C haracteristics ........................................................................... 32
Tabl e 31: Control and Status Reg ister M ap ............................................................................................ 37
Tabl e 32: Alphabetical Bit Map .............................................................................................................. 38
Tabl e 33: PCM Cont r ol Functi ons .......................................................................................................... 52
Tabl e 34: Tran smi t Gain C ontrol ............................................................................................................ 57
Table 35: Recommended Gain Setting ................................................................................................... 57
Tabl e 36: Receive G ai n Cont r ol ............................................................................................................. 59
Tabl e 37: Barri er Cont r ol Functions ........................................................................................................ 61
Tabl e 38: DAA Control Funct i ons ........................................................................................................... 68
Tabl e 39: Recommended R egi ster Set ti ngs for I nternational Compatibility ............................................. 72
Table 40 : Li ne Sensing Control Functi ons .............................................................................................. 75
Tabl e 41: Loopbac k Modes .................................................................................................................... 78
Tabl e 42: Loopbac k Modes Summary .................................................................................................... 79
Tabl e 43: Order N um ber s and Pac kaging Mar ks .................................................................................... 87
73M1866B/73M1966B Data Sheet DS_1x66B_001
6 Rev. 1.6
1 Introduction
The 73M1966B is a two-device chip set that provides embedded FXO functionality by connecting a PCM
interface to a voic e-band P STN. The devic e set supports ITU-T Recom mendati o n G. 7 11 µ-law and A-law
compand ing, and al so a 16-b it linear m ode. High -volt age i solation is pr ovided by the physical separation
of the H ost-Side (73M19106) and Line-Side (73M1916) Devices. The Host-Side and the Li ne -Side
Dev ices communicat e with each other using a single pul se trans former. A few low-cost compon ent s
complete t he DA A in terfac e to the net work . Th e pul se transformer trans mits encoded digi tal data rather
t han anal og signal s as with ot her transformer designs. Dat a i s transm itted and r eceived without the usu al
degradat ion from c om mon m ode noise and magneti c coupl ing t ypical of ot her capacit i ve and voice-band
t r ansformer tec hni ques. The data stream passed bet ween t he H ost -Side and Line-Side Devices includ es
t he m edi a stream data, control, s tatus, and clocki ng i nformat i on.
This data s heet des cribes both the 73M1966B and 73M1866B, whi ch will be coll ectiv ely re ferr ed to as t he
73M1x66B in this document.
A unique capabi l it y of the 73M 1x66B Hos t Side device (73M1906B) is it s abilit y to provide po wer to t he
73M1x66B Line Side device (73M1916) via the pulse transformer.
The 73M1906B exchanges control and status information with the host u sing the SPI interfac e, wh i le t he
P CM enc oded media streams connect wit h other PCM-enabled devices using the PCM highway bus
interface.
Figure 1 shows a referenc e bl ock diagram of th e 73M1x66B connec ted by a p ul se transformer and
example exter nal line interface circ ui try s hown for clarification.
PRM SCM
(LSBI) SinC3
Filter
On-Chip
LIC
(OnLIC)
SPI
Interface
PCM
Interface
Interpolation
Filter
Filter
PCM
SPI
Tip
Ring
PRP SCP
Host -Side Device
73M1906B
Line-Side Device
73M1916
Aux A/D
TxA
RxA
Off-Chip
LIC
(OffLIC)
(HSBI)
Decimation
Transmit
Receive
Host
Interface
Side
Barrier Interface
Side
Barrier
Line
Digital
Sigma
Delta
Modulator
Transmit
Analog
Front End
Receive
Analog
Front End
(with Sigma
Delta
Modulator)
Call Progress Monitor Audio Out
Figure 1: Simple 73M 1x66B Reference Block Diagram
The H ost -Side Device (73M1906B) consists of:
1. PCM Interface B lock (PCM )
2. SPI Interface B lock (SPI )
3. Transmit Interpolation Filter
4. Receive Dec imation F i lt er
5. Host-Side Barrier I nt erface Circuit (HSBI)
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 7
The Line-Si de D evice (73M1916) consists of:
1. Di git al Si gma Delta Modulat or
2. Transmit Analog Front End
3. Receive A nalog Front End inc lud ing S igma Del ta Modul ator
4. Sinc3 Filter (Sinc3 )
5. On-chip Line Interface Circuit
6. Line-Sid e Bar r i er Interfac e C irc ui t (LSBI)
Rec eived data from a host connected to the PCM bus is interpol ated from the s am pl ing freq uency of
8 kH z or 16 kHz (for PCM encoded streams) to twice the s am pl ing frequency. Th e control i nformat i on is
multiplexed with the audio stream signals and t r ansmi tted acros s t he isol ati on bar r i er to the Line-Side
Device. In the Line-Si de Device, the t wo streams are sep ar ated and the audio signal is converted to
analog for trans mis sion to the l i ne.
A n audio stream received at the analog line input pins is converted to a serialized data stream an d, al ong
with st atus information su ch as line c ondi ti on from t he Auxili ary Anal og to Dig it al Converter , is transmitted
over the isolation bar r i er using the pulse t r ansformer. Th e data is extr act ed with status information being
t r ansmitted on the SPI . Th e audi o stream i s sent to a hos t using the P CM bus.
The 73M1x66B is an enhanced version of the 73M1966 that includes the additional functionality of finer
res ol uti on of trans mit and rec ei ve gain, receive r DC offset s ubtract ion and support for T-1 PCLK
frequencies.
73M1866B/73M1966B Data Sheet DS_1x66B_001
8 Rev. 1.6
2 Pinout
The 73M1906B and the 73M1916 are supplied as 20-pi n TS SOP packages and as 32-pin QFN packages.
2.1 73M190 6 B 20-Pin TSSOP Pinout
Figure 2 shows t he 73M 1906B 20-pin TSSOP pinout.
73M1906B
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
CS
VPD
DR
DX
FS
PCLKO
PCLKI
VNA/VND
AOUT
VPA VNT
SCLK
SDI
SDIT
SDO
RST
PRM
PRP
VPT
INT
Figure 2: 73M1906B 20-Pin TSSOP Pinout
Tabl e 1 describes the pin functions for the devic e. D ecoupling capacit or s on t he power s uppl i es s hould
be included for each pair of supply pins.
Table 1: 73M1906B 20-Pin TSSOP Pin Definitions
Pin
Number Pin
Name Type Description
1 CS I S PI c hip sel ect (ac tive low)
2 VPD PWRI P osit ive dig ital supp ly
3 DR I P CM transmit data s ent to the D to A
4 DX O P CM received data from the A to D
5 FS I/O PC M frame synchr oni zation
6 PCLKO O PCM clock output
7 PCLKI I PCM clock in
8 VNA/VND GND Negativ e analog/ di gi tal gr ound
9 AOUT O A udio out put – m ust be buffered for speaker
10 VPA PWRI P ositive analog supply
11 VNT GND N egati ve t r ansformer supply
12 PRM I/O Tran sformer pr imary minus
13 PRP I/O Trans former pri mary plus
14 VPT PWRI P ositive trans former supply
15 RST I Hardware reset ( act ive low)
16 SDIT O S PI data out for dai sy chain mode
17 SDI I S PI data in
18 SDO O S PI data out
19 INT O Interrupt / ring detect (active low – open drain)
20
SCLK
I
SPI clock
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 9
2.2 73M191 6 20-Pin TSSOP Pinout
Figure 3 shows the 73M1916 20-pin TSS OP pi no u t .
73M1916
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DCI
RGN
RGP
OFH
VNX
SCP
MID
VPX
SRE
SRB VBG
DCS
DCD
TXM
RXM
RXP
ACS
VNS
VPS
DCG
Figure 3: 73M1916 20-Pi n TSSOP Pinout
Tabl e 2 describes the pin functions for the device. Decoupling capacitors on the power supplies should
be included for each pair of supply pins.
Table 2: 73M1916 20-Pi n TSSOP Pin Definiti ons
Pin
Number Pi n Name Type Description
1 DCI I DC loop input
2 RGN I Ring detec t negative voltag e inp ut
3 RGP I Ring detect positive voltage input
4 OFH O Off-hook cont r ol
5 VNX GND N egati ve suppl y volt age ( line s i de of the barri er )
6 SCP I/O Positive si de of the secondary p ulse transformer winding
7 MID I/O C ha r ge pum p mi d po i nt
8
VPX
PWR
S upply fr om t he bar r i er
9 SRE I Vol tage regul ator sense
10 SRB O V olt age r egul ator dr i ve
11
VBG
O
VBG bypass, connect to 0.1 μF capacitor to VNS
12 ACS I AC current sense
13 VNS GND A nalog n egati ve suppl y voltage
14 VPS PWRO Analog positive suppl y voltage (output)
15 RXP I Rec eive plus – s ig nal input
16 RXM I R eceive minus – signal input
17 TXM O T ra ns mit minus – transh ybri d cancellation output
18 DCD O DC l oop output
19 DCS I DC loop cur r ent s ense
20 DCG O DC loop control
73M1866B/73M1966B Data Sheet DS_1x66B_001
10 Rev. 1 .6
2.3 73M190 6 B 32-Pin QFN Pinout
Figure 4 shows t he 73M 1906B 32-pin QFN pinout.
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
GPIO7
TSC
DX
VPD
FS
PCLKO
PCLKI
VND
SDO
SDI
SDIT
RST
VPD
VPT
PRP
PRM
VNA /
VNPLL
VBG
AOUT
VPA /
VPPLL
N/C
VNT
N/C
N/C
73M1906B
GPIO5
GPIO6
DR
VPD
CS
SCLK
INT
VND
Figure 4: 73M1906B 32-Pin QFN Pinout
Table 3 describes the pin functions for the device. Decoupling capacitors on the power supplies should
be included for each pair of supply pins.
Table 3: 73M1906B 32-Pin QFN Pin Definitions
Pin
Number
Pi n Na me
Type Description
1 GPIO7 I/O Configurable input/output pin
2 TSC O P CM time slot c ontrol ( active low)
3 DX O P CM received data from the A to D
4 VPD PWR Posit ive dig ital supp ly
5 FS I/O PC M frame synchr oni zation
6 PCLKO O PCM clock output
7
PCLKI
I
PCM clock in
8 VND GND Negative digital gr ound
9 VNA/VNPLL GND Negative analog/PLL ground
10 VBG O B and gap voltage reference monitor
11 AOUT O Audi o output – must be buffered for speaker
12
VPA/VPPLL
PWR
P ositive analog/PLL supply
13 N/C – No c onnect
14 VNT GND N egati ve t r ansformer supply
15 N/C – No c onnect
16 N/C – No c onnect
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 11
Pin
Number Pi n Name Type Description
17 PRM I/O Tran sformer pr imary minus
18 PRP I/O Trans former pri mary plus
19 VPT PWR Positive t r ansf or mer s uppl y
20 VPD PWR Posit ive digital supply
21
RST
I
Hardw ar e reset (act ive low)
22 SDIT O S PI data out for daisy-chain mode
23 SDI I S PI data in
24 SDO O S PI data out
25 GPIO5 I/O Configurable input/output pin
26 VND GND N egative digi tal gr ound
27 INT O Interrupt / ring detect (active low – open drain)
28 SCLK I SPI clock
29 CS I S PI c hip sel ect (active low)
30 VPD PWR Positive dig ital supp ly
31 DR I P CM transmit data s ent to the D to A
32 GPIO6 I/O Configurable input/output pin
73M1866B/73M1966B Data Sheet DS_1x66B_001
12 Rev. 1 .6
2.4 73M191 6 32-Pin QFN Pinout
Figure 5 shows the 73M1916 32-pin QF N pinout .
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
CKO
OFH
CKI
VNX
SCP
MID
SCM
VPX
RST
DCD
TST
TXM
SACIN
RXM
RXP
VPS
RCT
BYP
SRE
SRB
VNS
VBG
ACS
VNS
73M1916
DCS
GPO
GPI
VNS/VND
RGP
RGN
DCI
DCG
Figure 5: 73M1916 32-Pi n QFN Pinout
Table 4 describes the pin functions for the device. Decoupling capacitors on the power supplies should
be inc lud ed for each pair of supply pins.
Table 4: 73M1916 32-Pi n QFN Pin De finitions
Pin
Number
Pin
Name Type Description
1 CKO O Tes t point for recovered clock
2 OFH O Off-hook control
3 CKI I Test input for clock
4 VNX GND N egati ve suppl y volt age
5 SCP I/O Positive si de of the secondary p ulse transformer winding
6 MID I/O C ha r ge pum p mi d po i nt
7 SCM I/O Neg ative s i de of the secondary p ulse transformer winding
8 VPX PWR Supply from the barrier
9
RCT
I
E xternal r ect ific ation – disabl es internal r ect ifier when low,
lea ve open
10 BYP I Tes t pin, l eave open
11 SRE I Voltage regul ator sens e
12 SRB O V olt age regulat or drive
13 VNS GND Digital negat ive supply voltag e
14
VBG
O
VBG bypass, connect to 0.1μF capacitor to VNS
15 ACS I AC current sense
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 13
Pin
Number Pin
Name Type Description
16 VNS GND A nalog n egati ve suppl y voltage
17 VPS PWRO Analog positive supply voltage (output)
18 RXP I Receive plus – signal input
19 RXM I Rec eive minus – s i gnal input
20 SACIN I Caller ID mode AC impedance connec tion
21 TXM O Transm it Minus – trans hybrid canc el lat i on output
22 TST I F act ory tes t mode, l eave open
23 RST I Reset s t he control r egi st er s to defau l t – weakly pulled high
24 DCD O DC loop output
25 DCS I DC loop cu rrent sense
26
DCG
O
DC loop control
27 DCI I DC loop input
28 RGN I Ring detec t negative voltag e inp ut
29
RGP
I
Ring detect positive voltage input
30 VNS GND Negative suppl y volt age ( l in e side of the barri er )
31 GPI I G ener al pur pose input (test pin)
32 GPO O G eneral purpose output (tes t pin)
73M1866B/73M1966B Data Sheet DS_1x66B_001
14 Rev. 1 .6
2.5 73M186 6 B Pi n out
Figure 6 shows t he 73M 1866B 42-pin pinout.
DX
VPD
FS
PCLKO
VNA
PCLKI
AOUT
VPA
VNT
PRM
PRP
VPT
RST
SDIT
SDI
VND
SDO
INT
SCLK
CS
DR
SRE
SRB
VBG
ACS
VNS
VPS
RXM
RXP
TXM
DCD
DCS
DCG
DCI
RGN
RGP
OFH
M20PB
VNX
SCP
MID
VPX
73M1866B
1
2
3
4
5
6
7
8
9
10
20
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
30
31
32
33
35
34
36
37
38
39
40
41
42
Figure 6: 73M1866B 42-Pin Pinout
Table 5 describes the pin functions for the device. Decoupling capacitors on the power supplies should
be included for each pair of supply pins.
Table 5: 73M1866B Pin Definitio ns
Pin
Number Pi n Name Type Description
1
DX
O
P CM received data from the A to D
2 VPD PWR Posit ive dig ital supp ly
3 FS I/O PC M frame synchr oni zation
4 PCLKO O PCM clock output
5 VNA GND Negative analog ground
6 PCLKI I P CM c lock in
7 AOUT O A udio out put – m ust be buffered for speaker
8
VPA
PWR
P ositive analog supply
9 VNT GND Neg ati ve t r ansformer supply
10 PRM I/O Transformer pri mary m inus
11 PRP I/O Transformer pr imary p lus
12 VPT PWR Positive t r ansformer supply
13 RST I Hardware reset ( act ive low)
14 SDIT O SPI data out for daisy-chain mode
15 SDI I S PI data in
16 SDO O S PI data out
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 15
Pin
Number Pi n Name Type Description
17 VND GND Negative digi tal ground
18 INT O Interrupt / ring detect (active low – open drain)
19 SCLK I SPI clock
20 CS I SPI chip select ( act ive l ow)
21 DR I PCM transmit data s ent to the D to A
22 SRE I Voltage regulator sense
23 SRB O Vol tage regul ator dr i ve
24 VBG O VBG bypass, connect to 0.1μF capacitor to VNS
25 ACS I AC current sense
26 VNS GND An alog negat i ve s uppl y voltag e
27 VPS PWRO Analog positive supply voltage (output)
28 RXP I Receive p lus – s ig nal input
29 RXM I R eceive minus – s i gnal input
30 TXM O Transm it Minus – trans hybri d cancellation output
31
DCD
O
DC loop out put
32 DCS I D C loop c ur r ent s ense
33 DCG O DC l oop cont r ol
34 DCI I DC loop input
35 RGN I Ring detec t negative voltage inp ut
36 RGP I Ring detect positive voltage input
37 OFH O Off-h ook control
38 M20PB I Test pin. C onnect t o VNX.
39 VNX GND Negative suppl y volt age
40 SCP I/O Positive si de of the s econdary p ul se t r ansformer winding
41
MID
I/O
Charge pum p mi d po i nt
42 VPX PWR Supply from t he bar r i er
2.6 Requ isit e U se of Ex pos ed Bottom P a d on 7 3M1866B and 7 3M19 66 B QFN
Packages
The exposed bottom pad i s not intended for thermal r elief (heat dis sipation) and should not be
sol der ed to the PCB. Solder in g of the exp osed pad could al so c om pr omis e electri cal
isolation/ insulation requiremen ts for proper voltage is olat i on. Avoid any PC B traces or through-hole
vi as on the P CB beneath the exposed pad area.
73M1866B/73M1966B Data Sheet DS_1x66B_001
16 Rev. 1 .6
3 Electrical Characteristics and Specifications
3.1 Isolation Barrier Characteristics
Table 6 provides the characteristic s of t he 73M1x66B Is olat i on Bar r i er .
Table 6: Isolation Barrier Characteristics
Parameter
Rating
B arrier freq u en cy 768 kHz
Data t r ansfer rate ac ross t he bar r i er for the s ampling r ate of 8 k H z 1. 536 M bps
When 16 kHz sampli ng r ate i s selected, t he frequency and data trans fer r ates are t wice t hose shown
above.
3.2 Ele ctric al Specif ic ations
Thi s section provides the abs olut e maximum ratings, the recommended oper ating condi ti ons and th e D C
characteristics.
3.2.1 Abso lute Maximum Ratings
Table 7 lis ts t he maximum operating cond it i ons for the 73M1x66B. Perm anent devic e damage may occur
if absolut e maximum ratings are exceeded. E xpos ur e to the extremes of the absolut e m aximum r ati ng for
extended peri ods may affect device reli abi lity.
Table 7: Absolute Maximum Devic e Rati ngs
Parameter
Min
Max
Unit
S upply vol tage -0.5 4.0 V
Pin input voltage (except OSCIN) -0.5 6.0 V
P in input volt age (OSCIN ) -0.5 to VDD 0.5 V
3.2.2 Recomm ended Operating Conditions
Funct i on oper ation should be restrict ed to the rec om mended operating c ondi ti ons specified i n Table 8.
Table 8: Recommended Operating Conditions
Parameter
Min
Max
Unit
S upply vol tage (VD D ) with res pect t o VSS 3.0 3.6 V
Operating temperature -40 85 °C
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 17
3.2.3 DC Characteristics
Table 9 lis ts t he 73M1x66B DC chara cter istics.
Table 9: DC Characteristics
Parameter
Condition
Min
Nom
Max
Unit
I nput low voltage VIL – -0.5 – 0.2 ∗ VDD V
Input high voltage VIH1 – 0. 7 VD D
–
5.5 V
O utput low voltage VOL IOL=4 mA
–
–
0.45 V
O utput low voltage
FSB,SCLK, VOL IOL= 1 mA
–
–
0.45 V
Output high voltage VOH IOH=-4 mA VDD - 0.45
–
V
Output high voltage
FSB, FSBD, SCLK VOH IOH=-1 mA VDD - 0.45
–
V
I nput low leak age current
IIL1 VSS < Vin < VIL1 10
–
40 μA
I nput high l eakage
current IIH1 VIH1 < Vi n < 5.5 –
–
1 μA
ID D cur r en t at 3. 0 V – 3.6 V Nom inal at 3.3 V
Ac tive digital current IDD1dig
–
–
1.0 1.5 mA
A ctive P LL current IDD1pll
–
–
1.0 1.5 mA
A ctive an alog curr ent IDD1ana
–
–
12 17 mA
IDD t otal current* IDD1
–
–
15 20 mA
IDD total current* IDD2
–
–
20 30 mA
IDD c urrent
PWDN=1 IDD3
–
–
1.0 5 μA
IDD c urrent
SLEEP=1 (Ext Ref Clk) IDD4
–
–
0.5 1.0 mA
IDD c urrent
ENFEH=0 (Ext Ref Clk ) IDD6
–
–
1.0 1.5 mA
*Note: IDD1 is with the secondary of the barrier left open.
IDD2 is with the secondary of the barrier connected to 73M1916 fully powered.
73M1866B/73M1966B Data Sheet DS_1x66B_001
18 Rev. 1 .6
3.3 Interface Timing Specification
There ar e three in terfaces associated wit h the 73M1x66B: th e SPI interfac e, the PCM hi ghway in terfac e
and the line interface. This sec tion pr ovides t he timing sp ecificat ion fo r the SPI i nterface and the PCM
highway i nterface.
3.3.1 SPI Interface
Table 10 lists the ch ar act er istics for the SPI in terface.
Table 10: SPI Int erface Switching Characteristics
Parameter Symbol Min Typ Max Unit
SCLK cyc le t ime
1
tscy 62.5
–
– ns
SCLK rise tim e tscr
–
–
25 ns
SCLK fall t ime tscf
–
–
25 ns
CS set up time tics 25
–
–
ns
CS hold time tich 20
–
–
ns
SDI setu p time tids 25
–
–
ns
SDI hold time tidh 20
–
–
ns
S DO turn on del ay todd –
–
20 ns
S DO turn off delay
t
odo
–
–
20
ns
SDO hold time
t
odh
–
–
20
ns
S DI to SDITHRU pr opagation del ay tidt – 6 – ns
Note1: The minimal value of t his par ameter is for the c ase where only one 73M1906B i s connected t o the
host. If t he dai sy chain m ode i s used, the m inimum S CL K cycle time inc r eases accor ding to the number
of slaves i n the ch ain.
CS
SCLK
SDI
SDO
t
ics
t
scy
t
ids
t
idh
t
odd
t
odh
t
odo
t
ich
Figure 7: SPI Timing Diag ra m
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 19
3.3.2 PCM Highway In terface
Table 11: Switching Characteristics – PCM Interface (Slave Mode)
Parameter
Symbol
Min
Typ
Max
Unit
PCLK_I N cycle t ime t
pcy
122
–
3906 ns
PCLK_I N rise tim e tpcr
–
–
25 ns
PCLK_I N fall time tpcf
–
–
25 ns
FS s etup tim e tifs 25
–
–
ns
FS hold time tifh 20
–
–
ns
FS c ycle time tifc – 125
–
μs
DR setup time t
ids
25
–
–
ns
DR hold time t
idh
20
–
–
ns
DX turn on delay t
odd
–
–
20 ns
DX turn off delay t
odo
–
–
20 ns
DX hold time todh
–
–
20 ns
Table 12: Switching Cha racte ristics – PCM Interface (Master M ode)
Parameter
Symbol
Min
Typ
Max
Unit
PCLK_O UT cyc le time
t
pcy
–
488
–
ns
PCLK_O UT rise tim e tpcr
–
–
25 ns
PCLK_O UT fall time tpcf
–
–
25 ns
FS s etup tim e tifs 50
–
–
ns
FS hold time tifh 50
–
–
ns
FS c ycle time tifc – 125
–
μs
DR setup time tids 25
–
–
ns
DR hold time tidh 20
–
–
ns
DX turn on delay
t
odd
–
–
20
ns
DX turn off delay
t
odo
–
–
20
ns
DX hold time todh
–
–
20 ns
FS
PCLK
DR
DX
t
ifs
t
pcy
t
ids
t
idh
t
ird
t
odd
t
odo
t
ifh
t
ifc
t
odh
Figure 8: PCM Timing Diagr am for Positive E d ge T r ansmit Mo de and N eg at ive Ed ge R ec eive Mo d e
73M1866B/73M1966B Data Sheet DS_1x66B_001
20 Rev. 1 .6
FS
PCLK
DR
DX
t
ifs
t
pcy
t
ids
t
idh
t
ird
t
odd
t
odo
t
ifh
t
odh
Figure 9: PCM Timing Diagr am for Negative Edge Transmit Mode and Positive Edge Re ce i ve Mode
3.4 Analog Specifications
Thi s section provides the el ect r ical charact er i zations of the 73M1x66B anal og circuitry.
3.4.1 DC Specifications
V BG is to be c onnected to an ext er nal bypass c apacitor wit h a minimu m value of 0.1 μF . This pin is n ot
intended for any other ext er nal use.
Table 13: Reference Voltage Specifications
Parameter Te st Condition Min Nom Max Units
VBG V DD=3.0 V – 3.6 V 0.9 1.19 1.4 V
VBG Nois e 300 Hz – 3.3 kHz – -86 -80 dBm600
VBG PSRR 300 Hz – 3 0 kHz 40 – – dB
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 21
3.4.2 Call Progress Monit or
The C al l P r ogr ess Mon it or mon it or s acti vities on t he l ine. The aud io outp ut c ontains both t r ansmit and
recei ve data with a configurable level individually set by Register 10h.
Figure 10 shows the frequency res ponse of the Call Pr ogress M oni tor Fil ter based upon the
char act er istics of the device pl us th e ext er nal ci r cuitry as shown.
Figure 10: Frequency Response of the Call Progress Monitor F ilter
U1 NJM2135
CD
1-VIN
4
V+ 6
GND 7
VOUT1 5
VOUT2 8
VREF1
2
VREF2
3
AOUT
VCC
VCC
R3 120K
+
C2
2.2uF
LS1
INTERVOX
AT-2308
C4
1uF
R2 120KR1 120K
C3
1uF
C1 0.1uF
Figure 11: Demo Boar d Ci rcuit Connecting AOUT to a Speaker
Table 14: Component Values for the Speaker Driver
Quantity
Reference
Part Description
Part
1 C1 Cer amic capac i tor 0.1 μF
1 C2 Cer amic capac i tor 2.2 μF (optional)
2 C3, C4 C er amic capac i tor 1 μF
1 LS1 Sound transducer Speaker (Intervox)
3 R1, R2, R3 1/ 8 W r esist or 0603 120 kΩ
1 U1 Audio amplifier NJM 2135 (New Jap an Radio)
A ll measurements ar e at the AO U T pin wit h CMVSEL = 0. Note that when CM VSEL=1, the p eak s i gnal at
A OU T is incr eased t o appr oximately 1.11 Vpk.
73M1866B/73M1966B Data Sheet DS_1x66B_001
22 Rev. 1 .6
Table 15: Call Progress M onitor Specification
Parameter
Test Condition
Min
Nom
Max
Units
AOUT for transmit
1 kHz full swing code (ATX)
CMRXG=11 (Mu te)
O bserve A OUT pin
–
–
–
–
CMTXG=00 – 0.98 – Vpk
CMTXG=01 relative
to CMTXG =00 – -6 – dB
CMTXG=10 relative
to CMTXG =00 – -12 – dB
CMTXG=11 (Mu te) – Mute – dB
AOUT transmit THD
CMTXG=00
–
40
–
dB
A OU T for rec eive
1.0 Vp k, 1 kHz at the line or 0.5
Vpk at RXP/RXM with
RXG=10
CMTXG=11 (Mu te)
O bserve A OUT pin
–
–
–
–
CMRXG=00
–
0.96
–
Vpk
CMRXG =01 relative
t o C M RX G=00
–
-6
–
dB
CMRXG =10 relative
t o C M RX G=00
–
-12
–
dB
CMRX G=11 (Mut e)
–
Mute
–
dB
A OU T rec eive THD CMRXG=00
–
40
–
dB
AOUT outpu t
impedance
–
10
–
kΩ
3.5 73M1x6 6 B Line-Side Electrical Specifications (73M1916)
Table 16 lists the abs olu te maximum ratings for t he l ine sid e. Operation outside these rating l imits m ay
cause permanent damage t o this device.
Table 16: Line-Si de Absolute Maximum Ratings
Parameter Min Max Unit
P in input volt age from VPX to VNX -0.5 6.0 V
P in input volt age (all other pins) to VNS -0.5 4.0 V
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 23
3.6 Reference and Regulation
Table 17 lists th e VBG specifications. VBG should be connected to an external bypas s capacitor wit h a
minimum value of 0.1 μF. This pin is not intended for any other external use.
The following conditions apply: VP X=5 V; Barrier Powered M ode; Barrier Data Rate acros s th e
Barrier=1.5 Mbps; VBG connec ted to 0.1 μF external cap.
Table 17: VBG Specifications
Parameter
Test Condition
Min
Nom
Max
Units
VBG See c ondi tions above. – 1.19 – V
VBG noise
300 Hz – 3.3 kHz
–
-86*
-80
dBm
600
VBG PSRR
300 Hz – 30 kHz
40
–
–
dB
VPS VPX=5.5 V – 3.15 – V
VPS PSRR VPX=4.5 V to 5.5 V – 40 – dB
3.7 DC Transfer Characteristics
Table 18 lists th e maximum DC transmit levels . All tests are driven at pin DCI an d measured at pin DCS.
DCEN=1. ILM=1.
Table 18: Ma xi mu m D C Tr an smit L ev els
Parameter Te st Condition Min Nom Max Units
VDCON
(DC "On" Voltage) DCIV=00 0.62 0.69 0.78 V
DCIV=01
0.83
0.92
1.00
V
DCIV=10
1.08
1.16
1.24
V
DCIV=11 1.32 1.42 1.53 V
W ith ENAC=0 DCIV=XX 0.20 0.26 0.30 V
DC Gain VDCON<VDCI<0.4V+VDCON -0.30 0 .0 +0.25 dB
IDCI before ILI M ILM=1 VDCI=0.28V+VDCON – – 10 µA
IDCI after ILIM ILM=1 VDCI=0.44V+VDCON 20 – – µA
Delta V
Delta IDCI
DCS 8.2∗45mA< VDCS < 8.2∗60mA – 0.85 – mA/V
*Noise
At the line with 300 Ω(ac) (0.15 - 4.0 kHz)
–
-85 -80 dBm
73M1866B/73M1966B Data Sheet DS_1x66B_001
24 Rev. 1 .6
3.8 T r ansm i t P ath
Table 19 list t he transmit path char act er istics . A pattern for a s inusoi d of 1 k Hz, full scale (c ode word of
+/- 32,767) from the 73M1x66B is forced and ACS is measured with R10=174 Ω. U nless stated
otherwise, test conditions are: ACZ=0000 (600 Ω termination), THEN=1, ATEN=1, DAA=01, TXBST=0,
sample rate=8kHz .
Table 19: Trans mit Path
Parameter Te st Condition Min Nom Max Units
Offset volt ag e
8 and 16 kHz sam ple rate 50% 1’s density relative to 1.4
V common mode. – 25 – mV
Tx gain, relative to
DAA[1:0]=01 DAA=00 2.5 +3 3.5 dB
DAA=01 -0.5 0 0.5 dB
DAA=10 -4.5 -4 -3.5 dB
DAA=11 -8.5 -8 -7.5 dB
AC s wing
(1 kHz sinusoid)
8 and 16 kHz sam ple rate
DAA=01
–
0.317
–
Vpk
DAA=00
–
0.447
–
Vpk
TXBST=1, DAA=xx
–
0.634
–
Vpk
ACZ=0001
–
0.211
–
Vpk
ACZ=0010
–
0.211
–
Vpk
ACZ=0011
–
0.200
–
Vpk
ACZ=0100
–
0.254
–
Vpk
ACZ=0101
–
0.220
–
Vpk
ACZ=0110
–
0.171
–
Vpk
ACZ=0111
–
0.194
–
Vpk
ACZ=1000
–
0.222
–
Vpk
ACZ=1001
–
0.205
–
Vpk
ACZ=1010
–
0.223
–
Vpk
ACZ=1011
–
0.313
–
Vpk
ACZ=1100
–
0.208
–
Vpk
ACZ=1101
–
0.211
–
Vpk
ACZ=1110
–
0.285
–
Vpk
ACZ=1111
–
0.235
–
Vpk
I dl e noise 300 Hz – 4 kHz
–
-80
–
dBm
THD 300 Hz – 4 kHz
–
-80
–
dB
I ntermod d istortion
1. 0 kHz and 1.2 kHz
summed 300 Hz – 4 kHz – -85 – dB
Passband ripple
150 Hz – 3.3 kHz
-0.125
–
+0.125
dB
G ai n r elat i ve to 1 kH z
–
–
–
dB
0. 5 kHz
–
0.17
–
dB
1. 0 kHz
–
0
–
dB
2. 0 kHz
–
0.193
–
dB
3. 3 kHz
–
-0.12
–
dB
A lias ed image F s +/- 1 kHz, rel ati ve t o 1 kHz
–
-75
–
dB
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 25
3.9 R ec eiv e P ath
Table 20 lists the receive p ath charac teri stic s. A l l t est inputs are dr iven through an AC couplin g network
shown in Figure 29. The rec ei ve bit s tream is m easured at th e DX pin . R XEN= 1.
Table 20: Recei ve Path
Parameter
Test Condition
Min
Nom
Max
Units
Differen tial input
resistance RXP/RXM – 1000 – kΩ
Input level Differen tial, RX P/RXM – 1.1 1.16 Vpk
Input level Common mode, R XP/RXM – 1.37 – V
Overall sig ma-delta A DC
modulation gai n incl usive
of 73M1906B processing
Normalized t o VBG=1.1 9 V.
RXG=00
Divide Vrxp/m by PCM
Output
– 47.3 – µV/bit
Offset voltage R6=17.4 kΩ, R8=52.3 kΩ,
R9=21 kΩ.
See Figure 12. – 0 +/- 30 mV
Rx gain
(See Note 1.) RXG=00 -0.5 0 0.5 dB
RXG=01 2.5 3 3.5 dB
RXG=10 5.5 6 6.5 dB
RXG=11 8.5 9 9.5 dB
RXBST=1, RXG=00 18.3 19.3 20.3 dB
O verall receive
frequen cy response
inclusive of 73M1906B
processing
Relative to 1 k H z – – – –
0.3 kHz – 3.3 kHz -0.25 0 +0.25 dB
Fs (8 kHz) – -75 – dB
I dl e noise 300 Hz – 4 kHz – -80 – dBm
THD RXG=00 – -85 – dB
RXBST=1 – -60 –
I ntermod Dist 1.0 kHz
and 1. 2 kHz sum med 300 Hz – 4 kHz – -85 – dB
Crosstalk 1 Vpk 1 kHz sine wave at
TXP; FFT on Rx ADC
samples , first fou r har mon ics
reflec ted to the line. – -90 – dBm
CMRR RXP =R XM 1 Vpk 40 – – dB
PSRR -30 dBm signal at VPX in
B ar r ier Powered M ode;
300 Hz – 30 kHz. – – 40* dB
On-Hook AC Impedance 300 Hz – 4 kHz, without E MI
caps. – 2 – MΩ
Note 1: RXG controls t he amount of gain or attenuat ion of the receiver analog gai n element as speci fi ed
in Table 20. Th e overall receiver channel gai n has 6 dB of att enuation and the net effect of t he
RXG bi ts on the receiver c hannel gai n is defined i n Table 36.
73M1866B/73M1966B Data Sheet DS_1x66B_001
26 Rev. 1 .6
3.10 Transmit Hybrid Cancellation
Table 21 lists the transmit hybrid cancellation ch ar acterist ics. Un less stated otherwis e, tes t c ondi ti ons
are: ACZ[3:0]=0000 (600 Ω termination), THEN=1, ATEN=1, DAA[1:0]=01, TXBST=0. TXM is externally
fed back in to the 73M1916 to effect cancell ation of trans mit s i gnal .
Table 21: Transmit Hy brid Cancellation Characteristics
Parameter
Test Condition
Min
Nom
Max
Units
Transmit hybrid cancellation Measure i n
73M1906B – 20 – dB
O ffs et volt ag e 50% 1’s densit y – 0 25 mV
AC s wing 1 kHz sin usoid 1.00 1.05 1.10 Vpk
I dl e noise 300 Hz – 4 kHz – -80 – dBm
3.11 Receive Notch Filter
Table 22 lists the receive n otch filter charac teri st ics. Al l measurements taken with RL PN EN =1 , TX EN = 0,
RXG=00, ATEN=1. RXP is driven with 1 Vpk signal.
Table 22: Receive Notch Filter
Parameter Te st Condition Min Nom Max Unit
Magnitude response
RLPNH=0 (12 kHz Notch)
300 Hz
–
0.0
–
dB
1 k Hz
–
+0.03
–
dB
3 k Hz
–
+0.04
–
dB
12 kH z -30 -50
–
dB
P ass band R ipp le (0.3 kH z – 3.4 kHz)
–
+/- 0.15
–
dB
Delay
–
28.8
–
μs
300 Hz
–
28.93
–
μs
1 k Hz
–
30.25
–
μs
3 k Hz
–
41.62
–
μs
12 kH z
–
9.95
–
μs
Magnitude response
RLPNH=1 (16 kHz Notch)
300 Hz
–
0.0
–
dB
1 k Hz
–
+0.04
–
dB
3 k Hz
–
+0.11
–
dB
16 kH z
-30
-50
–
dB
P ass band R ipp le (0.3 kH z – 3.4 kHz)
–
+/- 0.15
–
dB
Delay
–
30.53
–
μs
300 Hz
–
30.66
–
μs
1 k Hz
–
31.93
–
μs
3 k Hz
–
42.26
–
μs
16 kH z
–
4.74 – μs
DS_1x66B_001 73M1866B/73M 1966B D ata Sheet
Rev. 1.6 27
3.12 Detectors
Thi s section provides elec tri cal charac teri stic s for t he fol lowing detect or s:
• Over-Voltage.
• Over-Current.
• Under-Voltage.
• Over-Load.
3.12.1 Over-Vol tag e Detector
The values in Table 23 were measured between RGP and RGN .
Table 23: Over-voltage Detector
Parameter Te st Condition Min Nom Max Unit
O ver voltage levels OVDTH=0 0.52 0.6 0.68 V
OVDTH=1 0.59 0.7 0.77 V
3.12.2 Over-Current Detector
The values in Table 24 were measured in Barr ier Powered M ode.
Table 24: Over-current Detector
Parameter Te st Condition Min Nom Max Unit
O ver c ur r ent l evel Measured at DCS. 0.90 1.025 1.20 V
3.12.3 Under-Voltag e Detector
The values in Table 25 were measured in Barr ier Powered M ode. In th e r ecommended schem atic (see
Figure 12), disconnect Q5 collec tor and connect to an external power supply, VPE, through a 600 Ω
resistor.
Table 25: Under-voltage Detector
Parameter Te st Condition Min Nom Max Unit
Under voltage det ect Meas ur e VPE when U VD i s
det ect ed as VPE i s dec r eased. – 7.5 – V
3.12.4 Over-Load Detector
The values in Table 26 were measured in Barr ier Powered M ode.
Table 26: Over-load Detector
Parameter
Test Condition
Min
Nom
Max
Unit
O ver load level M easured at DC I wit h 1 kHz. 0.6 0.75 0.9 Vpk
73M1866B/73M1966B Data Sheet DS_1x66B_001
28 Rev. 1.6
R69
100K*
C14
15pF
INT\
SCLK
C41
220pF, 300V
SDO
SDI
VCC
SDITHRU
+
C8
4.7uF
R2
10M, 0805
R12 5.1K
R11
3K
C39
5.6nF
Q7
MMBTA42
1
3
2
R68
1M, 0805
C3 0.022uF , 200 V
RST\
C48
0.1uF
Q6
BCP-56
1
23 4
DR
VPS
C49
100pF
C1 0.022uF , 200V
R8 52.3K, 1% R9 21K, 1%
R5 8.2, 0805
R3
412K, 1%
U1 73M1916-20
OFH
4
VNX
5
SCP
6
MID
7
VPX
8
VBG 11
ACS 12
SRE
9
SRB
10 VNS 13
VPS 14
RXP 15
RXM 16
TXM 17
DCS 19
DCD 18
DCI
1
RGN
2
RGP
3DCG 20
R6 17.4K, 1%
R66
1M, 0805
C38
0.1uF
C12
0.1uF
R4
100K, 1%
C7
4.7uF , 25V
U2 73M1906B-20
CS
1
AOUT
9
VPD
2
VPT 14
PCLKO
6
PCLKI
7
SCLK 20
DX
4DR
3
FS
5SDIT 16
SDO 18
SDI 17
VPA
10 VNA/VND
8
PRM 12
PRP 13
RST 15
VNT 11
INT 19
DX
AUDIO
C33
1nF
FSIO
I SO L AT ION BARRIER
C31
0.1uF
CLKO
C35
220pF, 3KV
CLKI
-+
BR1
HD04
4
1
3
2
C36
220pF, 3KV
C37
0.01uF
TP15
VPS
1
TP14
OFH
1
R58 240
L1
2K Ohms @ 100 MHz
C9
0.22uF
T1
1 4
2 3
F1
TRF600-150
L2
2K Ohms @ 100 MHz
C10
0.22uF
TISP4290T3BJ
R10
174, 1%
Q3
MMBTA42
1
32
R65 200
Q4
MMBTA92
1
3 2
E1
P3100SBRP
Q5
MMBTA06
1
32
C24
NC (TBD as needed, 3KV)
C13
15pF
C26
1nF
CS\
SRE
SRB
C20
1nF
SCP
C43
1nF
NOTE: GND for C35 and
C36 should be on the host
side of the barrier
+
C4
10uF
VCC
C30
1nF
+
C21
3.3uF
C17
0.1uF
+
C45
3.3uF
VCC
TIP
RING
D1
MMSZ4710T1*
4 Applications Information
Thi s section provides gener al u sage information f or the des i gn and implementation of the 73M1x66B.
4.1 Example Schemat ic o f t he 73M19 66 B and 73M1866B
Figure 12 shows a typical appl ication sc hemati c for t he implem entation of t he 73M1966B. Figure 13 shows a typi cal appl ication schemat ic for the
impl ementation of t he 73M1866B. Note that min or changes m ay occur to t he r eference materi al from t i me t o ti me and the reader i s encour aged to
contac t Teridi an for the lates t i nformati on. F or more informati on about s chematic and layout d esign, s ee the 73M 1866B/73M 19 66B Sc hemati c an d
Layout Guidelines.
Figure 12: Recom m ended Circuit for the 73 M1 9 66B
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 29
Figure 13: Recommended Circuit for the 73M 1866B
R6
17. 4K, 1%
T1
Puls e Trans form er
14
2 3
C1
0. 022uF , 200V
C3
0. 022uF , 200V
C43
1nF
C49
100pF
C35
220pF , 3k V
C30
1nF
R5
8.2
C33
1nF
R3 412K, 1%
R66
1M, 08 05
VNS
VCC
C37
0.01uF
Maint ain 2.5 mm Spac ing B etween
Line and Host S ide Components
I solation B ar r ier
C38
0.1uF
F1
TRF600-150
E1
P3100SBRP
C20
1nF
U1
73M1866B
DX
1VPD
2FS
3PCLKO
4VNA
5PCLKI
6AOUT
7VPA
8VNT
9PRM
10
PRP
11 VPT
12 RST
13 SDIT
14 SDI
15 SDO
16 VND
17 INT
18 SCLK
19 CS
20 DR
21
SRE 22
SRB 23
VBG 24
ACS 25
VNS 26
VPS 27
RXP 28
RXM 29
TXM 30
DCD 31
DCS 32
DCG 33
DCI 34
RGN 35
RGP 36
OFH 37
M20PB 38
VNX 39
SCP 40
MID 41
VPX 42
RSTB
C26
1nF
SDITHRU
SPI OU T
SPI I N
SPI C LK
C39
5.6nF
C36
220pF , 3k V
VNS
SPI C SB
C9
0.22uF
P CM TX
C41
220pF , 300V
INTB
R11
3K
VCCVCCVCC
R68
1M, 08 05
C17
0.1uF
PCM CLKIN
C13
15pF
C12
0.1uF
L1 2 k Ohm @100MH z
PC M C LKO C14
15pF
VNS
VNS
AOUT
R2
10M
+
C45
3.3uF
+
C21
3.3uF
+
C8
4.7uF
RING
TIP
R12
5.1K
-+
BR1
HD04
4
1
3
2
R58 240
R9
21K, 1%
Q3
MMBTA42
1
32
Q6
BCP56
1
23 4
L2 2 k Ohm @100MH z
Q4
MMBTA92
1
3 2
R10
174, 1%
R4
100K, 1%
Q5
MMBTA06
1
3
2
PCM FS
C10
0.22uF
Q7
MMBTA42
1
32
C7
4. 7uF , 25V
PCM RX
R65
200
NOTE: GND for C35 and C36 should be on
the host side of the barri er
C31
0.1uF
C48
0.1uF
R8
52. 3K, 1%
C24
N C (as needed, 3KV)
+
C4
10uF
D1
MMSZ4710T1*
R69
100K*
73M1866B/73M1966B Data Sheet DS_1x66B_001
30 Rev. 1 .6
4.2 Bill of Materials
Table 27 provides the 73M1x66 bill of materials for the reference schematics provided in Figure 12 and
Figure 13.
Table 27: Reference Bill of Materials for 73M1x66B
Qty Reference Part Description Source Example MFR P/N
1 BR1 HD04 rectifier bridge, 0.8A, 400V Diodes Inc. HD04-T
2 C1, C3 0.022μF 200V, X7R, 1206 Panasonic ECJ-3FB2D223K
1 C4 10μF 6.3V, tantalum, 0805 AVX, Pan asonic TCP0J106M8RA
1 C7 4.7μF 25V, X5R, 0805 AVX, Panasonic 08053D475KAT2A
1 C8 4.7uF 6.3V, t antalum, 08 05 Rohm TCP0J475M8R
2 C9, C10 0.22μF 16V, X7R, ceramic, 0603 Panasonic C0603C224K8RACTU
4 C12,C17,C31,
C38, C48 0.1μF 16V, X7R, ceramic, 0603 Panas oni c, K em et C0603C104K8RACTU
2 C13, C14 15pF 50V, ceramic, 0603 Panasonic ECJ-1VC1H150J
5 C20, C26, C30,
C33, C43 1nF 10V, X7R, ceramic, 0603 Panasonic C0603C102K8RACTU
2 C21, C45 3.3μF 6.3V, tantalum, 0805 Rohm TCP0J335M8R
1 C37 0.01μF 50V, X7R, ceramic, 0603 AVX, Panasonic 06035C103KAT2A
1 C39 5.6nF 50V, X7R , ±10% ceramic, 0603 Panasonic ECJ-1VB1H562K
1 C49 100pF 50V, ceramic, 0603 Taiyo Yuden UMK107CH101JZ-T
1 D1 25V , 500mW Zener diode ON Semi MMSZ4710T1,
1 Q5 MM BTA06, NPN 80 V tr a ns i stor
SOT23 Diodes, Fairchild,
Central, On Semi MMBTA06LT1G
1 Q4 MMBTA92, PNP 300 V transistor
SOT23 Diodes, Fairchild,
Central, On Semi MMBTA92LT1G
2 Q3, Q7 MMBTA42, NPN 300 V transistor
SOT23 Diodes, Fairchild,
Central, On Semi MMBTA42LT1G
1 Q6 NPN 80 V transistor SOT223 Fairc hild , On Semi BCP56
1
R2
10M, 5 %, 1/8W resist or 0805
Yageo
RC0805JR-0710ML
1
R3
412K , 1%, 1/10W resist or 0603
Yageo
RC0603FR-07412KL
1 R4 100K, 1% , 1/ 10W resi stor 0603 Yageo RC0603FR-07100KL
1 R5 8.2, 5%, 1/8W resistor 0805 Yageo RC0805JR-078R2L
1 R6 17.4K, 1%, 1/ 10W r e s i stor 0 60 3 Yageo RC0603FR-0717K4L
1 R8 52.3K, 1%, 1/ 10W r e s i stor 0 60 3 Yageo RC0603FR-0752K3L
1 R9 21K, 1%, 1/10W res i stor 0603 Yageo RC0603FR-0721KL
1 R10 174, 1%, 1 /10W r esistor 0603 Yageo RC0603FR-07174RL
1 R11 3K, 5 %, 1/10W resist or 0603 Yageo RC0603JR-073K0L
1
R12
5. 1 K, 5% , 1/10W resis tor 0603
Yageo
RC0603JR-075K1L
1
R58
240, 5%, 1 /10W r esist or 0603
Yageo
RC0603JR-07240RL
1 R65 200, 5%, 1 /10W r esistor 0603 Yageo RC0603JR-07200RL
2 R66, R68 1 M, 5%, 1/8W res i stor 0805 Yageo RC0603JR-071ML
1 R69* 100K typ . 5%, 1/10W resist or 0603 Yageo RC0603JR-07100KL
1 T1 Pulse trans former See Table 29.
* Optional – see t he 73M1866B/1966B Sc hematic s and Lay o ut G uidelines for details.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 31
4.3 Over-Voltage and EMI Protection
Over-v olt age pr otec ti on i s requir ed to meet worst-case condi tions for target countri es. UL195 0,
E N60950 , IEC 60950, ITU-T K. 20/K.21 and G R -1089-CORE s pecificat ions define the protec ti on
requir emen ts for many countries. A single design can be i m pl ement ed to meet all these r equi r ement s.
Figure 14 shows a recommend ed pr otec ti on circuit topol ogy. Fuse ( F1) sh oul d be rated appropr iat el y for
t he count r y of op er ati on, and the bidir ect ional thyris tor ( E1) shoul d have a minimum break-over of 220 V,
a maximum br eak-over of 275 V and be able to survive a 100 A fas t trans ien t. In additi on to over-voltage
and current protection, the 73M1x66B should make provis i ons to prev ent EMI emissions and EMC
su s c eptibility. Figure 14 also illustrates how L1, L2, C35, C36 and C41can provide this suppression. The
ferrite beads , L1 and L2, should be capable of passing 150 mA and have an impedance of 2K Ω at 100
MHz. C35, C3 6 and C 41 should be between 47pF and 220nF, and r ated for a breakdown voltage greater
t han the highest is ol ati on voltage or l i ne voltage that i s requi r ed for count r y compat ibilit y. C3 5 and C36
should be returned to an earth ground. EMI suppression is highly dependent on the physical design of
t he overall ci r cuit and not all the s uppr ess i on comp onents may be needed in every design and
application.
C35
220pF , 3k V
C36
220pF , 3k V
L1
2K Ohm @ 100MH z F1
TR600-150
L2
2K Ohm @ 100MH z
J1
RJ-11
1
2
3
4
5
6
E1
P3100SBRP
or equiv.
T
R
C41
220pF , 300V
Figure 14: Suggested Ove r -Voltage Prote ction and E MI Suppression Ci rcuit
Table 28: Reference Bill of Materials for Figure 14
Reference Part Description Source Example MFR P/N
E1 Bidirect ional Th y ris tor Diodes Inc., Bourns TB3100H-13-H,
TISP4290T3BJR-S
F1 PPTC Fu se Tyco, Bourns MF-R015/60 0 or equiv.
L1,L2 2 KΩ @ 100 MHz, 150 mA min, 0805 Steward , TDK MPZ2012S601A
C35, C36 220 pF , 3000 V TDK C4532COG3F221K
C41 220 pF , 300 V Vishay VJ1206Y221KXEAT5Z
73M1866B/73M1966B Data Sheet DS_1x66B_001
32 Rev. 1 .6
4.4 Isolati o n B arr i er Pu ls e Tr an sf ormer
The i solation el ement used by t he 73M1x66B is a standard digit al pulse transformer. Severa l vendors
suppl y c omp ati bl e transformers with up to 6000 V r atings. Si nce the t r ansformer i s the only c omp onent
crossin g the isolation bar r i er other than EMI c apacitors th at may be r equi r ed, i t s olely d etermines the
is olat i on betw een the PSTN an d the FXO’s dig it al int er face. This met hod of isolation is signi ficant ly
super i or to other isolation techn iques with maj or advantag es in hi gh com mon mode vol tage operation,
lower radiated noise (EMI) and im pr oved operation in noisy environments. Table 29 lists som e pulse
transformers compatible with the 73M1x66B. Th e table also i ncludes low-voltage transformers that offer
low-cost alternatives if such voltages are sufficient.
Table 29: Compatible Pulse Transformer Sources
Company Number
Sumida ESMIT 4180
E SM IT 41 81
Wurth Elect ronics Midcom Inc. 750110001
UMEC TG-UTB01543S
Datatronics PT79280
AAsupreme P950003
Table 30 lists some of t he typ ical pulse transformer speci fi cat ions used by t he 73M1 x66B. C ontact the
manufacturer di r ect ly for pr oduct i nformat i on.
Table 30: P ulse Transfor mer Electrical Characteristics
Parameter Te st Condition Min Nom Max Tolerance Unit
Inductance 100 kHz , 10 mV AC , 1-2 , Ls. 54 60 200 – μH
Interwinding
Capacitance – – – 6 – pF
Turn Rat io – – 1:1 – ±2 % N/A
DC Resistan c e Primary – – 0.25 – Ω
Secondary – – 0.25 – Ω
Dielectri c Break down
Voltage 1 sec 2000 3750 – – Vrms
E T Const ant – – 1.2 – – Vμs
S ur ge Test 1.2 x 50 μs 2800 6000 – V
O per ating Temperature – -40 – 85 – °C
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 33
5 SPI Inte rface
The host access es t he 73M1x66B usi ng an SPI interface to w r i te to c ontrol r egisters and read s tatus
regist er s. The hos t i s th e master of the t r ansac tion. Fou r pin s orchestrate the communic ati on between
the host and the SPI, and a fifth pin is dedicated to support the daisy-chain m ode. The s i gnal s are as
follows:
• SDI Serial data input driven by the host.
• SDO Serial data output driven by the 73M1x66B.
• SCLK Clock input driven by the host.
• CS Chip s elect input dri ven by the host .
• SDIT Ser ial data out put for daisy -c hai n mod e.
The SPI im plemented by the 73M1x66B has the following key features:
• S uppor t for 8-bit a n d 16-bit mode operations.
• S uppor t for daisy-chain operations.
• S uppor t for both conti nuously active SCLK or SCLK act i ve duri ng transfers onl y.
• S uppor t for broadcast mode.
Transac tions bet ween t he host and the 73M1x66B requi r e three byt es. A ll bytes are transmitted most
si gnificant byte fi r st . Th e fi r st is the c ontrol byte, the s econd th e addr ess byte and the thir d i s the d ata
byte. The cont r ol byte is struc tured as follows:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BRCT
R/W
X
X
CID[0]
CID[1]
CID[2]
CID[3]
The value of CID[0:3] determines which 73M1x66B in the daisy chain should execute th e r ead or write
operation requested by the host. Up to 16 devices in the daisy chain can be supported. The daisy chain
organization is shown in Figure 15. The cont r ol byte is s ubmitt ed to the first 73M1x66B in the daisy
chai n. If t he value of CID[0:3] i s different from z er o, the SPI of that devic e decreases the value of
CID[0:3] by one and passes the new value through SDIT to the next 73M1x66B in the chain. This
process continues until CID[0:3] is zero, thus st opping at the device designated to ex ecute t he operati on.
The value of CID will be the position in the daisy chain for the device being addressed minus one.
I f the host i s control ling only one 73M1x66B, CID[0:3] must be set to 0.
The BRCT bi t overri des t he chip addressing driven by CID[ 0:3]. The host as serts BRCT for al l write
operations that mus t be executed by all 73M1x66B devic es in the ch ai n. At t hat tim e, whatever c omes i n
S DI comes out through SD IT. BR C T does not affect read operations.
73M1866B/73M1966B Data Sheet DS_1x66B_001
34 Rev. 1 .6
HOST
73M1906B
Channel 0
73M1906B
Channel 1
73M1906B
Channel 15
...
SCLK
SCLK
SCLK
SCLK
CS
CS
CS
SDO
SDO
SDO
SDO
CS
SDI
SDI
SDI
SDI SDITHRU
SDITHRU
SDITHRU
CID=CIDin-1
CID=CIDin-2
CIDin
CID=000
(target)
Figure 15: Daisy-Cha i n Configuration
The R /W bi t determin es whether the host requests a r ead (1) or a write (0) oper ation.
The second byt e of the SP I trans action is the add r ess byt e. Th e address byte simply contains the 8-bit
val ue for the regi ster target ed by the op er ati on. F or the 73M1x66B , onl y six bi ts of the addres s are
relevant for the regi ster s pace, and the two most-signi ficant bits of the address byt e ar e always set to 0.
The third byt e of the SP I trans action is the data byte. It contains the data to wr it e to the addressed
73M1x66B regist er s or the dat a r ead from t he addr essed 73M 1x66B r egister.
In the 8-bi t mode, the th r ee bytes ar e exchanged over three frames, as directed by CS. Figure 16 and
Fi gur e 17 show a write and read transaction between the 73M1x66B and the host in 8-bit mode.
CONTROL ADDRESS DATA [7:0]
SCLK
SDI
SDO HI-Z
CS
Figure 16: SPI Write Operation – 8-bit Mode
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 35
CS
SCLK
SDO HI-Z DATA [7:0]
CONTROL ADDRESS DATA [7:0]
SDI
Figure 17: SPI Re ad Tr ansaction – 8-bit Mode
In 16-bit m ode, the firs t frame of 16 bits contains both the control and addr ess bytes, and the second
frame c ontains th e data byt es. Not e that th e second par t of t he sec ond frame is i r r elevant. Fi gur e 18 and
Fi gur e 19 show the write and r ead transac tions in 16-bit mode.
CONTROL
CS
SCLK
SDI
SDO
HI-Z
ADDRESS DATA[7:0] XXXXXXXX
Figure 18: SP I Wr ite Trans act ion – 16-bit Mode
CONTROL
CS
SCLK
SDI
SDO
HI-Z
ADDRESS XXXXXXXX XXXXXXXX
DATA[15:8] DATA[7:0]
Figure 19: SPI Re ad Tr ansaction – 16-bit Mode
The transaction di agr ams show the c ase where SC LK i s only active during the trans action frames. The
same t r ansaction r emains vali d even if SCLK runs contin uously, r egar dless of frame bou ndar ies.
The SPI state machine r eset s when the hos t s ends a frame c ontai ni ng a num ber of SCLK peri ods
different from a multiple of eight:
73M1866B/73M1966B Data Sheet DS_1x66B_001
36 Rev. 1 .6
• In 8-bit mode, i f ei ther the c ontrol or the address frames do not correspond to a multiple of eight
S CLK cycl es, t he SPI state mac hine res ets and the trans action is aborted. If the dat a frame is shorter
t han ei ght SCLK cycles, the s tate machin e r esets and the trans act ion is abor ted. I f the data frame i s
longer than eight S CLK cycles, while not bei ng a mu l ti pl e of eight cycles, the write/ r ead transaction is
performed and the state mach ine res ets .
• In 16-bit m ode, if the control/ addr ess frame does not c ontain a m ultiple of eight SCLK c ycles, the S PI
state mac hine res ets and the trans action is aborted. If the dat a frame is shorter than ei ght SC LK
cycles, the state machine r esets and the trans act ion is abor ted. I f the dat a frame is longer than eight
SCLK cycl es, while not being a m ul tip l e of ei ght c yc l es, t he write/read t r ansac tion i s performed and
t he st ate machine resets. Th i s s cheme c an be used t o r eset the SPI if one looses track of frames.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 37
6 Control and Status Registers
Table 31 shows the 73M1x66B reg i ster map of addres sable registers. The shaded cell s indicate read-only
bits and cannot be m odified. R eserved bits should be l eft in their defaul t s tate. Acces sing unspeci fi ed
regist er s s houl d be avoided. Each r egi ster and bit is described in detail in the following sections.
For registers 0x12 through 0x1F, which are located in the Line-Si de D evice, there is a minimum t ime
bet we en consecutive write t r ansac tions of 30 0 µs when using an 8 kHz sam pl e r ate.
Table 31: Control and Status Regist er Map
Address
(hex) Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
02 10h TMEN Reserved Reserved Reserved Reserved ENLPW Reserved Reserved
03 E0h GPIO7 GPIO6 GPIO5 PCLKDT RGMON DET SYNL RGDT
04 E4h DIR7 DIR6 DIR5 Reserved REVHSD3 REVHSD2 REVHSD1 REVHSD0
05 1Bh ENGPIO7 ENGPIO6 ENGPIO5 ENPCLKDT ENAPOL ENDET ENSYNL ENRGDT
06 00h POL7 POL6 POL5 Reserved Reserved Reserved Reserved Reserved
07 00h Reserved Reserved Reserved Reserved Reserved Reserved DTST1 DTST0
08 00h TXDG -12 TXDG -6 TXDG +3.5 TXDG +2 TXDG +1 TXDG +0.5 TXDG +0.25 TXDG +0.125
09 00h RXDG -12 RXDG -6 RXDG +3.5 RXDG +2 RXDG +1 RXDG +0. 5 RXDG +0.25 RXDG +0.125
0D 40h LOKDET SLHS Reserved Reserved RSTLSBI Reserved Reserved Reserved
0E 00h FRCVCO Reserved Reserved Reserved Reserved Reserved RGTH1 RGTH0
0F 80h ENFEH PWDN SLEEP Reserved Reserved Reserved Reserved Reserved
10 00h Reserved Reserved Reserved CMVSEL CMTXG1 CMTXG0 CMRXG1 CMRXG0
12 00h OFH ENDC ENAC ENSHL ENLVD ENFEL ENDT ENNOM
13 00h DCIV1 DCIV0 ILM Reserved PLDM OVDTH IDISPD SEL16K
14 00h TXBST DAA1 DAA0 Reserved RXBST RLPNH RXG1 RXG0
15 00h ENOLD DISNTR Reserved CIDM THEN ENUVD ENOVD ENOID
16 00h TXEN RXEN RLPNEN ATEN ACZ3 ACZ2 ACZ1 ACZ0
17 00h Reserved Reserved RXOCEN Reserved Reserved Reserved Reserved Reserved
18 01h TEST3 TEST2 TEST1 TEST0 Reserved Reserved Reserved Reserved
19 00h POLL MATCH Reserved Reserved INDX3 INDX2 INDX1 INDX0
1A 00h RNG7 RNG6 RNG5 RNG4 RNG3 RNG2 RNG1 RNG0
1B 00h LV7 LV6 LV5 LV4 LV3 LV2 LV1 Reserved
1C 00h LC6 LC5 LC4 LC3 LC2 LC1 LC0 Reserved
1D 00h REVLSD3 REVLSD2 REVLSD1 REVLSD0 Reserved Reserved Reserved Reserved
1E 00h ILMON UVDET OVDET OIDET OLDET SLLS Reserved Reserved
1F 00h POLVAL7 POLVAL6 POLVAL5 POLVAL4 POLVAL3 POLVAL2 POLVAL1 POLVAL0
20 00h TPOL TTS6 TTS5 TTS4 TTS3 TTS2 TTS1 TTS0
21 00h RPOL RTS6 RTS5 RTS4 RTS3 RTS2 RTS1 RTS0
22 00h SR ADJ RCS2 RCS1 RCS0 TCS2 TCS1 TCS0
23 00h PCMEN MASTER PCODE3 PCODE2 PCODE1 PCODE0 LIN LAW
24 00h Reserved Reserved Reserved Reserved Reserved Reserved Reserved LB
25 00h RXOM7 RXOM6 RXOM5 RXOM4 RXOM3 RXOM2 RXOM1 RXOM0
73M1866B/73M1966B Data Sheet DS_1x66B_001
38 Rev. 1 .6
Throughout t hi s document, type W i s read/writ e, type WO is write only and t ype R i s read only. Regist er s
and bits are defined as 0x16[3:0], where 0x16 is the register address and the number s in square brac kets
specify the address bi ts. The bit order is [msb – lsb] for a fiel d. F or example, [3: 0] means bits 3 through 0
of a p ar ticular fiel d.
Table 32: Alphabetical Bit M ap
Bit Name
Register
Page
Default
Type
Category
ACZ
ADJ
ATEN
CIDM
CMRXG1/0
CMTXG1/0
CMVSEL
DAA1/0
DCIV1/0
DET
DIR5
DIR6
DIR7
DISNTR
DTST1/0
ENAC
ENAPOL
ENDC
ENDET
ENDT
ENFEH
ENFEL
ENGPIO7
ENGPIO6
ENGPIO5
ENLPW
ENLVD
ENNOM
ENOID
ENOLD
ENOVD
ENPCLKDT
ENRGDT
ENSHL
ENSYNL
ENUVD
FRCVCO
GPIO5
GPIO6
GPIO7
IDISPD
ILM
ILMON
INDX
LAW
LB
LC
LIN
LOKDET
0x16[3:0]
0x22[6]
0x16[4]
0x15[4]
0x10[1:0]
0x10[3:2]
0x10[4]
0x14[6:5]
0x13[7:6]
0x03[2]
0x04[5]
0x04[6]
0x04[7]
0x15[6]
0x07[1:0]
0x12[5]
0x05[3]
0x12[6]
0x05[2]
0x12[1]
0x0F[7]
0x12[2]
0x05[7]
0x05[6]
0x05[5]
0x02[2]
0x12[3]
0x12[0]
0x15[0]
0x15[7]
0x15[1]
0x05[4]
0x05[0]
0x12[4]
0x05[1]
0x15[2]
0x0E[7]
0x03[5]
0x03[6]
0x03[7]
0x13[1]
0x13[5]
0x1E[7]
0x19[3:0]
0x23[0]
0x24[0]
0x1C[7:1]
0x23[1]
0x0D[7]
68
52
69
75
44
44
44
52
69
76
43
43
43
61
79
69
61
69
76
76
42
70
43
43
43
61
70
70
77
77
77
52
75
70
61
76
42
43
43
43
69
70
70
40
52
79
76
52
42
0000
0
0
0
00
00
0
00
00
0
1
1
1
0
00
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
WO
WO
R
W
W
W
WO
W
WO
W
WO
W
WO
W
WO
W
W
W
W
WO
WO
WO
WO
WO
W
W
WO
W
WO
W
W
W
W
WO
WO
R
W
W
W
R
R/W
R
DAA Control Fun ction
P CM Control Functi on
DAA Control Fun ction
DAA Control Fun ction
Call P r ogr ess M oni tor
Call P r ogr ess M oni tor
Call Progres s Moni tor
P CM Control Functi on
DAA Control Fun ction
Line Sensing Control
GPIO Control
GPIO Control
GPIO Control
B ar r ier Control Function
Loopb ack C ontrol
DAA Control Fun ction
B ar r ier Control Function
DAA Control Fun ction
Line Sensing Control
Line Sensing Control
Power Management
Curr ent Lim it i ng D etect i on Cont r ol and Status
GPIO Control
GPIO Control
GPIO Control
B ar r ier Control Function
Curr ent Lim it i ng D etect i on Cont r ol and Status
DAA Control Fun ction
Over-Curren t D etec ti on C ontrol and Status
Over-Load Detect ion Cont r ol and Status
Over-V olt age D etect i on C ontrol and Status
P CM Control Functi on
Ring Detect ion Function
Curr ent Lim it i ng D etect i on Cont r ol and Status
B ar r ier Control Function
Under-Vol tage Detec ti on C ontrol an d Status
Dev ice C lock Management
GPIO Control
GPIO Control
GPIO Control
DAA Control Fun ction
Curr ent Lim it i ng D etect i on Cont r ol and Status
Curr ent Lim it i ng D etect i on Cont r ol and Status
Line-S ide Device Register Polling
P CM Control Function
Loopb ack C ontrol Function
Auxiliary A/D Con verter Status
P CM Control Functi on
Dev ice C lock Management
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 39
Bit Name Register Page Default Type Category
LV
MASTER
MATCH
OFH
OIDET
OLDET
OVDET
OVDTH
PCLKDT
PCMEN
PCODE
PLDM
POL7
POL6
POL5
POLL
POLVAL
PWDN
RCS
REVHSD
REVLSD
RGDT
RGMON
RGTH1/0
RLPNEN
RLPNH
RNG
RPOL
RSTLSBI
RTS
RXBST
RXDG
RXEN
RXG0
RXG1
RXOCEN
RXOM
SLEEP
SLHS
SLLS
SR
SYNL
TCS
THEN
TMEN
TPOL
TEST
TTS
TXBST
TXDG
TXEN
UVDET
0x1B[7:1]
0x23[6]
0x19[6]
0x12[7]
0x1E[4]
0x1E[3]
0x1E[5]
0x13[2]
0x03[4]
0x23[7]
0x23[5:2]
0x13[3]
0x06[7]
0x06[6]
0x06[5]
0x19[7]
0x1F[7:0]
0x0F[6]
0x22[5:3]
0x04[3:0]
0x1D[7:4]
0x03[0]
0x03[3]
0x0E[1:0]
0x16[5]
0x14[2]
0x1A[7:0]
0x21[7]
0x0D[3]
0x21[6:0]
0x14[3]
0x09[7:0]
0x16[6]
0x14[0]
0x14[1]
0x17[5]
0x25[7:0]
0x0F[5]
0x0D[6]
0x1E[2]
0x22[7]
0x03[1]
0x22[2:0]
0x15[3]
0x02[7]
0x20[7]
0x18[7:4]
0x20[6:0]
0x14[7]
0x08[7:0]
0x16[7]
0x1E[6]
76
52
41
70
77
77
77
77
52
52
53
70
43
43
43
40
40
42
53
41
41
78
78
75
71
71
76
53
62
53
75
54
54
54
54
54
54
42
62
62
55
62
55
71
79
55
79
55
55
56
56
76
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0100
0
0
0
0
0
0
0
0
0
0000000
0
00000000
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0000000
0
00000000
0
0
R
W
R
WO
R
R
R
WO
R
W
W
WO
W
W
W
W
R
W
W
R
R
R
R
W
W
W
R
W
W
W
WO
WO
WO
WO
WO
W
W
W
R
R
W
R
W
W
W
W
W
W
WO
WO
WO
R
Auxiliary A/D Con verter Status
P CM Control Functi on
Line-S ide Device Register Polling
DAA Control Fun ction
Over-Curren t D etec ti on C ontrol and Status
Over-Load Det ect ion Control and Status
Over-V olt age D etect i on C ontrol and Status
Over-V olt age D etect i on C ontrol and Status
P CM Control Functi on
P CM Control Functi on
P CM Control Functi on
DAA Control Fun ction
GPIO Control Function
GPIO Control Function
GPIO Control Function
Line-Side D evice Regis ter Polling
Line-S ide Device Register Polling
P ower Management
P CM Control Functi on
Device Revisi on
Device Revision
Ring Detect ion Function
Ring Detect ion Function
Ring Detect ion Function
DAA Control Fun ction
DAA Control Fun ction
Auxiliary A/D Con verter Status
P CM Control Functi on
B ar r ier Control Function
P CM Control Functi on
PC M Cont rol Functi on
P CM Control Functi on
P CM Control Functi on
P CM Control Functi on
P CM Control Functi on
P CM Control Functi on
PCM C ontrol Functi on
P ower Management
B ar r ier Control Function
B ar r ier Control Function
P CM Control Functi on
B ar r ier Control Function
PCM C ontrol Funct i on
DAA Control Fun ction
Loopb ack C ontrol Funct i on
P CM Control Functi on
Loopb ack C ontrol Funct i on
P CM Control Functi on
P CM Control Functi on
P CM Control Functi on
P CM Control Functi on
Under-Vol tage Detec ti on C ontrol an d Status
73M1866B/73M1966B Data Sheet DS_1x66B_001
40 Rev. 1 .6
Whil e al l regist er s may b e r ead or written to via an SPI operation without er r or , some regi st er s react
differently to read and write operations, as follows:
• Read/Write (W) registers change i n r esponse to an SPI writ e transaction and r epor t their correct
current value for a read SPI t r ansaction.
• Read Only (R) registers do not change in r esponse to an SPI write transaction but repor t their
cor r ect current value for a read SPI transac tion.
• Write Only (WO) registers are s hadow regist er s t o corresponding regi sters on the Line-Side
Device (0x12-0x18) that are writt en to duri ng the barrier c ommunicat i ons, and so ar e written to
indir ectly. The t r ue cont ents of thes e Line-Side registers cannot be r ead di r ect ly from the shadow
regist er s represent ing them, but these Line-Sid e r egi sters can be read us in g the polling register
described i n 6.1. C er tai n event s, such as lightning or voltage s ur ges, could corrupt the c ontents
of the Line-Side registers , s o to verify thei r content s, the polling regi st er s (0 x19 and 0x1F) must
be used.
6.1 Line-Side Dev i c e Register Pol l in g
The R egi ster Map as r ead from a 73M1x66B Host-S ide Devic e consists of two gr oups. The fir st is the
Host-Side Device registers (0x00 through 0x10 and 0x20 through 0x24) and the second is a copy of the
Line-Side D evice registers (0x12 through 0x1F).
A s an extr a degree of i ntegri ty, the 73M1x66B supports the abil it y t o manuall y monitor the regi sters of its
Line-Side Device. This is achieved by using the Manual Poll Function. The Line-Side regi sters that can
be polled are 0x12 through 0x18 (index values 0x0-0x6 respectively).
The method is to write t he offs et address of the Line-S ide Devic e r egi st er to be read i nto the INDX field.
The value of t hi s is th e offset index fr om 0x12; that is, Register 0x12 is 0x0, 0x13 is 0x1, et c. The next
step is to set t he POLL bi t, whi ch c auses the devic e to read the request ed register from t he Li ne-Side
Dev ice. Th e value of t he r equest ed Lin e-Side Device regi ster is writ ten by the Line-Side Devic e into
POLVAL (0x1F). This value is comp ar ed with t hat of t he H ost-Sid e copy and, i f they ar e the s ame, the
MATCH bit is s et to 1.
The values presented at MATCH an d POLVAL are valid approximately 6 00 μs after a pol l r equest , and
are valid only aft er the POLL bit has been res et by the Host-Side Device.
Function
Mnemonic
Register
Location Type Description
INDX 0x19[3:0] W Index
A ddr ess of the regist er to be manually p ol led with the res ult s placed in
P OLVAL. Th i s address should be c leared aft er the poll . D efault = 0.
MATCH 0x19[6] R P olling Match
0 = No m atc h. (D efaul t)
1 = This read-only bit indi cates that th er e is match with the
corresponding polled register in the Host-Side Devic e. Th e resul t of
t he pol ling function can be read on ly after the P OLL bi t is reset to z er o
by the 73M1x66B.
POLL 0x19[7] W Pollin g Enab le
0 = Poll i ng di sabled. (D efaul t)
1 = Manually polls the control register in the Line-Si de D evice whos e
address is given by INDX. The Poll bit remains high until the MA TCH
res ul t i s available at which tim e it will be r eset t o 0 and the MATCH bit
status can be read.
POLVAL 0x1F[7:0] R P olling Value
When 73M1x66B is polled, the content of the Line-Side Device
Register given by the offset address in INDX is placed in this register.
Default = 0. Thi s regi st er can be read aft er the PO LL bi t ha s be e n
res et to zer o, indicating the result is ready.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 41
7 Hardware Control Functions
Th is section describes the 73M1x66B capabilities with respect to its configuration and hardware pin
control . Th ese include feat ur es such as D evice Revis ion , Interrupt Management, Power Management,
Clock C ontrol, General Purpose Inpu t/Out put (GPIO ) and cont r ol of the Cal l P r ogr ess M onit or .
7.1 Device Revision
The 73M1x66B pr ovides t he device revisi on num ber for the Host-Side Device and the Line-Si de D evice.
For the 73M1x66B:
• Rev isi on for the Host-Si de Device i s: 0100.
• Revision for the Line-Side D evice is : 1101.
Function
Mnemonic
Register
Location Type Description
REVHSD 0x04[3:0] R Host-Side Device Re vision
These read only status bit s indicate th e r evision of t he 73M1x66B
Host-Side D evice (73M1906B).
REVLSD 0x1D[7:4] R Line-Side Devic e Revis ion
These read-
onl y status bits provide the Device ID for the 73M1x66B
Line-Side Device (73M1916).
When barri er is synchronized, REV has the value of 1101.
When barri er is not synchronized, the value of the field is 0000.
7.2 Interrupt Control
The 73M1x66B supports a si ngle interrupt that can be ass er ted under sever al configurabl e conditions.
These include status of GPIOs, PCLKDT, RGMON, DET, SYNL and RGDT.
A ll interr upt sourc es th at are enabl ed ar e ORed together to cr eate the INT output sign al. GPIO ports that
are c onfigur ed to be output will n ot generate i nterrupts.
When th e INT pin goes active (low), the host should read the interrupt source Register 0x03, which is
then automatically cleared after the read operation. An interr upt dur i ng wake-on-r ing sho uld be
interpreted as the det ect ion of a valid ring signal.
Address 0x03
Res et Stat e E0h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO7 GPIO6 GPIO5 PCLKDT RGMON DET SYNL RGDT
73M1866B/73M1966B Data Sheet DS_1x66B_001
42 Rev. 1 .6
7.3 Power Management
The 73M1x66B supports th r ee mod es of power cont r ol f or the device.
Normal mode Th e 73M 1x66B operates normall y.
ENFEH = 0 In this mod e the H ost Sid e of the Barri er i nterface is disabl ed and the
line side device is disab led. The H ost si de cont inues to operate
normally.
S leep mode The devi ce PLL is turn ed off and PCLK is propagated on the clock
t r ee. Th e PC M D X and TSC ou tputs ar e tri -s tated. Control and st atus
regist er s of t he H ost si de maintain their content .
Power Down The dev ice i s s hut down altoget her . Th e r egi st er s remain accessible
through the SPI. Control and stat us regist er s of t he H ost si de m ai ntai n
t hei r conten t. To restart the P CM operations, the P CO D E r egi ster
mus t be s et for the appropri ate PCLK frequenc y value.
I n al l reduced power modes of op eration t he SPI interface remains ac tive.
Function
Mnemonic Register
Location Type Description
ENFEH 0x0F[7] W E nabl e Front End Host
1 = Enable F r ont E nd of the 73M1906B Host-Si de D evice. ( Default )
0 = Dis ab le Front End of t he 73M1906B Host-S i de D evice.
PWDN
0x0F[6]
W
Power Down Mode
0 = Di sable Power Down M ode. (D efault)
1 = Enable Power Down Mode.
SLEEP 0x0F[5] W Sl eep M ode
0 = Di sable Sleep M ode. (Default )
1 = Enable Sleep M ode.
7.4 Device Clock Management
Function
Mnemonic
Register
Location Type Description
FRCVCO 0x0E[7] W Force VCO
0 = The system c l ock i s the same as PCLK. (D efaul t)
1 = The system c l ock i s deri ved from lock ed PLL. Thi s is set to 0
upon r eset, Sl eep or Powe r D own mode enabled.
LOKDET 0x0D[7] R Phase Lock ed Loop Lock D etect
0 = PLL is not l ocked. (Defau l t)
1 = PLL is locked t o PC LK.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 43
7.5 GP IO Registers
Three user-defined I/O pins are provided in the 32-p in Q FN package of the 73M1966B onl y. The pi ns are
GPIO7, GPIO6 a n d GPIO5.
GPIO p ins are not available on the 20-pin pac kage of t he 73M1966B.
G PIO pins ar e not availabl e on the 42-p in package of the 73M 1866B.
E ach pi n can be c onfigur ed i ndependently as ei ther an i nput or an output by writ i ng to the cor r esponding
I/O Direction (DIR) register.
A t powe r on and after a reset , the G PIO pins ar e initial i zed t o a high impedance state to avoi d unwan ted
cur r ent c ontention and con sumption. Th e i nput s tructures ar e pr otec ted from floatin g input s, and no
out put levels are dri ven by any of the GPIO pins.
The mappi ng of GPIO pins i s designed to cor r espond t o the bi t location in their control and st atus
registers.
The 73M1x66B supports th e abi lity to generate an interr upt on the INT pin. The source can be configured
t o gener ate on a rising or a trailing edge. Only GPIO ports that are configured as inputs can be used to
generate interrupts .
Function
Mnemonic Register
Location Type Description
DIR 0x04[7:5] W GPI O I np ut/ Ou tp ut Sel e ct
These control bi ts are us ed to des i gnate the GP IO pins as ei ther
inputs or outputs.
0 = GPIO pin is defined as an output.
1 = GPIO pin is defined as an input. (Default)
GPIOn 0x03[7:5] W GPIO State
These b its reflect the status of the GPIO7 , GPIO6 and GPIO5 pins.
If the DIR bit is reset, reading
this field returns the logical value of the
appropriate GPI On pi n as an input.
If the DIR bit is set, the pins output the logical value as written.
ENGPIOn 0x05[7:5] W GPIO Enab le
E ach of t he GPIO enable bits in thi s register enables th e
co r r espo nding G PIO bit as an edge-trigger ed i nterr upt sou r ce. I f a
G PIO bit i s s et to one, an edge ( whic h edge depends on the value in
t he GIP regist er ) of the cor r esponding GPI O pi n will caus e the INT pin
t o go act ive lo w, and the edge detec tors will be r earmed when the
G PIO dat a r egi ster is read.
POLn 0x06[7:5] W GP IO Int er r upt Edge Selection
Defines t he i nterr upt s our ce as being either on a ri sing or a falling
edge of the corresponding GPIO pi n.
0 = A rising edge will trigger an interrupt from the corresponding pin.
(Default)
1 = A falling edge will trigger an interrupt from the corresponding pin.
73M1866B/73M1966B Data Sheet DS_1x66B_001
44 Rev. 1 .6
7.6 Call Progress Monitor
For the purpose of monitoring act ivities on the li ne, a C al l P r ogr ess M onit or i s provided in the 73M1x66B.
Thi s audio output contains both t r ansmit and receive dat a with configur abl e level s.
7.7 16 k Hz Operation of Call Progress Monitor
After switching from 8 kHz sampling rate to 16 kHz sampling rate, the SLEEP bit must be enabled then
disabled if the Call Progress Monitor function is used. After cycling the SLEEP bit, the Line-Si de D evice
registers (Registers 0x12 to 0x18) must be reconfigured.
7.8 Devi ce Reset
For a correct res et of t he 73M1 x66B, the RST si gnal must be ass er ted for a mi ni m um period of 1 ms.
P CLK must be act ive for a mi nimum of 8 clock cyc l es before t he RST signal can be de-asserted. The
P LL locks to the PCLK aft er 20 PC M frames as defined by the oc currence of the Frame Sync Signal (FS) .
Thi s gives a minim um period of 3 .5 ms from the assertion of RST un ti l the PLL is locked and normal
operations may occur , i ncluding acc ess to al l device regist er s and th e transmi ssion and r eception of PCM
dat a samples. If P C LK changes frequency, then the PLL will l ose lock so a stabl e clock must be used
during this res et period. If a PCLK frequenc y change i s requi r ed after the res et, t he user shou ld
implement the procedure described for PCODE (Register 0x23 bits 2 to 5).
Function
Mnemonic Register
Location Type Description
CMRXG 0x10[1:0]
W Receive P ath Gain Sett ing
00 0 dB (for full swing, AOUT=1.08 Vpk) (Default)
01 -6 dB
10
-12 dB
11
MUTE
CMTXG 0x10[3:2]
W Transmit Path Gain Setting
00 0 dB (for full swing, AOUT=1.08 Vpk) (Default)
01 -6 dB
10 -12 dB
11 MUTE
CMVSEL 0x10[4] W Call Progress M onit or Vol tage Reference Selec t
Q ui esc ent DC voltage select at AOUT.
0 = 1.5 Vd c. (Default)
1 = VCC/2 Vdc.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 45
8 PCM Highway Interface and Signal Processing
The PCM highway is the m ethod by which the 73M1x66B exchanges PCM data with the host or other
PCM-enabled devic es. The PCM data c an be in eit her 8-bi t compr essed m ode or in 16-bit l i near mode.
Compr ession of the received sign als from t he PSTN li ne i nterfac e is select abl e A-law or μ-l aw, as
specified by ITU-T Recommendation G.711. The 73M1x66B is configurable with respect to tuning the
cl ock and tim e slot rel ati onships . See Sec tion 8.1 for d etai l s.
The PCM interface provided by the 73M1x66B consists of the following signals:
• PCLK The frequency at which bits are driven on the PCM highway. (Goes to the PCLKI p i n.)
• FS PCM frame synchr oni zat ion pu lse.
• DX PC M data transmitt ed to the PCM high way.
• DR PCM data received from th e PC M highway.
The basic tim ing relationship of PCM highway interface signals is shown in Figure 20.
FS
PCLK
DX MSB LSB
Figure 20: 8 -bit Trans miss ion Ex ampl e
8.1 PCM Highway Interface Timing
Signal FS defines the frame boundaries by being as serted at a rate of 8 kHz. The duration of FS is
defined by the s etup and hold times ar ound the fallin g edge of PCLK and can be extended to mul ti pl e
P CLK cycl es. The timing rel ationship between FS an d PC LK i s determined by the rising edge of FS and
the first falling edge of PCLK that follows the FS ris ing edge. PCLK and FS are com mon t o all devic es
connect ed to the PCM hi ghway. The r ati o of PCLK frequenc y to FS frequenc y determines the number of
bit slot s available dur i ng a frame, i .e., th e num ber of bi ts per frame. The number of bit s l ots divided by 8
is the number of 8-bit tim e slots availabl e during th e frame.
PCLK Frequency
= Bi ts per Frame
Bits per Frame
= Num ber of Time Slots per Fr ame
FS
Frequency (8 kHz)
8-bits per Time Slot
Refined granul ar it y t o the time slot c an be achieved by pr ogramming the c lock slot offset. The clock slot
defines an offset i n terms of the number of bits from th e st ar t of th e time sl ot. The combi nation of the
t r ansmit and receive t i me slot and cloc k s l ot registers det er mines the bit slot at whic h the 73M1x66B
begins transmitting or r eceiving a data samp le. Adju stment s of a h alf clock per iod can be made using
these controls in conjunction with TPOL and RPOL.
The 73M1x66B supports a 16-bit l in ear transmi ssion and r eceive mode. The transmission and r eception
of the data s amples consumes two adjacent 8-bit time slots each on th e PC M highway. The 16 -bit data
sample is transm itted most significant bit first starting at the bit slot defined by the TTS and TCS controls.
The transmission lasts for 16 cons ecut i ve bit s lot s, as il lustrated in Figure 21.
73M1866B/73M1966B Data Sheet DS_1x66B_001
46 Rev. 1 .6
FS
PCLK
DX MSB LSB
Figure 21: 16-bit Transmission Example
Similarly, the 16-bit dat a sample is r eceived mos t s i gnificant bi t first , begi nni ng at the bit s l ot defined by
the RTS and RCS cont r ol regist er s. The recept ion las ts for 1 6 cons ecut ive bi t s lot s.
S R sel ects between 8 kHz and 16 kHz sampling rates. However, FS remains c onst ant at 8 kHz.
Therefore, i n 16 kHz sampling mode, two data samples are trans mitt ed to (or r eceived from) the P CM
highway st ar ti ng at the bit slot di ctat ed by t he tim e and clock slot regi st er s. In 16 kHz mode, either two or
fou r adj acent 8-bit tim e slots ar e used for t wo compr ess ed 8-bit data s am ples or two linear 16-bit data
samples , respecti vely. The 1 6 kH z mode is enabled by s etting SR=1 follow ed by SEL16K=1.
When switching t o 16 kHz sampling rate and if the Cal l Progr ess M oni tor func ti on i s being used, the
Line-Side D evice need s to be rec onfigur ed. See Section 7.7.
P CM highway in terfaces ar e designed s uch th at a devic e can t r ansmi t and receive t o other devic es on the
P CM highway. For example, C odec A will us e a time sl ot assi gnment for it s trans m i t to t he PC M high way
and Codec B will assig n it s rec eiver to the same t ime slot . Th e time sl ot assig nment is such that if Codec
A want s t o transmi t its dat a sample to Codec B, then Codec A t r ansmi t ti me/ clock slot value is identical to
t he C odec B rec eive time/ clock slot value.
The 73M1x66B uses the DX signal pin t o transmit to t he PC M high way and the DR signal pin to receive
from the PCM highway. Fi gur e 22 i llus trates a typical example.
Codec A
DR
DX TSC
Codec B
DR
DX TSC
Codec N
DR
DX TSC
PCM Highway To System
Figure 22: Example of PCM Highway Interconnect
Larger syst ems may use buffers to intercon nect multiple segments of the PC M hi ghway ( acros s li ne cards
for ins tance). I n the 73M1x66B, Control TSC is used to c ontrol the tri -s tate mod e of the transmit s i de of
the PCM highway as shown in Figure 23. TSC is asserted (ac ti ve low) f or the duration of the t i me slot
dur ing w hi ch t he 73M1x66B is transmitting to the PCM highway.
Codec A
DR
DX TSC
Codec B
DR
DX TSC
Codec N
DR
DX TSC
Receive PCM Highway
Transmit PCM Highway
TSC Tri-State Control
From System
To System
Figure 23: Example of PCM Highway Interconnect for Typical Large Systems
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 47
8.2 PCM Clock Frequencies
The 73M1x66B supports the following PCLK input frequencies:
• 256 kHz
• 512 kHz
• 768 kHz
• 1. 024 M H z
• 1. 536 M H z
• 1. 544 M H z
• 2. 048 M H z
• 3. 088 M H z
• 4. 096 M H z
• 6. 176 M H z
• 8. 192 M H z
The 73M1x66B automaticall y detects the frequenc y of P CL K and adj usts i ts internal P LL par amet er s
accordingl y. A t st ar tup, th e fi r st eig ht frames are di scar ded. Th e next eig ht frames are used to count the
number of PCLK c ycles dur i ng each frame. I f the c ount differ s among these ei ght fr ames or i f the c ount is
a non-supported value, then a PC LKD T interrupt is as serted.
I f PCLK i s set at a frequency different from the above lis t, t he PLL will be set for a PC LK of 2.04 8 M Hz.
S ince there will be a discrepancy between the frequency of PCLK and the frequency considered for PLL
settings, a PCLKD T interrupt may occur i f requi r ed. It takes about 20 PC M frames before PLL i s locked,
which is shown t hrough the asser tion of the FR CV CO stat us bit. PCLK must be runni ng for sever al
cycles when reset is d e-ass er ted. After that point, SPI transacti ons can start.
8.3 Master Mode
The default mode of operation for the PCM hig hway in the 73M1x66B i s the s lave mode i. e., FS and
P CLK are inputs to the device. Th e 73M1x66B offers a master mod e by whi ch a 4.0 96 M Hz cloc k is
applied to the PCLKI p in. The master c l ock i s divided by two t o generate a 2.048 M H z c l ock th at is
connect ed to the PCM hi ghway via the PCLKO pin. Simil ar l y, FS of one 2. 048 M Hz period long is
generated and driven to the PCM highway.
The master mode i s set by setting the MA STE R bit.
8.4 A-law / μ-law Compander
The 73M1x66B may be pr ogr am med for compress ed A-law mode, compressed μ-la w mode, or linear
mode. Compressi on sch emes are used to minimize the bandwidth required for exchanging data samples
on the PCM highway. For instance, when PCLK is 8.192 MHz there are 128 8-bit tim e slots availab le.
The density of the overall s ystem is halved when working in linear mode, which requires 16-bit time slots.
The 73M1x66B fully complies with the A-law and μ-law companding specifications defined in the ITU-T
Recommendation G.711.
73M1866B/73M1966B Data Sheet DS_1x66B_001
48 Rev. 1 .6
8.5 Transmit and Receive Levels
8.5.1 A-Law
A cc or di ng to the ITU-T Recommendation G.711, A-law assumes + 4096 ( i n sign pl us 12 bit) to represent
3.1 4 dBm. That is, a sinusoid having a peak value of +4095 to correspond to +3.14 dBm or 1.1119 Vrms
or 1.5725 Vpk or 3.145 Vpp.
Figure 24 shows the mapping implied in the ITU-T Recommendation G.711. Therefore, one least
sig nificant bit in 16-bit code is equivalent to:
bitV
V
LSB /0.48
8
2
5725.1 15
µ
=
−
=
A-Law (Sign + 12 bits)
16 bits Linear
0111111111111
0111111111111000
Figure 24: Mappi ng of A-l aw Code t o 16-bit Code
For A-law, 0 dBm=774.6 m Vrms=1.095 Vp (sinusoid) im plies a peak code of 22,821=5925h.
8.5.2 μ-Law
Similarly, μ-Law assumes +8159 (in sign plus 13 bit) to represent 3.17 dBm. That is, a sinusoid having a
peak value of +8159 to corresp ond to +3.17 dBm or 1.1157 Vrms or 1.578 Vpk or 3.156 Vpp.
Figure 25 shows the mapping implied in the ITU-T Recommendation G.711. Therefore, one leas t
sig nificant bit in 16-bit code is equivalent to:
bitV
V
LSB /35.48
32636
578.1
µ
==
u-Law (Sign + 13 bits)
16 bits Linear
0111111101
0111111101111100
1111
Figure 25: Mapping of μ-law Code to 16-bit Code
For μ-law, 0 dBm=774.6 mVrms=1.095 Vp (sinusoid) implies a peak code of 22,647=5876h.
8.5.3 Transm it and Receive L evel Con trol
The 73M1x66B provides di git al and anal og control over the gains of trans mit and receive si gnal . Th e
overall transmit gain adjustment is +13.4 dB to –26 dB and the range of the rec eiver gain is + 10.4 dB to
–24 dB . Both gai n adj ustment s are i n st eps of 0 .125 dB. Op tim al performance on how t he overall g ain is
t o be achieved r equires the appropriat e man agem ent of t he gain elements in the signal path s.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 49
8.6 T r ansmit Path S ig nal Pr o ce ss ing
8.6.1 General Description
I n the transmit path, dat a i s first sent by the host DSP th r ough a serial interface to the 73M1x6 6B then
interpolated by an int er pol ation fi l ter, serial ized and transmitted acr oss bar r ier interfac e to the Line-Side
Dev ice, which i s floating rel ati ve t o the Host-Si de Device earth ground. The dat a r eceived on t he
Line-Side D evice is then de-serialized and dig itally sigma-delta modulated t o a one-bit data stream of
1. 536 M bps for a sample frequency of 8 kHz or 3.072 Mbp s for a sample frequenc y of 16 kHz. The s ign al
is further fi l tered fir st by a swi tc hed capacit or filt er and then a c ontinuous t ime anti-aliasing circuit.
• The 0.2 dB pas s-band ripp le frequency is fr om dc to 3.422 kHz for an 8 kHz sample r ate or 6.844 kHz
for a 16 kHz sam ple rate.
• The 3 dB bandwidth is 3.65 kHz for an 8 k H z s am pl e r ate or 7.299 k Hz for a 16 k Hz sample r ate.
8.6.2 Total T ran smit Path Resp onse
Fi gur e 26 and Figure 27 show the trans mit path frequency response. Th e r esponse shape is the same,
but the frequencies doubl e for a 16 kHz sample rate.
012345678
100
90
80
70
60
50
40
30
20
10
0
10
Transmit P a t h Over all F requenc y Response
Freq(kHz)
Gain (dB)
10
100−
composite x( )
80 x 16⋅
com
iplo
xou
xou
Figure 26: Transmit Path Overall Frequency Response to Fs of 8 kHz
0 0.5 1 1.5 2 2.5 3 3.5 4
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
Transmit Passband Response
Freq(kHz)
Gain (dB)
1.
1.0−
composite x( )
40 x 16⋅
Figure 27: Transm it Path Passband Response for a n 8 kHz Sample Rate
73M1866B/73M1966B Data Sheet DS_1x66B_001
50 Rev. 1 .6
8.6.3 73M1x66B Transmit Spectrum
Fi gur e 28 shows t he transmit s pectrum observed on the line from dc to 32 kHz for a sampl e frequency
(Fs) of 8 k H z. The trans mit s i gnal is band-li mited ( by defau l t) to F s/2=4 kHz and is flat (wit h 0.2 dB ripple)
t o 3.65 k Hz and i s marked as Txdb( x) in the figure. All frequ encies double for a 16 kH z s am pl e r ate
Also shown , and mar ked as signal db( x), is t he baseband sig nal from 1 k H z to 2 kHz for an 8 kHz sample
rate (2 k H z to 4 for a 16 kHz sam ple rate). The aliases of si gnal db( x) are shown as ali asdb(x) and are
at tenuated sig nificantly wit h better than 80 dB att enuation at 8 k Hz, bett er than 60 dB at 16 kHz , better
t han 100 dB at 24 kHz, etc for an 8 kHz sam pl e r ate and the frequenci es doubl e for a 16 kHz sam pl e r ate.
0 4 8 12 16 20 24 28 32
140
120
100
80
60
40
20
0
20 Transmit Spectrum
Freq
Spectrum (dB)
20
140−
signaldb x( )
aliasdb x( )
Txdb x( )
320 16x
Figure 28: Transmit Sp ect r um to 3 2 kH z fo r an 8 kH z Sample Rate
8.7 R ec eiv e P ath Si gn a l Pr ocessi n g
8.7.1 General Description
I n the receive p ath, the si gnal from t he tel ephone l i ne is in put to t he anti-aliasing filter and passed through
a sel ectable low pass (notch) filt er , which can be us ed to attenu ate i n-band Bi l ling Tones. Th e analog
sig nal is di gi t iz e d by a sigma-delta analog to digital converter. The resulting high frequency one-bit dat a
stream is decim ated and s ent to t he H ost -Side D evice via t he bar r ier. A nother decimati on FI R fi l ter in the
Host-Side D evice filters the rec eived data and s ends it to the host DSP for pr oces sing.
The response of the receive p ath, in conjunction with the decimation filt er i n the H ost -Side D evice,
provides a flat pass-band res ponse to 3.342 kHz at an 8 kHz sam ple rate or 6.744 kHz with a 16 kHz
sample rate with 0.2 dB ri ppl e. Th e 3 dB bandwidt h is 3.58 k Hz at 8k H z s am pl e r ate or 7.226 kH z at a
16 k Hz sample r ate. . The one-bit data stream is 1.536 Mbps for an 8 kHz sample r ate or 3.072 Mbps
with a 16 kHz sampl e r ate.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 51
8.7.2 Total Receive Path Response
Figure 29: Overall Frequency Response of the Receive Path
Figure 30: Pass-ba nd Response of the Overa l l Receive Path
8.7.3 Receiver DC Offset S u b traction
The 73M1x66B pr ovides a method to improve audio quali ty by red ucing unwant ed DC offset from the
rec eiver signal path in A-law or μ-l aw comp r ess i on modes. Th i s met hod r equi r es th at a signal path
cal ibration be performed. Th i s c al ibration is benign to the p er formance of the device and i s only required
after an i ni ti al ization or device reset sequence. Receiver DC of fs et calibr ation can onl y be executed when
t he device is on-hook and not in l inear mode, oth er wis e the proces s wi l l d isturb signal quality. S ee the
73M1866B/73M 1966B Implementer’s Guide for the s teps to enable the calibration of receive DC offset.
73M1866B/73M1966B Data Sheet DS_1x66B_001
52 Rev. 1 .6
8.8 PCM Control Functions
Table 33: PCM Control Functions
Function
Mnemonic
Register
Location Type Description
ADJ 0x22[6] W A dj acent Time S lot D r iver Cont r ol
A llows LSB of the PC M frame (DX) to be tri-s tated during t he second
half of the clock cycle. Th i s feat ure allows adjacent ti me sl ots to be
used by different devices without r isking a c ontention at the tim e slot
boundary.
0 = Drives DX during the entire bi t time. (Defau l t)
1 = Drives DX only during the first half of bit tim e.
DAA 0x14[6:5] W DAA Transmit Gain
Us ed in conju nct ion wit h TX BST to m anage transmit l evel. See
Section 8.8.1.
ENPCLKDT 0x05[4] W Enable PCLK Err or Det ect ion Interrupt
0 = Disables this function.
1 = Enables the detec tion of an interr upt resulting from an
inc oher ency in t he PCL K count dur ing th e second set of ei ght
frames r eceived after power up. ( Defau l t)
LAW 0x23[0] W Law Compres sion Mode
S elects the PCM compress i on mode.
0 = Select s th e A-law compr ession mode. (Default)
1 = Selects the μ-law compres sion mod e.
LIN 0x23[1] W Linear M ode Enable
0 = The compression modes of either A-law or μ-la w are en abl ed.
(Default.) See the LAW bi t.
1 = 16-b i t l i near mode.
MASTER 0x23[6] W M ast er /Slave Mode
The 73M1x66B is in Sl ave Mode by d efault. See Section 8.3 for
det ai ls of mast er and slave operation.
0 = Enables Sl ave Mode. (D efault)
1 = Enables M aster Mode.
PCLKDT 0x03[4] R PCLK Detec t Error
PCLKDT is an interrupt resulting from the det ect ion of two p ossible
events:
1. The number of PCLK peri ods per frame is n ot consi stent among
t he second set of ei ght frames after powe r up.
2. The number of PCLK peri ods per frame does not equate t o any
of the acceptable PC LK frequencies . Th is is a mas kable i nterr upt. It
is enabled by the ENPCL KD T bit. S ee Sect i on 7.2.
PCMEN 0x23[7] W P CM Transmit En able
Controls DX and TSC. This bit must b e set on compl etion of all
configur ation changes to enable transmission on to the PCM
highway.
When powered up, the 73M1x66B PCM outputs ar e tri -s tated. The
host must set PC M EN after set ting the time/cloc k s l ot cont r ol bits to
avoid contention on the PCM highway.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 53
Function
Mnemonic Register
Location Type Description
PCODE 0x23[5:2] W PCM Clock Code
The default s tate of P C OD E out of res et is 0000. In PCM Sl ave
Mode at res et, t he device will att empt to automatical ly detec t the
cor r ect frequency of PCLK. If the PCL K frequency is different from
t hose li st ed in the tabl e below or an i ncorrect P C OD E value is
written, the PLL will not lock (LOCKDET 0x0D[7] == 0). To modify
t he value of PCODE, first write a v al ue of 0000 and then write the
required PCODE value. Toggling of the MASTER bit 0x23[6]
(0 1 0) wit h a PC ODE of 0000 will also r est ar t the aut omat i c
PCLK frequenc y det ection function.
PCLK
Frequency PCODE [3:0]
256 kHz 0001
512 kHz 0010
768 kHz 0011
1. 024 M H z 0100
1. 536 M H z 0101
1. 544 M H z 0110
2. 048 M H z 0111
3. 088 M H z 1000
4. 096 M H z 1001
6. 176 M H z 1010
8. 192 M H z 1011
RCS 0x22[5:3] W Rec eive Cloc k Slot
These bits cont r ol t he st ar ti ng clock of the rec ei ve c hannel . Th e
clock slot value allows the adding of an offset of up to 7 (111) bits to
t he tim e slot value. A value of 000 is zer o offs et.
RPOL 0x21[7] W Rec eive Polarity
0 = The r eceive P CM data is to be sampled on the fallin g edge of
PCLK. (Defau lt)
1 = The r eceive P CM data is to be sampled on the ri sing edge of
PCLK.
RTS 0x21[6:0] W Receive Time Sl ot
S elects the tim e slot number on the PCM h i ghway for the receiver.
The maximu m number of 8-bit time slots is 128 (with a PCLK
frequen cy o f 8.192 MHz). A value of 0000000 is time sl ot zero and
1111111 is tim e slot 128. The default is 0000000.
73M1866B/73M1966B Data Sheet DS_1x66B_001
54 Rev. 1 .6
Function
Mnemonic Register
Location Type Description
RXDG 0x09[7:0] WO Receiver Digital Gain
These bits cont r ols the value of t he di gi tal gai n secti on of the
73M1x66B receive pat h. Eac h bi t indicates eit her a gai n or
at tenuation value. The net value of the gai n set ti ng i s th e linear sum
of e ach at trib uted value. Reading the R XDG register r eturns all
zer os, r egar dless of wh at w as writ ten to t hem .
RXDG –12dB
RXDG –6dB
RXDG +3.5dB
RXDG +2dB
RXDG +1dB
RXDG +0.5dB
RXDG +0.25dB
RXDG +0.125dB
Gain/Attenuate
0 0 0 0 0 0 0 0 0dB (default)
1 0 0 0 0 0 0 0 -12 dB
0 1 0 0 0 0 0 0 -6 dB
0 0 1 0 0 0 0 0 +3.5 dB
0 0 0 1 0 0 0 0 +2 dB
0 0 0 0 1 0 0 0 +1 dB
0 0 0 0 0 1 0 0 +0.5 dB
0 0 0 0 0 0 1 0 +0.25 dB
0 0 0 0 0 0 0 1 +0.125 dB
Examples:
10000 000 -12dB
00100 000 + 3.5dB
00010 011 + 2 + 0.25 + 0.125 =2.375dB
01001 000 -6 + 1 = -5dB
RXEN 0x16[6] W Receive P ath Enable
1 = Enable Receive Pat h.
0 = Di sable R eceive P ath. (D efault)
RXG 0x14[1:0] W R eceive G ai n
S ets th e r eceive pat h gai n/att enuation. See Table 36.
RXOCEN 0x17[5] W Rx DC Offset Calibrate E nable
When RXOCEN is set to 1 and OFH, EN DC and ENN OM ar e r eset
t o 0, t he r eceiver dc offset calibr ation pr oces s is en abled. R XOCEN
mus t be reset to 0 before OFH , ENDC and ENNOM ar e set t o 1 in
order for the c al ib r ati on to operate c or r ect ly. R XOCEN should not
be used in l inear mode.
Default value is 0 .
RXOM 0x25[7:0] W R X Offset Measurement
S tores the res ul t of th e r eceive offset meas ur emen t.
S ee Sect ion 8.8.3.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 55
Function
Mnemonic Register
Location Type Description
SEL16K 0x13[0] W S ample Rate Mode C onfi gur ation Sel ect
Configures t he 16 kHz mode of operati on. See also SR.
0 = 8 k H z s am pl i ng r ate. (D efault)
1 = 16 kHz sampling rate.
The 16 kHz mode is enabled by setting SR=1 followed by
SEL16K=1.
SR 0x22[7] W Sampling Rate Mode
E nables the 16 k H z mode of op er ation. See also SEL16K.
0 = 8 k H z s am pl i ng r ate. (D efault)
1 = 16 kHz sampling rate.
The 16 kHz mode is enabled by setting SR=1 followed by
SEL16K=1.
TCS 0x22[2:0] W Transmit Clock Slot
Controls the starting clock of the t r ansmi t ch annel . The c l ock slot
value allows the adding of an offset of up to 7 (111) bits to the time
sl ot value. A valu e of 000 is zero offset.
TPOL 0x20[7] W Transmit Polarity
0 = The transmit PCM data i s t o be transmitted based on the falling
edge of PC LK. (D efaul t)
1 = The transmit PCM data i s t o be transmitted based on the ri sing
edge of PC LK.
TTS 0x20[6:0] W Trans mit Time Slot
S elects the tim e slot number on the PCM h i ghway for the
t r ansmitter. The maximum number of 8-b it time sl ots is 128 ( with a
PCLK frequency of 8.192 MHz). A value of 0000000 is time slot
zer o and 1111111 i s t ime s l ot 128. The default is 0000000.
TXBST 0x14[7] WO Transmit Boost
Us ed in conju nct ion wit h D AA to manag e transmi t level. See
Section 8.8.1.
73M1866B/73M1966B Data Sheet DS_1x66B_001
56 Rev. 1 .6
Function
Mnemonic Register
Location Type Description
TXDG 0x08[7:0] WO Transmitter Digital G ain
These bits cont r ol t he value of t he digital gai n section of the
73M1x66B transmit path. Each bi t i ndi cates ei ther a gai n or
at tenuation value. The net value of the gai n set ti ng i s th e linear sum
of e ach at trib uted value. Reading the TX D G regi ster returns all
zer os, r egar dless of wh at w as writ ten to them.
TXDG –12dB
TXDG –6dB
TXDG +3.5dB
TXDG +2dB
TXDG +1dB
TXDG +0.5dB
TXDG +0.25dB
TXDG +0.125dB
Gain/Attenuate
0 0 0 0 0 0 0 0 0 dB (default)
1 0 0 0 0 0 0 0 -12 dB
0 1 0 0 0 0 0 0 -6 dB
0 0 1 0 0 0 0 0 +3.5 dB
0 0 0 1 0 0 0 0 +2 dB
0 0 0 0 1 0 0 0 +1 dB
0 0 0 0 0 1 0 0 +0.5 dB
0 0 0 0 0 0 1 0 +0.25 dB
0 0 0 0 0 0 0 1 +0.125 dB
Examples:
10000 000 -12dB
00100 000 + 3.5dB
00010 011 + 2 + 0.25 + 0.125 =2.375dB
01001 000 -6 + 1 = -5dB
TXEN 0x16[7] WO T ra ns mit P a th Enabl e
1 = Enable Transmit Path.
0 = Di sable Transmit Path . (Default)
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 57
8.8.1 Transm it and Receive L evel Con trol
Refer to Section 8.5 for informati on about 73M1x66B l evels.
8.8.1.1 Transmit Gain Scaling
The fir st gain stage in the t r ansmit signal path i s th e dig it al gain whose value is control l ed by wr i ti ng to
Register 0x08 ( TXDG). The second gai n stages ar e the analog gains that are c ontrol led b y Regi ster
0x14[7] (TXBST) and Register 0x14[6:5] (DAA). As a general rule to prevent clipping of the analog gain
stages, it is important to ch oose a v al ue of the digital gai n such that the transmit data aft er multipl i ed by
TXDG does not exceed + 1.25 dBm. So for correct use of the gai n controls t he appr opr i ate mix of digi tal
and an alog settings must be used. Generally speakin g, for best S/N per formance, i t is advisabl e to make
t he dig it al words , aft er di git al gai n sc al ing, as large as possibl e without goi ng over the +1.25 dBm limit .
Example:
If +2 dBm transmi t level i s des i r ed for the c ase where the maximum input i s 0 dBm:
Set anal og gai n to +3 d B (i. e. TXBST an d D AA = 0) add attenuat ion of –1 dB by setting TXDG to
01101 100 ( -6 + 3.5 + 1 + 0.5 = -1); th erefore, +3 - 1 = +2. Note i n this c ase any di git al gain coul d
cause clipping at high input levels in the analog circuitry.
Table 34 lists transmit l evel analog gain adjustment sett i ngs based upon th e values of TXB ST and DAA .
Table 34: Transmit Gain Control
TXBST
0x14[7] DAA1
0x14[6] DAA0
0x14[5] Gain,
Nom. (dB)
0 0 0 +3.0
0
0
1
0.0
0
1
0
-4.0
0 1 1 -8.0
1 0 0 +6.0
1 0 1 +6.0
1 1 0 +2.0
1 1 1 -2.0
Table 35 shows a recommended gai n set tin gs for var ious transmit l evels. With 0 dBm of T x Data and
default setting of DAA1:0 = 01, Txbst=0, TXDG=00h, the transmit level is slightly off at –0. 25 dBm.
TXDG= 00000010 i s requir ed to ac hi eve 0 dBm transmit level. For Tx l evel > 6 dBm, Tx Data i s assumed
less than 0 dBm such that the product of Tx Data and TXDG is less than 1 .2 5 dBm.
Table 35: Recommended Gain Setting
TX L evel
Ana log Ga in
Dig ital Ga in
Ana+Dig
dBm TxBst DAA1 DAA0 dB
TXDG dB dB
-26
0
1
1
-8
1100_0010
-17.75
-25.75
-25
0
1
1
-8
1100_1010
-16.75
-24.75
-24 0 1 1 -8 1101_0010 -15.75 -23.75
-23 0 1 1 -8 1101_1010 -14.75 -22.75
-22 0 1 1 -8 1110_0110 -13.75 -21.75
-21 0 1 1 -8 1110_1110 -12.75 -20.75
-20 0 1 1 -8 1000_0010 -11.75 -19.75
-19 0 1 1 -8 1000_1010 -10.75 -18.75
-18 0 1 1 -8 1001_0010 -9.75 -17.75
73M1866B/73M1966B Data Sheet DS_1x66B_001
58 Rev. 1 .6
TX L evel
Ana log Ga in
Dig ital Ga in
Ana+Dig
dBm TxBst DAA1 DAA0 dB
TXDG dB dB
-17 0 1 1 -8 1001_1010 -8.75 -16.75
-16 0 1 1 -8 1010_0110 -7.75 -15.75
-15
0
1
1
-8
1010_1110
-6.75
-14.75
-14 0 1 1 -8 0100_0010 -5.75 -13.75
-13 0 1 1 -8 0100_1010 -4.75 -12.75
-12 0 1 1 -8 0101_0010 -3.75 -11.75
-11 0 1 1 -8 0101_1010 -2.75 -10.75
-10 0 1 1 -8 0110_0110 -1.75 -9.75
-9
0
1
1
-8
0110_1110
-0.75
-8.75
-8 0 1 1 -8 0000_0010 0.25 -7.75
-7 0 1 1 -8 0000_1010 1.25 -6.75
-6 0 1 0 -4 0110_0110 -1.75 -5.75
-5 0 1 0 -4 0110_1110 -0.75 -4.75
-4 0 1 0 -4 0000_0010 0.25 -3.75
-3
0
1
0
-4
0000_1010
1.25
-2.75
-2 1 1 1 -2 0000_0010 0.25 -1.75
-1 0 0 1 0 0110_1110 -0.75 -0.75
0 0 0 1 0 0000_0010 0.25 0.25
1 0 0 1 0 0000_1010 1.25 1.25
2 1 1 0 2 0000_0010 0.25 2.25
3
0
0
0
3
0000_0010
0.25
3.25
4 0 0 0 3 0000_1010 1.25 4.25
5 1 0 0 6 0110_1110 -0.75 5.25
6 1 0 0 6 0000_0010 0.25 6.25
Note (1) 1 0 0 6 0000_1010 1.25 7.25
Note (1) 1 0 0 6 0001_0010 2.25 8.25
Note (1)
1
0
0
6
0001_1010
3.25
9.25
Note (1) 1 0 0 6 0010_0110 4.25 10.25
Note (1) 1 0 0 6 0010_1110 5.25 11.25
Note (1) 1 0 0 6 0011_0110 6.25 12.25
Note 1. Tx Dat a i s as sumed small enough that th e combi nation of T x Data and TXDG is le s s than 1.25 dBm.
8.8.1.2 Receiv e Ga in S ca ling
O n the receive si de, a 0 dBm rec eive signal on the li ne r esults in ~ 0 dBm at the P CM interfac e.
Means i s provided to adjus t receive si gnal pat h gai n by use of a digit al gain stage. Th is gai n value i s
controlled by Register 0x09[7:0] (RXDG). The gain values are explained in Table 33.
The two R XG bits (Regi st er 0x14[1 :0]) cont r ol the value of t he r eceiver analog gain. T he RXG bi ts m ust
be set to 10 t o enabl e 0 dB gai n i n the receive pat h.
For the best S/N performance it i s recommended t o use a gain value up front in th e anal og domain. The
digital control should be used to fine-tune the recei ver signal path gain.
When th e r eceived line signal exceeds a voltage level greater than specified by ITU-T
Recommendation G.711, the receive gain must be reduced to prevent saturation and clipping within
t he r eceive si gnal pr oces sing path.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 59
Table 36 lists the value of Rec eive Gai n for each val ue of RXG.
Table 36: Recei ve Gain Cont ro l
RXG1
0x14[1]
RXG0
0x14[0]
Gain Nom
(dB)
0 0 -6.0
0
1
-3.0
1
0
0.0
1 1 +3.0
The precise valu es of t he di gi tal gai n set ti ngs are:
Bit
7
6
5
4
3
2
1
0
Gain
0.25
0.5
1.5
1.25
1.125
1.0625
1.03125
1.015625
Gain / Attenuation
-12.04dB
-6.02dB
3.52dB
1.94dB
1.02dB
0.53dB
0.27dB
0.13dB
8.8.1.3 Maximum Levels
The 73M1x66B is capable of providing gain attenuation in bot h the di gi ta l and analog domain. It is important
t o note that for optim um performance the transmitter out put and receiver input s houl d not exceed mor e than
+7.25 dBm. Signal levels that are greater than this will cause dist or tion and r educed performance.
This imp lies that the maximum input s ig nal capabl e by t he transmitter, if adjust ed for unit y gain, is th e
+7.25 dBm, e.g. digi ta l ga i n of -6.0 dB ( ensures anal og input i s less than +1.25 dBm) and analog gain of
+6 dB gives +7.25 dBm.
8.8.2 Tim e Slot Assignment Example
Figure 31 shows an ex ample of t he ti ming of t r ansmit and receive t ime slot s with changes in the tim e slot,
cl ock slot and edge controls. Refer to Sec ti on 8.8, PC M C ontrol Functi ons.
To progr am t he fir st t r ansmit time sl ot aft er FS, TTC=31, TCS=7 and TPOL=1:
• The fir st r eceive t ime s l ot after FS would be RTS=31, RCS=7 and RPOL=0.
• A djustments of ½ clock per i od can be m ade using t hese registers .
FS
PCLK
DR
DR
RTS, RCS = 0, 0
RPOL=0
RTS, RCS = 0, 0
RPOL=1
RTS, RCS = 31, 7
RPOL=0
RTS, RCS = 31, 7
RPOL=1
DX
DX
TTS, TCS = 0, 0
TPOL=1
TTS, TCS = 0, 0
TPOL=0
TTS, TCS = 31, 7
TPOL=0
TTS, TCS = 31, 7
TPOL=1
Figure 31: Timing Relati onships w i th Vari ous TTS, TCS, TPOL, and RTS, RCS, RPOL S ettings
73M1866B/73M1966B Data Sheet DS_1x66B_001
60 Rev. 1 .6
9 Barri er In f orm ation
9.1 Isolati o n B arr i er
The 73M1x66B uses t he Teridi an M icr oD AA propr i etary isolation met hod based upon low -cost pu lse
transformer coupling. This technique provides several advantages over other methods , i ncluding:
• Lower BO M cos t.
• Reduc ed comp onent count .
• Lower radi ated noise (EMI).
• I m pr oved operation in noisy environments.
The MicroDAA has additional and enhanced functionality such as the support of powering the Line-Side
DAA circuit from the Host-Side Device. This allows oper ation on l eased li nes circ ui ts and on low current
condi ti ons commonly en count er ed in long loops. The Micr oD AA can als o oper ate entirely from li ne power
when s ufficient loop current is available.
S ince the trans former is t he onl y c ompon ent cros sing the isolation barr ier, it solely determines the
is olat i on betw een the PSTN an d the FXO’s dig it al int er face. Several vendors can supply compatible
t r ansformers with r atings up to 6000 V.
Communicati on of PCM data, control data and s tatus data is per formed in the digital domain and i s
bidirectional at a rate of 1.536 Mbps.
9.2 B arr ier Pow er ed Opt i ons
The 73M1x66B has the ability to be us ed eit her i n a Li ne Powe r ed M ode or one wh er e the Line-Side
Device can be power ed acros s the barri er from the Host-S i de Device. The power-on defau lt for the
73M1x66B is Barrier Powered M ode.
9.2.1 Barrier P ow er ed Operation
I n this default mode of operation, the 73M1x66B Host-S i de D evice drives the pulse t r ansformer in such a
way that pow er pul ses ar e ti me d ivisi on m ul ti pl exed into th e transmi t bit st r eam (half the time) that is
rectified by circuitry in the Line-Side D evice an d uses this energy to power its elf.
9.2.2 Line Power ed Oper ation
I f there is s ufficient cur r ent availabl e from t he PSTN li ne, the 73M1x66B can be pr ogr am med t o use line
power i nstead of pow er from across the barr i er .
9.3 Sy nchro niz at ion of the B arri er
S ince the c om munic ati on acros s th e bar r ier is digital , s ync hr oni zat ion of d ata ac r oss the barr ier is of
absolute importance. To that end, th e devices implement speci al procedur es to ensur e r el iab ility across
t he bar r i er .
When loss of s ync hronization is detec ted, the SLHS bit i s set to 1 and l ikewis e SYNL is al so s et to 1 and
initi ates an in terr upt to the h ost. Once th e SYN L bi t is as serted a new barr ier s ynch r onization sequence
will au tomatic ally begin.
O nce read, th e SLH S bi t is reset , but will be set again if the synchronization loss continues.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 61
Upon power up, the following sequence should be used to ensure barri er synchronization:
1. The 73M1906B starts i n Bar r i er Powered Mode and transm it s a pr eamb le t o ai d the PLL locking of
the Line-Side Device.
2. When PLL Lock detect i s ac hi eved t he Lin e-Side D evice t r ansmi ts status data to the Hos t-Side
Device.
3. When the Line-Side stat us Data is det ect ed by the Hos t-S id e Device, the barri er i s c onsidered to be
in synchronization by the Host-Si de Device.
4. If th e auto-pol l mode is enabl ed, the Devic e ID is transmitted, whic h is followed by transmit data.
5. Upon detec tion of the Device ID, the Line-Side Device consi der s t he bar r ier to b e in synchr oni zation
in host-to-line side direction .
6. The Line-Side Device s tarts sending R eceive Data.
7. If th e Auto-Poll bit is en abled, the Host-Side Devic e will have polled the Device ID of the Line-Side
Device. If the barrier is synchronized, then Regis te r 1D h, bits 7-4, will be 1101. If not synchronized,
the n 00 00.
9.4 Auto-Poll
O nce th e Barr ier Int er face acqui r es s ynchr oni zation, t he Barr ier Int er face state mac hine au tomati call y
sends a polling command to Li ne -Side Device request ing it to r eturn i ts Devic e ID. This is provided in
REV. Upon p ower up or l oss of barr ier s ync hr oni zat ion, the c ontents of R EV is c l eared . Aft er the
auto-pol l sequence, the host should read R EV. A non-zer o value i ndi cat es that synchronization is
established.
The auto-poll mechanism is disabled by resetting the ENAPOL control bit.
9.5 Barrier Control Functions
Table 37: Barrier Control Functions
Function
Mnemonic Register
Location Type Description
DISNTR 0x15[6] WO Disab le No-Transit i on Timer
I f enabled, the No-Tran sition Timer is a safety feat ure. If t he bar r i er
fails, i .e. no trans i ti on i s det ected for 4 00 μs, the Line-Side Device
res ets it self and goes on hook t o pr event line hol ding in a failur e
condition.
0 = Enables No-Transition Timer of 400 μs. (Default)
1 = Dis ab les No-Trans i ti on Timer .
ENAPOL 0x05[3] W En ab le Automatic P ollin g
0 = Di sables aut omat i c poll i ng.
1 = Initiates automati c pol l ing of the 73M1x66B Device ID upon the
establishment of the barri er SYN . (D efaul t)
I f SYN i s lost , the Devic e ID will be r eset t o 0000.
ENLPW 0x02[2] W Enable Line Power
0 = Barri er Pow er ed M ode i s s el ected. ( D efault)
1 = Line Powered M ode is select ed.
Bit ENLVD must have the value of 0 before switching from Lin e
P owered Mode to Barri er Pow ered Mode. Otherwise level
det ect ion is di sabled and the transition to Barrier Powered M ode
will not occur.
ENSYNL
0x05[1]
W
E nable S ynch Loss Det ection Int er r upt
0 = Di sables S ync h Loss Det ect i on Interrupt.
1 = Enables Synch Loss Detec ti on Interrupt. (Default) When the
73M1x66B detects a los s of synchr onization i n Host-S ide B ar r ier
I nterfac e, SYNL 0x03[1 ] will be set and r eset when read.
73M1866B/73M1966B Data Sheet DS_1x66B_001
62 Rev. 1 .6
Function
Mnemonic Register
Location Type Description
RSTLSBI 0x0D[3] W Reset Line-Side Barr ier Int er fac e
To reset t he Li ne-Side Barr i er Interfac e, set th is bit to 1.
1 = Reset s th e Line-Side Barr i er Interface. The chip sets th is bit back
t o 0 after it has com pl eted reset ti ng the Lin e-Side Barrier Interface.
SLHS 0x0D[6] R Synchronization Lost H ost S ide
Thi s bit indi cat es the status of the Barr ier In terface as seen from the
Host-Side.
0 = Host -Side Barr i er Interfac e i s s ynchr oni zed.
1 = Host -Side Barr i er Interfac e l ost synchr oni zation.
O nce read, th e SLH S bi t is reset , but will be set again if the
synchr oni zation loss cont inu es.
SLLS
0x1E[2]
R
Synchroniza t ion Los s Li ne Si de
0 = TXRDY will continuously be generated following Synchronization
Loss so as to allow SLLS informat ion to be transferred acr oss the
barri er . Th i s c auses an automatic transfer of 1Eh. (Defau l t)
1 = Synchronization is lost in th e Lin e-S ide Devic e due to Header .
SYNL 0x03[1] R Bar r i er Synchr oni zation Los s
0 = Ind icates syn chronizat ion of d ata ac r oss the barrier.
1 = Ind icates a loss of synchr oni zat ion of d ata ac r oss the barrier.
Thi s status bi t is reset wh en r ead. Th i s is a maskable interr upt. It is
e na bl e d by the EN SYNL bi t.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 63
9.6 Line-Side Dev i c e Op er at i ng M o des
The architec ture of the 73M1x66B is unique i n that the is olation barri er device, an inexpensiv e pul se
t r ansformer, is us ed to pr ovide power an d also bi di r ectional data between the Host -Side Device and t he
Line-Side D evice. When the 73M1x66B is on hook, all the power f or the Line-Side Device is prov i ded
over the barr i er in terface. A fter the Line-Side Device goes off hook, the t elco l ine suppl i es approximately
8 mA to the Li ne -Side Device while the host provides t he r emainder acros s t he bar r i er . It is also possib le
to power the Line-Side D evice ent irely from the li ne provided there i s at leas t 17 mA of loop c ur r ent
avai lable. Set ti ng the ENLPW bi t enables this m ode and turns off the power supplied across the barr i er .
There is a penal ty in us i ng this mode in that the noi se and dynamic range are about 6 dB worse than wit h
t he Barr ier Powered M ode. It is therefore recommended t hat the Li ne Powe r ed M ode be reserv ed for
applications wh er e the absolute minimum power fr om t he host si de i s a pr i or it y and t he r educt i on in
performanc e can be toler ated.
Figure 32 shows the AC and DC circuits of the Line-Side Device.
+
C4
10uF
Q7
MMBTA42
1
3
2
Q6
BCP-56
1
2
3
4
R65
200
U2
73M1916-20
OFH
4
VNX
5
SCP
6
MID
7
VPX
8
VBG
11
ACS
12
SRE
9
SRB
10
VNS
13
VPS
14
RXP
15
RXM
16
TXM
17
DCS
19
DCD
18
DCI
1
RGN
2
RGP
3
DCG
20
R3
412K, 1%
R12
5.1K
TP14
OFH
1
R11
5.1K
R58
240
R4
100K, 1%
Q3
MMBTA42
1
3
2
Q4
MMBTA92
1
3
2
Q5
MMBTA06
1
3
2
OHS
TXM
SRE
RXM
SRB
RXP
DCI
DCD
R5
8.2
-
+
BR1
HD04
4
1
3
2
Figure 32: Line-Side De vice AC and DC Circu its
The D C IV bits c ontrol t he voltage ver sus current ch ar act er istics of the 73M1x66B by monitoring the
voltage at the line divided down by the ratios of (R3+R4)/R4 (5:1) measured at the DCI pin. This voltage
does not include the volt age acros s the Q4 and the bri dge. When both th e ENAC and END C bits are set
(the hold mode), th e D CI V charac teri stic s follow ap pr oximately a 5 0 Ω l oad l ine offset by a factor
determined by the DCIV bits. If ENDC=1 and ENAC=0, the 73M1x66B will go into the ”Seize state mode”
and the DC voltage load c har act er istic will be r educed t o m eet the Austr alian s ei ze vo l tage requi r ement s
regardl ess of the setting of th e DCIV bits.
9.7 Fail-Safe Operation of Line-Sid e Dev i ce
The 73M1x66B provides addi ti onal pr otec ti on agai nst improper oper ation during error and harmful
external event s. These inc lu de power or communi cat i on fai l ur e with t he Lin e-Side Devi ce and t he
det ect ion of abnor mal voltages and currents on the lin e. Th e basis of thi s pr otect i on i s to ensur e that
under th ese c ondi ti ons th e device is in t he On-Hook st ate and the isolation i s provided.
The following events will cause the 73M1x66 Line-Si de D evice t o go to the O n-Hook state if it is Off-Hook:
1. A Power-On Reset occurs while Off-Hook.
2. The non-trans i ti on timer function ( see DISNTR) is triggered by the absence of any signal transitions
for more than 400 µs on the barrier interfac e, indicating a pr obl em with communic ati ons.
3. The power supply to the Line-Side Device is below nor mal operating l evels.
73M1866B/73M1966B Data Sheet DS_1x66B_001
64 Rev. 1 .6
10 Configurable Direct Access Arrangement (DAA)
The 73M1x66B Line-Si de D evice integrates most of t he cir cuitry t o i mplement a PSTN line i nterface or
DAA that is c apable of being globally comp liant with a single bill of materials.
The 73M1x66B supports the following DAA functions:
• Pulse d ialing
• O n and Off Hook switch c ontrol
• Loop current (DC-IV) reg ulat i on
• Line im pe da nc e ma tching
• Ri ng de tection
• Tip and R i ng voltage polar ity revers al detect i on
• Billing ton e rejection
• Trans-h ybrid canc el lat i on
The device is able to support Barrier Powered Mode in which the PSTN loop cur r ent may be as l ow as 8 mA.
10.1 Puls e Dial ing
The 73M1x66B supports Pul se Di aling. See Sec tion 10.6 for the des cripti ons of ap pl icabl e control and
status bits.
10.2 DC Termination
DC Termi nati on or Loop C ur r ent (D C-IV) r egul ati on i s man aged by th e 73M1x66B Line-Side D evice b y
co nfigur i ng the appro pr i a te registers. N o addit i onal components are necess ar y.
The 73M1x66B pr ovides a DC transc onduct ance circu i t that r egulat es th e tip to ring voltage dependi ng on
t he D C cur r ent s uppl ied by the li ne. There are four sett i ngs t hat can be us ed to set the voltage t o current
ratio.
Figure 33 shows the DC -IV charact er i st ics of the 73M1x66B with special r egion s of interes t.
Figure 33: DC-IV Characteristics
V
I
41 Ω*
Programmable
Turn-on Voltage
Given by
DCIV Control
Bits
Current Limit Turn-on=42 mA
2.2 kΩ
Current Limit Turned on
* ~50 Ω with 8 Ω fuse resistance
Seize Voltage
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 65
The 73M1x66B can:
• Sh ift th e characteristics by setting the turn-on voltage.
• E nable a curr ent l imit of 42 mA.
The 73M1x66B meets a wide range of d if ferent c ountri es’ r equi r ement s under s oftware control. See
Section 10.7.
There ar e two oper ati ng st ates for the D C -IV ci r cuits: H old and Seize.
0
2
4
6
8
10
12
14
5
9
15
20
30
40
50
60
70
80
90
96
110
Tip/ Ri ng Vol tage
DC Current, mA
DCVI Performance
DCIV=00
DCIV=01
DCIV=10
DCIV=11
Figure 34: Tip-Ring Voltag e versus Current Using Different DCIV Settings
The H ol d stat e i s th e nom inal operational point for the DC -IV ci r cuits. The res ponse shown in Figure 34
is for the H ol d stat e ( both DC and AC transconductance circuits are enabled). The slope of the DC-IV
characteristics is approximately 50 Ω when the series resistance of a typical PPTC resettable fuse is
t aken into ac count .
The Seize s tate is a condi tion that is used by some central offi ces to determine an off-h ook condi ti on. In
this state an additional load is added to the nominal operational DC-I V ch ar acterist ics used dur in g the
Hold stat e
I n the Seize state (only the DC transconductance circuit is enabled), the tu rn-on volt age i s reduc ed on the
line ind ependent of th e DCIV control bit s. See Figure 35 and the description of the DCIV bits in
Section 10.6.
73M1866B/73M1966B Data Sheet DS_1x66B_001
66 Rev. 1 .6
A n exampl e of the use of the Seiz e stat e i s for Aust r alia, whi ch requir es t his st ate for the first 300 ms
immediately a fter goi ng off hook.
0
2
4
6
8
10
12
14
0
10
20
30
40
50
60
70
80
90
100
Tip/Ring Voltage
DC current, mA
DCVI Performance
DCIV=xx
Austral ian Not Recommended Region
Australian
Prohibi ted Regi on
Figure 35: Voltage versus Current in the Se ize M ode is the Same for All DCIV Settings
To facilitate the quick capture of the loop, the bandwidth of the DC loop is high upon power up. On the
completion of DC l oop captu r e, i t sh ould b e lowered to avo id t he i nteract ion of DC and AC loop s. See the
description of the ENNOM bit in Section 10.6.
10.2.1 Current Limit Detectio n
I f the DAA Cur r ent Limiting feature is ena bled and the device detects an I-limit c ondit i on, a st atus bi t i s set
t o r epor t this event.
10.3 AC Termination
The 73M1x66B supports 16 impedance configurations. This set of AC impedances has been select ed to
provide global coverage without the need for changi ng ext er nal components.
The AC Termi nation funct i on i s c ontrol led by an enabl e and a di sable cont r ol bi t and by wr it i ng the
appropriate networ k confi gurati on code t o the devic e. Th e AC Termi nations provided include ones
sui tabl e for ETSI ES 203 021-2, Au strali a, F CC and Chi na, among others. See Sect i on 10.7 on how to
sel ect a configur ation.
When using the 900 Ω termination, an additional gain of 1.75 dB shoul d be added to the t r ansmi tter
path.
Upon s election of a particular AC impedance configuration, the 73M1x66B monitors the line and cont r ols
the AC current bac k to th e l ine, such that t he desired impedance looki ng int o the RXP pins is realized.
The 73M1x66B pr ovides an A C trans conduc tanc e cir cuit th at i s used to modulate the AC signal onto th e
line as wel l as to regul ate the cur r ent and provide the AC load in the AC signal path.
Figure 36 shows the magnitude response of the impedance mat ching fil ter for the c ase of E S 203 021-2.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 67
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
4
5
6
7
8
9
10
Fr e q Response of IPMF, AZ =01
kHz
10
0
F1db f 1000⋅( )
50 f
Figure 36: Magnitude Response of Impedance Matching Filter, ACZ (3:0)=0010 (ES 203 021-2)
10.4 Billing Tone Rejection
S ome countri es us e a l ar ge amplitude out-of-band tone to meas ur e call dur ation and to allow remote
central of fi ces to determin e the durati on of a c al l for billing purposes. To avoid sat ur ati on and distortion of
t he i nput c aused by t hese tones, it i s impor tant t o be able t o r ej ect t hem. These frequencies are typically
12 kHz or 16 kHz.
The 73M1x66B has an integr ated notch fi l ter that att enuates ei ther of these tones. By enab ling this filter
and selecting the position of the notch frequency, such tones will be attenuated.
Figure 37 shows the magnitude response of the filter with a not ch at eit her 12 kHz (F1) or 16 kHz (F 2).
0 2 4 6 8 10 12 14 16 18 20
50
40
30
20
10
0
10
Spans 20kHz
10
50−
F1db f 1000⋅( )
F2db f 1000⋅( )
200 f
Figure 37: Magni tude Response of Bi lling Tone Notch Filter
I n addi ti on to the notch fi l ter, the 73M1x66B can indi cat e the presence of an overload condition when a
line’s AC voltage exceeds 3.5 Vpk.
73M1866B/73M1966B Data Sheet DS_1x66B_001
68 Rev. 1 .6
10.5 Trans-Hybrid Cancellation
I n or der to im pr ove performance, the Trans-hyb r i d Can cell ati on option al lows a repli ca of the transmit
si gnal t o be created withi n the 73M1x66B and fed bac k to th e R XM pin via an ext ern al circuit at the line
interface. Wi th a well match ed AC impedance the amount of cancellation ac hieved i s >26 dB. This
function can be enabled or disabled.
RXM
RXP
TXM
Tx Buf
Vin
-
Vin+
Rp
Rn
52.3 kΩ
17.4 kΩ
21 kΩ
4.7 uF
+
-
Rx Buf From the Line
Figure 38: Trans-hybrid Cancellation
10.6 Dir ect Ac ce ss Arr a ngement Control Functions
These Transmit C ontrol Regis ters c ontain cont r ol information to s et up the li ne side of the 73M1x66B.
I ncluded are D C-IV characteristics, off-hook c ontrol , etc.
Table 38: DAA Contr ol Functions
Function
Mnemonic Register
Location Type Description
ACZ 0x16[3:0] W Active Ter mination Loop
Controls the sel ection of t he act ive termination loops per the table
shown belo w. ATE N must be set to 1 for s election to be enabled.
ACZ Field Active Termination Loop Setting
0000 600 Ω
0001 900 Ω
0010 270 Ω + 75 0 Ω || 150 nF and 275 Ω +
780 Ω || 150 nF (ETSI ES 203 021-2)
0011 220 Ω + 82 0 Ω || 120 nF and 220 Ω +
820 Ω || 115 nF (Australia)
0100 370 Ω + 62 0 Ω || 310 nF
0101 320 Ω + 10 50 Ω || 230 nF
0110 370 Ω + 82 0 Ω || 110 nF
0111 275 Ω + 78 0 Ω || 115 nF
1000 120 Ω + 82 0 Ω || 110 nF
1001 350 Ω + 10 00 Ω || 210 nF
1010 200 Ω + 68 0 Ω || 100 nF (China)
1011 600 Ω + 2.1 6 µF
1100 900 Ω + 1 µF
1101 900 Ω + 2.1 6 µF
1110 220 Ω + 40 0 Ω || 70 nF (China)
1111 270 Ω + 600 Ω || 150 nF (Global
Impedance)
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 69
Function
Mnemonic Register
Location Type Description
ATEN 0x16[4] W A ct ive Termi nation Loop Enable
E nables or di sables A ctive Termination Loop.
0 = Dis ab le. (Default)
1 = Enable Acti ve Termination Loop.
Note: nor mal operation r equi r es this bit to be set to always enable a
term ination c ircuit.
DCIV 0x13[7:6] W D C Current Voltage Charact er istic Control
Hold state with E NDC an d E NAC=1 , at 20 mA D C loop cur r ent
meas ur ed at DCI . The Tip/Ring voltage assumes that there i s a 5:1
at tenuation of of f-hook voltage at t he D C I i nput pin.
DCIV1 DCIV0 Description
0 0 DC Loop On Voltage of 0.73 V
(5.60 V at Tip/Ri ng assuming a
5:1 step down of off-hook
voltage)
0 1 DC Loop On Voltage of 0 .977 V
(6.75 V at Tip/Ri ng assuming a
5:1 step down of off-hook
voltage)
1 0 DC Loop On Voltage of 1 .232 V
(7.65 V at Tip/Ri ng assuming a
5:1 step down of off-hook
voltage)
1 1 DC Loop On Voltage of 1 .488 V
(9.35 V at Tip/Ri ng assuming a
5:1 step down of off-hook
voltage)
*Sei ze s tate with EN D C=1 and ENAC= 0, 20 mA loop c ur r ent.
DCIV =xxProvides a DC Loop “On” Voltage of 0. 281V (3.9 V at Tip/Ring
assuming 5:1 step down of off-hook voltage)
ENAC 0x12[5] WO Enable AC Transconductance Circuit
0 = Shut Down AC Transconductance Circuit. Aux A/D input = Ring
Detect Buffer (RGP/RG N ) / Lin e Vol tage (D CI ) . Sei ze s tate for going
of f hook . (Def aul t)
1 = Enable AC Transconductance Circuit. Aux A/D input = Line Current
(DCS) / Line Voltag e (DCI).
ENDC 0x12[6] WO Enable DC Transconductance Circuit
0 = Shut down Transconductance Circuit. (Default)
1 = Enable Transconductance Circuit.
ENFEL 0x12[2] WO Ena bl e F r o nt En d Li ne-S ide Circu it
0 = Power down Front End Line-Side circu its. (Default )
1 = Enable F r ont E nd blocks exc l udi ng DCGM, ACGM, shunt r egul ator.
73M1866B/73M1966B Data Sheet DS_1x66B_001
70 Rev. 1 .6
Function
Mnemonic Register
Location Type Description
ENLVD 0x12[3] WO LeV Detection (OVDET, UVDET, OIDET mon it or s)
0 = Enable LeV detection. (Default )
1 = Disable LeV detection (used in line-powered mod e to save power).
This bit will be 0 when Line Powered Mode is detected (ENLPW is set
in Register 0x02[2]) and set to 1 when an interrupt occurs within the
73M1916. This bit m ust be reset prior to switching back to Barrier
P owered Mode.
ENNOM 0x12[0] WO E nable Nomin al Oper ati on
0 = Speeds up the on and off hook transitions time by increasing the
DC loop bandwidth of the DC transconductance circuit in the
73M1x66B. This should be used for puls e dialing, going on and off
hook, etc. In addition, ENN OM=0 pr event s the res et of all bit s in
Register 0x12. (Default)
1 = Ent er N ominal Operation. Reduces the loop bandwidth of the DC
transconductance circuit. Allows reset of R egi ster 0x12 caus ed by bits
UVDE T, OV DET or OIDET.
ENSHL 0x12[4] WO Enable Shunt L oading
0 = Di sable shunt l oading. ( D efault)
1 = Enable s hunt l oadi ng of the li ne. Not us ed for most applications.
IDISPD 0x13[1] WO Discharge and Puls e Dialing
Controls the DC discharge current and how fast the loop turns off.
A ffec ts pulse di al ing waveform. C ontrols the amount of disc har ge
cur r ent duri ng hook switch transitions.
0 = Minimum curren t. (Default )
1 = Maxim um curren t.
I t is recommended to set IDISPD to 1 pr i or to hook switchi ng
operations.
ILM 0x13[5] WO Cur r e nt Li mit Ena bl e
Thi s control en ables or di sables loop c ur r ent l i mit.
0 = No current limit . (Defau lt)
1 = 42 mA current limit enabled.
ILMON 0x1E[7] R Current Lim it Mode On
Th is status b i t i s effective on ly when t he ILM bit i s s et t o 1.
0 = Loop current is lower than 42 mA.
1 = Loop current is hi gher than 42 mA and th e current limiting m ode is
active.
OFH 0x12[7] WO Off-Hook Enable
Thi s bit c ontrol s th e stat e of the Hook si gnal .
0 = On-Hook. (Default)
1 = Off-Hook.
PLDM 0x13[3] WO Pulse Dialing Mode Enable
Alleviates the s trict timing requirement s for th e Host having to control
ENDC an d O FH dur i n g pul se di aling. With PLDM = 1, t he Ho st o nl y
has to toggle OFH t o per form pu lse di aling.
0 = Pu ls e Dialing Mode is disab led . (Default)
1 = Pul se Dialing Mode i s enabled.
RLPNEN 0x16[5] W Receive Low P ass N otch En abl e
0 = Bil l ing Tone Receive L ow P ass N otc h ( RLP N) filter bypassed.
(Default)
1 = RLPN Filter Enabl ed. See RLPNH for notch frequenc y s el ection.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 71
Function
Mnemonic Register
Location Type Description
RLPNH 0x14[2] W Rec eive Low P ass Not ch
0 = Select s Receive L ow P ass Not ch (RLPN ) at 12 k Hz. (D efaul t)
1 = Select s RLPN at 16 k Hz. See RLPNEN (Register 0x16[5]) to
enable the filter.
THEN 0x15[3] W Enable Transhybrid Circuit
The rejec tion of the t r ansmi t s ig nal from the rec ei ve s i gnal path.
0 = Transhybrid Circuit disabled. (Default)
1 = Transhybrid Circuit enabled.
This bit should always be set for optimal performance.
73M1866B/73M1966B Data Sheet DS_1x66B_001
72 Rev. 1 .6
10.7 International Register Settings Table for DC and AC Terminations
Table 39 lists the recommended ACZ and DC IV register s ettings for var i ous c ountri es. Other paramet er s
can al so be s et in addi ti on to the AC and DC termin ati on. These s ettings along with the reference
schematic (s ee Figure 12) can r eal ize a single design for gl obal usage without c ountry-specific
modifications . F or more information on wor ldwid e appr ovals, r efer to the 73 M1x 66 Wor l dwide Design
Gui d e Ap pl i c ation Not e.
Table 39: Recommended Re gi ster Settings for International Compatibility
Country ACZ(3:0) DCIV(1:0) Country ACZ(3:0) DCIV(1:0) Country ACZ(3:0) DCIV(1:0)
Argentina 0000 10 Hungary1 0010 10 Pakistan 0000 10
Australia 0011 11 Iceland2 0010 10 Peru 0000 10
Austria1 0010 10 India 0000 10 Philippines 0000 10
Bahrain 0000 10 Indonesia 0000 10 Poland1 0010 10
Belgium1 0010 10 Ireland1 0010 10 Portugal1 0010 10
Bolivia 0000 10 Israel 0000 10 Romania1 0010 10
Brazil 0000 10 Italy1 0010 10 Russia 0000 10
Bulgaria1 0010 10 Japan 0000 00 Saudi Arabia 0000 10
Canada 0000 10 Jordan 0000 10 Singapore 0000 10
Chile 0000 10 Kazakhstan 0000 10 Slovakia1 0010 10
China3 1110 10 Kuwait 0000 10 Slovenia1 0010 10
Columbia 0000 10 Latvia1 0010 10 South Africa3 0011 10
Croatia
0010 10 Lebanon 0000 10 South Korea 0000 10
Cyprus1 0010 10 Leichtenstein2 0010 10 Spain1 0010 10
Czech Rep1 0010 10 Lithuania1 0010 10 Sweden1 0010 10
Denmark1 0010 10 Luxembourg1 0010 10 Switzerland2 0010 10
Ecuador 0000 10 Macao 0000 10 Syria 0000 10
Egypt 0000 10 Malaysia 0000 10 Taiwan 0000 10
El Salvador 0000 10 Malta1 0010 10 ES 203
021-2 0010 10
Estonia1 0010 10 Mexico 0000 10 Thailand 0000 10
Finland1 0010 10 Morocco 0000 10 Turkey 0000 10
France1 0010 10 Netherlands1 0010 10 UAE 0000 10
Germany1 0010 10 New Zeal and3 0100 10 UK1 0010 10
Greece1 0010 10 Nigeria 0000 10 Ukraine 0000 00
Guam 0000 10 Norway2 0010 10 USA 0000 10
Hong Kong 0000 10 Oman 0000 10 Yemen 0000 10
1 These countri es are members of the European Uni on, wh er e there are no long er any regulatory
requir emen ts for A C impedance. The s uggested setting c om plies with ETSI E S 20 3 021-2. Ot he r
settings can be used if desired.
2 These countri es are members of the European Fr ee Trade As sociat i on, and their r egul ati ons
generally follow the European Uni on model. The suggest ed set ti ng complies with ETS I ES 203 021 -2.
3 These countri es can use the su ggested complex setting for voice or data products
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 73
11 Line Se nsing and St atus
The 73M1x66 supports the means to implement several line status functions such as ring detection, Line
I n U se detec ti on, paral lel pickup detect i on, and line voltage pol ar it y reversal s. To support t hese
functions, 73M1x66 is able to measure the l i ne voltage and cur r ent charac teri st ics. In conjunc tion with
t hese meas ur ement s, pr ocedures can be i m plemented in the host to fully s uppor t these capabil i ti es in an
application.
11.1 Auxiliary A/D Converter
An 8-b it auxil iary A/D converter in tegrated i n the 73M1x66B provides l ine monitori ng and sensi ng
capabi lities. Th e A/D convert er i nput sig nals ar e connected to t he RG P and RGN pi ns of t he devic e. It is
possibl e to us e this A/D converter to sample signals unr elated to PSTN DAA fun ct ions. However , in this
application, it is necessary to isolat e the input s ignal wit h optical or other means since t he 73M1x66B is
connect ed di r ectly to the PSTN. U nder nor mal c ondi ti ons, RGP an d RG N ar e AC coupled to th e line
through high voltage (250 V) capacitors.
Through the use of this auxil iary A/D converter , the following li ne st atus sensing feat ur es are su ppor ted
by the 73M1x66B:
• Ri ng detec ti o n.
• P STN line already in use det ect ion.
• Off-hook det ection that a par al lel phone has been pi cked-up – p arallel pick-up det e c ti on (PPU).
• On-h ook det ection of DC l oop voltage polar i ty reversal s.
• On-h ook det ection of Type II Caller ID.
11.2 Ring D et ecti on
Ring Detection is provided through circuitry connected to the device pins RGP and RGN. Any large
voltage transition (ringing or li ne r eversal) will be a sourc e for the “Wake up” signal to the 73M1x66B.
Upon recept i on of a w ake-up signal, the 73M1x66B p asses th e detect ed signal to the hos t wher e i t i s t o
be qualified for frequency and cadence (on and off timing of the ring tone burst s ) as a valid ring sign al.
11.3 Line In U se Detection (LIU)
If the 73M1x66B is preparing to go off-hook and dial, it is required to be aware whether the phone line is
already in us e by anoth er device. If the 73M1x66B determines that the ph one line is pres ently in use, it
can avoid going off-h ook and interrupting the call in pr ogr ess . The timing of t he FXO’s off-h ook t r ansition
can be del ayed unt il the F XO det er mines that th e phone l ine is available. LI U sensing is done at pin
DCIN with the Aux A/D.
11.4 Parallel Pick Up ( P PU)
P ar allel Pi ck U p i s a means for the 73M1x66B to determi ne and notify a host in the case wh en the DAA i s
off-hook and a second or parall el-connec ted device dur in g the cou r se of a connect ion is also mad e to go
off-hook.
11.5 Polarity Reversal Detection
A thi r d typ e of line sensing requi r ement is ass ociated with Caller ID protocols found in Japan and s ome
E ur opean count r ies. In th ese countries, the Cal l er ID signals are sent pr i or to the start of normal ringi ng.
A polarity rever sal i s used to i ndi cate t o the FXO that transmi ssion of C al ler ID informat i on is about to
begin. The detec tion of a polar ity reversal takes place while t he FX O i s in the on-hook st ate.
11.6 Off-hook Detection of Caller ID Type II
I t is also possibl e to receive Caller ID signals whi le t he telephone i s in use, r eferr ed to as Type II CID.
Thi s requir es t he 73M 1916 to c onstant l y monitor the l i ne for signal s, such as sp ecial i n-band or CAS
t ones, while the F XO is in the off-hook stat e. Th i s is done t hr ough the normal rec eive path.
73M1866B/73M1966B Data Sheet DS_1x66B_001
74 Rev. 1 .6
11.7 Voltage and Current D e tection
The 73M1x66B is capable of det ecting the follow i ng circumst ances:
• Under voltage on t he line.
• O ver voltage on t he l ine.
• Over cu rrent.
These 73M1x66B built-in me c ha ni sms pro vide pro tection to bot h the de vic e itself and the exter nal line
circuitry.
I f enabled, Over V ol tage and Over Current detec tion will caus e the 73M1x66B to go on-hook wit hout the
interven ti on of the host.
I f c onfi gured in Line Powered Mode, t he detec ti on of an under-voltag e condition causes the 73M1x66B to
switch automaticall y to B ar r ier Power ed Operation ( see Section 9.2.1). Th i s is done wit hout the
interven ti on of the host.
For each of t he detec tion func ti ons th er e ar e enabl e control bi ts an d detect i on st atus bits. F or each
fu nct ion there is a master detec tion funct i on enabl e bit that must be s et i n or der for the functi ons t o work .
11.8 Under Voltage Detection (UVD)
Under Vol tage Detec ti on i s an imp or tant featur e of 73M1x66B. It d etermines if t he phone l in e is not
capabl e of supplying the current that the 73M1x66B r equi r es from the li ne for pr oper operati on. If this
function is enabled and if the line is not capable of providing this current, the UVD condition will be
asserted and can become a s our ce of interrupt from the 73M1x66B to its connect ed host.
11.9 Over Voltage Detection (OVD)
I f enabled, Over V ol tage D etec ti on i s indi cat ed if the devic e sens es t hat the li ne voltage exceeds a
defined threshold. The device allows the selection of choice of either 60 Vpk or 70 Vpk (depending upon
t he attenuat i on r ati o, typical ly thi s is 100: 1) .
I f enabled, the 73M1x66B will au tomati cally go on-hook if over voltage is det ect ed.
11.10 AC Sig nal Overload Detection
Thi s is t he same feat ur e as used for the detecti on of bil ling t ones (s ee Sect ion 10.4) . In th i s most generi c
sense, thi s det ect or pr ovides an indicator that the AC signal on the line exceeds a value of 3.5 Vpk.
11.11 Over Current Detection (OID)
When th e line c ur r ent exceeds the safe operating range of th e 73M1x66B or the exter nal t r ansis tors, t he
device i ndi cat es this condition. If en abled, the 73M1x66B wi l l au tomati call y go on-hook i f an over c ur r ent
event is detected.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 75
11.12 Line Sensing Control Functions
These regist er s c ontain cont r ol information to s et up and us e the 73M1x66B line sensing functions.
Table 40: Li ne S ensing Control Functions
Function
Mnemonic
Register
Location Type Description
CIDM 0x15[4] W Calle r ID Mode
0 = Dis ab le Caller ID Mode. (Default)
1 = Enables Caller ID M ode by coupling the signal from the RGN/RGP
pins to the PC M D X pi ns in the appropri ate PCM codec format. A 20 dB
gain boost is included in the signal path. The RXBST bit should also be
set to all ow the total nominal gai n of 40 dB in th e C aller ID path. The
normal signal path i s disconnect ed.
RXBST 0x14[3] WO Rec eived Boost
I f s et to 1, Rec eive signal is i ncreased b y 20 dB. Default i s 0. This is
used to am plify signals that are passed through the auxiliary A/D when
On-Hook.
Rin g D etec tion Status Bits
ENRGDT
0x05[0] W En able Ring Det ect ion Interrupt
This control bit enables the ring detection interrupt.
0 = Ri ng D etect i on Interrupt Disabl ed.
1 = Ri ng D etect i on Interrupt Enabled. (D efault)
When 73M1922 detects an incom ing ring signal, this bit will be set, if
enabled, and res et when r ead.
RGDT 0x03[0] R Ring or Lin e Rever sal D etec tion
V olt age gr eater than the Ring D etect Thres hol d was detec ted at
RGP/RGN. Th i s value is latched upon the event and cleared on r ead.
The threshold is d etermined by RGTH. This is a maskable interr upt. It is
enabled by the ENRGDT bit.
0 = No Latch ed R ing or Line R eversal D etec tion event. ( D efault)
1 = A Latched Ring or Line Rever sal D etect ion event.
RGMON 0x03[3] R Ringing Mon itor
B it 3 m oni tors the activity of Ringing for further cadence check by the
host:
0 = Silent
1 = Ring ing
This bit is not latched. This status bit is reset when read.
RGTH 0x0E[1:0] W R i ng Det ect Thres hol d
Controls the Ring D etect Thres hol d assuming a 100:1 reduc ti on of Rin g
Voltage into the RGP/RGN pins.
RGTH1 RGTH0 Description
0 0 Ring Detec t disabled. For r ing
det ect ion t o occur , these bit s
mus t be program med to a non-
zer o st ate.
0
1
0.15 Vpk equivalent to ±15 Vpk
at Auxiliary A/D input.
1 0 0.30 Vpk equivalent to ±30 Vpk
at Auxiliary A/D input.
1 1 0.45 Vpk equivalent to ±45 Vpk
at Auxiliary A/D input.
73M1866B/73M1966B Data Sheet DS_1x66B_001
76 Rev. 1 .6
Function
Mnemonic Register
Location Type Description
Auxiliary A/D Converter Status Bits
LC 0x1C[7:1] R Loop Current In DC Path
Res ult of Auxili ary A/D measuri ng the Loop Curren t (7-bit resolution,
least sig nificant bits only).
Note: LC0= 1 l sb= 1.31/128= ~ 10.23 mV=1. 25 m A; magnit ude onl y.
The value of t he r esist or between the rect ifier bri dge and the DCS pin is
assumed to be 8.2 Ω.
E xampl e: 0000011 30. 7 m V/R E=3.7 4 m A; 00 10000 20 mA
Note: The AC path als o has ~7 mA of loop current that should be added
t o get the t otal l oop current provided by the l ine.
LV 0x1B[7:1] R Li ne Vol tage On and O ff Hook
Contains the seven most s ign ificant bi ts of an 8-bit A/D repr esentat i on of
t he voltage of the input of pin D CI . The voltag e at the DC I pi n i s equal to
t he decimal valu e of LV bits [7:1] x 11 mV. For exampl e, if the value of
0100000x i s read from LV bi ts [7:1], this has a decimal value of 64,
t her efore D CI voltage equals 64 x 11 = 704 m V.
Note t hat the volt age at the DCI pin is the voltage div ided by 5 (off hook)
or 100 (on hook ) . When offhook the diode br i dge, switch saturation
vol tage, etc. s hould also be added to c al culate the voltage at tip and r i ng.
RNG 0x1A[7:0] R Resul t of Auxiliary A/D measuring t he attenuated ring voltage.
Note: 1 lsb=1.31/128=~10.23 mV; 1’s com plim ent.
E xampl e: 00100000 32 7 m V or Ring Voltage=32.7 V
Line Sensing Contro l
DET 0x03[2] R Detection of V olt age or Current Faul t
0 = None of the t hr ee conditions is detect ed.
1 = Indicates the detecti on of one of t hr ee conditions:
Under Vol tage, O ver Voltage and Over Cur r ent.
Thi s status bi t is reset wh en r ead. Th i s is a maskable interr upt. It is
enabled by the ENDET bit.
ENDET 0x05[2] W Enables Line Sensing Interrupt On Host -S ide Device
This bit cont r ols wh ether an i nterr upt i s generated bas ed upon the
det ect ion of Under Voltage, O ver Voltage and Over Current.
0 = Di sable detec tor i nterr upt (D efaul t)
1 = Enable detector int er r upt.
ENDT 0x12[1] WO Enable D etect or s On Li ne -Side Device
0 = UVD, OVD and OID c ondi ti ons are ignor ed. (D efaul t)
1 = Enables UVD, OVD and OID in the Line-Side Device and allows
t hem to be used in the Host -Side D evice.
Under-V ol tage Detection Control and Status
ENUVD 0x15[2] WO Enable Under Vol tage D etec tor On Line -Side Devic e
0 = Under Vol tage D etec tor not enabled.
1 = Under Vol tage D etec tor enabl ed. When enabl ed, t he EN N OM bit i s
t emporari l y s et to t he wide bandwid th mode if an
under-vol tage c ondi ti on detec ted to all ow fast reac qui sition of the li ne.
UVDET 0x1E[6] R Under-Vol tage Detec tor On Line-S ide Device
0 = Under Vol tage conditi on i s not detected at VPS.
1 = Under Vol tage conditi on i s detect ed at VPS.
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 77
Function
Mnemonic Register
Location Type Description
Over-Vol ta ge Detection Control and Status
ENOVD 0x15[1] WO Enable Over-Voltage Det ect or On Line -Sid e Devic e
0 = Over Volt age D etec tor not enabled.
1 = Over Volt age D etec tor enabled ( not l atc hed) . Over vol tage detector
is enabled if ENO VD, EN FE L and EN N OM all equal 1.
OVDET 0x1E[5] R Over-Voltage Detec tor On Line-Side Device
0 = Over Volt age condition is not detec ted at RGP/ R GN inputs.
1 = Over Volt age C ondi ti on i s detec ted at RGP/ RG N inputs.
OVDTH 0x13[2] WO Over-Voltage Threshold Setting
0 = Over Volt age Th r eshold i s 0. 6 Vpk at the ch ip or 60 Vp on the li ne.
1 = Over Voltage Threshold is 0.7 Vpk at the chip or 70 Vp on the li ne.
Over-Load De tection Control and Status
ENOLD 0x15[7] WO Enable Over-Load D etect or
0 = Over Load Det ect or is not enabled.
1 = Over Load Det ect or is enabl ed ( not latched ) .
OLDET 0x1E[3] R Over-Load Detec tor
0 = Ove r-Load condition is not detected.
1 = Ove r-L oad condition detec ted. As serted when the li ne voltage
exceeds 3.5 Vpk typ ical ly. OLDET is per formed p ar ti al ly in analog
domain and parti al ly in digital domain. OLD ET is ass er ted when the
delta from aux A/D between tw o consecut ive DCI samp les i s greater
tha n 76 .
Over-Curre nt De tection Control and Sta tus
ENOID 0x15[0] WO Enable Over-Cu r r ent D etec tor On Line-Sid e Devic e
0 = Ove r-Current Detect or i s not en abled. ( D efault)
1 = Ove r-Current Detect or i s enabled.
OIDET 0x1E[4] R Over-C ur rent ( I) D etect or On Line-S ide Device
0 = Ove r-Current (I) condition is not detected.
1 = Ove r-Current (I) condition is detected at the DCS pin when Loop
Cu rrent is > 125 mA if ILM=0, or > 55 mA if ILM=1.
73M1866B/73M1966B Data Sheet DS_1x66B_001
78 Rev. 1 .6
12 Loopback and Testing Modes
Figure 39 shows the six lo op back m odes available within the 73M1x66B.
TBS
DSDM
PRM SCM
MSBI LSBI
RxAFE
SinC3
Filter
Onchip
LIC
SPI
Interface
PCM
Interface
TxAFE
Interp.
Filter
Decim.
Filter
TxData
RxData
RBS
Tip
Ring
PRP SCP
TxD
RxD
CTL
STA
External
LIC
73M1906B 73M1916
Aux A/D
STA
ALB
INTLB1 DIGLB2
DIGLB1
INTLB2
RxA
TxA
PCMLB
Figure 39: Loopback Mode s Highlighted
Table 41 describes how the above control bi ts interac t to provide eac h of the six l oopback m odes.
Table 41: Loopback Modes
TEST
TMEN
DTST
LB
Loopback Mode
Mnemonic
0000 0 00 0 Normal Mode. (D efault)
No Loops
0000 0 00 1 L oopback between PC M Compander
and FXO cor e. PCMLB
0000 1 10 0
Digit al Loopback M ode
I nterpol ated TxData (TxD) is looped
back t o the D ecimated RxData input
(RxD).
DIGLB1
0000 1 11 0
Remote Analog Loopback
Rec eived R xD i s looped back as TxD
and transmitted back to the
73M1x66B
Line-S ide Device; RxD is D/A
converted to yield the analog transmit
signal (TxA).
INTLB1
0001 0 00 0
Digit al Loopback M ode
DR Tran s mit Bit Stream (TBS) is
looped bac k t o r eceive digi tal channel
and rec ei ved at DX ( DI GLB2).
DIGLB2
0010 0 00 0
Remote Analog Loopback
Rec eive anal og signal is converted to
Rec eived Bi t St r eam (RBS) and is
looped bac k t o TBS and the anal og
transm it channel (INTLB2).
INTLB2
0011 0 00 0
A nalog L oopback
The transmit DR data is connect ed to
t he r eceiver at t he anal og i nterface
and received at the DX pin (ALB).
ALB
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 79
12.1 Loopback Controls
Table 42 describes t he r egisters used for loopbac k control.
Table 42: Loopback Controls
Function
Mnemonic
Register
Location Type Description
TMEN 0x02[7] W Test Mode Enabl e
Us ed to enable the act i vation of t he tes t l oops controlled by
t he D TST bi ts ( DI GLB1 and I NTLB1).
0 = Dis ab les DTST loops .
1 = Enables DTST loops.
TMEN has to b e set t o 1 before the s etting of the DTST
bits.
DTST 0x07[1:0] W Digi tal Test Mode Sel ect
These control bi ts enable DIGLB1 and INTLB1.
P r ior to wri ti ng to these bi ts, TM EN m ust be set t o 1.
DTST1
DTST0
Sel ected T es t Mo de
0 0 Normal (Default )
1 0 DIGLB1
1 1 INTLB1
LB 0x24[0] W Loopback
0 = Di sables P CM Loopback.
1 = Enables PCM Loopback within the Host-S ide Devic e.
TEST 0x18[7:4] W This four-bi t fiel d i s us ed to enable the loopback m ode per the
following table:
TEST
Loopback Mode
0000
Normal Mode. (D efault)
Transmi t and receive channel s are independent.
0001
Digit al Loopback M ode.
DR Tran s mit Bit Stream (TBS) i s looped back to
rec eive dig it al channel and received at DX ( DI GLB2).
0010 Remot e Anal og Loopback.
Rec eive anal og signal is converted to R eceived Bi t
S tream (RBS) and i s looped back to TBS and the
analog trans mit channel (INTLB2 ) .
0011 Analog Loopback.
The transmit DR data is connect ed to the rec eiver at
t he anal og i nterface and rec eived at the DX pin
(ALB).
73M1866B/73M1966B Data Sheet DS_1x66B_001
80 Rev. 1 .6
13 Performance
Thi s section provides an overview of typical performanc e charac teri stic s measured using 73M1x66B
producti on devices on a Teridi an R eference Board. The measurements wer e made usi ng a Wand el and
Goltermann PCM-4 tes t unit. The t est s c onform to ITU-T Recommendation G.712 (2001). For more
information, see t he 73M 1966B Per formance Ch ar acteri z ation.
13.1 Transmit
Figure 40 pr ovides performanc e charac teristics for transmit gain track i ng.
Figure 40: Variation of Transmi t Gain Digital Input to Analog Output at the Li ne
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 81
Figure 41 pr ovides performanc e charac teristics for r eceive gain variation agai nst freq uency.
Figure 41: Gain versus Frequency for Digita l I nput to Analog Output at the Line
Figure 42 pr ovides performanc e charac teristics for di st ort i on i n the di r ect i on of the digi tal por t to analog port.
Figure 42: Signal to Tota l Distortion versus Input Level for Digital Input to Analog Output to the Line
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 83
Figure 44 pr ovides performanc e charac teristics for gai n variati on agai nst frequency.
Figure 44: Gain versus Frequency for Analog I nput at the Li ne to the Di gital DX Output
Figure 45 pr ovides performanc e charac teristics for di st or ti on i n the dir ection of t he anal og por t to digital
port.
Figure 45: Signal to Tota l Distortion versus Input Level for Analog at the Line to the Digital DX Output
73M1866B/73M1966B Data Sheet DS_1x66B_001
84 Rev. 1 .6
Figure 46: Return Loss, @ 80 mA
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 85
14 Pack age Lay o ut
Figure 47: 20-Pin TSSOP Package Dimensions
2.5
5
2.5
5
TOP VIEW
1
2
3
0.2 MIN.
0.35 / 0.45
1.5 / 1.875
3.0 / 3.75
0.18 / 0.3
BOTTOM VIEW
1
2
3
0.25
0.5
0.5
0.25
3.0 / 3.75
1.5 / 1.875
0.35 / 0.45
CHAMFERED
0.30
Figure 48: 32-Pin QFN Package Dimensions
0.85 NOM.
/
0.9MAX. 0.00 / 0.005
0.20 REF.
SEATING
PLANE
SIDE VIEW
73M1866B/73M1966B Data Sheet DS_1x66B_001
86 Rev. 1 .6
Figure 49: 42-Pin QFN Package Dimensions
DS_1x66B_001 73M1 866B/73M1966B Data Sheet
Rev. 1.6 87
15 Ordering Information
Table 43 lists the order numbers and packagin g mark s used to identify 73M1x66B products.
Table 43: Order Numbers and Packaging Ma rks
Part Description
Order Number
Packaging Ma r k
Host/Line
73M1966B 32-Pin QFN, Lead free 73M1966B-IM/F 73M1916A-M
73M1906B Line-Side I C
Host-Side IC
73M1966B 32-Pin QFN, Lead free,
Tape and Reel
73M1966B-IMR/F
73M1916A-M
73M1906B
Line-Side IC
Host-Side IC
73M1966B 20-Pin TSSOP, Lead free 73M1966B-IVT/F 73M1916AVT
73M1906BVT Line-Side I C
Host -Si de IC
73M1966B 20-Pin TS SOP, Lead free,
Tape and Reel 73M1966B-IVTR/F 73M1916AVT
73M1906BVT Line-Side I C
Host -Si de IC
73M1866B 42-Pin QF N, Lead free 73M1866B-IM/F 73M1866B-IM
73M1866B 42-Pin QF N, Lead free,
Tape and Reel 73M1866B-IMR/F 73M1866B-IM
16 Contact Information
For more informat i on about Teridian Semiconduct or pr oduct s or to c heck the availabi lity of the
73M1966B, cont act us at :
6440 Oak Canyon Road
Suite 100
I r vine, CA 92618-5201
Telephone: (714) 508-8800
FAX : (71 4) 50 8-8878
Email: fxo.support@teridian.com
For a compl ete list of worldwid e sales of fices , go to http://www.teridian.com.
73M1866B/73M1966B Data Sheet DS_1x66B_001
88 Rev. 1 .6
Rev isi on Histor y
Revision Date Description
1.0 11/7/2007 First publication.
1.1 5/13/2008
1.2 7/30/2008
1.3 11/17/2008
1.4 7/21/2009
1.5
10/16/2009
1.6 4/2/2010 Replaced Table 16 wit h a new table.
Replaced th e sc hem atics i n Figure 12 and Figure 13 with new schematics.
Mov ed the s teps to enabl e the c al ibration of rec eive DC offset from Sec ti on
8. 8.3 to t he 73M1866B/73M1966B Implementer’s Guide.
Corr ect ed the T ypes ( R, W, WO) in Table 32.
Rewrote the descr i ption of the ADJ bit.
A dded clar i fi cat ion t o the des cri ption of the PLDM bit.
A dded clar i fi cat ion t o the des cri ption of the RGDT bit .
Teridian Semiconduc tor C or por ation is a r egi stered t r ademark of Teridian Semic onduct or Corporation.
S impli fying System Int egr ation i s a trademark of Teridian Semiconductor C or por ation.
MicroDAA i s a registered t r ademark of T er i dian S emic onductor Cor porati on.
A ll other trademar ks ar e the proper ty of their r espec tive owners.
Teridian Semiconduc tor C or por ation makes no warran ty fo r the us e of its products, other than expressl y
contained i n the C om pany’s warranty d etailed in the Teridian Semi conductor Corporation st andar d Terms
and Conditions. Th e company assumes no respons ib i lity for any error s whi ch may ap pear in thi s
documen t, reserves the right to change devices or specificati ons det ai led herein at any ti me without
not i ce and does not m ake any commitment to update the information cont ained herein. Accordin gl y, the
reader i s cauti oned to verify that th is document is curr ent by com par i ng i t to the latest vers ion on
http://www.teridian.com or by checki ng with your sales represent ati ve.
Teridian Semiconduc tor C or p., 6440 Oak Can yon, S uit e 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
