2N6107G - ON Semiconductor

October, 2011 − Rev. 9

1Publication Order Number:

2N6107/D

PNP - 2N6107, 2N6109,

2N6111; NPN - 2N6288,

2N6292

Complementary Silicon

Plastic Power Transistors

These devices are designed for use in general−purpose amplifier and

switching applications.

Features

•DC Current Gain Specified to 7.0 Amperes

hFE = 30−150 @ IC

= 3.0 Adc − 2N6111, 2N6288

= 2.3 (Min) @ IC = 7.0 Adc − All Devices

•Collector−Emitter Sustaining Voltage −

VCEO(sus) = 30 Vdc (Min) − 2N6111, 2N6288

= 50 Vdc (Min) − 2N6109

= 70 Vdc (Min) − 2N6107, 2N6292

•High Current Gain − Bandwidth Product

fT= 4.0 MHz (Min) @ IC = 500 mAdc − 2N6288, 90, 92

= 10 MHz (Min) @ IC = 500 mAdc − 2N6107, 09, 11

•TO−220AB Compact Package

•Pb−Free Packages are Available*

MAXIMUM RATINGS (Note 1)

Rating Symbol Value Unit

Collector−Emitter Voltage

2N6111, 2N6288

2N6109

2N6107, 2N6292

VCEO 30

Vdc

Collector−Base Voltage

2N6111, 2N6288

2N6109

2N6107, 2N6292

VCB 40

Vdc

Emitter−Base Voltage VEB 5.0 Vdc

Collector Current − Continuous

− Peak

IC7.0

Adc

Base Current IB3.0 Adc

Total Power Dissipation @ TC = 25_C

Derate above 25_C

PD40

0.32

W/°C

Operating and Storage Junction

Temperature Range

TJ, Tstg −65 to +150 °C

THERMAL CHARACTERISTICS

Characteristics Symbol Max Unit

Thermal Resistance, Junction−to−Case RqJC 3.125 _C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Indicates JEDEC Registered Data.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

7 AMPERE

POWER TRANSISTORS

COMPLEMENTARY SILICON

30 − 50 − 70 VOLTS, 40 WATTS

TO−220AB

CASE 221A

STYLE 1

123

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MARKING

DIAGRAM

2N6xxxG

AYWW

2N6xxx = Specific Device Code

xxx = See Table on Page 4

G = Pb−Free Package

A = Assembly Location

Y = Year

WW = Work Week

See detailed ordering, marking, and shipping information in

the package dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

PNP − 2N6107, 2N6109, 2N6111; NPN − 2N6288, 2N6292

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00 20 40 60 80 100 120 160

Figure 1. Power Derating

TC, CASE TEMPERATURE (°C)

PD, POWER DISSIPATION (WATTS)

140

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted) (Note 2)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

OFF CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector−Emitter Sustaining Voltage (Note 3)

(IC = 100 mAdc, IB = 0) 2N6111, 2N6288

2N6109

2N6107, 2N6292

ÎÎÎÎÎ

VCEO(sus)

ÎÎÎ

ÎÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector Cutoff Current

(VCE = 20 Vdc, IB = 0) 2N6111, 2N6288

(VCE = 40 Vdc, IB = 0) 2N6109

(VCE = 60 Vdc, IB = 0) 2N6107, 2N6292

ÎÎÎÎÎ

ICEO

ÎÎÎ

−

ÎÎÎÎ

1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector Cutoff Current

(VCE = 40 Vdc, VEB(off) = 1.5 Vdc) 2N6111, 2N6288

(VCE = 60 Vdc, VEB(off) = 1.5 Vdc) 2N6109

(VCE = 80 Vdc, VEB(off) = 1.5 Vdc) 2N6107, 2N6292

(VCE = 30 Vdc, VEB(off) = 1.5 Vdc, TC = 150_C) 2N6111, 2N6288

(VCE = 50 Vdc, VEB(off) = 1.5 Vdc, TC = 150_C) 2N6109

(VCE = 70 Vdc, VEB(off) = 1.5 Vdc, TC = 150_C) 2N6107, 2N6292

ÎÎÎÎÎ

ICEX

ÎÎÎ

−

ÎÎÎÎ

100

2.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Emitter Cutoff Current (VBE = 5.0 Vdc, IC = 0)

ÎÎÎÎÎ

IEBO

ÎÎÎ

−

ÎÎÎÎ

1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ON CHARACTERISTICS (Note 3)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current Gain

(IC = 2.0 Adc, VCE = 4.0 Vdc) 2N6107, 2N6292

(IC = 2.5 Adc, VCE = 4.0 Vdc) 2N6109

(IC = 3.0 Adc, VCE = 4.0 Vdc) 2N6111, 2N6288

(IC = 7.0 Adc, VCE = 4.0 Vdc) All Devices

ÎÎÎÎÎ

hFE

ÎÎÎ

2.3

ÎÎÎÎ

150

−

ÎÎÎ

−

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector−Emitter Saturation Voltage (IC = 7.0 Adc, IB = 3.0 Adc)

ÎÎÎÎÎ

VCE(sat)

ÎÎÎ

−

ÎÎÎÎ

3.5

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Base−Emitter On Voltage (IC = 7.0 Adc, VCE = 4.0 Vdc)

ÎÎÎÎÎ

VBE(on)

ÎÎÎ

−

ÎÎÎÎ

3.0

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DYNAMIC CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Current Gain — Bandwidth Product (Note 4)

(IC = 500 mAdc, VCE = 4.0 Vdc, ftest = 1.0 MHz) 2N6288, 92

2N6107, 09, 11

ÎÎÎÎÎ

ÎÎÎ

4.0

ÎÎÎÎ

−

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Capacitance (VCB = 10 Vdc, IE = 0, f = 1.0 MHz)

ÎÎÎÎÎ

Cob

ÎÎÎ

−

ÎÎÎÎ

250

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Small−Signal Current Gain (IC = 0.5 Adc, VCE = 4.0 Vdc, f = 50 kHz)

ÎÎÎÎÎ

hfe

ÎÎÎ

ÎÎÎÎ

−

ÎÎÎ

−

2. Indicates JEDEC Registered Data.

3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.

4. fT = |hfe| • ftest

PNP − 2N6107, 2N6109, 2N6111; NPN − 2N6288, 2N6292

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Figure 2. Switching Time Test Circuit

+11 V

25 ms

-9.0 V

-4 V

SCOPE

VCC

+30 V

tr, tf ≤ 10 ns

DUTY CYCLE = 1.0%

D1 MUST BE FAST RECOVERY TYPE, eg:

1N5825 USED ABOVE IB ≈ 100 mA

MSD6100 USED BELOW IB ≈ 100 mA

RB and RC ARE VARIED TO OBTAIN DESIRED CURRENT LEVELS

2.0

0.07

Figure 3. Turn−On Time

IC, COLLECTOR CURRENT (AMP)

1.0

0.7

0.5

0.3

0.2

0.1

0.02 0.1 0.2 0.3 0.5 2.0 3.0 7.0

TJ = 25°C

VCC = 30 V

IC/IB = 10

0.05

t, TIME (s)μ

1.0 5.0

td @ VBE(off) ≈ 5.0 V

0.07

0.03

Figure 4. Thermal Response

t, TIME (ms)

1.0

0.01

0.5

0.2

0.1

0.05

0.02

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.05 1.0 2.0 5.0 10 20 50 100 200 1.0 k500

ZqJC(t) = r(t) RqJC

RqJC = 3.125°C/W MAX

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) - TC = P(pk) ZqJC(t)

P(pk)

DUTY CYCLE, D = t1/t2

D = 0.5

0.2

0.05

0.02

0.01

SINGLE PULSE

0.1

0.7

0.3

0.07

0.03

0.02 0.1 0.50.2

PNP − 2N6107, 2N6109, 2N6111; NPN − 2N6288, 2N6292

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1.0

Figure 5. Active−Region Safe Operating Area

VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)

7.0

5.0

2.0

0.15 5.0 10

CURRENT LIMIT

SECONDARY

BREAKDOWN LIMIT

THERMAL LIMIT

@ TC = 25°C (SINGLE PULSE)

7.0

IC,

LLE

URRENT (AMP

)

0.1 ms

1.0

0.5

0.2

0.3

2.0 3.0

0.5 ms

20 30 50 70 100

3.0

0.7

0.1

5.0 ms

There are two limitations on the power handling ability of

a transistor: average junction temperature and second

breakdown. Safe operating area curves indicate IC − VCE

limits of the transistor that must be observed for reliable

operation; i.e., the transistor must not be subjected to greater

dissipation than the curves indicate.

The data of Figure 5 is based on TJ(pk) = 150_C; TC is

variable depending on conditions. Second breakdown

pulse limits are valid for duty cycles to 10% provided

TJ(pk) v 150_C. TJ(pk) may be calculated from the data in

Figure 4. At high case temperatures, thermal limitations will

reduce the power that can be handled to values less than the

limitations imposed by second breakdown.

300

0.5

VR, REVERSE VOLTAGE (VOLTS)

30 3.0 5.0 501.0 2.0

C, CAPACITANCE (pF)

200

TJ = 25°C

Cib

100

Figure 6. Turn−Off Time

10 20 30

5.0

0.07

Figure 7. Capacitance

IC, COLLECTOR CURRENT (AMP)

3.0

2.0

1.0

0.7

0.5

0.3

0.05 0.1 0.2 0.3 0.5 2.0 3.0 7.0

TJ = 25°C

VCC = 30 V

IC/IB = 10

IB1 = IB2

0.1

t, TIME (s)μ

1.0 5.0

0.2

0.07

Cob

ORDERING INFORMATION

Device Device Marking Package Shipping

2N6107

TO−220AB

50 Units / Rail

2N6107G TO−220AB

(Pb−Free)

2N6109

TO−220AB

50 Units / Rail

2N6109G TO−220AB

(Pb−Free)

2N6111

TO−220AB

50 Units / Rail

2N6111G TO−220AB

(Pb−Free)

2N6288

TO−220AB

50 Units / Rail

2N6288G TO−220AB

(Pb−Free)

2N6292

TO−220AB

50 Units / Rail

2N6292G TO−220AB

(Pb−Free)

PNP − 2N6107, 2N6109, 2N6111; NPN − 2N6288, 2N6292

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PACKAGE DIMENSIONS

TO−220

CASE 221A−09

ISSUE AG

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE

ALLOWED.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.570 0.620 14.48 15.75

B0.380 0.405 9.66 10.28

C0.160 0.190 4.07 4.82

D0.025 0.036 0.64 0.91

F0.142 0.161 3.61 4.09

G0.095 0.105 2.42 2.66

H0.110 0.161 2.80 4.10

J0.014 0.025 0.36 0.64

K0.500 0.562 12.70 14.27

L0.045 0.060 1.15 1.52

N0.190 0.210 4.83 5.33

Q0.100 0.120 2.54 3.04

R0.080 0.110 2.04 2.79

S0.045 0.055 1.15 1.39

T0.235 0.255 5.97 6.47

U0.000 0.050 0.00 1.27

V0.045 --- 1.15 ---

Z--- 0.080 --- 2.04

123

SEATING

PLANE

−T−

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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2N6107/D

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