SONY CXA1396D/K/P 8-bit 125 MSPS Flash A/D Converter Description The CXA1396D/K/P are 8-bit ultrahigh-speed flash A/D converter ICs capable of digitizing analog signals at the maximum rate of 125 MSPS. The digital /O levels of these A/D converters are compatible with the ECL 100K/10KH/10K. The CXA1396D/P is pin-compatible with the earlier model CX20116, and the CXA1396K with the CXATO66K. They can replace the earlier models respectively, without any design changes, in most cases. Compared with the earlier models, these new models have been greatly improved in performance, by. incorporating advanced process, new circuit design and carefully considered layout. Features ; * Ultrahigh-speed operation with maximum conversion rate of 125 MSPS (Min.) * Wide analog input bandwidth: 200MHz (Min. for full-scale input) * Low Power consumption: 870mW (Typ.) * Single power supply: -5.2V * Low input capacitance * Built-in integral linearity compensation circuit * Low error rata * Operable at 50% clock duty cycle * Good temperature charactcristics * Capable of driving 50Q loads Pin Configuration Pins without name are NC pins (not connected). CXA1I9ODYP (Top View) CXA1396K 68 pin LCC (Ceramic) CXA1396D 42 pin DIP (Ceramic) Gi <> CXA1396P 42 pin DIP (Plastic) Structure Bipolar silicon monolithic IC Applications * Digital oscilloscopes * HOTY (high-definition TVs) * Other apparatus requiring ultrahigh-speed A/D conversion oo 0 = asdages 43 BRRIGRS sl AVEE [62 427 AVEE Avee [63 417 AVee Ver Fes 397 Vre Aves [67 68 ut CKA1306K 357 CuK Ci UNV FS tk 327 MINV OVee [5 307 OVEE DGNCGt [7 DGND2 Fe Ye sesreses ax BaRBABRS 23 g g 8 (Top View) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices, Sony cannot assume responsibility for any problems arising out of the use of these circuits. 1- E94521STSONY CXA1396D/K/P Absolute Maximum Ratings (Ta=25C) * Supply voltage AVEE, DVEE ~7 10 +0.5 * Analog Input voltage VIN 2.7 to +0.5 * Reference input voltage VrT, VrRe, VRM -2.7 to +0.5 | VaTVae | 2.5 Digital input voltage CLK, CLK, MINV, LINV 4 to +0.5 | CLKCLK | 2.7 * Vam pin input curent IVRM ~3 to +3 * Digital output current IDo to IDr 30 to 0 * Storage temperature Tstg ~65 to +150 Recommended Operating Conditions Min. Typ. * Supply voltage AVee, DVEE -5.5 -5.2 AVee - DVEE -0.05 0 AGNDDGND -0.05 0 * Reference input voltage VAT ~0.1 0 VAB -2.2 -2.0 * Analog Input voltage VIN VRB * Pulse width of clock Tew 4.0 Tpwo 4.0 * Operating temperature Ta (CXA1396D/P) -20 Te (CXA1396K) -20 <<< << < mA mA c Max. -4.95 +0.05 +0.05 +0.1 -1.8 VAT +75 +100 unit <<a ac <SONY CXA1396D/K/P Block Diagram MINV VAT Comparator /2 mp D7 (MSB} D VIN D5 D4 5 be a VRM Ww 5 9 De wi DI DO (LSB) VIN VRB CLK CLOCK CLK DRIVER LINVSONY CXA1396D/K/P Pin Description and I/O pin Equivalent circuit Pin No. Symbol! 0 Standard E D mbo voltage uivalent circuit escription DIP Loc y level 4 P Analog GND. Used as GND for input 29, 31, | 49, 51, _ buffers and tatches of 33, 35 | 53,55 | AGND ov comparators. Isolated from DGND1, DGND2. Analog VEE -5.2V (Typ.). Internally connected with DVEE (resistance: 4 to 6). A ceramic chip capacitor of at least 0.1uF should be used to connect to AGND and be placed near the pins. 21 | 35 | CLK IT CLK input _ r rx A | Input complementary 1,25, | 41, 42, 26, 38, | 62,63,} AVeE - -5.2V 39 67 CK Yat to CLK, uv By With open connection, I ECL CLK Ny kept at threshold W K voltage (-1.3V). Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain the stable high-speed operation. 20 a4 CLK ia Digital GND for internal circuits Digital GND for output transistors Digital Vee Intemally connected with AVEE (resistance:4 to 622) 4,17 | 5,30 | DVee ~ -5.2V Aceramic chip capacitor of at least 0.ipF should be used to connect to DGNB and be placed near the pins. 5,16 | 7,24 |IDGND1]| OV 6,15 | 8,23 |DGND2| OVSONY CXA1396D/K/P Pin No, DIP LCC Symbol VO Standard voltage level Equivalent circuit Description 14 DO 15 D1 16 D2 10 17 D3 11 18 D4 12 19 DS 13 20 D6 14 21 D7 ECL DGND2 DVEE LSB of data outputs. External pull-down resistor is required. Data outputs. External pull-down resistors are required. MSB of data outputs. External pull-down resistor is required. LINV ECL 18 32 MINV ECL DGND1 1.3V of Input pin for DO (LSB) to D6 output polarity inversion (see output code table). With open connection, kept at "L" level. tnput pin for D7(MSB) output polarity inversion (see output code table). With open connection, kept at "L" level. 30, 34 50, 54 VIN VAT to Vrs AGND VIN o VIN Wk OO 7X Avec | Analog input pins. These two pins must be connected externally, since they are not internally connected, See Application Note for precautions.SONY CXA1396D/K/P Pin No. - DIP LOG Symbol VO Standard voltage level Equivalent circuit Description 23 39 VRB -2V 32 52 Vam Vas/2 41 65 VAT ov Vat mM 42 Comparator Comparator WW -- = t Comparator = Comparator Vram oife A_eAA r Comparator r Comparator Comparator VAB org 72 127 128 129 130 255 Reference voltage (bottom) Typically -2V A ceramic capacitor of at least 0.1,.F and a tantalus capacitor of at least 10uF should be used to connect to AGND and be placed near the pins. Reference voltage mid point Can be used as a pin for integral linearity compensation. Reference voltage (top) Typically OV When a voltage different from AGND is applied to this pin, a ceramic capacitor of at least O.1uF anda tantalus capacitor of at least 10:F should be used to connect to AGND and be placed near the pins. 1,2, 4, 6, 9 to 13, 22, 25 to 29, 31, 33, 36 to 38, 40, 43 to 48, 56 to 61, 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 NC 66,68 Unused pins No internal connections have been made to these pins. Connecting them to AGND or DGND on PC board is recommended.SONY CXA1396DIYP Electrical Characteristics (CXA1396D/K) (Ta=25'C , AVee=DVeE=5.2V, VaT=OV, VrRB=2V) Item Symbol Condition Min. Typ. Max. | Unit. Resolution n 8 bits DC characteristics Integral linearity error EI Fe=125MSPS 40.3 | +0.5.] LSB Differential linearity error | Eo Fo=125MSPS 40.3 |; +0.5 | LSB Analog input Analog input capacitance | Cin Vin=-1V+0.07Vrms 17 pF Analog input resistance | Rin 190 ko Input bias current lin ViIN=-1V 130 320 HA Reference inputs Reference resistance RREF 75 110 155 Q Offset voltage Vat Eor 8 19 32 mV VRB Eos 0 15 a4 mV Digital inputs . Logic H level Vin -1.13 Vv Logic L level VIL 1.50 Vv Logic H current he Input connected to -0.8V 0 50 HA Logic L current Ite Input connected to -1.6V -50 50 HA Input capacitance 7 pF Switching characteristics Maximum conversion rate | Fc Error rate 10-8 TPS*! 125 MSPS Aperture jitter Taj 10 ps Sampling delay Tds 1.5 ns Output delay Tdo 3.0 3.6 4.2 ns H pulse width of clock Tews 4.0 ns L pulse width of clock TPwo 4.0 ns Digital outputs Logic H level VoH RL=50Q to -2V ~-1.10 Vv Logic L level VoL RL=502 to -2V ~1.62 Vv Output rising time Tr Ri=5022 to -2V, 20% to 80% 0.8 ns Output falling time Tf RL=5022 to -2V, 80% to 20% 1.0 ns Dynamic characteristics Input bandwidth Vin=2Vp-p 200 MHz S/N ratio Input=1MHz, FS 46 dB Clock=125MHz Input=31.5MHz, FS 40 dB Clock=125MHz Error rate Input=31.249MHz, FS Error> 16LSB 10 |TPS*! Clock=125MHz Differential gain error DG NTSC 40IRE mod.ramp, 1.0 %e Differential phase error | DP Fo=125MSPS 0.5 deg Power supply Supply current IgE -230 | 160 mA Power consumption*2 Pd 870 mW *1 TPS: times Per Sample (VATVaB)? *2 Pd=lee + Veet RAEESONY CXA1396D/K/P Electrical Characteristics (CXA1396P) (Ta=25'C , AVee=DVee=-5.2V, VaT=0V, VaB=-2V) Item Symbol Condition Min. Typ. Max. | Unit Resolution n 8 bits DC characteristics Integral linearity error Ett Fe=125MSPS +0.8 | LSB Differential linearity error | Eor Fe=125MSPS +0.7 | LSB Analog input Analog input capacitance | Cin Vin=-1V+0.07Vrms 18 pF Analog input resistance | RIN 50 190 kQ Input bias current JIN Vin=-1V 20 130 400 pA Reference inputs Reference resistance RREF 75 110 155 Q Offset voltage Vat Eor 8 17 32 mv VRB Eos 0 9 24 mV Digital inputs ; Logic H level VIH 1.13 Vv Logic L level ViL -1.50 Vv Logic H current IIH Input connected to -0.8V 0 50 pA Logic L current lie Input connected to -1.6V -50 50 HA Input capacitance 7 pF Switching characteristics Maximum conversion rate | Fc Error rate 10-* TPS*1 125 MSPS Aperture jitter Taj 10 ps Sampling delay Tds 0.3 1.5 3.0 ns Output delay Tdo Ri=502 to -2V 3.0 3.6 4.2 ns H pulse width of clock Tew 3.8 ns L pulse width of clock TPwo 3.8 ns Digital outputs Logic H level VoH Ri=502 to -2V 1.10 Vv Logic L level VoL RL=502 to -2V ~1.62 Vv Output rising time Tr RL=502 to ~2V, 20% to 80% 0.5 0.9 12 ns Output falling time Tf RL=502 to -2V, 80% to 20% 0.5 1.0 1.3 ns Dynamic characteristics Input bandwidth VIN=2Vp-p 200 Mrz S/N ratio Input=1MHz, FS 46 dB Clock=125MHz Input=31.5MHz, FS 40 dB Clock=125MHz Input=31.249MHz, FS Error rate Error>16LSB 10-9 | TPS" Clock=125MHz Differential gain error DG NTSC 40IRE mod.ramp, 1.0 % Differential phase error DP Fco=125MSPS 0.5 deg Power supply Supply current lee -230 | -160 mA Power consumption*? Pd 870 mw *1 TPS: times Per Sample (VaTVaB)? *2 Pd=lee: VEE+ RAEESONY CXAIS96D/K/P Output Code Table MINV 1 0 1 0 D7? DO | D7 DO D? DO | D7 DO ov 000-00 10000 O1ter 41 T1 dere 11 0 000-00 100800 Oder 41 11 deve 11 1 O00 04 100-01 OT dre 10 T1110 ~1V 127 OL dere 14 Titer 11 000-00 100+" 00 128 100-00 000-00 tte Ofte 11 254 11d 10 O11 10 10004 000-01 255 D1 dee 11 Otten 11 10000 000-00 eV TA dre 11 011 14 100-00 000% 00 *VaT=0V, VaAB=-2V Timing diagram NN Tds N Analog In __. _ , 80% 80% KS nbd Digital out x N-1 209X N X 20% " Tdo >t Tr < TrSONY CXA1396D/K/P Electrical Characteristics Test Circuit Maximum conversion rate test circuit Signal Vin CXAI396 8 | ECL Source D/K/P 7) Lateh p| Comparator Pulse A>B Counter TAM tke CLK CLK ECL | Latch 2Vp-p Sin Wave DATA 16 Signal 174 Source foLk Differential gain error test circuit Differential phase error test circuit {(CX20202A-1) vin 7 OUT | 8 ec. | & 10bit CXA1396 |- Lateh 7 D/A ioQ | D/K/P CLK| | CiK NTSG Signal / Source i Delay = i VeB SG (CW) . : Vector Scope 50 DG. DP Integral linearity error test circuit Differential linearity error test circuit 2 - 2 were ny { St IA<B:ION AS! | $2: A>B: ON +; ' 17 > 1 A<BA>B Comparator DUT 8 8 VIN | exat396 [> . i A| Butter D/K/P AL Bt AQ BO }+ y t 9 qe DVM a* on000000 t CLK (125MHz) to Controller 14111110SONY CXAT396D/K/P Power Supply Current Test Circult Analog input bias current test circuit if 1 D6 2 I 2 41 AS bn 3 40 4 '39) 5 38 6 37 7 36, 8 36 8 34 10, 33 11) cxarsseD/p (2 12 at 13 a0 14 15. 268 16 27, 17 26, 15 25 419 24 20 2 a ~2V 21 22 A) TEE 5.2 Sampling delay test circuit Aperture jitter test circuit 67.5MHz Amp Osc : Variable r VIN cxaizas | 8 | Logic f Analizer CLK D/K/P 1024 osce2 samples ECL Buffer 67.5MHz S.2V CXALISGK Aperture jitter test method &v At 4 CLK fff Apertura jitter 129 128 127 126 125 Apeature jitter is defined as follows: Av At Taj= 0 / =o / (3 X2al) , a (LSB) Where @ (unit: LSB) Is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point.SONY CXAIZ96D/K/P 8bit, 125MSPS ADC Evaluation board Description The CXA1396D/P EVALUATION BOARD WITH DAC is a tool for customers to evaluate the performance of the CXA1396D/P (8bit, 125MSPS, high-speed A/D converter). In addition to indispensable features such as the reference voltage generator, this tool equips two sets of analog inputs (the direct input and the buffer amplifier input), the input voltage offset generator, the clock decimator, the output data latches, the 10-bit high- speed DAC, and the 20-pin cable connector for digital outputs. This evaluation board provides full performance of the CXA1396D/P and it is designed to facilitate evaluation. Features * Resolution: 8bits Maximum conversion rate: 125MSPS * Supply voltage: +5.0V, ~5.2V, -2,0V * Two analog inputs (Direct input, buffer amplifier input) * Clock level converter: Sine wave to ECL level signal * Reference voltage adjustment circuit for the A/D converter * Built-in clock frequency decimation circuit: (1/1 to 1/16) Fig. 1. Block Diagram ~5.2V (A) H L Veo VRB (2k) 2v r Swi f sw2 5.2V (A) DIGITAL OUT (CONNECTOR) Vas Vin LINV MINV (2k) OFFSET Vere (D? te Do) 8 DATA [g a VRM | LATCH +4 BUFFER 7 CXA1396D/P r ] CLK AMP. IN Vin CLK _ __ (Dr te Do) 4 & 2 (CLK.CLK) 51 DIR.IN O.1 py PN BK. D/A CLK Ik LY DECIMATOR > CONVERTER} o pa QUT cLK 1/1to 1/46 +5 5.2V (A) AGND 5.2V (D) DGND 2 (D)SONY CXA1396D/K/P Supply Current ltem Min. Typ. Max. Unit ~.2V 0.85 1.0 A +5.0V 15 30 mA -2.0V 0.45 0.6 A (Note: Supply current -2.0V is the value when Rn10, Rn1t and An12 are net mounted.) Analog Input (DIR. IN, AMP. IN) item Min. Typ. Max. Unit Input voltage (DIR. IN) -2.0 0 Vv (AMP. IN) *# -0.5 +0.5 Vv Input impedance 50 Q (*1: Adjustable by VR1) Clock Input (CLK) Item Min. Typ. Max. Unit Input voltage 1.0 Vp-p (Peak to Peak) Input impedance 50 Q Digital Output (DO to D7) ECL 10kH level Clock Output ECL 10kH level, complementary output Output Code Table MINV 0 0 1 1 LINV 0 1 0 1 OV 1 panees 11 100 enenne oo 011 paneue 11 000 weeeee oo 1 1 1 eeenee 1 0 1 0 0 seeeee 0 1 0 1 1 weaves 1 0 0 0 0 weaene 0 1 Vin 100-00 Td free 11 000-700 OL dere 11 Older tt 000-00 T1iceed4 400-00 O00---- 01 Oder 10 TOG ss 01 111: 10 -2V O00--- 00 OD des 11 TO00-- 00 P11 11SONY CXA1S96D/K/P Fig. 2. Timing Chart A/Dinput pin Vin (DIR. IN, AMP, IN) PCB Input pin CLK CLK A/Dclock CLK A/Doutputl D7~DO PCB output pin D7 to BO (For 7/1 traquency division) CLIN PCB output pin CLK (For 1/1 frequency division} PCB output pin. DATA OUT (For 1/2 trequency division) CLKN PCB output pin CLK (For 1/2 trequancy division) ee Toh 1.8ns (Typ) Adjustment Methods and Notes on Operation 1) 2) 3) Vin Offset (VR1) bene renee eee The volume to adjust the signal range (OV center assumed) with the A/D converter input range when a waveform is input through AMP. IN. A/D Full Scale (VR2) The volume to adjust A/D converter VRB voltage. Linearity (VR3) The volume to adjust VRM (linearity) voltage. D/A Full Scale (VR4) The volume to adjust D/A output full scale (-1V)SONY CXA1396D/K/P 5) J1 (Input selection) A: Shorts to adjust VRM voltage. B: Shorts to supply DC voltage to Vin. C: Shorts to select AMP.IN input. D: Shorts to select DIR.IN input. [Jumper Position at shipment] Jt AOO BOO COO DOO 6) Swi The switch for LINV High/Low 7) SWe2 The switch for MINV High/Low 8) SWS (Decimation) The switch to select clock frequency decimation. Switch position: decimation ratio o:1/1 1:1/2 2: 1/4 3: 1/8 4: 1/16 9) SW4 (D/A INV) The switch for D/A converter output inversion. 10) Rni0, Ani1 and Rni2 are not mounted at shipment. They are not required during evaluation.SONY CXA1396D/K/P 11) Waveform probe pins P5 and P8 through P28 are devised to facilitate GND connection in order to reduce the distortion. As shown in the diagram below, the distance between the probe point and the GND is 300 mils, and there is 1.2mm throughhole at each. The signal and GND locations are suit for a Tektronix GND tip (part number 013-1185-00). epee GND ~ Probe point 300mil Fig. 3 12) D/A converter (C13) input data (waveform probe pins P21 through P28) are the complementary signals of the decimated A/D converter outputs. Those are inverted again in the D/A converter so that the direction of reproduced waveform can agree with the A/D input signal converter. 13) The part unmber of the digita! output connector is KEL. 8830E-020-170S. A corresponding connector and cable assembly is JUNKOSMA KBOO20MCGS5O0BI.SONY PCB Circuit Schematic FERRITE BEAD cs ia 5.2V (Al AGND 52 (0) Ove +5 (A) cr Ty AGND 5 a es : CXA1I960,/P AMPIN AGND e 8.2V (A) AGNDAGND DIRLIN cw ip C16 ate FERRITE BEAD < 8 TOTES CUK KS R 8 8 R bo 2 wT cio Oty fC =CXA1396D/AGP =2 {0} CONNECTOR WEL BBI0E-020- 1705. (TOP VIEW NO E qaio1 10H 76 g oF os 1 rE wiz 2 DIGITAL OUT esi Bip 2 (0) DGND Pay CAY +5 (A) Seg AGNO > 0 AaGAD AGND E E Z g 0} z 5 i614: toH10T 3 0C9 2 1OH178 z E Z a 5 g AGAD cx au h.2 CA) 7 OHNe Lo cu D/ACUT Of, OGNO s.2V (D) $wi Decimation AGNO Swap OGNO D/AWY 1. 7 DGND cae \nSONY CXA1396D/K/P Characteristic Graph Gain (dB) SNR (dB) 2nd, 3rd Harmonic Distortion (dB) Galn vs. Input Frequency (CLK=125MHz) 4 IN : \ 8 10 10 100 Input Frequency (MHz) SNA vs. Input Frequency 50 (CLK=125MHz) = DIR. IN Eee AMP. IN 45 TPS 40 Ne XK 35 NA WN NN 30 \ 25 N\ 20 1 19 100 Input Frequency (MHz) 2nd, 3rd Harmonic Distortion vs. Input Frequency (CLK=125MHz} 2nd OIF. IN 2nd AMP. sees 3rd DIR. IN ~-- 3rd AMP. IN 10 100 Input Frequency (MHz)SONY CXA1396DAGP Parts Layout cLK sav lat) aqua] =s2v0) es2viod 9 gos esbGy . oGno] 2, 2, 5 3 i - r 2, rt MOD feo tVAD (os.2v0) (DOMDS Bot-tyv0 tt a ay icp ya fe . we {vn 0 Pra CLM) ee Ig 1d cia froaldl zz ar ' * = 4 2 Ale . ' rr ivan ; m poe wove y| 15 : s jee =f toa . 3 uw mA g o 13 (Dawe = e ) SB m 5 . (pares s uv 5 4301 4 . 3 CLEP ra by g PrLctoa = ' 1 wi a Io Ko Zz - = = 2 om <I! ag bron a5 foyer} z 2 3 de Hl 13 : uot u 2 a cl 6}: 3 COUP at o mo ? 5 3 oo (DG Hey POP 6 ice 4 cnt {AGHEP (AWE) aq e , ss ea I i. oo (3 = VE aa pr wk PTT s da BF 3 icra a | de oe 7 Zz ' f - a 2 Bo 700 (OTP te . Fhe ' , a iobier? > uv 1 p} > ma CF tose ae) 7a "Puy SCALE - ipa iP2s 3 , | (one2. t 1. 1 ie 1 ie (pnp? z a top za = Ea OvAQYT el (ooo 21 s cd +3 zl! 3 z wus 3 3 3 5 z uw ICLMNIATO iE 1s 15 o% r APT na? t ul 5 HORM 6 CXAIZB96D EVALUATION BOARD SONY usc 5 Cine APA Swe (0-4 Mv JSONYCXA1396D/K/P SONY o eececeesos eetes Oo - a - - e - Ceeessee eescece _Seececeegerses CHeesses eseesceee Soecoecess seooee evece Q eovece eeeeeen0 eo ~ oo | areata oS Kesesses eseesoee e co ta eh. . Coesesdtes eeeesee e666 te ee0ce o60e0 eece ; eese e000 e Coa oe eee0 Ort Cer . Deeseese Teeegece - Oo ee eo Oe om oo ied } o " @ CHeeeede Deseoses e 2 : ovens. i . 096 6217600060062: 6008 ~ fa) ee Tosesese $ ay eeee | - ~ eeegeee 000088620 e De eeeeeee eon fa - - ees a i e me . oeee eceee r _. eeoee - - eoce e- e ce . Coeecece a ~.- ecoe 90 . oee _ ofee0ee @ 8 ee i em . o o _ eoe 6ec8 @ Ceceedos e 0 e008 6 & Se ' ee 2#8 600 6 int eoGce 6 8 oo | - e e Oe IN nm rn rat) ee eo ~ Or) ~ os o Cx) a . _ , . ) : GND plane (Top View) 2nd layer Oe @ e eeeeeceees eecce * e Seeceese e6600000 a raececosoooses 000000e) ensesees S0CCCTCES 89008 eeccee secce. eesecece PI) ee eeoeenee oe 80Cseees 8 a8eneeee e e. .. * 6 Seesese: seeseee e 6 oe eeeed eoeed eeee eese eeeen . . eo ee es eeee e peed . eseseces seensess i * ef oe * . e @ eeseeee) esseeee a e e eeece ba * e e e e eo _ . : 200g eeeeseeeseee eee . ae tou ~ eeeeeeee cm) e os eee 6 - _- _ _ 909666. -, 203 000000000007: 0 08 eee tg 1. z eee e . ecees a esete . @eo 66 2 @ ecesteos e . eee Se eee eoecete @ eo et & 8 Oe e e _. @ & see0 a eeecese! * #0 cee @ & 86 e e@ ees 4e0 6 eee * 68 e e e seee ee. 6 ee ee we . ee e @ * * Power supply plane (Top View) 3rd layerSONY CXA1396D/K/P Package outline Unit : mm CXA1396D 42PIN DIP (CERAMIC) 600mil ee tr 8 a tA 9 o 1s 3 4 a s z = a 3 PACKAGE STRUCTURE PACKAGE MATERIAL | CERAMIC SONY CODE DIP-42t-01 LEAD TREATMENT | GOLO PLATING EtAs CODE #* DIPOS2-C-0600-A LEAD MATERIAL 42 ALLOY JEDEC CODE PACKAGE WEIGHT 81g CXA1396K 68PIN LCC (CERAMIC) 21.59+0.2 1.27 0.2 +0.38 13-025 1.270.1 20.32+ Oka. 7 1940.25 O15.8840,2 03 LIDULAE TEE S+O1B 1,950.25 1.27 oatstoo7 = g PIN NO,1 / INDEX 21640.25 PACKAGE STAUCTURE PACKAGE MATEPIAL | CERAMIC SONY CODE Locesc.o1 LEAD TREATMENT GOLD PLATING ElAJ CODE + CFNOBR-C.$950-4 LEAD MATERIAL JEDEC CODE PACKAGE WEIGHT 27gSONY CXA1396D/K/P CXA1396P 42PIN DIP (PLASTIC) 600mil oa) 2 +04 orth #4 o 42 22 DOO Oooo oo Ooo oO, \ f a oO -15 oF Oo Oo SF "| & 1 21 2.54 z2\*3 =/F7 a; q PACKAGE STAUCTURE PACKAGE MATERIAL | EPOXY RESIN SONY CODE OIP-42P.01 LEAD TREATMENT SOLDER PLATING BIA GOOG DIPQ42-P-0600-8 LEAD MATERIAL 42 ALLOY JEDEC CODE PACKAGE WE.GHT 64g