LMV844MT/NOPB - Texas Instruments

SENSOR

VS+

Active Band-Pass Filter

High Impedance Sensor Interface

CMOS Input Feature

High-Side, Current-Sensing

Rail-to-Rail Input and Output Feature

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMV841

LMV842

LMV844

SNOSAT1I –OCTOBER 2006–REVISED OCTOBER 2017

LMV84x CMOS Input, RRIO, Low Power, Wide Supply Range,

4.5-MHz Operational Amplifiers

1 Features

1• Unless Otherwise Noted, Typical Values at

TA= 25 °C, V+= 5 V.

• Small 5-Pin SC70 Package (2.00 mm × 1.25 mm

× 0.95 mm)

• Wide Supply Voltage Range: 2.7 V to 12 V

• Specified Performance at 3.3 V, 5 V and ±5 V

• Low Supply Current: 1 mA Per Channel

• Unity Gain Bandwidth: 4.5 MHz

• Open-Loop Gain: 133 dB

• Input Offset Voltage: 500 µV Maximum

• Input Bias Current: 0.3 pA

• CMRR at 112 dB and PSSR at 108 dB

• Input Voltage Noise: 20 nV/√Hz

• Temperature Range: −40°C to 125°C

• Rail-to-Rail Input and Output (RRIO)

2 Applications

• High Impedance Sensor Interface

• Battery-Powered Instrumentation

• High Gain and Instrumentation Amplifiers

• DAC Buffers and Active Filters

3 Description

The LMV84x devices are low-voltage and low-power

operational amplifiers that operate with supply

voltages ranging from 2.7 V to 12 V and have rail-to-

rail input and output capability. Their low offset

voltage, low supply current, and CMOS inputs make

them ideal for high impedance sensor interface and

battery-powered applications.

The single LMV841 is offered in the space-saving 5-

pin SC70 package, the dual LMV842 in the 8-pin

VSSOP and 8-pin SOIC packages, and the quad

LMV844 in the 14-pin TSSOP and 14-pin SOIC

packages. These small packages are ideal solutions

for area-constrained PCBs and portable electronics.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LMV841 SC70 (5) 2.00 mm × 1.25 mm

LMV842 VSSOP (8) 3.00 mm × 3.00 mm

SOIC (8) 4.90 mm × 3.91 mm

LMV844 SOIC (14) 8.65 mm × 3.91 mm

TSSOP (14) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Applications

LMV841

LMV842

LMV844

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Product Folder Links: LMV841 LMV842 LMV844

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics – 3.3 V ............................. 5

6.6 Electrical Characteristics – 5 V ................................ 6

6.7 Electrical Characteristics – ±5-V .............................. 7

6.8 Typical Characteristics............................................ 10

7 Detailed Description............................................ 16

7.1 Overview................................................................. 16

7.2 Functional Block Diagram....................................... 16

7.3 Feature Description................................................. 16

7.4 Device Functional Modes........................................ 17

7.5 Interfacing to High Impedance Sensor .................. 20

8 Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Applications ................................................ 21

9 Power Supply Recommendations...................... 25

10 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 25

10.2 Layout Example .................................................... 25

11 Device and Documentation Support................. 26

11.1 Related Links ........................................................ 26

11.2 Receiving Notification of Documentation Updates 26

11.3 Community Resources.......................................... 26

11.4 Trademarks........................................................... 26

11.5 Electrostatic Discharge Caution............................ 26

11.6 Glossary................................................................ 26

12 Mechanical, Packaging, and Orderable

Information........................................................... 26

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (July 2016) to Revision I Page

• Changed ESD Ratings table footnotes to TI standard .......................................................................................................... 4

• Changed Thermal Information table....................................................................................................................................... 4

• Changed Phase Margin vs CLgraphic ................................................................................................................................ 13

• Changed Overshoot vs CLgraphic....................................................................................................................................... 14

Changes from Revision G (February 2013) to Revision H Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

Changes from Revision F (February 2013) to Revision G Page

• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 23

LMV841

LMV842

LMV844

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SNOSAT1I –OCTOBER 2006–REVISED OCTOBER 2017

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5 Pin Configuration and Functions

DCK Package

5-Pin SC70

Top View D or DGK Package

8-Pin SOIC and VSSOP

Top View

D or PW Package

14-Pin SOIC and TSSOP

Top View

Pin Functions

PIN DESCRIPTION

NAME I/O.

+IN I Noninverting Input

–IN I Inverting Input

OUT O Output

V+ P Positive Supply

V– P Negative Supply

LMV841

LMV842

LMV844

SNOSAT1I –OCTOBER 2006–REVISED OCTOBER 2017

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office / Distributors for availability and

specifications.

(3) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)

MIN MAX UNIT

VIN differential –300 300 mV

Supply voltage (V+– V−) 13.2 V

Voltage at input and output pins V++ 0.3 V−– 0.3 V

Input current 10 mA

Junction temperature (3) 150 °C

Soldering

information Infrared or convection (20 s) 235 °C

Wave soldering lead temperature (10 s) 260 °C

Storage temperature, Tstg −65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic

discharge Human-body model (HBM)(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250

(1) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

6.3 Recommended Operating Conditions MIN MAX UNIT

Temperature(1) −40 125 °C

Supply voltage (V+– V−) 2.7 12 V

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

6.4 Thermal Information

THERMAL METRIC(1)

LMV84x

UNIT

DCK (SC70) DGK

(VSSOP) D (SOIC) PW

(TSSOP)

5 PINS 8 PINS 8 PINS 14 PIN 14 PINS

RθJA Junction-to-ambient thermal resistance(2) 269.9 179.2 121.4 85.4 113.3 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 93.8 69.2 65.7 43.5 38.9 °C/W

RθJB Junction-to-board thermal resistance 48.8 99.7 62.0 39.8 56.3 °C/W

ψJT Junction-to-top characterization parameter 2.0 10.0 16.5 9.2 3.1 °C/W

ψJB Junction-to-board characterization parameter 47.9 98.3 61.4 39.6 55.6 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A °C/W

LMV841

LMV842

LMV844

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(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using

statistical quality control (SQC) method.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped

production material.

(4) This parameter is ensured by design and/or characterization and is not tested in production.

(5) Positive current corresponds to current flowing into the device.

6.5 Electrical Characteristics – 3.3 V

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3.3 V, V−= 0 V, VCM = V+/ 2, and RL> 10 MΩto V+/

2.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

VOS Input offset voltage –500 ±50 500 µV

at the temperature extremes –800 800

TCVOS Input offset voltage drift (4) 0.5 µV/°C

at the temperature extremes –5 5

IBInput bias current (4) (5) 0.3 10 pA

at the temperature extremes 300

IOS Input offset current 40 fA

CMRR

Common-mode rejection ratio

LMV841 0 V ≤VCM ≤3.3 V 84 112 dB

at the temperature

extremes 80

Common-mode rejection ratio

LMV842 and LMV844 0 V ≤VCM ≤3.3 V 77 106 dB

at the temperature

extremes 75

PSRR Power supply rejection ratio 2.7 V ≤V+≤12 V, VO= V+

/ 2

86 108 dB

at the temperature

extremes 82

CMVR Input common-mode voltage

range CMRR ≥50 dB, at the temperature extremes –0.1 3.4 V

AVOL Large signal voltage gain

RL= 2 kΩ

VO= 0.3 V to 3 V

100 123 dB

at the temperature

extremes 96

RL= 10 kΩ

VO= 0.2 V to 3.1 V

100 131 dB

at the temperature

extremes 96

Output swing high,

(measured from V+)

RL= 2 kΩto V+/2 52 80 mV

at the temperature

extremes 120

RL= 10 kΩto V+/2 28 50 mV

at the temperature

extremes 70

Output swing low,

(measured from V−)

RL= 2 kΩto V+/2 65 100 mV

at the temperature

extremes 120

RL= 10 kΩto V+/2 33 65 mV

at the temperature

extremes 75

LMV841

LMV842

LMV844

SNOSAT1I –OCTOBER 2006–REVISED OCTOBER 2017

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Product Folder Links: LMV841 LMV842 LMV844

Electrical Characteristics – 3.3 V (continued)

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3.3 V, V−= 0 V, VCM = V+/ 2, and RL> 10 MΩto V+/

2.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

(6) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

(7) Short circuit test is a momentary test.

(8) Number specified is the slower of positive and negative slew rates.

IOOutput short-circuit current(6)(7)

Sourcing VO= V+/2

VIN = 100 mV

20 32 mA

at the temperature

extremes 15

Sinking VO= V+/2

VIN =−100 mV

20 27 mA

at the temperature

extremes 15

ISSupply current Per channel 0.93 1.5 mA

at the temperature

extremes 2

SR Slew rate (8) AV= 1, VO= 2.3 VPP

10% to 90% 2.5 V/µs

GBW Gain bandwidth product 4.5 MHz

ΦmPhase margin 67 Deg

enInput-referred voltage noise f = 1 kHz 20 nV/

ROUT Open-loop output impedance f = 3 MHz 70 Ω

THD+N Total harmonic distortion + noise f = 1 kHz , AV= 1

RL= 10 kΩ0.005%

CIN Input capacitance 7 pF

(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using

statistical quality control (SQC) method.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped

production material.

(4) This parameter is ensured by design and/or characterization and is not tested in production.

(5) Positive current corresponds to current flowing into the device.

6.6 Electrical Characteristics – 5 V

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/ 2, and RL> 10 MΩto V+/ 2.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

VOS Input offset voltage –500 ±50 500 µV

at the temperature extremes –800 800

TCVOS Input offset voltage drift(4) 0.35 µV/°C

at the temperature extremes –5 5

IBInput bias current(4)(5) 0.3 10 pA

at the temperature extremes 300

IOS Input offset current 40 fA

CMRR

Common-mode rejection ratio

LMV841 0 V ≤VCM ≤5 V 86 112 dB

at the temperature

extremes 80

Common-mode rejection ratio

LMV842 and LMV844 0 V ≤VCM ≤5 V 81 106 dB

at the temperature

extremes 79

PSRR Power supply rejection ratio 2.7 V ≤V+≤12 V, VO=

V+/2

86 108 dB

at the temperature

extremes 82

LMV841

LMV842

LMV844

www.ti.com

SNOSAT1I –OCTOBER 2006–REVISED OCTOBER 2017

Product Folder Links: LMV841 LMV842 LMV844

Electrical Characteristics – 5 V (continued)

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/ 2, and RL> 10 MΩto V+/ 2.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

(6) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

(7) Short circuit test is a momentary test.

(8) Number specified is the slower of positive and negative slew rates.

CMVR Input common-mode voltage

range CMRR ≥50 dB, at the temperature extremes –0.2 5.2 V

AVOL Large signal voltage gain

RL= 2 kΩ

VO= 0.3V to 4.7 V

100 125 dB

at the temperature

extremes 96

RL= 10 kΩ

VO= 0.2V to 4.8V

100 133 dB

at the temperature

extremes 96

Output swing high,

(measured from V+)

RL= 2 kΩto V+/2 68 100 mV

at the temperature

extremes 120

RL= 10 kΩto V+/2 32 50 mV

at the temperature

extremes 70

Output swing low,

(measured from V–)

RL= 2 kΩto V+/2 78 120 mV

at the temperature

extremes 140

RL= 10 kΩto V+/2 38 70 mV

at the temperature

extremes 80

IOOutput short-circuit current(6) (7)

Sourcing VO= V+/2

VIN = 100 mV

20 33 mA

at the temperature

extremes 15

Sinking VO= V+/2

VIN =−100 mV

20 28 mA

at the temperature

extremes 15

ISSupply current Per channel 0.96 1.5 mA

at the temperature

extremes 2

SR Slew rate (8) AV= 1, VO= 4 VPP

10% to 90% 2.5 V/µs

GBW Gain bandwidth product 4.5 MHz

ΦmPhase margin 67 Deg

enInput-referred voltage noise f = 1 kHz 20 nV/

ROUT Open-loop output impedance f = 3 MHz 70 Ω

THD+N Total harmonic distortion +

noise f = 1 kHz , AV= 1

RL= 10 kΩ0.003%

CIN Input capacitance 6 pF

(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device.

6.7 Electrical Characteristics – ±5-V

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= –5 V, VCM = 0 V, and RL> 10 MΩto VCM.(1)

LMV841

LMV842

LMV844

SNOSAT1I –OCTOBER 2006–REVISED OCTOBER 2017

www.ti.com

Product Folder Links: LMV841 LMV842 LMV844

Electrical Characteristics – ±5-V (continued)

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= –5 V, VCM = 0 V, and RL> 10 MΩto VCM.(1)

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using

statistical quality control (SQC) method.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped

production material.

(4) This parameter is ensured by design and/or characterization and is not tested in production.

(5) Positive current corresponds to current flowing into the device.

(6) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) - TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

(7) Short circuit test is a momentary test.

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

VOS Input offset voltage –500 ±50 500 µV

at the temperature extremes –800 800

TCVOS Input offset voltage drift (4) 0.25 µV/°C

at the temperature extremes –5 5

IBInput bias current (4) (5) 0.3 10 pA

at the temperature extremes 300

IOS Input offset current 40 fA

CMRR

Common-mode rejection ratio

LMV841 –5 V ≤VCM ≤5 V 86 112 dB

at the temperature

extremes 80

Common-mode rejection ratio

LMV842 and LMV844 –5 V ≤VCM ≤5 V 86 106 dB

at the temperature

extremes 80

PSRR Power supply rejection ratio 2.7 V ≤V+≤12 V, VO=

0 V

86 108 dB

at the temperature

extremes 82

CMVR Input common-mode voltage

range CMRR ≥50 dB –5.2 5.2 V

AVOL Large signal voltage gain

RL= 2 kΩ

VO=−4.7 V to 4.7 V 100 126 dB

at the temperature

extremes 96

RL= 10 kΩ

VO=−4.8 V to 4.8 V 100 136 dB

at the temperature

extremes 96

Output swing high,

(measured from V+)

RL= 2 kΩto 0 V 95 130 mV

at the temperature

extremes 155

RL= 10 kΩto 0 V 44 75 mV

at the temperature

extremes 95

Output swing low,

(measured from V−)

RL= 2 kΩto 0 V 105 160 mV

at the temperature

extremes 200

RL= 10 kΩto 0 V 52 80 mV

at the temperature

extremes 100

IOOutput short-circuit current (6) (7)

Sourcing VO= 0 V

VIN = 100 mV

20 37 mA

at the temperature

extremes 15

Sinking VO= 0 V

VIN =−100 mV

20 29 mA

at the temperature

extremes 15

LMV841

LMV842

LMV844

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SNOSAT1I –OCTOBER 2006–REVISED OCTOBER 2017

Product Folder Links: LMV841 LMV842 LMV844

Electrical Characteristics – ±5-V (continued)

Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= –5 V, VCM = 0 V, and RL> 10 MΩto VCM.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

(8) Number specified is the slower of positive and negative slew rates.

ISSupply current Per channel 1.03 1.7 mA

at the temperature

extremes 2

SR Slew rate (8) AV= 1, VO= 9 VPP

10% to 90% 2.5 V/µs

GBW Gain bandwidth product 4.5 MHz

ΦmPhase margin 67 Deg

enInput-referred voltage noise f = 1 kHz 20 nV/

ROUT Open-loop output impedance f = 3 MHz 70 Ω

THD+N Total harmonic distortion + noise f = 1 kHz , AV= 1

RL= 10kΩ0.006%

CIN Input capacitance 3 pF

TEMPERATURE (°C)

VOS (PV)

200

150

100

-50

-100

-150

-200

-50 -25 0 25 50 75 100 125

3.3V

5V ±5V

OUTPUT SWING FROM RAIL (mV)

OPEN LOOP GAIN (dB)

140

130

120

110

100

900 100 200 300 400 500

RL = 600Ö

RL = 10 k:

RL = 2 k:

VSUPPLY (V)

VOS (PV)

200

150

100

-50

-100

-150

-2002 4 6 8 10 12 14

-40°C

25°C

85°C

125°C

VCM (V)

VOS (PV)

200

150

100

-50

-100

-150

-200

-6 -4 -2 0 2 4 6

-40°C

25°C

85°C

125°C

VS = ±5V

VCM (V)

VOS (PV)

200

150

100

-50

-100

-150

-200

-1 0 1 2 3 4

-40°C

25°C

85°C

125°C

VS = 3.3V

VCM (V)

VOS (PV)

200

150

100

-50

-100

-150

-200

-1 0 1 2 3 4 5 6

-40°C

25°C

85°C

125°C

VS = 5.0V

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6.8 Typical Characteristics

At TA= 25°C, RL= 10 kΩ, VS= 5 V. Unless otherwise specified.

Figure 1. VOS vs VCM Over Temperature at 3.3 V Figure 2. VOS vs VCM Over Temperature at 5 V

Figure 3. VOS vs VCM Over Temperature at ±5 V Figure 4. VOS vs Supply Voltage

Figure 5. VOS vs Temperature Figure 6. DC Gain vs VOUT

SUPPLY VOLTAGE (V)

ISINK (mA)

202 4 6 8 10 12

-40°C 25°C

85°C 125°C

SUPPLY VOLTAGE (V)

ISOURCE (mA)

252 4 6 8 10 12

-40°C 25°C

85°C

125°C

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

1.4

1.3

1.2

1.1

1.0

0.9

0.82 4 6 8 10 12 14

-40°C

25°C

85°C

125°C

VCM (V)

IBIAS (pA)

200

150

100

-50

-100

-150

-200

-5 -4 -3 -2 -1 0 1 2 3 4 5

3.3V

5.0V

±5V

TA = 125°C

VCM (V)

IBIAS (pA)

0.20

0.15

0.10

0.05

-0.05

-0.10

-0.15

-0.20

-5 -4 -3 -2 -1 0 1 2 3 4 5

3.3V

±5V

TA = 25°C

VCM (V)

IBIAS (pA)

-5

-10

-15

-20

-5 -4 -3 -2 -1 0 1 2 3 4 5

3.3V

5.0V

±5V

TA = 85°C

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, VS= 5 V. Unless otherwise specified.

Figure 7. Input Bias Current vs VCM Figure 8. Input Bias Current vs VCM

Figure 9. Input Bias Current vs VCM Figure 10. Supply Current Per Channel vs Supply Voltage

Figure 11. Sinking Current vs Supply Voltage Figure 12. Sourcing Current vs Supply Voltage

ILOAD (mA)

VOUT FROM RAIL (V)

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

0 5 10 15 20 25 30

-40°C

SINK

SOURCE

25°C

125°C

85°C

VS= 3.3V, 5.0V, +/-5V

PHASE (°)

FREQUENCY (Hz)

GAIN (dB)

-20

130

-30

10k 100k 1M 10M

-40°C

125°C

-40°C

PHASE

125°C

GAIN

CL = 20 pF

SUPPLY VOLTAGE (V)

VOUT FROM RAIL LOW (mV)

150

140

130

120

110

100

502 4 6 8 10 12 14

-40°C

25°C

85°C

125°C

RL = 2 k:

SUPPLY VOLTAGE (V)

VOUT FROM RAIL LOW (mV)

252 4 6 8 10 12 14

-40°C

25°C

85°C

125°C

RL = 10 k:

SUPPLY VOLTAGE (V)

VOUT FROM RAIL HIGH (mV)

135

125

115

105

352 4 6 8 10 12 14

-40°C

25°C

85°C

125°C

RL = 2 k:

SUPPLY VOLTAGE (V)

VOUT FROM RAIL HIGH (mV)

152 4 6 8 10 12 14

-40°C

25°C

85°C

125°C

RL = 10 k:

LMV841

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LMV844

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, VS= 5 V. Unless otherwise specified.

Figure 13. Output Swing High vs Supply Voltage RL= 2 kΩFigure 14. Output Swing High vs Supply Voltage RL= 10 kΩ

Figure 15. Output Swing Low vs Supply Voltage RL= 2 kΩFigure 16. Output Swing Low vs Supply Voltage RL= 10 kΩ

Figure 17. Output Voltage Swing vs Load Current Figure 18. Open-Loop Frequency Response Over

Temperature

400 ns/DIV

500 mV/DIV

f = 250 kHz

AV = +1

VIN = 2 VPP

CL = 20 pF

FREQUENCY (Hz)

CHANNEL SEPARATION (dB)

100

120

140

160

180

100 1k 10k 100k 1M

VS = 3.3V, 5.0V, ±5V

FREQUENCY (Hz)

CMRR (dB)

100 1k 10k 100k 1M

±5V

5.0V

3.3V

3.3V : VCM = 1V

5.0V : VCM = 2.5V

±5V : VCM = 0V

110

100 1k 10k 100k 1M

FREQUENCY (Hz)

100

120

PSRR (dB)

3.3V

5.0V

±5V

3.3V

±5V

+PSRR

-PSRR

3.3V: VCM = 1V

5.0V: VCM = 2.5V

±5V: VCM = 0V

PHASE (°)

FREQUENCY (Hz)

GAIN (dB)

-20

130

-30

10k 100k 1M 10M

GAIN PHASE

VS = 3.3V, 5.0V, 10V

CL = 20 pF, 50 pF, 100 pF

CL=20 pF

VS=10V

VS = 3.3V

CL = 100 pF

CLOAD

PHASE (q)

1 2 3 4 5 67 10 20 30 50 70100 200 500 1000

D001

Vs = 3.3 V

Vs = 5 V

Vs = 10 V

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, VS= 5 V. Unless otherwise specified.

Figure 19. Open-Loop Frequency Response Over Load

Conditions

Figure 20. Phase Margin vs CL

Figure 21. PSRR vs Frequency Figure 22. CMRR vs Frequency

Figure 23. Channel Separation vs Frequency Figure 24. Large Signal Step Response With Gain = 1

FREQUENCY (Hz)

NOISE (nV/Hz)

100

10 100 1k 10k 100k

3.3V

5.0V

±5V

CLOAD (pF)

OVERSHOOT (%)

10 20 30 4050 70 100 200 300 500 7001000

D002

V(s) = 3.3 V

V(s) = 5 V

V(s) = ±5 V

400 ns/DIV

20 mV/DIV

f = 250 kHz

AV = +10

VIN = 10 mVPP

CL = 20 pF

SUPPLY VOLTAGE (V)

SLEW RATE (V/µs)

3.0

2.5

2.0

1.5

1.0 2 4 6 8 10 12

FALLING EDGE

RISING EDGE

AV= +1

VIN = 2 VPP

RL= 10 kΩ

CL= 20 pF

400 ns/DIV

200 mV/DIV

f = 250 kHz

AV = +10

VIN = 100 mVPP

CL = 20 pF

400 ns/DIV

50 mV/DIV

f = 250 kHz

AV = +1

VIN = 200 mVPP

CL = 20 pF

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, VS= 5 V. Unless otherwise specified.

Figure 25. Large Signal Step Response With Gain = 10 Figure 26. Small Signal Step Response With Gain = 1

Figure 27. Small Signal Step Response With Gain = 10 Figure 28. Slew Rate vs Supply Voltage

Figure 29. Overshoot vs CLFigure 30. Input Voltage Noise vs Frequency

FREQUENCY (Hz)

ROUT (:)

100

0.1

0.01

0.001

100 1k 10k 100k 1M 10M

10x

100x

VOUT (V)

THD + N (%)

0.1

0.01

0.001

0.001 0.01 0.1 1 10

AV= +1

AV= +10

VS= 5V

RL= 10 kΩ

CL= 20 pF

f = 1 kHz

FREQUENCY (Hz)

THD + N (%)

0.1

0.01

0.001

10 100 1k 10k 100k

AV= +1

AV= +10

VS= 5V

RL= 10 kΩ

CL= 50 pF

VOUT = 4.5 VPP

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, VS= 5 V. Unless otherwise specified.

Figure 31. THD+N vs Frequency Figure 32. THD+N vs VOUT

Figure 33. Closed-Loop Output Impedance vs Frequency

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7 Detailed Description

7.1 Overview

The LMV84x devices are operational amplifiers with near-precision specifications: low noise, low temperature

drift, low offset, and rail-to-rail input and output. Possible application areas include instrumentation, medical, test

equipment, audio, and automotive applications.

Its low supply current of 1 mA per amplifier, temperature range of −40°C to +125°C, 12-V supply with CMOS

input, and the small SC70 package for the LMV841 make the LMV84x a unique op amp family and a perfect

choice for portable electronics.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Input Protection

The LMV84x devices have a set of anti-parallel diodes D1and D2between the input pins, as shown in Figure 34.

These diodes are present to protect the input stage of the amplifier. At the same time, they limit the amount of

differential input voltage that is allowed on the input pins.

A differential signal larger than one diode voltage drop can damage the diodes. The differential signal between

the inputs needs to be limited to ±300 mV or the input current needs to be limited to ±10 mA.

NOTE

When the op amp is slewing, a differential input voltage exists that forward-biases the

protection diodes. This may result in current being drawn from the signal source. While

this current is already limited by the internal resistors R1and R2(both 130 Ω), a resistor of

1 kΩcan be placed in the feedback path, or a 500-Ωresistor can be placed in series with

the input signal for further limitation.

ESD

IN+

ESD D1D2

ESD

V-

V+

IN-

V+

V-

VOUT

V+

V-

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Feature Description (continued)

Figure 34. Protection Diodes Between the Input Pins

7.3.2 Input Stage

The input stage of this amplifier consists of both a PMOS and an NMOS input pair to achieve a rail-to-rail input

range. For input voltages close to the negative rail, only the PMOS pair is active. Close to the positive rail, only

the NMOS pair is active. In a transition region that extends from approximately 2 V below V+to 1 V below V+,

both pairs are active, and one pair gradually takes over from the other. In this transition region, the input-referred

offset voltage changes from the offset voltage associated with the PMOS pair to that of the NMOS pair. The input

pairs are trimmed independently to ensure an input offset voltage of less then 0.5 mV at room temperature over

the complete rail-to-rail input range. This also significantly improves the CMRR of the amplifier in the transition

region.

NOTE

The CMRR and PSRR limits in the tables are large-signal numbers that express the

maximum variation of the input offset of the amplifier over the full common-mode voltage

and supply voltage range, respectively. When the common-mode input voltage of the

amplifier is within the transition region, the small signal CMRR and PSRR may be slightly

lower than the large signal limits.

7.4 Device Functional Modes

7.4.1 Driving Capacitive Load

The LMV84x can be connected as noninverting unity gain amplifiers. This configuration is the most sensitive to

capacitive loading. The combination of a capacitive load placed on the output of an amplifier along with the

output impedance of the amplifier creates a phase lag, which reduces the phase margin of the amplifier. If the

phase margin is significantly reduced, the response is under-damped, which causes peaking in the transfer.

When there is too much peaking, the op amp might start oscillating.

The LMV84x can directly drive capacitive loads up to 100 pF without any stability issues. To drive heavier

capacitive loads, an isolation resistor (RISO) must be used, as shown in Figure 35. By using this isolation resistor,

the capacitive load is isolated from the output of the amplifier, and hence, the pole caused by CLis no longer in

the feedback loop. The larger the value of RISO, the more stable the output voltage is. If values of RISO are

sufficiently large, the feedback loop is stable, independent of the value of CL. However, larger values of RISO

result in reduced output swing and reduced output current drive.

en in

-VOUT

VIN

RISO

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Device Functional Modes (continued)

Figure 35. Isolating Capacitive Load

7.4.2 Noise Performance

The LMV84x devices have good noise specifications and are frequently used in low-noise applications. Therefore

it is important to determine the noise of the total circuit. Besides the input-referred noise of the op amp, the

feedback resistors may have an important contribution to the total noise.

For applications with a voltage input configuration, in general it is beneficial general, beneficial to keep the

resistor values low. In these configurations high resistor values mean high noise levels. However, using low

resistor values will increase the power consumption of the application. This is not always acceptable for portable

applications, so there is a trade-off between noise level and power consumption.

Besides the noise contribution of the signal source, three types of noise need to be taken into account for

calculating the noise performance of an op amp circuit:

• Input-referred voltage noise of the op amp

• Input-referred current noise of the op amp

• Noise sources of the resistors in the feedback network, configuring the op amp

To calculate the noise voltage at the output of the op amp, the first step is to determine a total equivalent noise

source. This requires the transformation of all noise sources to the same reference node. A convenient choice for

this node is the input of the op amp circuit. The next step is to add all the noise sources. The final step is to

multiply the total equivalent input voltage noise with the gain of the op amp configuration.

If the input-referred voltage noise of the op amp is already placed at the input, the user can use the input-

referred voltage noise without further transferring. The input-referred current noise needs to be converted to an

input-referred voltage noise. The current noise is negligibly small, as long as the equivalent resistance is not

unrealistically large, so the user can leave the current noise out for these examples. That leaves the user with

the noise sources of the resistors, being the thermal noise voltage. The influence of the resistors on the total

noise can be seen in the following examples, one with high resistor values and one with low resistor values. Both

examples describe an op amp configuration with a gain of 101 which gives the circuit a bandwidth of 44.5 kHz.

The op amp noise is the same for both cases, that is, an input-referred noise voltage of 20 nV/ and a

negligibly small input-referred noise current.

Figure 36. Noise Circuit

F G

R R k 100

RR R k 100

10 99

´W ´ W

= = = W

+ W + W

n out n in noise

e e A

nV/ Hz V/ Hz45 101 4.5

= ´

= ´ = m

n in nv nr

e e e

nV/ Hz nV/ Hz 45 nV/ Hz

2 2

(20 ) (40 )

= +

= + =

nr eq

e kTR

J/K K k

nV/ Hz

4 1.38 10 298 99

= ´ ´ ´ ´ W

F G

R R M 100 k

R k

R R M 100 k

10 99

´W ´ W

= = = W

+ W + W

n out n in noise

e e A= ´

n in nv nr

e e e

2 2

= +

nr eq

e kTR4=

F G

R R

RR R

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Device Functional Modes (continued)

To calculate the noise of the resistors in the feedback network, the equivalent input-referred noise resistance is

needed. For the example in Figure 36, this equivalent resistance Req can be calculated using Equation 1:

(1)

The voltage noise of the equivalent resistance can be calculated using Equation 2:

where

• enr = thermal noise voltage of the equivalent resistor

• Req (V/ )

• k = Boltzmann constant (1.38 x 10–23 J/K)

• T = absolute temperature (K)

• Req = resistance (Ω) (2)

The total equivalent input voltage noise is given by Equation 3:

where

• en in = total input equivalent voltage noise of the circuit

• env = input voltage noise of the op amp (3)

The final step is multiplying the total input voltage noise by the noise gain using Equation 4, which is in this case

the gain of the op amp configuration:

(4)

The equivalent resistance for the first example with a resistor RFof 10 MΩand a resistor RGof 100 kΩat 25°C

(298 K) equals Equation 5:

(5)

Now the noise of the resistors can be calculated using Equation 6, yielding:

(6)

The total noise at the input of the op amp is calculated in Equation 7:

(7)

For the first example, this input noise, multiplied with the noise gain, in Equation 8 gives a total output noise of:

(8)

In the second example, with a resistor RFof 10 kΩand a resistor RGof 100 Ωat 25°C (298 K), the equivalent

resistance equals Equation 9:

(9)

The resistor noise for the second example is calculated in Equation 10:

SENSOR V+

V-

RS+

IBVIN+

VS+

n out n in noise

e e A

nV/ Hz 101 = 2 V/ Hz20

= ´

= ´ m

n in nv nr

e e e

nV/ Hz nV/ Hz

nV/ Hz

2 2

(20 ) (1 )

= +

nr eq

e kTR

J/K 298 K

nV/ Hz

4 1.38 10 99

= ´ ´ ´ ´ W

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Device Functional Modes (continued)

(10)

The total noise at the input of the op amp is calculated in Equation 10:

(11)

For the second example the input noise, multiplied with the noise gain, in Equation 12 gives an output noise of:

(12)

In the first example the noise is dominated by the resistor noise due to the very high resistor values, in the

second example the very low resistor values add only a negligible contribution to the noise and now the

dominating factor is the op amp itself. When selecting the resistor values, it is important to choose values that do

not add extra noise to the application. Choosing values above 100 kΩmay increase the noise too much. Low

values keep the noise within acceptable levels; choosing very low values however, does not make the noise

even lower, but can increase the current of the circuit.

7.5 Interfacing to High Impedance Sensor

With CMOS inputs, the LMV84x are particularly suited to be used as high impedance sensor interfaces.

Many sensors have high source impedances that may range up to 10 MΩ. The input bias current of an amplifier

loads the output of the sensor, and thus cause a voltage drop across the source resistance, as shown in

Figure 37. When an op amp is selected with a relatively high input bias current, this error may be unacceptable.

The low input current of the LMV84x significantly reduces such errors. The following examples show the

difference between a standard op amp input and the CMOS input of the LMV84x.

The voltage at the input of the op amp can be calculated with Equation 13:

VIN+ = VS– IB× RS(13)

For a standard op amp, the input bias Ib can be 10 nA. When the sensor generates a signal of 1 V (VS) and the

sensors impedance is 10 MΩ(RS), the signal at the op amp input is calculated in Equation 14:

VIN = 1 V – 10 nA × 10 MΩ= 1 V - 0.1 V = 0.9 V (14)

For the CMOS input of the LMV84x, which has an input bias current of only 0.3 pA, this would give Equation 15:

VIN = 1 V – 0.3 pA × 10 MΩ= 1 V – 3 µV = 0.999997 V (15)

The conclusion is that a standard op amp, with its high input bias current input, is not a good choice for use in

impedance sensor applications. The LMV84x devices, in contrast, are much more suitable due to the low input

bias current. The error is negligibly small; therefore, the LMV84x are a must for use with high-impedance

sensors.

Figure 37. High Impedance Sensor Interface

mid

k k

f kHz

nF k k k

1 2 6.2 11.2

27 2 6.2 45

W + W

= =

p ´ W ´ W ´ W

mid

k k

f kHz

nF k k k

1 2 6.2 9.2

33 2 6.2 45

W + W

= =

p ´ W ´ W ´ W

mid

R R

C R R R

1 3

1 2 3

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The rail-to-rail input and output of the LMV84x and the wide supply voltage range make these amplifiers ideal to

use in numerous applications. Three sample applications, namely the active filter circuit, high-side current

sensing, and thermocouple sensor interface, are provided in the Typical Applications section.

8.2 Typical Applications

8.2.1 Active Filter Circuit

Figure 38. Active Band-Pass Filter Implementation

8.2.1.1 Design Requirements

In this example it is required to design a bandpass filter with band-pass frequency of 10 kHz, and a center

frequence of approximately 10% from the total frequence of the filter. This is achieved by cascading two band-

pass filters, A and B, with slightly different center frequencies.

8.2.1.2 Detailed Design Procedure

The center frequency of the separate band-pass filters A, and B can be calculated by Equation 16:

where

• C = 33 nF

• R1 = 2 KΩ

• R2 = 6.2 KΩ

• and R3 = 45 Ω(16)

This gives Equation 17 for filter A:

(17)

and Equation 18 for filter B with C = 27nF:

(18)

Bandwidth can be calculated by Equation 19:

LOAD

V+

FREQUENCY (Hz)

GAIN (dB)

-10

-20

-30

-40

1k 10k 100k

FILTER A FILTER B

COMBINED

FILTER

B kHz

k nF

11.9

6.2 27

= =

p ´ W ´

B kHz

k nF

11.6

6.2 33

= =

p ´ W ´

R C

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Typical Applications (continued)

(19)

For filter A, this gives Equation 20:

(20)

and Equation 21 for filter B:

(21)

8.2.1.3 Application Curve

The responses of filter A and filter B are shown as the thin lines in Figure 39; the response of the combined filter

is shown as the thick line. Shifting the center frequencies of the separate filters farther apart, results in a wider

band; however, positioning the center frequencies too far apart results in a less flat gain within the band. For

wider bands more band-pass filters can be cascaded.

Figure 39. Active Band-Pass Filter Curve

NOTE

Use the WEBENCH internet tools at www.ti.com for your filter application.

8.2.2 High-Side, Current-Sensing Circuit

Figure 40. High-Side, Current-Sensing Circuit

Metal A

Metal B

Thermocouple

Cold junction Reference

Cold junction Temperature

Copper

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Amplified

Thermocouple

Output

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Typical Applications (continued)

8.2.2.1 Design Requirements

In this example, it is desired to measure a current between 0 A and 2 A using a sense resistor of 100 mΩ, and

convert it to an output voltage of 0 to 5 V. A current of 2 A flowing through the load and the sense resistor results

in a voltage of 200 mV across the sense resistor. The op amp amplifies this 200 mV to fit the current range to the

output voltage range.

8.2.2.2 Detailed Design Procedure

To measure current at a point in a circuit, a sense resistor is placed in series with the load, as shown in

Figure 40. The current flowing through this sense resistor results in a voltage drop, that is amplified by the op

amp. The rail-to-rail input and the low VOS features make the LMV84x ideal op amps for high-side, current-

sensing applications.

The input and the output relation of the circuit is given by Equation 22:

VOUT = RF/RG× VSENSE (22)

For a load current of 2 A and an output voltage of 5 V the gain would be VOUT / VSENSE = 25.

If the feedback resistor, RF, is 100 kΩ, then the value for RGis 4 kΩ. The tolerance of the resistors has to be low

to obtain a good common-mode rejection.

8.2.3 Thermocouple Sensor Signal Amplification

Figure 41 is a typical example for a thermocouple amplifier application using an LMV841, LMV842, or LMV844. A

thermocouple senses a temperature and converts it into a voltage. This signal is then amplified by the LMV841,

LMV842, or LMV844. An ADC can then convert the amplified signal to a digital signal. For further processing the

digital signal can be processed by a microprocessor, and can be used to display or log the temperature, or the

temperature data can be used in a fabrication process.

Figure 41. Thermocouple Sensor Interface

8.2.3.1 Design Requirements

In this example it is desired to measure temperature in the range of 0°C to 500°C with a resolution of 0.5°C using

a K-type thermocouple sensor. The power supply for both the LMV84x and the ADC is

3.3 V.

8.2.3.2 Detailed Design Procedure

A thermocouple is a junction of two different metals. These metals produce a small voltage that increases with

temperature. A K-type thermocouple is a very common temperature sensor made of a junction between nickel-

chromium and nickel-aluminum. There are several reasons for using the K-type thermocouple. These include

temperature range, the linearity, the sensitivity, and the cost.

TEMPERATURE (°C)

THERMOCOUPLE VOLTAGE (mV)

-10

-200 0 200 400 600 800 1000 1200

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Typical Applications (continued)

A K-type thermocouple has a wide temperature range. The range of this thermocouple is from approximately

−200°C to approximately 1200°C, as can be seen in Figure 42. This covers the generally used temperature

ranges.

Over the main part of the range the behavior is linear. This is important for converting the analog signal to a

digital signal. The K-type thermocouple has good sensitivity when compared to many other types; the sensitivity

is 41 µV/°C. Lower sensitivity requires more gain and makes the application more sensitive to noise. In addition,

a K-type thermocouple is not expensive, many other thermocouples consist of more expensive materials or are

more difficult to produce.

Figure 42. K-Type Thermocouple Response

The temperature range of 0°C to 500°C results in a voltage range from 0 mV to 20.6 mV produced by the

thermocouple. This is shown in Figure 42.

To obtain the best accuracy the full ADC range of 0 to 3.3 V is used and the gain needed for this full range can

be calculated Equation 23:

AV= 3.3 V / 0.0206 V = 160 (23)

If RGis 2 kΩ, then the value for RFcan be calculated with this gain of 160. Because AV= RF/ RG, RFcan be

calculated in Equation 24:

RF= AV× RG= 160 × 2 kΩ= 320 kΩ(24)

To achieve a resolution of 0.5°C a step smaller than the minimum resolution is needed. This means that at least

1000 steps are necessary (500°C/0.5°C). A 10-bit ADC would be sufficient as this gives 1024 steps. A 10-bit

ADC such as the two channel 10-bit ADC102S021 would be a good choice.

At the point where the thermocouple wires are connected to the circuit on the PCB unwanted parasitic

thermocouple is formed, introducing error in the measurements of the actual thermocouple sensor.

Using an isothermal block as a reference will compensate for this additional thermocouple effect. An isothermal

block is a good heat conductor. This means that the two thermocouple connections both have the same

temperature. The temperature of the isothermal block can be measured, and thereby the temperature of the

thermocouple connections. This is usually called the cold junction reference temperature. In the example, an

LM35 is used to measure this temperature. This semiconductor temperature sensor can accurately measure

temperatures from −55°C to 150°C.

The ADC in this example also coverts the signal from the LM35 to a digital signal, hence, the microprocessor can

compensate for the amplified thermocouple signal of the unwanted thermocouple junction at the connector.

V-

OUTB

OUTA V+

-INA

+INA

+INB

-INB

GND RG

VOUTA

VIN

Place components close to

device and to each other to

reduce parasitic error

Run the input traces as

far away from the supply

lines as possible

GND VS-

Place low-ESR ceramic

bypass capacitor close to

device

GND

Place low-ESR ceramic

bypass capacitor close to

device

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9 Power Supply Recommendations

The LMV84x is specified for operation from 2.7 V to 12 V (±1.35 V to ±6 V) over a –40°C to 125°C temperature

range. Parameters that can exhibit significant variance with regard to operating voltage or temperature are

presented in the Absolute Maximum Ratings.

CAUTION

Supply voltages larger than 13.2 V can permanently damage the device.

For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI

suggests placing 10-nF capacitors as close as possible to the operational amplifier power supply pins. For single

supply, place a capacitor between V+and V–supply leads. For dual supplies, place one capacitor between V+

and ground, and one capacitor between V–and ground.

10 Layout

10.1 Layout Guidelines

• The V+ pin must be bypassed to ground with a low-ESR capacitor.

• The optimum placement is closest to the V+ and ground pins.

• Take care to minimize the loop area formed by the bypass capacitor connection between V+ and ground.

• The ground pin must be connected to the PCB ground plane at the pin of the device.

• The feedback components must be placed as close to the device as possible to minimize strays.

10.2 Layout Example

Figure 43. Layout Example (Top View)

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11 Device and Documentation Support

11.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 1. Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

LMV841 Click here Click here Click here Click here Click here

LMV842 Click here Click here Click here Click here Click here

LMV844 Click here Click here Click here Click here Click here

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 21-Oct-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMV841MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A97

LMV841MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A97

LMV842MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV84

2MA

LMV842MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV84

2MA

LMV842MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS

& no Sb/Br) CU NIPDAUAG | CU SN Level-1-260C-UNLIM -40 to 125 AC4A

LMV842MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS

& no Sb/Br) CU NIPDAUAG | CU SN Level-1-260C-UNLIM -40 to 125 AC4A

LMV844MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV844MA

LMV844MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV844MA

LMV844MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV844

LMV844MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV844

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

PACKAGE OPTION ADDENDUM

www.ti.com 21-Oct-2017

Addendum-Page 2

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMV841, LMV842, LMV844 :

•Automotive: LMV841-Q1, LMV842-Q1, LMV844-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMV841MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

LMV841MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

LMV844MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1

LMV844MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Aug-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMV841MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0

LMV841MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0

LMV844MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0

LMV844MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Aug-2018

Pack Materials-Page 2

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Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

LMV844MA/NOPB LMV844MAX/NOPB LMV844MT/NOPB LMV844MTX/NOPB