74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
Rev. 5 — 14 February 2019 Product data sheet
1. General description
The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock
inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an
asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH transition of
nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 when nCP0
is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input
may be used as a clock enable input. A HIGH on nMR, resets the counter (nQ0 to nQ3 = LOW)
independent of nCP0 and nCP1. Inputs include clamp diodes. It enables the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC4520: CMOS level
For 74HCT4520: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Applications
Multistage synchronous counting
Multistage asynchronous counting
Frequency dividers
4. Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74HC4520D
74HCT4520D
-40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC4520PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT403-1
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
5. Functional diagram
001aae698
1CP01
1CP12
1MR7
31Q0
41Q1
51Q2
61Q3
2CP09
2CP110
2MR15
112Q0
122Q1
132Q2
142Q3
Fig. 1. Functional diagram
001aae707
nCP0
nCP1
nMR
nQ0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
nQ1
nQ2
nQ3
Fig. 2. Timing diagram
aaa-015608
CP
FF2
RD
Q
Q
CP
FF1
RD
Q
Q
CP
FF3
RD
Q
Q
CP
FF4
RD
Q
Q
nQ0 nQ1 nQ2 nQ3
nCP1
nCP0
nMR
Fig. 3. Logic diagram for one counter
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 2 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
6. Pinning information
6.1. Pinning
1CP0 VCC
1CP1 2MR
1Q0 2Q3
1Q1 2Q2
1Q2 2Q1
1Q3 2Q0
1MR 2CP1
GND 2CP0
74HC4520
74HCT4520
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
aaa-015592
Fig. 4. Pin configuration SOT109-1 (SO16)
1CP0 VCC
1CP1 2MR
1Q0 2Q3
1Q1 2Q2
1Q2 2Q1
1Q3 2Q0
1MR 2CP1
GND 2CP0
74HC4520
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
aaa-015593
Fig. 5. Pin configuration SOT403-1 (TSSOP16)
6.2. Pin description
Table 2. Pin description
Symbol Pin Description
1CP0, 2CP0 1, 9 clock input (LOW-to-HIGH edge-triggered)
1CP1, 2CP1 2, 10 clock input (HIGH-to-LOW edge-triggered)
1Q0 to 1Q3 3, 4, 5, 6 output
1MR, 2MR 7, 15 asynchronous master reset input (active HIGH)
GND 8 ground (0 V)
2Q0 to 2Q3 11, 12, 13, 14 output
VCC 16 supply voltage
7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition.
nCP0 nCP1 nMR Mode
H L counter advances
L L counter advances
X L no change
X L no change
L L no change
H L no change
X X H nQ0 to nQ3 = LOW
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 3 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7.0 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA
IOoutput current VO = -0.5 V to VCC + 0.5 V - ±25 mA
ICC supply current - 50 mA
IGND ground current -50 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation [1] - 500 mW
[1] For SO16 package: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
74HC4520 74HCT4520Symbol Parameter Conditions
Min Typ Max Min Typ Max
Unit
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0 - VCC V
VOoutput voltage 0 - VCC 0 - VCC V
Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
Δt/ΔV input transition rise and fall rate
VCC = 6.0 V - - 83 - - - ns/V
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
74HC4520
VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VIH HIGH-level
input voltage
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VIL LOW-level
input voltage
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 4 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
VI = VIH or VIL
IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = -4.0; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
VOH HIGH-level
output voltage
IO = -5.2; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
VOL LOW-level
output voltage
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current
VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
- - 8.0 - 80.0 - 160.0 μA
CIinput
capacitance
- 3.5 - - - - - pF
74HCT4520
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V
VOH HIGH-level
output voltage
IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA - 0 0.1 - 0.1 - 0.1 V
VOL LOW-level
output voltage
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current
VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
- - 8.0 - 80.0 - 160.0 μA
per input pin; VI = VCC - 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
pin nCP0, nCP1 - 80 288 - 360 - 392 μA
ΔICC additional
supply current
pin nMR - 150 540 - 675 - 735 μA
CIinput
capacitance
- 3.5 - - - - - pF
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 5 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 8.
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
74HC4520
nCP0 to nQn; see Fig. 6 [1]
VCC = 2.0 V - 77 240 - 300 - 360 ns
VCC = 4.5 V - 28 48 - 60 - 72 ns
VCC = 5.0 V; CL = 15 pF - 24 - - - - - ns
VCC = 6.0 V - 22 41 - 51 - 61 ns
nCP1 to nQn; see Fig. 6 [1]
VCC = 2.0 V - 77 240 - 300 - 360 ns
VCC = 4.5 V - 28 48 - 60 - 72 ns
VCC = 5.0 V; CL = 15 pF - 24 - - - - - ns
tpd propagation
delay
VCC = 6.0 V - 22 41 - 51 - 61 ns
nMR to nQn; see Fig. 6
VCC = 2.0 V - 44 150 - 190 - 225 ns
VCC = 4.5 V - 16 30 - 38 - 45 ns
VCC = 5.0 V; CL = 15 pF - 13 - - - - - ns
tPHL HIGH to LOW
propagation
delay
VCC = 6.0 V - 13 26 - 33 - 38 ns
nQn; see Fig. 6 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
tttransition
time
VCC = 6.0 V - 6 13 - 16 - 19 ns
nCP0, nCP1 HIGH or LOW;
see Fig. 7
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
nMR HIGH; see Fig. 7
VCC = 2.0 V 120 39 - 150 - 180 - ns
VCC = 4.5 V 24 14 - 30 - 36 - ns
tWpulse width
VCC = 6.0 V 20 11 - 26 - 31 - ns
nMR to nCP0, nCP1; see Fig. 7
VCC = 2.0 V 0 -28 - 0 - 0 - ns
VCC = 4.5 V 0 -10 - 0 - 0 - ns
trec recovery time
VCC = 6.0 V 0 -8 - 0 - 0 - ns
nCP0 to nCP1; nCP1 to nCP0;
see Fig. 6
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
tsu set-up time
VCC = 6.0 V 14 4 - 17 - 20 - ns
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 6 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
nCP0, nCP1; see Fig. 7
VCC = 2.0 V 6 19 - 4.8 - 4 - MHz
VCC = 4.5 V 30 58 - 24 - 20 - MHz
VCC = 5.0 V; CL = 15 pF - 68 - - - - - MHz
fmax maximum
frequency
VCC = 6.0 V 35 69 - 28 - 24 - MHz
CPD power
dissipation
capacitance
VI = GND to VCC; VCC = 5 V;
fi = 1 MHz
[3] - 29 - - - - - pF
74HCT4520
nCP0 to nQn; see Fig. 6 [1]
VCC = 4.5 V - 28 53 - 66 - 80 ns
VCC = 5.0 V; CL = 15 pF - 24 - - - - - ns
nCP1 to nQn; see Fig. 6 [1]
VCC = 4.5 V - 25 53 - 66 - 80 ns
tpd propagation
delay
VCC = 5.0 V; CL = 15 pF - 24 - - - - - ns
nMR to nQn; see Fig. 6
VCC = 4.5 V - 16 35 - 44 - 53 ns
tPHL HIGH to LOW
propagation
delay
VCC = 5.0 V; CL = 15 pF - 13 - - - - - ns
nQn; see Fig. 6 [2]tttransition
time VCC = 4.5 V - 7 15 - 19 - 22 ns
nCP0, nCP1 HIGH or LOW;
see Fig. 7
VCC = 4.5 V 20 10 - 25 - 30 - ns
nMR HIGH; see Fig. 7
tWpulse width
VCC = 4.5 V 20 12 - 25 - 30 - ns
nMR to nCP0, nCP1; see Fig. 7trec recovery time
VCC = 4.5 V 0 -8 - 0 - 0 - ns
nCP0 to nCP1; nCP1 to nCP0;
see Fig. 6
tsu set-up time
VCC = 4.5 V 16 6 - 20 - 24 - ns
nCP0, nCP1; see Fig. 7
VCC = 4.5 V 30 58 - 24 - 20 - MHz
fmax maximum
frequency
VCC = 5.0 V; CL = 15 pF - 64 - - - - - MHz
CPD power
dissipation
capacitance
VI = GND to VCC - 1.5 V; VCC = 5 V;
fi = 1 MHz
[3] - 24 - - - - - pF
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC
2 × fi × N + Σ(CL × VCC
2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC
2 × fo) = sum of outputs.
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 7 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
11.1. Waveforms and test circuit
001aae702
VI
VI
VI
VM
VM
VM
VM
tt
tsu tsu
tt
tPHL tPLH
90 %
10 %
tPHL
VOH
nCP0 input
nCP1 input
nMR input
nQn output
0 V
0 V 0 V
0 V
VOL
Measurement points are given in Table 8.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Fig. 6. nCP0 and nCP1 set-up times, propagation delays and output transition times
001aae701
nCP1 input
(nCP0 = LOW)
nCP0 input
(nCP1 = HIGH)
nMR input
VM
VI
0 V
VI
0 V
VI
0 V
tW
1/fmax
VM
tW
VM
tW
trec
Measurement points are given in Table 8.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Fig. 7. nMR recovery time, minimum nCP0, nCP1, nMR pulse widths and maximum frequency
Table 8. Measurement points
Input OutputType
VMVIVM
74HC4520 0.5 × VCC GND to VCC 0.5 × VCC
74HCT4520 1.3 V GND to 3 V 1.3 V
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 8 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
G
Test data is given in Table 9.
Test circuit definitions:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistance.
S1 = Test selection switch
Fig. 8. Test circuit for measuring switching times
Table 9. Test data
Input Load S1 positionType
VItr, tfCLRLtPHL, tPLH
74HC4520 GND to VCC 6 ns 15 pF, 50 pF 1 kΩ open
74HCT4520 GND to 3 V 6 ns 15 pF, 50 pF 1 kΩ open
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 9 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
12. Package outline
Fig. 9. Package outline SOT109-1 (SO16)
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 10 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
UNIT A
1 A
2 A
3 b
p c D
(1) E (2) (1)
e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3 0.65 6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.1 0.2 1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
1 8
16 9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
Fig. 10. Package outline SOT403-1 (TSSOP16)
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 11 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
13. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4520 v.5 20190214 Product data sheet - 74HC_HCT4520 v.4
Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Type numbers 74HC4520DB and 74HCT4520DB (SOT338-1) removed.
74HC_HCT4520 v.4 20160510 Product data sheet - 74HC_HCT4520 v.3
Modifications: Type numbers 74HC4520N and 74HCT4520N (SOT38-4) removed.
74HC_HCT4520 v.3 20141204 Product data sheet - 74HC_HCT4520_CNV v.2
Modifications: The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
74HC_HCT4520_CNV v.2 19930927 Product specification - -
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 12 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
15. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Objective [short]
data sheet
Development This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification This document contains data from
the preliminary specification.
Product [short]
data sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
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or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 13 / 14
Nexperia 74HC4520; 74HCT4520
Dual 4-bit synchronous binary counter
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description............................................................. 3
7. Functional description................................................. 3
8. Limiting values............................................................. 4
9. Recommended operating conditions..........................4
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................6
11.1. Waveforms and test circuit........................................ 8
12. Package outline........................................................ 10
13. Abbreviations............................................................ 12
14. Revision history........................................................12
15. Legal information......................................................13
© Nexperia B.V. 2019. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 14 February 2019
74HC_HCT4520 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 5 — 14 February 2019 14 / 14