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0 0.5 1 1.5 22.5 3
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OUTPUT CURRENT(A)
EFFICIENCY (%)
VIN
CIN
10 PF
Enable
RON
See Table RFBT
CFF 0.022 PF
See Table
CSS
0.022 PF
RFBB
See Table 100 PF
LMZ12003
VOUT
FB
RON
SS
VIN
EN
GND
VOUT @ 3A
Product
Folder
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LMZ12003
SNVS636O –DECEMBER 2009–REVISED AUGUST 2015
LMZ12003 3-A Simple Switcher
®
Power Module with 20-V Maximum Input Voltage
1 Features 2 Applications
1• Integrated Shielded Inductor • Point-of-load Conversions from 5-V and 12-V
Input Rail
• Simple PCB Layout • Time-Critical Projects
• Flexible Start-up Sequencing Using External Soft-
start Capacitor and Precision Enable • Space-Constrained High Thermal Requirement
Applications
• Protection Against Inrush Currents and Faults
such as Input UVLO and Output Short Circuit • Negative Output Voltage Applications
(See AN-2027) SNVA425
• Junction Temperature Range –40°C to 125°C
• Single Exposed Pad and Standard Pinout for Easy 3 Description
Mounting and Manufacturing The LMZ12003 SIMPLE SWITCHER®power module
• Fast Transient Response for FPGAs and ASICs is an easy-to-use step-down DC-DC solution capable
• Low Output Voltage Ripple of driving up to 3-A load with exceptional power
conversion efficiency, line and load regulation, and
• Pin-to-Pin Compatible With Devices: output accuracy. The LMZ12003 is available in an
– LMZ14203/2/1 (42-V Maximum 3 A, 2 A, 1 A) innovative package that enhances thermal
– LMZ12003/2/1 (20-V Maximum 3 A, 2 A, 1 A) performance and allows for hand or machine
• Fully WEBENCH®Power Designer Enabled soldering.
• Electrical Specifications The LMZ12003 can accept an input voltage rail
between 4.5 V and 20 V and can deliver an
– 18-W Maximum Total Power Output adjustable and highly accurate output voltage as low
– Up to 3-A Output Current as 0.8 V. The LMZ12003 only requires three external
– Input Voltage Range 4.5 V to 20 V resistors and four external capacitors to complete the
– Output Voltage Range 0.8 V to 6 V power solution. The LMZ12003 is a reliable and
robust design with the following protection features:
– Efficiency up to 92% thermal shutdown, input undervoltage lockout, output
• Performance Benefits overvoltage protection, short circuit protection, output
– Operates at High Ambient Temperature With current limit, and this device allows start-up into a
No Thermal Derating prebiased output. A single resistor adjusts the
switching frequency up to 1 MHz.
– High Efficiency Reduces System Heat
Generation Device Information(1)(2)
– Low Radiated Emissions (EMI) Tested to PART NUMBER PACKAGE BODY SIZE (NOM)
EN55022 Class B Standard LMZ12003 NDW (7) 9.85 mm × 10.16 mm
– Passes 10-V/m Radiated Immunity EMI Test (1) For all available packages, see the orderable addendum at
Standard EN61000 4-3 the end of the data sheet.
(2) Peak reflow temperature equals 245°C. See SNAA214 for
more details.
Simplified Application Schematic Efficiency 12-V Input at 25°C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ12003
SNVS636O –DECEMBER 2009–REVISED AUGUST 2015
www.ti.com
Table of Contents
1 Features.................................................................. 18 Application and Implementation ........................ 11
8.1 Application Information............................................ 11
2 Applications ........................................................... 18.2 Typical Application ................................................. 11
3 Description............................................................. 19 Power Supply Recommendations...................... 17
4 Revision History..................................................... 210 Layout................................................................... 17
5 Pin Configuration and Functions......................... 310.1 Layout Guidelines ................................................. 17
6 Specifications......................................................... 310.2 Layout Examples................................................... 18
6.1 Absolute Maximum Ratings ..................................... 310.3 Power Dissipation and Thermal Considerations... 19
6.2 ESD Ratings.............................................................. 310.4 Power Module SMT Guidelines ............................ 20
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 21
6.4 Thermal Information.................................................. 411.1 Device Support...................................................... 21
6.5 Electrical Characteristics........................................... 411.2 Documentation Support ........................................ 21
6.6 Typical Characteristics ............................................. 611.3 Community Resources.......................................... 21
7 Detailed Description.............................................. 911.4 Trademarks........................................................... 21
7.1 Overview................................................................... 911.5 Electrostatic Discharge Caution............................ 21
7.2 Functional Block Diagram......................................... 911.6 Glossary................................................................ 21
7.3 Feature Description................................................... 912 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 10 Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (October 2013) to Revision O Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision M (March 2013) to Revision N Page
• Deleted 12 mils....................................................................................................................................................................... 4
• Changed 10 mils................................................................................................................................................................... 17
• Changed 10 mils................................................................................................................................................................... 20
• Added Power Module SMT Guidelines................................................................................................................................. 20
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5 Pin Configuration and Functions
NDW Package
7-Pin
Top View
Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
Enable — Input to the precision enable comparator. Rising threshold is 1.18-V nominal; 90-
EN 3 Analog mV hysteresis nominal. Maximum recommended input level is 6.5 V.
Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package
EP — Ground during operation. Must be electrically connected to pin 4 external to the package.
Feedback — Internally connected to the regulation, overvoltage, and short circuit
FB 6 Analog comparators. The regulation reference point is 0.8 V at this input pin. Connected the
feedback resistor divider between the output and ground to set the output voltage.
GND 4 Ground Ground — Reference point for all stated voltages. Must be externally connected to EP.
ON-Time Resistor — An external resistor from VIN to this pin sets the ON-time of the
RON 2 Analog application. Typical values range from 25 kΩto 124 kΩ.
Soft-Start — An internal 8-µA current source charges an external capacitor to produce the
SS 5 Analog soft-start function. This node is discharged at 200 µA during disable, overcurrent, thermal
shutdown and internal UVLO conditions.
Supply input — Nominal operating range is 4.5 V to 20 V. A small amount of internal
VIN 1 Power capacitance is contained within the package assembly. Additional external input capacitance
is required between this pin and exposed pad.
Output Voltage — Output from the internal inductor. Connect the output capacitor between
VOUT 7 Power this pin and exposed pad.
6 Specifications
6.1 Absolute Maximum Ratings (1)(2)(3)
MIN MAX UNIT
VIN, RON to GND –0.3 25 V
EN, FB, SS to GND –0.3 7 V
Junction Temperature 150 °C
Peak Reflow Case Temperature (30 sec) 245 °C
Storage Temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For soldering specifications, refer to the following document: SNOA549
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) The human body model is a 100pF capacitor discharged through a 1.5 kΩresistor into each pin. Test method is per JESD-22-114.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN 4.5 20 V
EN 0 6.5 V
Operation Junction Temperature –40 125 °C
6.4 Thermal Information LMZ12003
THERMAL METRIC(1) NDW UNIT
7 PINS
RθJA 4-layer JEDEC Printed-Circuit-Board, 100 19.3
vias, No air flow
Junction-to-ambient thermal resistance(2) °C/W
2-layer JEDEC Printed-Circuit-Board, No 21.5
air flow
RθJC(top) Junction-to-case (top) thermal resistance No air flow 1.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) RθJA measured on a 1.705-in × 3.0-in 4-layer board, with 1-oz. copper, thirty five thermal vias, no air flow, and 1-W power dissipation.
Refer to PCB layout diagrams.
6.5 Electrical Characteristics
Limits are for TJ= 25°C unless otherwise specified. Minimum and Maximum limits are ensured through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V, VOUT = 1.8 V(1).
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
SYSTEM PARAMETERS
ENABLE CONTROL
1.18
VEN EN threshold trip point VEN rising V
over the junction temperature (TJ)1.1 1.25
range of –40°C to +125°C
VEN-HYS EN threshold hysteresis VEN falling 90 mV
SOFT-START
8
ISS SS source current VSS = 0 V µA
over the junction temperature (TJ)5 11
range of –40°C to +125°C
ISS-DIS SS discharge current –200 µA
CURRENT LIMIT
4.2
DC average
ICL Current limit threshold A
over the junction temperature (TJ)
VIN= 12 V to 20 V 3.2 5.25
range of –40°C to +125°C
ON/OFF Timer
ON timer minimum pulse
tON-MIN 150 ns
width
tOFF OFF timer pulse width 260 ns
(1) EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 and layout for information on device under test.
(2) Minimum and Maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(3) Typical numbers are at 25°C and represent the most likely parametric norm.
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Electrical Characteristics (continued)
Limits are for TJ= 25°C unless otherwise specified. Minimum and Maximum limits are ensured through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V, VOUT = 1.8 V(1).
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
REGULATION AND OVERVOLTAGE COMPARATOR
VSS >+ 0.8 V 0.793
TJ= –40°C to V
over the junction temperature (TJ)
125°C 0.773 0.813
In-regulation feedback range of –40°C to +125°C
IO= 3 A
VFB voltage VSS >+ 0.8 V
TJ= 25°C 0.784 0.8 0.816
IO= 10 mA
Feedback overvoltage
VFB-OV 0.92 V
protection threshold
Feedback input bias
IFB 5 nA
current
Non-switching input
IQVFB= 0.86 V 1 mA
current
Shutdown quiescent
ISD VEN= 0 V 25 μA
current
THERMAL CHARACTERISTICS
TSD Thermal shutdown Rising 165 °C
Thermal shutdown
TSD-HYST Falling 15 °C
hysteresis
PERFORMANCE PARAMETERS
ΔVOOutput voltage ripple 8 mVPP
ΔVO/ΔVIN Line regulation VIN = 8 V to 20 V, IO= 3 A 0.01%
ΔVO/ΔVIN Load regulation VIN = 12 V 1.5 mV/A
VIN = 12 V, VO= 1.8 V, IO= 1 A 87%
ηEfficiency VIN = 12 V, VO= 1.8 V, IO= 3 A 77%
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50
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65
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75
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85
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00.5 1 1.5 2 2.5 3
OUTPUT CURRENT (A)
EFFICIENCY (%)
3.3
2.5
1.8
1.5
1.2
0.8
85°C
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5 3
OUTPUT CURRENT (A)
DISSIPATION (W)
3.3
2.5
1.8
1.5
1.2
0.8
85°C
50
55
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65
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0 0.5 1 1.5 22.5 3
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OUTPUT CURRENT(A)
EFFICIENCY (%)
0
0.5
1
1.5
2
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DISSIPATION (W)
25° C
5.0
3.3
2.5
1.8
1.5
0.8
1.2
LMZ12003
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6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 10-µF X7R Ceramic; CO= 100-µF X7R Ceramic;
TA= 25°C for efficiency curves and waveforms.
Figure 1. Efficiency 6-V Input at 25°C Figure 2. Dissipation 6-V Input at 25°C
Figure 4. Dissipation 12-V Input at 25°C
Figure 3. Efficiency 12-V Input at 25°C
Figure 6. Dissipation 6-V Input at 85°C
Figure 5. Efficiency 6-V Input at 85°C
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1.8
1.805
1.81
1.815
1.82
1.825
1.83
0 0.5 1 1.5 2 2.5 3
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
4.5
4.75
5
5.25
5.5
6
12
20
25°C
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5 3
OUTPUT CURRENT (A)
DISSIPATION (W)
5.0
3.3
2.5
1.8
1.5
1.2
0.8
85°C
50
55
60
65
70
75
80
85
90
95
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0 0.5 1 1.5 2 2.5 3
OUTPUT CURRENT (A)
EFFICIENCY (%)
5.0
3.3
2.5
1.8
1.5
1.2
0.8
85°C
1.5
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5 3
OUTPUT CURRENT (A)
DISSIPATION (W)
5.0
3.3
2.5
1.8
1.2
0.8
85°C
50
55
60
65
70
75
80
85
90
95
100
0 0.5 1 1.5 2 2.5 3
OUTPUT CURRENT (A)
EFFICIENCY (%)
5.0
3.3
2.5
1.8
1.5
1.2
0.8
85°C
LMZ12003
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 10-µF X7R Ceramic; CO= 100-µF X7R Ceramic;
TA= 25°C for efficiency curves and waveforms.
Figure 7. Efficiency 8-V Input at 85°C Figure 8. Dissipation 8-V Input at 85°C
Figure 9. Efficiency 12-V Input at 85°C Figure 10. Dissipation 12-V Input at 85°C
12 VIN 3.3 VO3 A 20 mV/div 1 μs/div
Figure 12. Output Ripple
Figure 11. Line and Load Regulation at 25°C
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4.5VIN
0
0.5
1
1.5
2
2.5
3
3.5
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
OUTPUT CURRENT (A)
VOUT = 1.8V
JA = 19.6°C/W
4.5VIN
20VIN
12VIN
LMZ12003
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 10-µF X7R Ceramic; CO= 100-µF X7R Ceramic;
TA= 25°C for efficiency curves and waveforms.
12 VIN 3.3 VO0.6-A to 3-A Step
Figure 13. Transient Response Figure 14. Thermal Derating
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0.47 éF
6.8 éHCo
CIN
Cvcc
CBST
FB
EN
SS
Vin
Linear reg
RON Timer
Css
RON
RFBT
RFBB
CFF
Regulator IC
VO
Internal
Passives
VOUT
GND
VIN 1
2
3
4
5
6
7
LMZ12003
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SNVS636O –DECEMBER 2009–REVISED AUGUST 2015
7 Detailed Description
7.1 Overview
The LMZ12003 power module is an easy-to-use step-down DC-DC solution capable of driving up to 3-A load with
exceptional power conversion efficiency, line and load regulation, and output accuracy.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 COT Control Circuit Overview
Constant ON-Time control is based on a comparator and an ON-time one-shot, with the output voltage feedback
compared with an internal 0.8-V reference. If the feedback voltage is below the reference, the main MOSFET is
turned on for a fixed ON-time determined by a programming resistor RON. RON is connected to VIN such that ON-
time is reduced with increasing input supply voltage. Following this ON-time, the main MOSFET remains off for a
minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the ON-time cycle is
repeated. Regulation is achieved in this manner.
7.3.2 Output Overvoltage Comparator
The voltage at FB is compared to a 0.92-V internal reference. If FB rises above 0.92 V the ON-time is
immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage
is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top
MOSFET ON-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain
on until inductor current falls to zero.
7.3.3 Current Limit
Current limit detection is carried out during the OFF-time by monitoring the current in the synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 4.2 A (typical) the
current limit comparator disables the start of the next ON-time period. The next switching cycle will occur only if
the FB input is less than 0.8 V and the inductor current has decreased below 4.2 A. Inductor current is monitored
during the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds 4.2 A,
further ON-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due
to the longer OFF-time.
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Feature Description (continued)
NOTE
Current limit is dependent on both duty cycle and temperature as illustrated in the graphs
in the Typical Characteristics section.
7.3.4 Thermal Protection
The junction temperature of the LMZ12003 should not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165°C (typical) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing VOto fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 145ºC (typical hysteresis = 20°C)
the SS pin is released, VOrises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require application
derating at elevated temperatures.
7.3.5 Zero Coil Current Detection
The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which
inhibits the synchronous MOSFET when its current reaches zero until the next ON-time. This circuit enables the
DCM operating mode, which improves efficiency at light loads.
7.3.6 Prebiased Start-Up
The LMZ12003 will properly start up into a prebiased output. This startup situation is common in multiple rail
logic applications where current paths may exist between different power rails during the start-up sequence. The
following scope capture shows proper behavior during this event.
Figure 15. Prebiased Start-Up
7.4 Device Functional Modes
7.4.1 Discontinuous Conduction and Continuous Conduction Modes
At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it will operate in continuous conduction mode (CCM). When operating in DCM the
switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to
zero before the end of the OFF-time. Note that during the period of time that inductor current is zero, all load
current is supplied by the output capacitor. The next ON-time period starts when the voltage on the at the FB pin
falls below the internal reference. The switching frequency is lower in DCM and varies more with load current as
compared to CCM. Conversion efficiency in DCM is maintained because conduction and switching losses are
reduced with the smaller load and lower switching frequency.
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4
5
6
7
3
2
1
EP
VOUT
FB
RON
SS
VIN
EN
GND
VIN
CIN2
10 PF
Enable
4.5V to 20V
CFF
0.022 PF
U1
CSS
0.022 PFRFBB
1.07k
LMZ12003TZ-ADJ
1.8VO @ 3A
CO1
1 PFCO2
100 PF
RON
32.4k
RENT
32.4k
RENB
11.8k
RFBT
1.37k
CIN1
1 PF
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ12003 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 3 A. The following design procedure can be used to select
components for the LMZ12003. Alternately, the WEBENCH software may be used to generate complete designs.
When generating a design, the WEBENCH software uses iterative design procedure and accesses
comprehensive databases of components. Please go to www.ti.com for more details.
8.2 Typical Application
Figure 16. Evaluation Board Schematic Diagram
8.2.1 Design Requirements
For this example the following application parameters exist.
• VIN Range = Up to 20 V
• VOUT =0.8Vto6V
• IOUT =3A
8.2.2 Detailed Design Procedure
The LMZ12003 is fully supported by WEBENCH and offers the following: component selection, electrical and
thermal simulations, as well as the build-it board for a reduction in design time. The following list of steps can be
used to manually design the LMZ12003 application.
1. Select minimum operating VIN with enable divider resistors
2. Program VOwith divider resistor selection
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Typical Application (continued)
3. Program turnon time with soft-start capacitor selection
4. Select CO
5. Select CIN
6. Set operating frequency with RON
8.2.2.1 Enable Divider, RENT and RENB Selection
The enable input provides a precise 1.18-V band-gap rising threshold to allow direct logic drive or connection to
a voltage divider from a higher enable voltage such as Vin. The enable input also incorporates 90 mV (typical) of
hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V.
For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to
limit this voltage.
The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit
will be disabled. This implements the feature of programmable under voltage lockout. This is often used in
battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for
sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at power-
up. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems
where a lower boundary of operation must be established. In the case of sequencing supplies, the divider is
connected to a rail that becomes active earlier in the power-up cycle than the LMZ12003 output rail. The two
resistors must be chosen based on the following ratio:
RENT / RENB = (VIN UVLO / 1.18V) – 1 (1)
The LMZ12003 demonstration and evaluation boards use 11.8 kΩfor RENB and 32.4 kΩfor RENT resulting in a
rising UVLO of 4.5 V. This divider presents 5.34 V to the EN input when the divider input is raised to 20 V.
The EN pin is internally pulled up to VIN and can be left floating for always-on operation.
8.2.2.2 Output Voltage Selection
Output voltage is determined by a divider of two resistors connected between VOand ground. The midpoint of
the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal
operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The main MOSFET ON-
time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage at
FB is above 0.8 V, ON-time cycles will not occur.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO= 0.8 V × (1 + RFBT / RFBB) (2)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO/ 0.8 V) - 1 (3)
These resistors must be chosen from values in the range of 1.0 kΩto 10.0 kΩ.
For VO= 0.8 V the FB pin can be connected to the output directly so long as an output preload resistor remains
that draws more than 20 µA. Converter operation requires this minimum load to create a small inductor ripple
current and maintain proper regulation when no load is present.
A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for
best transient response and minimum output ripple.
Table 1 lists the values for RFBT , RFBB , CFF and RON.
Table 1. Bill of Materials
REF DES DESCRIPTION CASE SIZE MANUFACTURER MANUFACTURER P/N
U1 SIMPLE SWITCHER PFM-7 Texas Instruments LMZ12003 TZ
Cin1 1-µF, 50-V, X7R 1206 Taiyo Yuden UMK316B7105KL-T
Cin2 10-µF, 50-V, X7R 1210 Taiyo Yuden UMK325BJ106MM-T
CO1 1-µF, 50-V, X7R 1206 Taiyo Yuden UMK316B7105KL-T
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Typical Application (continued)
Table 1. Bill of Materials (continued)
REF DES DESCRIPTION CASE SIZE MANUFACTURER MANUFACTURER P/N
CO2 100-µF, 6.3-V, X7R 1210 Taiyo Yuden JMK325BJ10CR7MM-T
RFBT 1.37 kΩ0603 Vishay Dale CRCW06031K37FKEA
RFBB 1.07 kΩ0603 Vishay Dale CRCW06031K07FKEA
RON 32.4 kΩ0603 Vishay Dale CRCW060332K4FKEA
RENT 32.4 kΩ0603 Vishay Dale CRCW060332K4FKEA
RENB 11.8 kΩ0603 Vishay Dale CRCW060311k8FKEA
CFF 22 nF, ±10%, X7R, 16 V 0603 TDK C1608X7R1H223K
CSS 22 nF, ±10%, X7R, 16 V 0603 TDK C1608X7R1H223K
8.2.2.3 Soft-Start Capacitor Selection
Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to
prevent overshoot.
Upon turnon, after all UVLO conditions have been passed, an internal 8-µA current source begins charging the
external soft-start capacitor. The soft-start time duration to reach steady-state operation is given by the formula:
tSS = VREF × CSS / Iss = 0.8 V × CSS / 8 µA (4)
This equation can be rearranged as follows:
CSS = tSS × 8 μA / 0.8 V (5)
Use of a 0.022-μF capacitor results in 2.2-ms soft-start duration. This is recommended as a minimum value.
As the soft-start input exceeds 0.8 V the output of the power stage will be in regulation. The soft-start capacitor
continues charging until it reaches approximately 3.8 V on the SS pin. Voltage levels between 0.8 V and 3.8 V
have no effect on other circuit operation. The following conditions will reset the soft-start capacitor by discharging
the SS input to ground with an internal 200-μA current sink.
• The enable input being pulled low
• Thermal shutdown condition
• Overcurrent fault
• Internal VCC UVLO (Approx 4-V input to VIN)
8.2.2.4 COSelection
None of the required COoutput capacitance is contained within the module. At a minimum, the output capacitor
must meet the worst case minimum ripple current rating of 0.5 × ILRP-P, as calculated in Equation 20. Beyond
that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum
value of 10 μF is generally required. Experimentation will be required if attempting to operate with a minimum
value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 for more detail.
Equation 17 provides a good first pass approximation of COfor load transient requirements:
CO≥ISTEP × VFB × L × VIN / (4 × VO× (VIN – VO) × VOUT-TRAN) (6)
Solving for Equation 7 yields the following:
CO≥3 A × 0.8 V × 6.8 μH × 12 V / (4 × 3.3 V × (12 V – 3.3 V) × 33 mV) (7)
≥52 μF
The LMZ12003 demonstration and evaluation boards are populated with a 100-uF 6.3-V X5R output capacitor.
Locations for extra output capacitors are provided.
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8.2.2.5 CIN Selection
The LMZ12003 module contains an internal 0.47-µF input ceramic capacitor. Additional input capacitance is
required external to the module to handle the input ripple current of the application. This input capacitance must
be located in very close proximity to the module. Input capacitor selection is generally directed to satisfy the input
ripple current requirements rather than by capacitance value. Worst case input ripple current rating is dictated by
Equation 8:
I(CIN(RMS))≊1 /2 × IO×√(D / 1-D)
where
• D ≊VO/ VIN (8)
As a point of reference, the worst case ripple current will occur when the module is presented with full load
current and when VIN = 2 × VO.
Recommended minimum input capacitance is 10-µF X7R ceramic with a voltage rating at least 25% higher than
the maximum applied input voltage for the application. TI recommends to pay attention to the voltage and
temperature deratings of the capacitor selected.
NOTE
Ripple current rating of ceramic capacitors may be missing from the capacitor data sheet
and you may have to contact the capacitor manufacturer for this rating.
If the system design requires a certain minimum value of input ripple voltage ΔVIN be maintained then Equation 9
may be used.
CIN ≥IO× D × (1 – D) / fSW-CCM ×ΔVIN (9)
If ΔVIN is 1% of VIN for a 20V input to 3.3-V output application this equals 200 mV and fSW = 400 kHz.
CIN ≥3 A × 3.3 V / 20 V × (1 – 3.3 V / 20 V) / (400000 × 0.200 V)
≥5.2 μF
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines.
8.2.2.6 RON Resistor Selection
Many designs will begin with a desired switching frequency in mind. For that purpose Equation 10 can be used.
fSW(CCM) ≊VO/ (1.3 × 10-10 × RON) (10)
This can be rearranged as
RON ≊VO/ (1.3 × 10 -10 × fSW(CCM)) (11)
The selection of RON and fSW(CCM) must be confined by limitations in the ON-time and OFF-time for the COT
Control Circuit Overview section.
The ON-time of the LMZ12003 timer is determined by the resistor RON and the input voltage VIN. It is calculated
as follows:
tON = (1.3 × 10-10 × RON) / VIN (12)
The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON must be
selected such that the ON-time at maximum VIN is greater than 150 ns. The ON-timer has a limiter to ensure a
minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by Equation 13:
fSW(MAX) = VO/ (VIN(MAX) × 150 ns) (13)
This equation can be used to select RON if a certain operating frequency is desired so long as the minimum ON-
time of 150 ns is observed. The limit for RON can be calculated as follows:
RON ≥VIN(MAX) × 150 ns / (1.3 × 10 -10) (14)
If RON calculated in Equation 11 is less than the minimum value determined in Equation 14 a lower frequency
must be selected. Alternatively, VIN(MAX) can also be limited in order to keep the frequency unchanged.
Additionally, consider the minimum OFF-time of 260 ns limits the maximum duty ratio. Larger RON (lower FSW)
should be selected in any application requiring large duty ratio.
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500 mA/Div 2.00 Ps/Div
500 mA/Div 2.00 Ps/Div
LMZ12003
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8.2.2.7 Discontinuous Conduction and Continuous Conduction Mode Selection
Operating frequency in DCM can be calculated as follows:
fSW(DCM) ≊VO× (VIN – 1) × 6.8 μH × 1.18 × 1020 × IO/ (VIN – VO) × RON2(15)
In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the
OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The
CCM operating frequency can be calculated using Equation 7.
Figure 17 is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.
VIN = 12 V, VO= 3.3 V, IO= 3 A/0.4 A 2 μs/div
Figure 17. CCM and DCM Operating Modes
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB ≊VO× (VIN – VO) / (2 × 6.8 μH × fSW(CCM) × VIN) (16)
Figure 18 is a typical waveform showing the boundary condition.
VIN = 12 V, VO= 3.3 V, IO= 0.5 A 2 μs/div
Figure 18. Transition Mode Operation
The inductor internal to the module is 6.8 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ILR). ILR can be calculated with:
ILR P-P = VO× (VIN – VO) / (6.8 µH × fSW × VIN)
where
• VIN is the maximum input voltage
• and fSW is determined from Equation 10. (17)
If the output current IOis determined by assuming that IO= IL, the higher and lower peak of ILR can be
determined. Be aware that the lower peak of ILR must be positive if CCM operation is required.
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8.2.3 Application Curves
VIN = 12 V, VOUT = 5 V
VIN = 12 V, VOUT = 5 V Figure 20. Thermal Derating Curve
Figure 19. Efficiency
Figure 21. Radiated Emissions (EN 55022 Class B) from Evaluation Board
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9 Power Supply Recommendations
The LMZ12003 device is designed to operate from an input voltage supply range between 4.5 V and 20 V. This
input supply should be well regulated and able to withstand maximum input current and maintain a stable
voltage. The resistance of the input supply rail should be low enough that an input current transient does not
cause a high enough drop at the LMZ12003 supply voltage that can cause a false UVLO fault triggering and
system reset. If the input supply is more than a few inches from the LMZ12003, additional bulk capacitance may
be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-
μF or 100-μF electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths during PCB layout.
The high current loops that do not overlap have high di/dt content that will cause observable high frequency
noise on the output pin if the input capacitor CIN1 is placed a distance away for the LMZ12003. Therefore,
physically place CIN1 asa close as possible to the LMZ12003 VIN and GND exposed pad. This will minimize
the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor
must consist of a localized top side plane that connects to the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components must be routed to the GND pin
of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior. Provide the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, RFBT and RFBB, and the feed forward capacitor CFF, must be located close to the FB
pin. Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from
RFBT, RFBB, and CFF must be routed away from the body of the LMZ12003 to minimize noise.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing
so will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to
inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with a minimum via diameter
of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep
the junction temperature below 125°C.
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
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RON
EN
SS
GND
FB
VIN
1 2 3 4 5 6 7
Top View
VIN
COUT
VOUT
RENT
RON
CSS
GND
Thermal Vias
VOUT
CIN
GND
RENB
CFF
RFBT
RFBB
GND Plane
EPAD
VIN
GND
VIN
VO
Cin1 CO1
Loop 1 Loop 2
LMZ14203 VOUT
High
di/dt
LMZ12003
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10.2 Layout Examples
Figure 22. Critical Current Loops to Minimize
Figure 23. PCB Layout Guide
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Layout Examples (continued)
Figure 24. Top View of Evaluation PCB
Figure 25. Bottom View of Evaluation PCB
10.3 Power Dissipation and Thermal Considerations
For the design case of VIN = 12 V, VO= 3.3 V, IO=3A,TAMB(MAX) = 85°C, and TJUNCTION = 125°C, the device
must see a thermal resistance from case to ambient of less than:
RθCA< (TJ-MAX – TAMB(MAX)) / PIC-LOSS – RθJC (18)
Given the typical thermal resistance from junction to case to be 1.9°C/W. Use the 85°C power dissipation curves
in the Typical Characteristics section to estimate the PIC-LOSS for the application being designed. In this
application it is 2.25 W.
RθCA< (125 – 85) / 2.25 W – 1.9 = 15.8 (19)
To reach RθCA = 15.8, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a
good estimate of the required board area covered by 1-oz. copper on both the top and bottom metal layers is:
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Power Dissipation and Thermal Considerations (continued)
Board Area_cm2> 500°C × cm2/W / RθJC (20)
As a result, approximately 31 square cm of 1-oz. copper on top and bottom layers is required for the PCB
design. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty six, 8 mils
thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an example
of a high thermal performance PCB layout, refer to the demo board application note AN-2024 SNVA422.
10.4 Power Module SMT Guidelines
The recommendations below are for a standard module surface mount assembly
• Land Pattern — Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads.
• Stencil Aperture
– For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern
– For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste — Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness — 0.125 to 0.15 mm
• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
• Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information.
• Maximum number of reflows allowed is one
Figure 26. Sample Reflow Profile
Table 2. Sample Reflow Profile Table
MAX TEMP REACHED TIME ABOVE REACHED TIME ABOVE REACHED TIME ABOVE REACHED
PROBE (°C) MAX TEMP 235°C 235°C 245°C 245°C 260°C 260°C
1242.5 6.58 0.49 6.39 0.00 – 0.00 –
2242.5 7.10 0.55 6.31 0.00 7.10 0.00 –
3241.0 7.09 0.42 6.44 0.00 – 0.00 –
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For developmental support, see the following:
WEBENCH Tool, http://www.ti.com/webench
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, (SNVA425)
•Absolute Maximum Ratings for Soldering, (SNOA549)
• AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422)
• AN-2085 LMZ23605/03, LMZ22005/03 Evaluation Board (SNVA457)
• AN-2054 Evaluation Board for LM10000 - PowerWise AVS System Controller (SNVA437)
• AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)
• AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424)
•Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214)
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMZ12003TZ-ADJ/NOPB ACTIVE TO-PMOD NDW 7 250 RoHS & Green SN Level-3-245C-168 HR -40 to 125 LMZ12003
TZ-ADJ
LMZ12003TZE-ADJ/NOPB ACTIVE TO-PMOD NDW 7 45 RoHS & Green SN Level-3-245C-168 HR -40 to 125 LMZ12003
TZ-ADJ
LMZ12003TZX-ADJ/NOPB ACTIVE TO-PMOD NDW 7 500 RoHS & Green SN Level-3-245C-168 HR -40 to 125 LMZ12003
TZ-ADJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMZ12003TZ-ADJ/NOPB TO-
PMOD NDW 7 250 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2
LMZ12003TZX-ADJ/NOP
BTO-
PMOD NDW 7 500 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMZ12003TZ-ADJ/NOPB TO-PMOD NDW 7 250 367.0 367.0 45.0
LMZ12003TZX-ADJ/NOPB TO-PMOD NDW 7 500 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2018
Pack Materials-Page 2
MECHANICAL DATA
NDW0007A
www.ti.com
TZA07A (Rev D)
TOP SIDE OF PACKAGE
BOTTOM SIDE OF PACKAGE
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