IRL540A - Fairchild Semiconductor

IRL540A

BVDSS = 100 V

RDS(on) = 0.058Ω

ID = 28 A

100

19.8

±20

522

12.1

6.5

121

0.81

- 55 to +175

300

1.24

62.5

0.5

♦ Avalanche Rugged Technol ogy

♦ Rugged Gate Oxide Technology

♦ Lower Input Capacitance

♦ Improved Gate Charge

♦ Extended Safe Operating Area

♦ Lower Leakage Current: 10µA (Max.) @ VDS = 100V

♦ Lower RDS(ON): 0.046Ω (Ty p .)

$GYDQFHG 3RZHU 026)(7

Thermal Resistance

Junction-to-Case

Case-to-Sink

Junction-to-Ambient

RθJC

RθCS

RθJA

°C/W

Characteristic Max. UnitsSymbol Typ.

FEATURES

Absolute Maximum Ratings

Drain- to-Source Volta ge

Conti nuous Drain Current (TC=25°C)

Conti nuous Drain Current (TC=100°C)

Drain Current-Pulsed (1)

Gate-t o-Source Voltage

Singl e Pulsed Aval anche Energy (2)

Avalanche Current (1)

Repetitive Avalanche Ener gy (1)

Peak Diode Recovery dv/dt (3)

Total Power Dissipati on (TC=25°C)

Linear Der ati ng Factor

Operating Junction and

Storage Temperature Range

Maxim um Lead Temp. for Soldering

Purposes, 1/8 from case for 5-seconds

Characteristic Value UnitsSymbol

IDM

VGS

EAS

IAR

EAR

dv/dt

TJ , TSTG

V/ns

W/°C

°C

VDSS V

TO-220

1.Gate 2. Drain 3. Source

Rev. B

IRL540A

100

1.0

0.1

310

145

38.4

6.2

23.3

2.0

100

-100

100

0.058

1580

390

180

1215

132

0.63

1.5

Notes;

(1) Repetitive Rati ng: Pulse Widt h Limited by Max imum Ju nction Temperatur e

(2) L=1mH, IAS=28A, VDD=25V, RG=27Ω, Starting TJ =25°C

(3) ISD ≤ 28A, di/dt ≤ 400A/µs, VDD ≤ BVDSS , Starti ng TJ =25°C

(4) Puls e Test: Pulse Width = 250 µs, Duty Cycle ≤ 2%

(5) Essentially Independent of O perating Temperat ure

1&+$11(/

32:(5 026)(7

Electrical Characteristics (TC=25°C unless otherwise specified)

Drain-Source Breakdown Voltage

Breakdown Voltage Temp. Coeff.

Gate Threshold Vo lt age

Gate-Source Leakage , Forward

Gate-Source Leakage , Reverse

CharacteristicSymbol Max. UnitsTyp.Min. Test Condition

Static Drai n-Source

On-State Resistance

Forward Transconduct ance

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Turn-On Delay Time

Rise Time

Turn-Off Delay Time

Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain ( Miller ) Charge

gfs

Ciss

Coss

Crss

td(on)

td(off)

Qgs

Qgd

BVDSS

∆BV/∆TJ

VGS(th)

RDS(on)

IGSS

IDSS

V/°C

µA

Ω

VGS=0V,ID=250µA

ID=250µA

See Fig 7

VDS=5V,ID=250µA

VGS=20V

VGS=-20V

VDS=100V

VDS=80V,TC=150°C

VGS=5V,ID=14A (4)

VDS=40V,ID=14A (4)

VDD=50V,ID=28A,

RG=4.6Ω

See Fig 13

(4) (5)

VDS=80V,VGS=5V,

ID=28A

See Fig 6 & Fig 12

(4) (5)

Drain- to-Source Leaka ge Current

VGS=0V,VDS=25V,f =1MHz

See Fig 5

Source-Drain Diode Ratings and Characteristics

Continuous Source Current

Pulsed- S ou rce Current (1)

Diode Forwar d Volta ge (4)

Reverse Recovery T ime

Reverse Recovery Ch arge

ISM

VSD

trr

Qrr

CharacteristicSymbol Max. UnitsTyp.Min. Test Condition

µC

Integral reverse pn -diode

in the MOSFET

TJ=25°C,IS=28A,VGS=0V

TJ=25°C,IF=28A

diF/dt=100A/µs (4)

IRL540A

10-1 100101

100

101

102

@ Notes :

1. 250

µs Pulse Test

2. TC = 25 oC

V GS

To p : 7 .0 V

6.0 V

5.5 V

5.0 V

4.5 V

4.0 V

3.5 V

B o ttom : 3 .0 V

ID , Drain Current [A]

DS , Drain-Source Voltage [V] 0246810

100

101

102

25 oC

175

- 55 oC

@ Notes :

1. VGS = 0 V

2. VDS = 40 V

3. 250 µs Pulse Test

, Drain Current [A]

VGS , Gate-Source Voltage [V]

0 30 60 90 120

0.00

0.02

0.04

0.06

0.08

@ Note : TJ = 25 oC

GS = 10 V

GS = 5 V

RDS(on) , [ Ω]

Drain-Source On-Resistance

, Drain Current [A] 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

100

101

102

175

25 oC

@ Notes :

1. VGS = 0 V

2. 250

µs Pulse Test

IDR , Reverse Drain Current [A]

SD , Source-Drain Voltage [V]

0 8 16 24 32 40

DS = 80 V

DS = 50 V

DS = 20 V

@ Notes : ID = 28 A

VGS , Gate-Source Voltage [V]

, Total Gate Charge [nC]

100101

500

1000

1500

2000

2500C

iss= Cgs+ Cgd ( C

ds= shorted

)

oss= Cds+ Cgd

rss= Cgd

@ Notes :

1. VGS = 0 V

2. f = 1 MHz

C rss

C oss

C iss

Capacitance [pF]

VDS , Drain-Source Voltage [V]

1&+$11(/

32:(5 026)(7

Fig 1. Output Characteristics Fig 2. Transfer Characteristics

Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Cap acitance vs. D rain- Sour ce Voltage

Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Cur rent

IRL540A

-75 -50 -25 0 25 50 75 100 125 150 175 200

0.8

0.9

1.0

1.1

1.2

@ Notes :

1. VGS = 0 V

2. ID = 250 µA

BVDSS , (Normalized)

Drain-Source Breakdown Voltage

J , Junction Temperature [oC]

100101102

10-1

100

101

102

100

µs

1 ms

10 ms

@ Notes :

1. TC = 25 oC

2. TJ = 175 oC

3. Single Pulse

Operation in This Area

is Limited by R DS(on)

ID , Drain Current [A]

DS , Drain-Source Voltage [V] 25 50 75 100 125 150 175

ID , Drain Current [A]

Tc , Case Temperature [oC]

10-5 10-4 10-3 10-2 10-1 100101

10-2

10-1

100

single pulse

0.2

0.1

0.01

0.02

0.05

D=0.5

@ Notes :

1. ZθJC(t)=1.24 oC/W Max.

2. Duty Factor, D=t1/t2

3. TJM-TC=PDM*ZθJC(t)

ZθJC

(t) , Ther mal Resp onse

t1 , Square W ave Puls e Du ration [sec]

-75 -50 -25 0 25 50 75 100 125 150 175 200

0.0

0.5

1.0

1.5

2.0

2.5

3.0

@ Notes :

1. VGS = 5 V

2. ID = 14 A

RDS(on) , (Normalized)

Drain-Source On-Resistance

, Junction Temperature [o

1&+$11(/

32:(5 026)(7

Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature

Fig 11. Thermal Response

Fig 10. Max. Drain Current vs. Case TemperatureFig 9. Max. Safe Operating Area

PDM

t1t2

IRL540A

1&+$11(/

32:(5 026)(7

Fig 12. Gate Charge Test Circuit & Waveform

Fig 13. Res istive Swit ching Test Circuit & Wavefo rms

Fig 14. Unclamped I nductive Sw itching T est Circuit & Waveforms

EAS =L

L IAS2

----

1--------------------

BVDSS -- VDD

BVDSS

Vin

Vout

10%

90%

td(on) tr

t on t off

td(off) tf

Charge

VGS

10V

Qgs Qgd

Vary t

to obtain

required peak ID

VDD

VDS

t p

DUT

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

VDD

( 0.5 rated VDS )

10V

Vout

Vin

DUT

3mA

VGS

Current Sampling (IG)

Resistor C urre nt Sampling (ID)

Resistor

DUT

VDS

300nF

50kΩ

200nF

12V

Same Type

as DUT

Current Regulator

R1R2

IRL540A

1&+$11(/

32:(5 026)(7

Fig 15. Peak Diode Recovery dv/dt Test Cir c uit & Waveforms

10V

VGS

( Driver )

I S

( DUT )

VDS

( DUT )

VDD

Body Diode

Forw ard Voltage D rop

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pulse Period

--------------------------

DUT

VDS

I S

Driver

VGS

RGSame Type

as DUT

VGS dv/dt controll ed by RG

IS controlled by Duty Factor D

VDD

Dimensions in Millimeters

September 1999, Rev B

TO-220 Package Dimensions

4.50 ±0.20

9.90 ±0.20

1.52 ±0.10

0.80 ±0.10 2.40 ±0.20

10.00 ±0.20

1.27 ±0.10

ø3.60 ±0.10

(8.70)

2.80 ±0.1015.90 ±0.20

10.08 ±0.30 18.95MAX.

(1.70)

(3.70)(3.00)

(1.46)

(1.00)

(45°)

9.20 ±0.2013.08 ±0.20

1.30 ±0.10

1.30 +0.10

–0.05

0.50 +0.10

–0.05

2.54TYP

[2.54 ±0.20]2.54TYP

[2.54 ±0.20]

TO-220 (FS PKG CODE AE)

TRADEMARKS

ACEx™

CoolFET™

CROSSVOLT™

E2CMOSTM

FACT™

FACT Quiet Series™

FAST®

FASTr™

GTO™

HiSeC™

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT ST A TUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Formative or

In Design

First Production

Full Production

Not In Production

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS P ATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

TinyLogic™

UHC™

VCX™

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench™

QFET™

QS™

Quiet Series™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8