To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
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Rev.1.40 Dec 08, 2006 Page 1 of 45
REJ03B0144-0140
R8C/1A Group, R8C/1B Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1. Overview
These MCUs are fabricated using the high-performance silicon gate CMOS process, embedding the R8C/
T iny Series CPU core, and is packaged in a 20-pin molded-plastic LSSOP, SDIP or a 28-pin plastic molded-
HWQFN. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of
address space, they are capable of executing instructions at high speed.
Furthermore, the R8C/1B Group has on-chip data flash ROM (1 KB × 2 blocks).
The difference between the R8C/1A Group and R8C/1B Group is only the presence or absence of data
flash ROM. Their peripheral functions are the same.
1.1 Applications
Electric household appliances, office equipment, housing equipment (sensors, security systems),
portable equipment, general industrial equ ipment, audio equipment, etc.
REJ03B0144-0140
Rev.1.40
Dec 08, 2006
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 2 of 45
REJ03B0144-0140
1.2 Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/1A Group and Table 1.2 outlines the
Functions and Specifications for R8C/1B Group.
NOTE:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Please contact Renesas Technology sales offices for the Y version.
Table 1.1 Functions and Specifications for R8C/1A Group
Item Specification
CPU Number of fundamental
instructions 89 instructions
Minimum instruction execution
time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity See Table 1.3 Product Information for R8C/1A Group
Peripheral
Functions Ports I/O ports: 13 pins (including LED drive port)
Input port: 3 pins
LED drive ports I/O ports: 4 pins
Timers Timer X: 8 bits × 1 channel, timer Z: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits × 1 channel
(Input capture and output compare circuits)
Serial interfaces 1 channel
Clock synchronous serial I/O, UART
1 channel
UART
Clock synchronous serial interface 1 channel
I2C bus Interface(1)
Clock synchronous serial I/O with chip select (SSU)
A/D converter 10-bit A/D converter: 1 circuit, 4 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
Reset start selectable, count source protection mode
Interrupts
Internal: 11 sources, External: 4 sources, Software: 4 sources,
Priority level s : 7 le ve l s
Clock generati on circuits 2 circuits
• Main clock oscillatio n circuit (with o n-chip feed back resistor)
• On-chip oscill ator (high speed, low speed)
High-speed on-chip oscillator has a frequency adjustment
function
Oscillation stop detection function Main clock oscillation stop detection function
Voltage detection circuit On-chip
Power-on reset circuit On-chip
Electric
Characteristics Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Current consumption Typ . 9 m A
(VCC = 5.0 V, f(XIN) = 20 MHz, A/D converter stopped)
Typ. 5 mA
(VCC = 3.0 V, f(XIN) = 10 MHz, A/D converter stopped)
Typ. 35 µA (VCC = 3.0 V, wait mode, peripheral clock off)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure
endurance 100 times
Operating Ambient Temperature -20 to 85°C
-40 to 85°C (D version)
-20 to 105°C (Y version) (2)
Package 20-pin molded-plastic LSSOP
20-pin molded-plastic SDIP
28-pin molded-plastic HWQFN
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 3 of 45
REJ03B0144-0140
NOTE:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Please contact Renesas Technology sales offices for the Y version.
Table 1.2 Functions and Specifications for R8C/1B Group
Item Specification
CPU Number of fundamental
instructions 89 instructions
Minimum instruction execution
time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity See Table 1. 4 Product Information for R8C/1B Group
Peripheral
Functions Ports I/O ports: 13 pins (including LED drive port)
Input port: 3 pins
LED drive po r ts I/O port s: 4 pi ns
Timers Timer X: 8 bits × 1 channel, timer Z: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits × 1 channel
(Input capture and output compare circuits)
Serial interfaces 1 channel
Clock synchronous serial I/O, UART
1 channel
UART
Clock synchronous serial interface 1 channel
I2C bus Interface(1)
Clock synchronous serial I/O with chip select (SSU)
A/D converter 10-bit A/D converter: 1 circuit, 4 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
Reset start selectable, count source protection mode
Interrupts
Internal: 11 sources, External: 4 sources, Software: 4 sources,
Priority levels: 7 levels
Clock generation circuits 2 circuits
• Main clock generation circuit (with on-chip feedback
resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chi p oscillator has a frequency a djustment
function
Oscillation stop detection function Main clock oscillation stop detection function
Voltage detection circuit On-chip
Power on reset circuit On-chip
Electric
Characteristics Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Current consumption Typ. 9 mA
(VCC = 5.0 V, f(XIN) = 20 MHz, A/D converter stopped)
Typ. 5 mA
(VCC = 3.0 V, f(XIN) = 10 MHz, A/D converter stopped)
Ty p. 35 µA (VCC = 3.0 V, wait mode, peripheral clock off)
Ty p. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure
endurance 10,000 times (data flash)
1,000 times (program ROM)
Operating Ambient Temperature -20 to 85°C
-40 to 85°C (D version)
-20 to 105°C (Y version) (2)
Package 20-pin molded-plastic LSSOP
20-pin molded-plastic SDIP
28-pin molded-plastic HWQFN
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 4 of 45
REJ03B0144-0140
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
Figure 1.1 Block Diagram
A/D converter
(10 bits × 4 channels)
UART or
clock synchronous serial I/O
(8 bits × 1 channel)
R8C/Tiny Series CPU core
8413
Timers
Timer X (8 bits)
Timer Z (8 bits)
Time r C (16 bits)
System clock generator
XIN-XOUT
High-speed on-chip
oscillator
Low-spee d on -c h i p
oscillator
Memory
Watchdog timer
(15 bits)
ROM(1)
RAM(2)
Multiplier
R0H R0L
R1H R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports Port P1 Port P3 Port P4
NOTES:
1. ROM siz e v ari e s with MCU type.
2. RAM size varies with MCU type.
UART
(8 bits × 1 channel) SSU (8 bits × 1 channel)
or I2C bus
Peripheral Function s
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 5 of 45
REJ03B0144-0140
1.4 Product Information
Table 1.3 list s Product Information fo r R8C/1A Grou p and Table 1.4 lists Prod uct Infor mation for R8C/1B
Group.
NOTE:
1. The user ROM is programmed before shipment.
Table 1.3 Product Information for R8C/1A Group Current of October 2006
Type No. ROM Capacity RAM Capacity Package Type Remarks
R5F211A1SP 4 Kbytes 384 bytes PLSP0020JB-A
R5F211A2SP 8 Kbytes 512 bytes PLSP0020JB-A
R5F211A3SP 12 Kbytes 768 bytes PLSP0020JB-A
R5F211A4SP 16 Kbytes 1 Kbyte PLSP0020JB-A
R5F211A1DSP 4 Kbytes 384 bytes PLSP0020JB-A D version
R5F211A2DSP 8 Kbytes 512 bytes PLSP0020JB-A
R5F211A3DSP 12 Kbytes 768 by te s PLSP0020JB-A
R5F211A4DSP 16 Kbytes 1 Kbyte PLSP0020JB-A
R5F211A1DD 4 Kbytes 384 bytes PRDP0020BA -A
R5F211A2DD 8 Kbytes 512 bytes PRDP0020BA -A
R5F211A3DD 12 Kbytes 768 bytes PRDP0020BA -A
R5F211A4DD 16 Kbytes 1 Kbyte PRDP0020BA-A
R5F211A2NP 8 Kbytes 512 bytes PWQN0028KA-B
R5F211A3NP 12 Kbytes 768 bytes PWQN0028KA-B
R5F211A4NP 16 Kbytes 1 Kbyte PWQN0028KA-B
R5F211A1XXXSP 4 Kbytes 384 bytes PLSP0020JB-A
Factory programming product
(1)
R5F211A2XXXSP 8 Kbytes 512 bytes PLSP0020JB-A
R5F211A3XXXSP 12 Kbytes 768 bytes PLSP0020JB-A
R5F211A4XXXSP 16 Kbytes 1 Kbyte PLSP0020JB-A
R5F211A1DXXXSP 4 Kbytes 384 bytes PLSP0020JB-A D version
R5F211A2DXXXSP 8 Kbytes 512 bytes PLSP0020JB-A
R5F211A3DXXXSP 12 Kbytes 768 bytes PLSP0020JB-A
R5F211A4DXXXSP 16 Kbytes 1 Kbyte PLSP0020JB-A
R5F211A1XXXDD 4 Kbytes 384 bytes PRDP0020BA-A
Factory programming product
(1)
R5F211A2XXXDD 8 Kbytes 512 bytes PRDP0020BA-A
R5F211A3XXXDD 12 Kbytes 76 8 bytes PRD P00 20BA-A
R5F211A4XXXDD 16 Kbytes 1 Kbyte PRDP0020BA-A
R5F211A2XXXNP 8 Kbytes 512 bytes PWQN0028KA-B
R5F211A3XXXNP 12 Kbytes 768 bytes PWQN0028KA-B
R5F211A4XXXNP 16 Kbytes 1 Kbyte PWQN0028KA-B
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 6 of 45
REJ03B0144-0140
Figure 1.2 Type Number, Memory Size, and Package of R8C/1A Group
Type No. R 5 F 21 1A 4 D XXX SP
Package type:
SP: PLSP0020JB-A
DD: PRDP0020BA - A
NP: PWQN0028KA-B
ROM number
Classification
D: Operating ambient temperature -40°C to 85°C
No Symbol: Operating ambient te mperature -20°C to 85°C
Y: Operating ambient temperature -20°C to 105°C (Note)
ROM capacity
1: 4 KB
2: 8 KB
3: 12 KB
4: 16 KB
R8C/1A Group
R8C/Tiny Se ri es
Memory type
F: Flash memory version
Renesas MCU
Renesas sem i c ond uc t o rs
NOTE: Pleas e con t act Renesas Techno l ogy s ales offices f or t he Y ver s i on.
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 7 of 45
REJ03B0144-0140
NOTE:
1. The user ROM is programmed before shipment.
Table 1.4 Product Information for R8C/1B Group Current of October 2006
Type No. ROM Capacity RAM
Capacity Package Type Remarks
Program ROM Data Flash
R5F211B1SP 4 Kbytes 1 Kbyte × 2 384 bytes PLSP0020JB-A
R5F211B2SP 8 Kbytes 1 Kbyte × 2 512 bytes PLSP0020JB-A
R5F211B3SP 12 Kbytes 1 Kbyte × 2 768 bytes PLSP0020JB-A
R5F211B4SP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLSP0020JB-A
R5F211B1DSP 4 Kbytes 1 Kbyte × 2 384 bytes PLSP0020JB-A D version
R5F211B2DSP 8 Kbytes 1 Kbyte × 2 512 bytes PLSP0020JB-A
R5F211B3DSP 12 Kbytes 1 Kbyte × 2 768 bytes PLSP0020JB-A
R5F211B4DSP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLSP0020JB-A
R5F211B1DD 4 Kbytes 1 Kbyte × 2 384 bytes PRDP0020BA-A
R5F211B2DD 8 Kbytes 1 Kbyte × 2 512 bytes PRDP0020BA-A
R5F211B3DD 12 Kbytes 1 Kbyte × 2 768 bytes PRDP0020BA-A
R5F211B4DD 16 Kbytes 1 Kbyte × 2 1 Kbyte PRDP0020BA-A
R5F211B2NP 8 Kbytes 1 Kbyte × 2 512 bytes PWQN0028KA-B
R5F211B3NP 12 Kbytes 1 Kbyte × 2 768 bytes PWQN0028KA-B
R5F211B4NP 16 Kbytes 1 Kbyte × 2 1 Kbyte PWQN0028KA-B
R5F211B1XXXSP 4 Kbytes 1 Kbyte × 2 384 bytes PLSP0020JB-A Factory programming
product (1)
R5F211B2XXXSP 8 Kbytes 1 Kbyte × 2 512 bytes PLSP0020JB-A
R5F211B3XXXSP 12 Kbytes 1 Kbyte × 2 768 bytes PLSP0020JB-A
R5F211B4XXXSP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLSP0020JB-A
R5F211B1DXXXSP
4 Kbytes 1 Kbyte × 2 384 bytes PLSP0020JB-A D version
R5F211B2DXXXSP
8 Kbytes 1 Kbyte × 2 512 bytes PLSP0020JB-A
R5F211B3DXXXSP
12 Kbytes 1 Kbyte × 2 768 bytes PLSP0020JB-A
R5F211B4DXXXSP
16 Kbytes 1 Kbyte × 2 1 Kbyte PLSP0020JB-A
R5F211B1XXXDD 4 Kbytes 1 Kbyte × 2 384 bytes PRDP0020BA-A Factory programming
product (1)
R5F211B2XXXDD 8 Kbytes 1 Kbyte × 2 512 bytes PRDP0020BA-A
R5F211B3XXXDD 12 Kbytes 1 Kbyte × 2 768 bytes PRDP0020BA-A
R5F211B4XXXDD 16 Kbytes 1 Kbyte × 2 1 Kbyte PRDP0020BA-A
R5F211B2XXXNP 8 Kbytes 1 Kbyte × 2 512 bytes PWQN0028KA-B
R5F211B3XXXNP 12 Kbytes 1 Kbyte × 2 768 bytes PWQN0028KA-B
R5F211B4XXXNP 16 Kbytes 1 Kbyte × 2 1 Kbyte PWQN0028KA-B
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 8 of 45
REJ03B0144-0140
Figure 1.3 Type Number, Memory Size, and Package of R8C/1B Group
Type No. R 5 F 21 1B 4 D XXX SP
Package type:
SP: PLSP0020JB-A
DD: PRDP0020BA-A
NP: PWQN0028KA-B
ROM number
Classification
D: Operating ambient temperature -40°C to 85°C
No Symbol: Ope rating ambient tem per at u re -20 °C to 85°C
Y: Operating ambient temperature -20°C to 105°C (Note)
ROM capacity
1: 4 KB
2: 8 KB
3: 12 KB
4: 16 KB
R8C/1B Group
R8C/Tiny Series
Memory Type
F: Flas h mem ory v er s i on
Renesas MCU
Renesas semiconductors
NOTE: Please contact Renesas Technology sales offices for the Y version.
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 9 of 45
REJ03B0144-0140
1.5 Pin Assignments
Figure 1.4 shows Pin Assignments for PLSP0020JB-A Package (Top View), Figure 1.5 shows Pin
Assignments for PRDP0020BA-A Package (Top View) and Figure 1.6 shows Pin Assignments for
PWQN0028KA-B Package (Top View).
Figure 1.4 Pin Assignments for PLSP0020JB-A Package (Top View)
1
2
3
4
5
6
7
8
9
10
20
P3_4/SCS/SDA/CMP1_1
19
P3_3/TCIN/INT3/SSI00/CMP1_0
18 P1_0/KI0/AN8/CMP0_0
17 P1_1/KI1/AN9/CMP0_1
16 P4_2/VREF
15 P1_2/KI2/AN10/CMP0_2
14 P1_3/KI3/AN11/TZOUT
13 P1_4/TXD0
12 P1_5/RXD0/CNTR01/INT11
11 P1_6/CLK0/SSI01
P3_5/SSCK/SCL/CMP1_2
P3_7/CNTR0/SSO/TXD1
RESET
XOUT/P4_7(1)
VSS/AVSS
XIN/P4_6
VCC/AVCC
MODE
P4_5/INT0/RXD1
P1_7/CNTR00/INT10
PIN assignments (top view)
Package: PLSP0020JB-A (20P2F-A)
R8C/1A Group
R8C/1B Group
NOTE:
1. P4_7 is an input-only port.
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 10 of 45
REJ03B0144-0140
Figure 1.5 Pin Assignme nts for PRDP0020BA -A Pac k age (Top View)
1
2
3
4
5
6
7
8
9
10
20
P3_4/SCS/SDA/CMP1_1
19
P3_3/TCIN/INT3/SSI00/CMP1_0
18 P1_0/KI0/AN8/CMP0_0
17 P1_1/KI1/AN9/CMP0_1
16 P4_2/VREF
15 P1_2/KI2/AN10/CMP0_2
14 P1_3/KI3/AN11/TZOUT
13 P1_4/TXD0
12 P1_5/RXD0/CNTR01/INT11
11 P1_6/CLK0/SSI01
P3_5/SSCK/SCL/CMP1_2
P3_7/CNTR0/SSO/TXD1
RESET
XOUT/P4_7(1)
VSS/AVSS
XIN/P4_6
VCC/AVCC
MODE
P4_5/INT0/RXD1
P1_7/CNTR00/INT10
R8C/1A Group
R8C/1B Group
Package: PRDP0020BA-A (20P4B)
NOTE:
1. P4_7 is an input-only port.
PIN assignments (top view)
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 11 of 45
REJ03B0144-0140
Figure 1.6 Pin Assignments for PWQN0028KA-B Package (Top View)
P1_4/TXD0
P1_5/RXD0/CNTR01/INT11
P1_6/CLK0/SSI01
P1_7/CNTR00/INT10
P4_5/INT0/RXD1
MODE
VCC/AVCC
P1_1/AN9/KI1/CMP0_1
P1_0/AN8/KI0/CMP0_0
PIN Assignment (top view)
Package: PWQN0028KA- B(28PJW- B)
R8C/1A Group
R8C/1B Group
14
13
12
11
10
9
8
22
23
24
25
26
27
28
P3_3/TCIN/INT3/SSI00/CMP1_0
P3_4/SCS/SDA/CMP1_1
P3_5/SSCK/SCL/CMP1_2
P3_7/CNTR0/SSO/TXD1
RESET
1234567
21 20 19 18 17 16 15
NC
XOUT/P4_7(1)
VSS/AVSS
NC
NC
XIN/P4_6
NC
P1_3/AN11/KI3/TZOUT
P1_2/AN10/KI2/CMP0_2
NC
NC
NC
P4_2/VREF
NC
NOTES:
1. P4_7 is a port for the input.
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 12 of 45
REJ03B0144-0140
1.6 Pin Functions
Table 1.5 lists Pin Functions, Table 1.6 lists Pin Name Information by Pin Number of PLSP0020JB-A,
PRDP0020BA-A Packages and Table 1.7 lists Pin Name Information by Pin Number of PWQN0028KA-
B Package.
I: Input O : Output I/O: Input and ou tp u t
Table 1.5 Pin Functions
Type Symbol I/O Type Description
Power Supply Input VCC, VSS I Apply 2.7 V to 5.5 V to the VCC pin.
Apply 0 V to the VSS pin.
Analog Power
Supply Input AVCC, AVSS I Power supply for the A/D converter
Connect a capacitor between AVCC and AVSS.
Reset Input RESET I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor.
Main Clock Input XIN I These pins are provided for main clock generation
circuit I/O. Connect a ceramic resonator or a
crystal oscillator between the XIN and XOUT pins.
To use an external clock, input it to the XIN pin and
leave the XOUT pin open.
Main Clock Output XOUT O
INT Interrupt INT0, INT1, INT3 I INT interrupt input pins
Key Input Interrupt KI0 to KI3 I Key input interrupt input pins
Timer X CNTR0 I/O T i mer X I/O pin
CNTR0 O Timer X output pin
Timer Z TZOUT O Timer Z output pin
Timer C TCIN I Timer C input pin
CMP0_0 to CMP0_2,
CMP1_0 to CMP1_2 O Timer C output pins
Serial Interface CLK0 I/O Transfer clock I/O pin
RXD0, RXD1 I Serial data input pins
TXD0, TXD1 O Serial data output pins
Clock synchronous
serial I/O with chip
select (SSU)
SSI00, SSI01 I/O Data I/O pin.
SCS I/O Chip-select signal I/O pin
SSCK I/O Clock I/O pin
SSO I/O Data I/O pin
I2C bus Interface SCL I/O Clock I/O pin
SDA I/O Data I/O pin
Reference Voltage
Input VREF I Reference voltage input pin to A/D converter
A/D Converter AN8 to AN11 I Analog input pins to A/D converter
I/O Port P1_0 to P1_7,
P3_3 to P3_5, P3_7,
P4_5
I/O CMOS I/O ports. Each port has an I/O select
direction register, allowi ng each pin in the port to
be directed for input or output individually.
Any port set to input can be set to use a pull-up
resistor or not by a program.
P1_0 to P1_3 also function as LED drive ports.
Input Port P4_2, P4_6, P4_7 I Input-only ports
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 13 of 45
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Table 1.6 Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages
Pin
Number Control
Pin Port
I/O Pin Functions for Peripheral Modules
Interrupt Timer Serial
Interface
Clock
Synchronous
Serial I/O with
Chip Select
I2C bus
Interface A/D
Converter
1 P3_5 CMP1_2 SSCK SCL
2P3_7
CNTR0 TXD1 SSO
3RESET
4XOUTP4_7
5 VSS/AVSS
6XINP4_6
7VCC/AVCC
8MODE
9P4_5
INT0 RXD1
10 P1_7 INT10 CNTR00
11 P1_6 CLK0 SSI01
12 P1_5 INT11 CNTR01 RXD0
13 P1_4 TXD0
14 P1_3 KI3 TZOUT AN11
15 P1_2 KI2 CMP0_2 AN10
16 VREF P4_2
17 P1_1 KI1 CMP0_1 AN9
18 P1_0 KI0 CMP0_0 AN8
19 P3_3 INT3 TCIN/
CMP1_0 SSI00
20 P3_4 CMP1_1 SCS SDA
R8C/1A Group, R8C/1B Group 1. Overview
Rev.1.40 Dec 08, 2006 Page 14 of 45
REJ03B0144-0140
Table 1.7 Pin Name Information by Pin Number of PWQN0028KA-B Package
Pin
Number Control
Pin Port
I/O Pin Functions for Peripheral Modules
Interrupt Timer Serial
Interface
Clock
Synchronous
Serial I/O with
Chip Select
I2C bus
Interface A/D
Converter
1NC
2XOUTP4_7
3 VSS/AVSS
4NC
5NC
6XINP4_6
7NC
8VCC/AVCC
9MODE
10 P4_5 INT0 RXD1
11 P1_7 INT10 CNTR00
12 P1_6 CLK0 SSI01
13 P1_5 INT11 CNTR01 RXD0
14 P1_4 TXD0
15 NC
16 P1_3 KI3 TZOUT AN11
17 P1_2 KI2 CMP0_2 AN10
18 NC
19 NC
20 VREF P4_2
21 NC
22 P1_1 KI1 CMP0_1 AN9
23 P1_0 KI0 CMP0_0 AN8
24 P3_3 INT3 TCIN/CMP1_0 SSI00
25 P3_4 CMP1_1 SCS SDA
26 P3_5 CMP1_2 SSCK SCL
27 P3_7 CNTR0 TXD1 SSO
28 RESET
R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU)
Rev.1.40 Dec 08, 2006 Page 15 of 45
REJ03B0144-0140
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB
configure a re gis ter ban k. There are two sets of register bank.
Figure 2.1 CPU Register
R2
b31 b15 b8b7 b0
Data registers (1)
Address registers (1)
R3 R0H (high-order of R0)
R2
R3
A0
A1
INTBHb15b19 b0
INTBL
FB Frame base register (1)
The 4 high order bits of INTB are INTBH and
the 16 low bits of INTB are INTBL.
Interrupt table register
b19 b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Rese rved bit
Processor interrupt priority level
Rese rved bit
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
NOTE:
1. These registers comprise a register bank. There are two register banks.
R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU)
Rev.1.40 Dec 08, 2006 Page 16 of 45
REJ03B0144-0140
2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit re gister for transfer, arithmetic , and logic operatio ns. The same applie s to R1 to R3. R0
can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data
registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-
bit data register (R2R0). R3R1 is analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
It is also used for transfer and arithmetic and logic operations. A1 is analogous to A0. A1 can be
combined with A0 and used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch
between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bits that have been generated by the arithmetic and
logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherw ise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Regi ster bank 1 is selecte d when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when the operation results in an overflow; otherwise to 0.
R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU)
Rev.1.40 Dec 08, 2006 Page 17 of 45
REJ03B0144-0140
2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I
flag is set to 0 when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide, assigns processo r inte rr up t priority lev els from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R8C/1A Group, R8C/1B Group 3. Memory
Rev.1.40 Dec 08, 2006 Page 18 of 45
REJ03B0144-0140
3. Memory
3.1 R8C/1A Group
Figure 3.1 is a Memory Map of R8C/1A Group. The R8C/1A Group has 1 Mbyte of address space from
addresses 00000h to FFFFFh.
The internal ROM is allocated lower addresse s, beginning with address 0FFFFh. For example, a 16 -
Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh . They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses, beginning with a ddress 00400h. For example, a 1-
Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only
for storing data but also for calling subroutines and as stacks when interrupt requests are
acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated here. All addresses within the SFR, which have nothing allocated are
reserved fo r fut ur e us e an d ca nn ot be ac cessed by users.
Figure 3.1 Memory Map of R8C/1A Group
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer•oscillation stop detection•voltage monitor 2
Address break
(Reserved)
Reset
FFFFFh
0FFFFh
0YYYYh
0XXXXh
00400h
002FFh
00000h
Internal ROM
Expanded area
Internal RAM
SFR
(See 4. Special Function
Registers (SFRs))
0FFFFh
0FFDCh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Part Number Internal ROM Internal RAM
Size Address
0YYYYh
R5F211A4SP, R5F211A4DSP, R5F211A4DD, R5F211A4NP,
R5F211A4XXXSP, R5F211A4DXXXSP, R5F211A4XXXDD,
R5F211A4XXXNP
R5F211A3SP, R5F211A3DSP, R5F211A3DD, R5F211A3NP,
R5F211A3XXXSP, R5F211A3DXXXSP, R5F211A3XXXDD,
R5F211A3XXXNP
R5F211A2SP, R5F211A2DSP, R5F211A2DD, R5F211A2NP,
R5F211A2XXXSP, R5F211A2DXXXSP, R5F211A2XXXDD,
R5F211A2XXXNP
R5F211A1SP, R5F211A1DSP, R5F211A1DD,
R5F211A1XXXSP, R5F211A1DXXXSP, R5F211A1XXXDD
16 Kbytes
12 Kbytes
8 Kbytes
4 Kbytes
0C000h
0D000h
0E000h
0F000h
1 Kbyte
768 bytes
512 bytes
384 bytes
007FFh
006FFh
005FFh
0057Fh
Size Address
0XXXXh
R8C/1A Group, R8C/1B Group 3. Memory
Rev.1.40 Dec 08, 2006 Page 19 of 45
REJ03B0144-0140
3.2 R8C/1B Group
Figure 3.2 is a Memory Map of R8C/1B Group. The R8C/1B Group has 1 Mbyte of address space from
addresses 00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For
example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh . They store the starting
address of each interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-
Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only
for storing data but also for calling subroutines and as stacks when interrupt requests are
acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated here. All addresses within the SFR, which have nothing allocated are
reserved fo r fut ur e us e an d ca nn ot be ac cessed by users.
Figure 3.2 Memory Map of R8C/1B Group
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer • oscillation stop detection • voltage monitor 2
Address break
(Reserved)
Reset
FFFFFh
0FFFFh
0YYYYh
0XXXXh
00400h
002FFh
00000h
Internal ROM
(program ROM)
Expanded area
Internal RAM
SFR
(See 4. Special Function
Registers (SFRs))
0FFFFh
0FFDCh
02BFFh
02400h Internal ROM
(data Flash)(1)
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
Part Number Internal ROM Internal RAM
Size Address
0YYYYh
R5F211B4SP, R5F211B4DSP, R5F211B4DD, R5F211B4NP,
R5F211B4XXXSP, R5F211B4DXXX SP, R5F211B4XXX DD,
R5F211B4XXXNP
R5F211B3SP, R5F211B3DSP, R5F211B3DD, R5F211B3NP,
R5F211B3XXXSP, R5F211B3DXXX SP, R5F211B3XXX DD,
R5F211B3XXXNP
R5F211B2SP, R5F211B2DSP, R5F211B2DD, R5F211B2NP,
R5F211B2XXXSP, R5F211B2DXXX SP, R5F211B2XXX DD,
R5F211B2XXXNP
R5F211B1SP, R5F211B1DSP, R5F211B1DD,
R5F211B1XXXSP, R5F211B1DXXX SP, R5F211B1XXX DD
16 Kbytes
12 Kbytes
8 Kbytes
4 Kbytes
0C000h
0D000h
0E000h
0F000h
1 Kbyte
768 bytes
512 bytes
384 bytes
007FFh
006FFh
005FFh
0057Fh
Size Address
0XXXXh
R8C/1A Group, R8C/1B Group 4. S pecial Function Registers (SFRs)
Rev.1.40 Dec 08, 2006 Page 20 of 45
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4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.4 list the
special function registers.
Table 4.1 SFR Information (1)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register.
3. After hardware reset.
4. After power-on reset or voltage monitor 1 reset.
5. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3.
Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 01101000b
0007h System Clock Control Register 1 CM1 00100000b
0008h
0009h Address Match Interrupt Enab le Register AIER 00h
000Ah Protect Register PRCR 00h
000Bh
000Ch Oscillation S top Detection Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 00X11111b
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h X0h
0013h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h X0h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 00h
001Dh
001Eh INT0 Input Filter Select Register INT0F 00h
001Fh
0020h High-Speed On-Chip Oscillator Control Register 0 HRA0 00h
0021h High-Speed On-Chip Oscillator Control Regist er 1 HRA1 When shipping
0022h High-Speed On-Chip Oscillator Control Register 2 HRA2 00h
0023h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h Voltage Detection Register 1(2) VCA1 00001000b
0032h Voltage Detection Register 2(2) VCA2 00h(3)
01000000b(4)
0033h
0034h
0035h
0036h Volta ge Monitor 1 Circuit Control Register (2) VW1C 0000X000b(3)
0100X001b(4)
0037h Volta ge Monitor 2 Circuit Control Register (5) VW2C 00h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
R8C/1A Group, R8C/1B Group 4. Special Function Registers (SFRs)
Rev.1.40 Dec 08, 2006 Page 21 of 45
REJ03B0144-0140
Table 4.2 SFR Information (2)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Addres s Register Symbol After re se t
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b
004Fh SSU/IIC Interrupt Control Register(2) SSUAIC/IIC2AIC XXXXX000b
0050h Compare 1 Interrupt Control Register CMP1IC XXXXX000b
0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b
0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b
0055h
0056h Timer X Interrupt Control Register TXIC XXXXX000b
0057h
0058h T i mer Z Interrupt Control Register TZIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XXXXX000b
005Ah INT3 Interrupt Control Register INT3IC XXXXX000b
005Bh T imer C Interrupt Control Register TCIC XXXXX000b
005Ch Compare 0 Interrupt Control Register CMP0IC XXXXX000b
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
R8C/1A Group, R8C/1B Group 4. Special Function Registers (SFRs)
Rev.1.40 Dec 08, 2006 Page 22 of 45
REJ03B0144-0140
Table 4.3 SFR Information (3)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. In input capture mode.
3. In output compare mode.
4. Selected by the IICSEL bit in the PMR register.
Addres s Register Symbol After re se t
0080h T i mer Z Mode Register TZMR 00h
0081h
0082h
0083h
0084h T i mer Z Waveform Output Control Register PUM 00h
0085h Prescaler Z Register PREZ FFh
0086h Timer Z Secondary Register TZSC FFh
0087h Timer Z Primary Register TZPR FFh
0088h
0089h
008Ah Timer Z Output Control Register TZOC 00 h
008Bh Timer X Mode Register TXMR 00h
008Ch Prescaler X Register PREX FFh
008Dh Timer X Register TX FFh
008Eh Timer Count Source Setting Register TCSS 00h
008Fh
0090h Timer C Register TC 00h
0091h 00h
0092h
0093h
0094h
0095h
0096h External Input Enable Register INTEN 00h
0097h
0098h Key Input Enable Register KIEN 00h
0099h
009Ah T imer C Control Register 0 TCC0 00h
009Bh T imer C Control Register 1 TCC1 00h
009Ch Capture, Compare 0 Register TM0 0000h(2)
009Dh FFFFh(3)
009Eh Compare 1 Register TM1 FFh
009Fh FFh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Rate Generator U0BRG XXh
00A2h UART0 Transmit Buffer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/Receive Cont rol Register 0 U0C0 00001000b
00A5h UART0 Transmit/Receive Cont rol Register 1 U0C1 00000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h UART1 Transmit/Receive Mode Register U1MR 00h
00A9h UART1 Bit Rate Generator U1BRG XXh
00AAh UART1 Transmit Buffer Register U1TB XXh
00ABh XXh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b
00ADh UART1 Transmit/Receive Control Register 1 U1C1 00000010b
00AEh UART1 Receive Buffer Register U1RB XXh
00AFh XXh
00B0h UART Transmit/Receive Control Register 2 UCON 00h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h SS Control Register H / IIC bus Control Register 1(4) SSCRH / ICCR1 00h
00B9h SS Control Register L / IIC bus Control Register 2(4) SSCRL / ICCR2 01111101b
00BAh SS Mode Register / IIC bus Mode Register(4) SSMR / ICMR 00011000b
00BBh SS Enable Register / IIC bus Interrupt Enable Register(4) SSER / ICIER 00h
00BCh SS Status Register / I IC bus Status Register(4) SSSR / ICSR 00h / 0000X000b
00BDh SS Mode Register 2 / Slave Address Register(4) SSMR2 / SAR 00h
00BEh SS Transmit Data Register / IIC bus Transmit Data Register(4) SSTDR / ICDRT FFh
00BFh SS Receive Data Register / IIC bus Receive Data Register(4) SSRDR / ICDRR FFh
R8C/1A Group, R8C/1B Group 4. Special Function Registers (SFRs)
Rev.1.40 Dec 08, 2006 Page 23 of 45
REJ03B0144-0140
Table 4.4 SFR Information (4)(1)
X: Undefined
NOTES:
1. Blank regions, 0100h to 01B2h and 01B8h to 02FFh are all reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a user program. Use a flash programmer to write to it.
Addres s Register Symbol After re se t
00C0h A/D Register AD XXh
00C1h XXh
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h A/D Control Register 2 ADCON2 00h
00D5h
00D6h A/D Control Register 0 ADCON0 00000XXXb
00D7h A/D Control Register 1 ADCON1 00h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h Port P1 Register P1 XXh
00E2h
00E3h Port P1 Direction Register PD1 00h
00E4h
00E5h Port P3 Register P3 XXh
00E6h
00E7h Port P3 Direction Register PD3 00h
00E8h Port P4 Register P4 XXh
00E9h
00EAh Port P4 Direction Register PD4 00h
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h Port Mode Register PMR 00h
00F9h
00FAh
00FBh
00FCh Pull-Up Control Register 0 PUR0 00XX0000b
00FDh Pull-Up Control Register 1 PUR1 XXXXX X0Xb
00FEh Port P1 Drive Capacity Control Register DRR 00h
00FFh Time r C Output Control Register TCOUT 00h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register 1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
0FFFFh Optional Function Select Register OFS (2)
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 24 of 45
REJ03B0144-0140
5. Electrical Characteristics
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. Typical values when average output current is 100 ms.
Table 5.1 Absolute Maximum Ratin gs
Symbol Parameter Condition Rated Value Unit
VCC Supply voltage VCC = AVCC -0.3 to 6.5 V
AVCC Analog supply voltage VCC = AVCC -0.3 to 6.5 V
VIInput voltage -0.3 to VCC+0.3 V
VOOutput voltage -0.3 to VCC+0.3 V
PdPower dissipation Topr = 25°C300mW
Topr Operating ambient temperature -20 to 85 / -40 to 85 (D version) °C
Tstg Storage temperature -65 to 150 °C
Table 5.2 R ecommended Operating Conditions
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
VCC Supply voltage 2.7 −5.5 V
AVCC Analog supply voltage −VCC −V
VSS Supply voltage −0−V
AVSS Analog supply voltage −0−V
VIH Input “H” voltage 0.8VCC −VCC V
VIL Input “L” voltage 0 −0.2VCC V
IOH(sum) Peak sum output
“H” current Sum of all pins
IOH (peak)
−−-60 mA
IOH(peak) Peak output “H” current −−-10 mA
IOH(avg) Average output “H” current −−-5 mA
IOL(sum) Peak sum output
“L” currents Sum of all pins
IOL (peak)
−−60 mA
IOL(peak) Peak output “L”
currents Except P1_0 to P1_3 −−10 mA
P1_0 to P1_3 Drive capacity HIGH −−30 mA
Drive capacity LOW −−10 mA
IOL(avg) Average output
“L” current Except P1_0 to P1_3 −−5mA
P1_0 to P1_3 Drive capacity HIGH −−15 mA
Drive capacity LOW −−5mA
f(XIN) Main clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
−System clock OCD2 = 0
Main clock selected 3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
OCD2 = 1
On-chip oscillator
clock selected
HRA01 = 0
Low-speed on-chip
oscillator clock selected
−125 −kHz
HRA01 = 1
High-speed on-chip
oscillator clock selected
−8−MHz
Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr =
-20°C to 105°C ).
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 25 of 45
REJ03B0144-0140
NOTES:
1. VCC = AVCC = 2.7 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. If f1 exceeds 10 MHz, divide f1 and ensure the A/D operating clock frequ ency (φAD) is 10 MHz or below.
3. If AVcc is less than 4.2 V, divide f1 and ensure the A/D operating clock frequency (φAD) is f1/2 or below.
4. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
Figure 5.1 Port P1, P3, and P4 Measurement Circuit
Ta ble 5.3 A /D Converter Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Resolution Vref = VCC −−10 Bits
−Absolute
accuracy 10-bit mode φAD = 10 MHz, Vref = VCC = 5.0 V −−±3 LSB
8-bit mode φAD = 10 MHz, Vref = VCC = 5.0 V −−±2 LSB
10-bit mode φAD = 10 MHz, Vref = VCC = 3.3 V(3) −−±5 LSB
8-bit mode φAD = 10 MHz, Vref = VCC = 3.3 V(3) −−±2 LSB
Rladder Resistor ladder Vref = VCC 10 −40 kΩ
tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = VCC = 5.0 V 3.3 −−µs
8-bit mode φAD = 10 MHz, Vref = VCC = 5.0 V 2.8 −−µs
Vref Reference voltage 2.7 −Vcc V
VIA Analog input voltage(4) 0−AVcc V
−A/D operating
clock
frequency(2)
Without sample and
hold 0.25 −10 MHz
With sample and hold 1 −10 MHz
P1
P3
P4
30pF
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 26 of 45
REJ03B0144-0140
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60 °C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting
prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the
normal time delay to suspend can be applied to the request. However, we recommend that a suspend request with an
interval of less than 650 µs is only used once because, if the suspend state continues, erasure cannot operate and the
incidence of erasure error rises.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the number of erase operations between block A and block B
can further reduce the effective number of rewrites. It is also advisable to retain data on the erase count of each block and
limit the number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support
representative.
8. The data hold time includes time that the power supply is off or the clock is not supplied.
Ta ble 5.4 Flash Memory (Program ROM) Electrical Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) R8C/1A Group 100(3) −−times
R8C/1B Group 1,000(3) −−times
−Byte program time −50 400 µs
−Block erase time −0.4 9 s
td(SR-SUS) Time delay from suspend request until
suspend −−97+CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−T ime from suspend until program/erase
restart −−3+CPU clo c k
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.7 −5.5 V
−Program, erase temperature 0 −60 °C
−Data hold time(8) Ambient temperature = 55 °C20 −−year
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 27 of 45
REJ03B0144-0140
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = −20 to 85 °C / −40 to 85 °C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting
prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the
normal time delay to suspend can be applied to the request. However, we recommend that a suspend request with an
interval of less than 650 µs is only used once because, if the suspend state continues, erasure cannot operate and the
incidence of erasure error rises.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support
representative.
8. -40 °C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) 10,000(3) −−times
−Byte program time
(Program/erase endurance ≤ 1,000 times) −50 400 µs
−Byte program time
(Program/erase endurance > 1,000 times) −65 −µs
−Block erase time
(Program/erase endurance ≤ 1,000 times) −0.2 9 s
−Block erase time
(Program/erase endurance > 1,000 times) −0.3 −s
td(SR-SUS) Time Delay from suspend request until
suspend −−97+CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−Time from suspend until program/erase
restart −−3+CPU clock
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.7 −5.5 V
−Program, erase temperature -20(8) −85 °C
−Data hold time(9) Ambient temperature = 55 °C20 −−year
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 28 of 45
REJ03B0144-0140
Figure 5.2 Transition Time to Suspend
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85 °C.
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
3. Ensure that Vdet2 > Vdet1.
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85 °C.
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
4. Ensure that Vdet2 > Vdet1.
Table 5.6 Voltage Detection 1 Circuit Elect ri cal C hara ct eris ti cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet1 Voltage detection level(3) 2.70 2.85 3.00 V
−Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V −600 −nA
td(E-A) Waiting time until voltage detection circuit operation
starts(2) −−100 µs
Vccmin MCU operating voltage minimum value 2.7 −−V
Table 5.7 Voltage Detection 2 Circuit Elect ri cal C hara ct eris ti cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet2 Voltage detection level(4) 3.00 3.30 3.60 V
−Voltage monitor 2 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V −600 −nA
td(E-A) Waiting time until voltage detection circuit operation
starts(3) −−100 µs
FMR46
Suspend req uest
(maskable inte rrupt re qu est)
Fixed time (97 µs)
td(SR-SUS)
Clock-
dependent time Access restart
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 29 of 45
REJ03B0144-0140
NOTES:
1. This condition is not applicable when using with Vcc ≥ 1.0 V.
2. When turning power on after the time to hold the external power below effective voltage (Vpor1) exceeds10 s, refer to Table
5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset).
3. tw(por2) is the time to hold the external power below effective voltage (Vpor2).
NOTES:
1. When not using voltage monitor 1, use with Vcc≥ 2.7 V.
2. tw(por1) is the time to hold the external power below effective voltage (Vpor1).
Figure 5.3 Reset Circuit Electrical Characteristics
Table 5.8 Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vpor2 Power-on reset vali d voltage -20°C ≤ Topr ≤ 85°C−−Vdet1 V
tw(Vpor2-Vdet1) Supply voltage rising time when power-on reset is
deasserted(1) -20°C ≤ Topr ≤ 85°C,
tw(por2) ≥ 0s(3) −−100 ms
Table 5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vpor1 Power-on reset valid voltage -20°C ≤ Topr ≤ 85°C−−0.1 V
tw(Vpor1-Vdet1) Supply voltage rising time when power-on reset is
deasserted 0°C ≤ Topr ≤ 85°C,
tw(por1) ≥ 10 s(2) −−100 ms
tw(Vpor1-Vdet1) Supply voltage rising time when power-on reset is
deasserted -20°C ≤ Topr < 0°C,
tw(por1) ≥ 30 s(2) −−100 ms
tw(Vpor1-Vdet1) Supply voltage rising time when power-on reset is
deasserted -20°C ≤ Topr < 0°C,
tw(por1) ≥ 10 s(2) −− 1ms
tw(Vpor1-Vdet1) Supply voltage rising time when power-on reset is
deasserted 0°C ≤ Topr ≤ 85°C,
tw(por1) ≥ 1 s(2) −−0.5 ms
NOTES:
1. Hold the voltage inside the MCU operation voltage range (Vccmin or above) within the sampling time.
2. The sampling clock can be selected. Refer to 7. Voltage Detection Circuit for d eta ils.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 7. Voltage Detection Circuit for details.
Vdet1(3)
Vpor1
Internal reset signal
(“L” valid )
tw(por1) tw(Vpor1–Vdet1) Sampling time(1, 2)
Vdet1(3)
1
fRING-S
× 32 1
fRING-S
× 32
Vpor2
Vccmin
tw(por2)
tw(Vpor2–Vdet1)
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 30 of 45
REJ03B0144-0140
NOTES:
1. The measurement condition is VCC = 5.0 V and Topr = 25 °C.
2. Refer to 10.6.4 High-Speed On-Chip Oscillator Clock for notes on high-speed on-chip oscillator clock.
3. The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to
00h.
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25 °C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until CPU clock supply starts after the interrupt is acknowledged to exit stop mode.
Table 5.10 High-Speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
−High-speed on-chip oscillator frequency when the
reset is deasserted VCC = 5.0 V, Topr = 25 °C−8−MHz
−High-speed on-chip oscillator frequency
temperature • supply voltage dependence(2) 0 to +60 °C/5 V ± 5 %(3) 7.76 −8.24 MHz
-20 to +85 °C/2.7 to 5.5 V(3) 7.68 −8.32 MHz
-40 to +85 °C/2.7 to 5.5 V(3) 7.44 −8.32 MHz
Table 5.11 Power Supply Circuit T iming Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during
power-on(2) 1−2000 µs
td(R-S) STOP exit time(3) −−150 µs
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 31 of 45
REJ03B0144-0140
NOTES:
1. VCC = 2.7 to 5.5V, VSS = 0V at Ta = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. 1tCYC = 1/f1(s)
Table 5.12 Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
tSUCYC SSCK clock cycle time 4 −−
tCYC(2)
tHI SSCK clock “H” width 0.4 −0.6 tSUCYC
tLO SSCK clock “L” width 0.4 −0.6 tSUCYC
tRISE SSCK clock rising time Master −− 1tCYC(2)
Slave −− 1µs
tFALL SSCK clock falling time Master −− 1tCYC(2)
Slave −− 1µs
tSU SSO, SSI data input setup time 100 −− ns
tHSSO, SSI data input hold time 1 −−
tCYC(2)
tLEAD SCS setup time Slave 1tCYC+50 −− ns
tLAG SCS hold time Slave 1tCYC+50 −− ns
tOD SSO, SSI data output delay time −− 1tCYC(2)
tSA SSI slave access time −−1.5tCYC+100 ns
tOR SSI slave out open time −−1.5tCYC+100 ns
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 32 of 45
REJ03B0144-0140
Figure 5.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 0
CPHS, CPOS: Bits in SSMR register
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 33 of 45
REJ03B0144-0140
Figure 5.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
VIH or VOH
VIH or VOH
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 0
tOD
tLEAD
tSA
tLAG
tOR
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
tOD
tLEAD
tSA
tLAG
tOR
CPHS, CPOS: Bits in SSMR register
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 35 of 45
REJ03B0144-0140
NOTES:
1. VCC = 2.7 to 5.5 V, VSS = 0 V and Ta = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. 1tCYC = 1/f1(s)
Figure 5.7 I/O Timing of I2C bus Interface
Table 5.13 Timing Requirements of I2C bus Interface (1)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
tSCL SCL input cycle time 12tCYC+600(2) −−ns
tSCLH SCL input “H” width 3tCYC+300(2) −−ns
tSCLL SCL input “L” width 5tCYC+300(2) −−ns
tsf SCL, SDA input fall time −−300 ns
tSP SCL, SDA input spike pulse rejection time −−
1tCYC(2) ns
tBUF SDA input bus-free time 5tCYC(2) −−ns
tSTAH Start condition input hold time 3tCYC(2) −−ns
tSTAS Retransmit start condition input setup time 3tCYC(2) −−ns
tSTOS Stop condition input setup time 3tCYC(2) −−ns
tSDAS Data input setup time 1tCYC+20(2) −−ns
tSDAH Data input hold time 0 −−ns
SDA
tSTAH
tSCLL
tBUF
VIH
VIL
tSCLH
SCL
tsf
tSDAH
tSCL
tSTAS tSP tSTOS
tSDAS
P(2) S(1) Sr(3) P(2)
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 36 of 45
REJ03B0144-0140
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN) = 20 MHz, unless otherwise specified.
Table 5.14 Electrical Characteristics (1) [VCC = 5 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except XOUT IOH = -5 mA VCC − 2.0 −VCC V
IOH = -200 µAVCC − 0.3 −VCC V
XOUT Drive capacity
HIGH IOH = -1 mA VCC − 2.0 −VCC V
Drive capacity
LOW IOH = -500 µAVCC − 2.0 −VCC V
VOL Output “L” voltage Except P1_0 to
P1_3, XOUT IOL = 5 mA −−2.0 V
IOL = 200 µA−−0.45 V
P1_0 to P1_3 Drive capacity
HIGH IOL = 15 mA −−2.0 V
Drive capacity
LOW IOL = 5 mA −−2.0 V
Drive capacity
LOW IOL = 200 µA−−0.45 V
XOUT Drive capacity
HIGH IOL = 1 mA −−2.0 V
Drive capacity
LOW IOL = 500 µA−−2.0 V
VT+-VT- Hysteresis INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
CNTR0, CNTR1,
TCIN, RXD0
0.2 −1.0 V
RESET 0.2 −2.2 V
IIH Input “H” current VI = 5 V −−5.0 µA
IIL Input “L” current VI = 0 V −−-5.0 µA
RPULLUP Pull-up resistance VI = 0 V 30 50 167 kΩ
RfXIN Feedback resistance XIN −1.0 −MΩ
fRING-S Low-speed on-chip oscillator frequency 40 125 250 kHz
VRAM RAM hold voltage D uring stop mode 2.0 −−V
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 37 of 45
REJ03B0144-0140
Table 5.15 Electrical Characteristics (2) [Vcc = 5 V] (Topr = -40 to 85
°
C, unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS,
A/D converter is
stopped
High-speed
mode XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−915mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−814mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−5−mA
Medium-
speed mode XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−4−mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−3−mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
High-speed
on-chip
oscillator
mode
Main clock off
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−48mA
Main clock off
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1.5 −mA
Low-speed
on-chip
oscillator
mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
FMR47 = 1
−110 300 µA
Wait mode Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = 0
−40 80 µA
Wait mode Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = 0
−38 76 µA
Stop mode Main clock off, Topr = 25
°
C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = 0
−0.8 3.0 µA
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 38 of 45
REJ03B0144-0140
Timing Requirements
(Unless otherwise specified: VCC = 5 V, VSS = 0 V at Ta = 25 °C) [ VCC = 5 V ]
Figure 5.8 XIN Input Timing Diagram when VCC = 5 V
Figure 5.9 CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 5 V
NOTES:
1. When using timer C input capture mode, adjust the cycle time to (1/timer C count source frequency x 3) or above.
2. When using timer C input capture mode, adjust the pulse width to (1/timer C count source frequency x 1.5) or above.
Figure 5.10 TCIN Input, INT3 Input Timing Diagram when VCC = 5 V
Table 5.16 XIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 50 −ns
tWH(XIN) XIN input “H” width 25 −ns
tWL(XIN) XIN input “L” width 25 −ns
Table 5.17 CNTR0 Input, CNTR1 Input, INT1 Input
Symbol Parameter Standard Unit
Min. Max.
tc(CNTR0) CNTR0 input cycle time 100 −ns
tWH(CNTR0) CNTR0 input “H” width 40 −ns
tWL(CNTR0) CNTR0 input “L” width 40 −ns
Table 5.18 TCIN Input, INT3 Input
Symbol Parameter Standard Unit
Min. Max.
tc(TCIN) TCIN input cycle time 400(1) −ns
tWH(TCIN) TCIN input “H” width 200(2) −ns
tWL(TCIN) TCIN input “L” width 200(2) −ns
tWH(XIN)
tc(XIN)
tWL(XIN)
XIN input
VCC = 5 V
tWH(CNTR0)
tc(CNTR0)
tWL(CNTR0)
CNTR0 input
VCC = 5 V
tWH(TCIN)
tc(TCIN)
tWL(TCIN)
TCIN input
VCC = 5 V
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 39 of 45
REJ03B0144-0140
i = 0 or 1
Figure 5.11 Serial Interface Timing Diagram when VCC = 5 V
NOTES:
1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
Figure 5.12 External Interrupt INT0 Input Timing Diagram when VCC = 5 V
Table 5.19 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 200 −ns
tW(CKH) CLKi input “H” width 100 −ns
tW(CKL) CLKi input “L” width 100 −ns
td(C-Q) TXDi output delay time −50 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 50 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.20 External Interrupt INT0 Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INT0 input “H” width 250(1) −ns
tW(INL) INT0 input “L” width 250(2) −ns
tW(CKH)
tc(CK)
tW(CKL) th(C-Q)
th(C-D)tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 5 V
i = 0 or 1
tW(INL)
tW(INH)
INT0 input
VCC = 5 V
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 40 of 45
REJ03B0144-0140
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN) = 10 MHz, unless otherwise specified.
Table 5.21 Electrical Characteristics (3) [VCC = 3V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except XOUT IOH = -1 mA VCC − 0.5 −VCC V
XOUT Drive capacity
HIGH IOH = -0.1 mA VCC − 0.5 −VCC V
Drive capacity
LOW IOH = -50 µAVCC − 0.5 −VCC V
VOL Output “L” voltage Except P1_0 to
P1_3, XOUT IOL = 1 mA −−0.5 V
P1_0 to P1_3 Drive capacity
HIGH IOL = 2 mA −−0.5 V
Drive capacity
LOW IOL = 1 mA −−0.5 V
XOUT Drive capacity
HIGH IOL = 0.1 mA −−0.5 V
Drive capacity
LOW IOL = 50 µA−−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
CNTR0, CNTR1,
TCIN, RXD0
0.2 −0.8 V
RESET 0.2 −1.8 V
IIH Input “H” current VI = 3 V −−4.0 µA
IIL Input “L” current VI = 0 V −−-4.0 µA
RPULLUP Pull-up resistance VI = 0 V 66 160 500 kΩ
RfXIN Feedback resistance XIN −3.0 −MΩ
fRING-S Low-speed on-chip oscillator frequency 40 125 250 kHz
VRAM RAM hold voltage D uring stop mode 2.0 −−V
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 41 of 45
REJ03B0144-0140
Table 5.22 Electrical Characteristics (4) [Vcc = 3 V] (Topr = -40 to 85
°
C, unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS,
A/D converter is
stopped
High-speed
mode XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−813mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−712mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−5−mA
Medium-
speed mode XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−3−mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.5 −mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1.6 −mA
High-speed
on-chip
oscillator
mode
Main clock off
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−3.5 7.5 mA
Main clock off
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1.5 −mA
Low-speed
on-chip
oscillator
mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
FMR47 = 1
−100 280 µA
Wait mode Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = 0
−37 74 µA
Wait mode Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = 0
−35 70 µA
Stop mode Main clock off, Topr = 25
°
C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = 0
−0.7 3.0 µA
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 42 of 45
REJ03B0144-0140
Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Ta = 25 °C) [VCC = 3 V]
Figure 5.13 XIN Input Timing Diagram when VCC = 3 V
Figure 5.14 CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 3 V
NOTES:
1. When using the timer C input capture mode, adjust the cycle time to (1/timer C count source frequency x 3) or above.
2. When using the timer C input capture mode, adjust the width to (1/timer C count source frequency x 1.5) or above.
Figure 5.15 TCIN Input, INT3 Input Timing Diagram when VCC = 3 V
Table 5.23 XIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 100 −ns
tWH(XIN) XIN input “H” width 40 −ns
tWL(XIN) XIN input “L” width 40 −ns
Table 5.24 CNTR0 Input, CNTR1 Input, INT1 Input
Symbol Parameter Standard Unit
Min. Max.
tc(CNTR0) CNTR0 input cycle time 300 −ns
tWH(CNTR0) CNTR0 input “H” width 120 −ns
tWL(CNTR0) CNTR0 input “L” width 120 −ns
Table 5.25 TCIN Input, INT3 Input
Symbol Parameter Standard Unit
Min. Max.
tc(TCIN) TCIN input cycle time 1,200(1) −ns
tWH(TCIN) TCIN input “H” width 600(2) −ns
tWL(TCIN) TCIN input “L” width 600(2) −ns
XIN input
tWH(XIN)
tc(XIN)
tWL(XIN)
VCC = 3 V
CNTR0 input
tWH(CNTR0)
tc(CNTR0)
tWL(CNTR0)
VCC = 3 V
TCIN input
tWH(TCIN)
tc(TCIN)
tWL(TCIN)
VCC = 3 V
R8C/1A Group, R8C/1B Group 5. Electrical Characteristics
Rev.1.40 Dec 08, 2006 Page 43 of 45
REJ03B0144-0140
i = 0 or 1
Figure 5.16 Serial Interface Timing Diagram when VCC = 3 V
NOTES:
1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater
2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater
Figure 5.17 External Interrupt INT0 Input Timing Diagram when VCC = 3 V
Table 5.26 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 300 −ns
tW(CKH) CLKi input “H” width 150 −ns
tW(CKL) CLKi input “L” width 150 −ns
td(C-Q) TXDi output delay time −80 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 70 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.27 External Interrupt INT0 Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INT0 input “H” width 380(1) −ns
tW(INL) INT0 input “L” width 380(2) −ns
tW(CKH)
tc(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 3 V
i = 0 or 1
INT0 input
tW(INL)
tW(INH)
VCC = 3 V
Rev.1.40 Dec 08, 2006 Page 44 of 45
REJ03B0144-0140
R8C/1A Group, R8C/1B Group Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
y
Index mark
110
11
20
F
*1
*3
*2
c
bp
e
A
D
E
H
E
INCLUDE TRIM OFFSET.
DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.
DIMENSIONS "*1" AND "*2"1.
2.
Detail F
A1
A2
L
0.320.220.17
b
p
Previous CodeJEITA Package Code RENESAS Code
PLSP0020JB-A 20P2F-A
MASS[Typ.]
0.1gP-LSSOP20-4.4x6.5-0.65
0.2
0.150.13
MaxNomMin
Dimension in Millimeters
Symbol
Reference
6.66.56.4
D
4.54.44.3
E
1.15
A
2
6.66.46.2
1.45
A
0.20.1
0
0.70.50.3
L
10°0°
c
0.65
e
0.10
y
H
E
A
1
0.53 0.77
2.0281.528
4.5
A
1
b
3
15°
e1.778
c
L3.0
0.51
0.9 1.0 1.3
A
E6.15 6.3 6.45
D18.8 19.0 19.2
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.22 0.27 0.34
P-SDIP20-6.3x19-1.78 1.0g
MASS[Typ.]
20P4BPRDP0020BA-A
RENESAS CodeJEITA Package Code Previous Code
b
p
0.38 0.48 0.58
e
1
7.627.32 7.92
A
2
3.3
0°
*3
*2
*1
SEATING PLANE
20 11
101
c
e1
E
AL
A2
A1
bp
b3
e
D
INCLUDE TRIM OFFSET.
DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.
DIMENSIONS "*1" AND "*2"1.
2.
Rev.1.40 Dec 08, 2006 Page 45 of 45
REJ03B0144-0140
R8C/1A Group, R8C/1B Group Package Dimensions
NOTE)
DO NOT INCLUDE MOLD FLASH.
DIMENSIONS "*1" AND "*2"1.
2.0
D
2
0.05
y
b
p
A
1
x0.05
e0.5
L
p
E
1
2.0
00
0.05
A0.8
A
2
0.75
E4.9 5.0 5.1
D4.9 5.0 5.1
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.15 0.2 0.25
0.5 0.6 0.7
P-HWQFN28-5x5-0.50 0.05g
MASS[Typ.]
28PJW-BPWQN0028KA-B
RENESAS CodeJEITA Package Code Previous Code
*2
*1
x
y
28
22
21
15
8
71
F
15
21
22
28
17
8
14
14
E
D
E
1
D
2
L
p
b
p
Detail F
A
1
A
A
2
e
A - 1
REVISION HISTORY R8C/1A Group, R8C/1B Group Datasheet
Rev. Date Description
Page Summary
0.10 Feb 18, 2005 −First Edition issued
0.20 Jun 01, 2005 2, 3 Tables 1.1, 1.2: Item name changed
9 Ta ble 1.5: Timer C’s Pin name revised,
Reference Voltage In put Description revised
0.30 Jul 04, 2005 16 Table 4. 1 the value afte r reset revised;
0009h address “XXXXXX00b” → “00h”,
000Ah address “00XXX000b” → “00h”,
001Eh address “XXXXX000b” → “00h”.
17 Table 4.2 004Fh address; “SSU/IIC Interrupt Control Register, SSUAIC/
IIC2AIC, XXXXX000b” added
18 Table 4.3 the v alue after rese t re vise d;
00BCh addre ss “00 h ” → “00h / 0000X000b”
20 to 39 5. Electrical Characteristics added
1.00 Sep 01, 2005 all pages “Under development” deleted
3 Table 1.2 Performance Outline of the R8 C/1B Group;
Flash Memory: (Data area) → (Data flash)
(Program area) → (Program ROM) revised
4 Figure 1.1 Block Diagram;
“Peripheral Function” added,
“System Clock Generation” → “System Clock Generator” revised
5 Table 1.3 Product Information of R8C/1A Group;
“(D)” and “(D): Under development” deleted
6 Table 1.4 Product Information of R8C/1B Group;
“(D)” and “(D): Under development” deleted
ROM capacity: (Program area) → (Program ROM),
(Data area) → (Data flash) revised
9 Table 1.5 Pin Description;
Power Supply Input: “VCC/AVCC” → “VCC”,
“VSS/AVSS” → “VSS” revised
Analog Power Supply Inpu t: ad d ed
11 Figure 2.1 CPU Register;
“Reserved Area” → “Reserved Bit” revised
13 2.8.10 Reserved Area;
“Reserved Area” → “Reserved Bit” revised
15 3.2 R8C/1B Group, Figure 3.2 Memory Map of R8C/1B Group;
“Data area ” → “Data flash”,
“Program area” → “Program ROM” revised
R8C/1A Group, R8C/1B Group Datasheet
REVISION HISTORY
A - 2
REVISION HISTORY R8C/1A Group, R8C/1B Group Datasheet
1.00 Sep 01, 2005 18 Table 4.3 SFR Information(3);
0085h: “Prescaler Z” → “Prescaler Z Register”
0086h: “Timer Z Secondary” → “Timer Z Secondary Register”
0087h: “Timer Z Primary” → “Timer Z Primary Register”
008Ch: “Prescaler X” → “Prescaler X Register”
008Dh: “Timer X” → “Timer X Register”
0090h, 0091h:“Timer C” → “Timer C Register” revised
21 Table 5.3 A/D Converter Cha racteristics;
Vref and VIA: Standard value, NOTE4 revised
22 Table 5.4 Flash Memory (Program ROM) Electrical Character i stics;
NOTES3 and 5 revised, NOTE8 deleted
23
T
able 5.5 Flash Memory (Data flash Block A, Block B) Electrical
Characteristics;
NOTES1 and 3 revised
25 Table 5.8 Reset Circuit Electrical Characteristics (When Using Voltage
Monitor 1 Reset); NOTE2 revised
26 Table 5.10 High-speed On-Chip Oscillator Circuit Electrical
Characteristics;
“High-S peed On-Chip Oscillator ...” → “High-S peed On-Chip Oscillator
Frequency ...” revised,
NOTE2 adde d
33 Table 5.15 Electrical Characteristics (2) [Vcc = 5V];
NOTE1 delet ed
37 Table 5.22 Electrical Characteristics (4) [Vcc = 3V];
NOTE1 delet ed
1.10 D ec 16 , 20 05 −Products of PWQN0028 KA-B package included
5, 6 Table 1.3, Table 1.4 revised
24 Table 5.4 Flash Memory (Program ROM) Electrical Character i stics;
NOTE 8 added, Topr →
Ambient temperature
25 Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical
Characteristics; NOTE 9 added, Top r →
Ambient temperature
28 Table 5.10 High-speed On-Chip Oscillator Circuit Electrical
Characteristics; NOTE 3 added
29 Table 5.12; tSA and tOR revised, NOTE: 1. VCC = 2.2 to → 2.7 to
33 Table 5.13; NOTE: 1. VCC = 2.2 to → 2.7 to
35, 39 Table 5.15, Table 5.22; The title revised, Condition of Stop Mode added
37, 41 Table 5.19, Table 5.26; td(C-Q) and tsu(D-C) revised
42, 43 Package Dimensions revised
1.20 Mar 31, 2006 5, 6 Table 1.3, Table 1.4; Type No. added, deleted
16, 17 Figure 3.1, Figure 3.2; Part Number added, deleted
24, 25 Table 5.4, Table 5.5; Conditions: VCC = 5.0 V at Topr = 25 °C deleted,
1.30 Oct 03, 2006 all pages Y version added
Factory programming product added
Rev. Date Description
Page Summary
A - 3
REVISION HISTORY R8C/1A Group, R8C/1B Group Datasheet
1.30 Oct 03, 2006 1 1.1 “portable equipment” added
2, 3 Table 1.1, Table 1.2; Specification Interrupts: “Internal: 9 sources” →
“Interna l: 11 sources”
24 Table 5.2; Parameter: System clock added
45 Package Dimensions; PWQN0028KA-B revised
1.40 Dec 08, 2006 20 Table 4.1; 000Fh: After reset “000XXXXXb” → “00X11111b”
24 Table 19.2; Parameter: OCD2 = 1 On-chip oscillator clock selected
revised
Rev. Date Description
Page Summary
Notes:
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