LM1971 Overture Audio Attenuator Series - National Semiconductor

LM1971Overture™Audio Attenuator Series

Digitally Controlled 62 dB Audio Attenuator with/Mute

General Description

The LM1971 is a digitally controlled single channel audio

attenuator fabricated on a CMOS process. Attenuation is

variable in 1 dB steps from 0 dB to −62 dB. A mute function

disconnects the input from the output, providing over 100 dB

of attenuation.

The performance of the device is exhibited by its ability to

change attenuation levels without audible clicks or pops. In

addition, the LM1971 features a low Total Harmonic Distor-

tion (THD) of 0.0008%, and a Dynamic Range of 115 dB,

making it suitable for digital audio needs. The LM1971 is

available in both 8-pin plastic DIP or SO packages.

The LM1971 is controlled by a TTL/CMOS compatible 3-wire

serial digital interface. The active low LOAD line enables the

data input registers while the CLOCK line provides system

timing. Its DATA pin receives serial data on the rising edge of

each CLOCK pulse, allowing the desired attenuation setting

to be selected.

Key Specifications

nTotal harmonic distortion 0.0008% (typ)

nFrequency response >200 kHz (−3 dB) (typ)

nAttenuation range (excluding mute) 62 dB (typ)

nDynamic range 115 dB (typ)

nMute attenuation 102 dB (typ)

Features

n3-wire serial interface

nMute function

nClick and pop free attenuation changes

n8-pin plastic DIP and SO packages available

Applications

nCommunication systems

nCellular Phones and Pagers

nPersonal computer audio control

nElectronic music (MIDI)

nSound reinforcement systems

nAudio mixing automation

Typical Application

Overture™is a trademark of National Semiconductor Corporation.

01235301

FIGURE 1. Typical Audio Attenuator Application Circuit

September 2002

LM1971 Overture Audio Attenuator Series Digitally Controlled 62 dB Audio Attenuator with Mute

Connection Diagram

Dual-In-Line Plastic or Surface Mount Package

01235302

Top View

Order Number LM1971M or LM1971N

See NS Package Number M08A or N08E

LM1971

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Absolute Maximum Ratings (Notes 1,

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage, V

15V

Voltage at any pin (GND −0.2V) to (V

+0.2V)

ESD Susceptibility (Note 4) 3000V

Soldering Information

N Package (10s)

M Package

Vapor Phase (60s)

Infrared (15s)

260˚C

215˚C

220˚C

Power Dissipation (Note 3) 150 mW

Junction Temperature 150˚C

Storage Temperature −65˚C to +150˚C

Operating Ratings (Notes 1, 2)

Temperature Range

MIN

≤T

MAX

−40˚C ≤T

≤+85˚C

Thermal Resistance

M08A Package, θ

167˚C/W

N08E Package, θ

102˚C/W

Supply Voltage 4.5V to 12V

Electrical Characteristics (Notes 1, 2)

The following specifications apply for V

= +12V (V

REF

IN = +6V), V

= 5.5 V

, and f = 1 kHz, unless otherwse specified.

Limits apply for T

= 25˚C. Digital inputs are TTL and CMOS compatible.

Symbol Parameter Conditions

LM1971 Units

(Limits)

Typical

(Note 5)

Limit

(Note 6)

Supply Current Digital Inputs Tied to 6V 1.8 3 mA (max)

THD Total Harmonic Distortion V

= 0.5V

@0 dB Attenuation 0.0008 0.003 % (max)

Noise Input is AC Grounded

@−12 dB Attenuation

A-Weighted (Note 7)

4.0 µV

DR Dynamic Range Referenced to Full Scale = +6 V

115 dB

Mute Attenuation 102 96 dB (min)

Attenuation Step Size Error 0 dB to −62 dB 0.009 0.2 dB (max)

Absolute Attenuation Attenuation @0dB

Attenuation @−20 dB

Attenuation @−40 dB

Attenuation @−60 dB

Attenuation @−62 dB

0.1

−20.3

−40.5

−60.6

−62.6

0.5

−19.0

−38.0

−57.0

−59.0

dB (min)

LEAK

Analog Input Leakage Current Input is AC Grounded 5.8 100 nA (max)

Frequency Response 20 Hz–100 kHz ±0.1 dB

AC Input Impedance Pin 8, V

= 1.0 V

, f = 1 kHz 40 20

kΩ(min)

kΩ(max)

Input Current @Pins 4, 5, 6 @0V <V

<5V 1.0 100 nA (max)

CLK

Clock Frequency 3 2 MHz (max)

High-Level Input Voltage @Pins 4, 5, 6 2.0 V (min)

Low-Level Input Voltage @Pins 4, 5, 6 0.8 V (max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which

guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit

is given, however, the typical value is a good indication of device performance.

Note 2: All voltages are measured with respect to the GND pin (pin 3), unless otherwise specified.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature TA. The maximum

allowable power dissipation is PD=(T

JMAX –T

A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LM1971N and LM1971M,

TJMAX = +150˚C, and the typical junction-to-ambient thermal resistance, θJA, when board mounted is 102˚ C/W and 167˚ C/W, respectively.

Note 4: Human body model, 100 pF discharged through a 1.5 kΩresistor.

Note 5: Typicals are measured at 25˚C and represent the parametric norm.

Note 6: Limits are guarantees that all parts are tested in production to meet the stated values.

Note 7: Due to production test limitations, there is no limit for the Noise test. Please refer to the noise measurements in the Typical Performance Characteristics

section.

LM1971

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Pin Descriptions

REF

IN (1): The V

REF

IN pin provides the reference for the

analog input signal. This pin should be biased at half of the

supply voltage, V

, as shown in Figure 1 and Figure 6.

OUT (2): The attenuated analog output signal comes from

this pin.

GND (3): The GND pin references the digital input signals

and is the lower voltage reference for the IC. Typically this

pin would be labeled “V

” but the ground reference for the

digital logic input control is tied to this same point. With a

higher pin-count there would generally be separate pins for

these functions; V

and Logic Ground. It is intended that

the LM1971 always be operated using a single voltage sup-

ply configuration, for which pin 3 (GND) should always be at

system ground. If a bipolar or split-supply configuration are

desired, level shifting circuitry is needed for the digital logic

control pins as they would be referenced through pin 3 which

would be at the negative supply. It is highly recommended,

however, that the LM1971 be used in a unipolar or

single-supply configuration.

LOAD (4): The LOAD input accepts a TTL or CMOS level

signal. This is the enable pin of the device, allowing data to

be clocked in while this input is low (0V). The GND pin is the

reference for this signal.

DATA (5): The DATA input accepts a TTL or CMOS level

signal. This pin is used to accept serial data from a micro-

controller that will be latched and decoded to change the

channel’s attenuation level. The GND pin is the reference for

this signal.

CLOCK (6): The CLOCK input accepts a TTL or CMOS level

signal. The clock input is used to load data into the internal

shift register on the rising edge of the input clock waveform.

The GND pin is the reference for this signal.

(7): The positive voltage supply should be placed to this

pin.

IN (8): The analog input signal should be placed to this pin.

Typical Performance Characteristics

Supply Current vs

Supply Voltage

Supply Current vs

Temperature

01235310 01235311

Noise Floor

Analog Measurement THD+NvsFreq and Amp

01235312 01235313

LM1971

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Typical Performance Characteristics (Continued)

THD+NvsFreq and Amp Noise Floor Spectrum by FFT

01235314 01235315

THD+NvsAmplitude THD+NvsAmplitude

01235316 01235317

Mute Attenuation

vs Frequency THD vs Freq by FFT

01235318 01235319

LM1971

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Typical Performance Characteristics (Continued)

THD vs Freq by FFT

Output Impedance vs

Attenuation Level

01235320 01235321

Application Information

SERIAL DATA FORMAT

The LM1971 uses a 3-wire serial communication format that

is easily controlled by a microcontroller. The timing for the

3-wire set, comprised of DATA, CLOCK, and LOAD is shown

in Figure 2. As depicted in Figure 2, the LOAD line is to go

low at least 150 ns before the rising edge of the first clock

pulse and is to remain low throughout the transmission of the

16 data bits. The serial data is composed of an 8-bit address,

which must always be set to 0000 0000 to select the single

audio channel, and 8 bits for attenuation setting. For both

address data and attenuation setting data, the MSB is sent

first with the address data preceding the attenuation data.

Please refer to Figure 3 to confirm the serial data format

transfer process.

Table 1 shows the various Address and Data byte values for

different attenuation settings. Note that Address bytes other

than 0000 0000 are ignored.

µPOT SYSTEM ARCHITECTURE

The µPot’s digital interface is essentially a shift register

where serial data is shifted in, latched, and then decoded.

Once new data is shifted in, the LOAD line goes high,

latching in the new data. The data is then decoded and the

appropriate switch is activated to set the desired attenuation

level. This process is continued each and every time an

attenuation change is made. When the µPot is powered up,

it is placed into the Mute mode.

µPOT DIGITAL COMPATIBILITY

The µPot’s digital interface section is compatible with TTL or

CMOS logic. The shift register inputs act upon a threshold of

two diode drops above the ground level (Pin 3) or approxi-

mately 1.4V.

TABLE 1. Attenuator Register Set Description

Address Register (Byte 0)

MSB LSB

A7–A0

0000 0000 Channel 1

0000 0001 Ignored

0000 0010 Ignored

Data Register (Byte 1)

Contents Attenuation (dB)

MSB LSB

D7–D0

0000 0000 0.0

0000 0001 1.0

0000 0010 2.0

0000 0011 3.0

::::: ::

0001 0000 16.0

0001 0001 17.0

0001 0010 18.0

0001 0011 19.0

::::: ::

0011 1101 61.0

0011 1110 62.0

0011 1111 96 (Mute)

0100 0000 96 (Mute)

::::: ::

1111 1110 96 (Mute)

1111 1111 96 (Mute)

LM1971

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Application Information (Continued)

µPOT LADDER ARCHITECTURE

The µPot contains a chain of R1/R2 resistor dividers in a

ladder form, as shown in Figure 4. Each R1 is actually a

series of 8 resistors, with a CMOS switch that taps into the

resistor chain according to the attenuation level chosen. For

any given attenuation setting, there is only one CMOS switch

closed (no paralleling of ladders). The input impedance

therefore remains constant, while the output impedance

changes as the attenuation level changes. It is important to

note that the architecture is a series of resistor dividers, and

not a straight, tapped resistor, so the µPot is not a variable

resistor; it is a variable voltage divider.

01235303

*Note: Load and clock falling edges can be coincident, however, the clock falling edge cannot be delayed more than 20 ns from the falling edge of load. It is

preferrable that the falling edge of clock occurs before the falling edge of load.

FIGURE 2. Timing Diagram

01235304

FIGURE 3. Serial Data Format Transfer Process

01235305

FIGURE 4. Resistor Ladder Architecture

LM1971

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Application Information (Continued)

ATTENUATION STEP SCHEME

The fundamental attenuation step scheme for the LM1971 is

shown in Figure 5. It is also possible to obtain any integer

value attenuation step through programming, in addition to

the 2 dB and 4 dB steps shown in Figure 5. All higher

attenuation step schemes can have clickless and popless

performance. Although it is possible to “skip” attenuation

points by not sending all of the data, clickless and popless

performance will suffer. It is highly recommended that all of

the data points should be sent for each attenuation level.

This ensures flawless operation and performance when

making steps larger than 1 dB.

INPUT IMPEDANCE

The input impedance of a µPot is constant at a nominal

40 kΩ. Since the LM1971 is a single-supply operating de-

vice, it is necessary to have both input and output coupling

caps as shown in Figure 1. To ensure full low-frequency

response,a1µFcoupling cap should be used.

OUTPUT IMPEDANCE

The output impedance of a µPot varies typically between

25 kΩand 35 kΩand changes nonlinearly with step

changes. Since a µPot is made up of a resistor ladder

network with logarithmic attenuation, the output impedance

is nonlinear. Due to this configuration, a µPot cannot be

considered as a linear potentiometer; it is a logarithmic

attenuator.

The linearity of a µPot cannot be measured directly without a

buffer because the input impedance of most measurement

systems is not high enough to provide the required accuracy.

The lower impedance of the measurement system would

load down the output and an incorrect reading would result.

To prevent loading, a JFET input op amp should be used as

the buffer/amplifier.

OUTPUT BUFFERING

There are two performance issues to be aware of that are

related to a µPot’s output stage. The first concern is to

prevent audible clicks with attenuation changes, while the

second is to prevent loading and subsequent linearity errors.

The output stage of a µPot needs to be buffered with a low

input bias current op amp to keep DC shifts inaudible. Addi-

tionally, the output of µPot needs to see a high impedance to

keep linearity errors low.

Attenuation level changes cause changes in the output im-

pedance of a µPot. Output impedance changes in the pres-

ence of a large input bias current for a buffer/amplifier will

cause a DC shift to occur. Neglecting amplifier gains and

speaker sensitivities, the audibility of a DC shift is dependent

upon the output impedance change times the required input

bias current. As an example, a 5 kΩimpedance change

timesa1µAbias current results ina5mVDCshift; a level

that is barely audible without any music material in the

system. An op amp with a bias current of 200 pA for the

same 5 kΩchange results in an inaudible 1 µV DC shift.

Since the worst case output impedance changes are on the

order of several kΩ, a bias current much less than 1 µA is

required for highest performance. In order to further quantify

DC shifts, please refer to the Output Impedance vs Attenu-

ation graph in the Typical Performance Characteristics

section and relate worst case impedance changes to the

selected buffer/amplifier input bias current.

Without the use of a high input impedance (>1MΩ)opamp

for the buffer/amplifier, loading will occur that causes linearity

errors in the signal. To ensure the highest level of perfor-

mance, a JFET or CMOS input high input impedance op

amp is required.

One common application that requires gain at the output of a

µPot is input signal volume control. Depending upon the

input source material, the LM1971 provides a means of

controlling the input signal level. With a supply voltage range

of 4.5V to 12V, the LM1971 has the ability of controlling fairly

inconsistent input source signal levels. Using an op amp with

gain at the µPot’s output, as shown in Figure 7, will also

allow the system dynamic range to be increased. JFET op

amps like the LF351 and the LF411 are well suited for this

application. If active half-supply buffering is also desired,

dual op amps like the LF353 and the LF412 could be used.

For low voltage supply applications, op amps like the CMOS

LMC6041 are preferred. This part has a supply operating

range from 4.5V–15.5V and also comes in a surface mount

package.

µPOT HALF-SUPPLY REFERENCING

The LM1971 operates off of a single supply, with half-supply

biasing supplied at the V

REF

IN terminal (Pin 1). The easiest

and most cost effective method of providing this half-supply

is a simple resistor divider and bypass capacitor network

shown in Figure 1. The capacitor not only stabilizes the

half-supply node by “holding” the voltage nearly constant,

but also decouples high frequency signals on the supply to

ground. Signal feedthrough, power supply ripple and fluctua-

tions that are not properly filtered could cause the perfor-

mance of the LM1971 to be degraded.

A more stable half-supply node can be obtained by actively

buffering the resistor divider network with a voltage follower

as shown in Figure 6. Supply fluctuations are then isolated

by the high input impedance/low output impedance mis-

match associated with effective filtering. Since the LM1971 is

a single channel device, using a dual JFET input op amp is

optimum for both output buffering and half-supply biasing.

A 10 µF capacitor or larger is recommended for better

half-supply stabilization. For added rejection of higher fre-

LM 1971 Channel Attenuation

vs Digital Step Value

(1 dB, 2 dB, and 4 dB Steps)

01235306

FIGURE 5. LM1971 Attenuation Step Scheme

LM1971

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Application Information (Continued)

quency power supply fluctuations, a smaller capacitor

(0.01 µF–0.1 µF) could be added in parallel to the 10 µF

capacitor.

LOGARITHMIC GAIN AMPLIFIER

The µPot is capable of being used in the feedback loop of an

op amp to create a gain controlled amplifier as shown in

Figure 8. In this configuration the attenuation levels from

Table 1 become gain levels with the largest possible gain

value being 62 dB. For most applications, 62 dB of gain will

cause signal clipping to occur. However, this can be con-

trolled through programming. It is important to note that

when in mute mode the input is disconnected from the

output, thus placing the amplifier in open-loop gain state. In

this mode, the amplifier will behave as a comparator. Care

should be taken with the programming and design of this

type of circuit. To provide the best overall performance, a

high input impedance, low input bias current op amp should

be used.

MUTE FUNCTION

A major feature of the LM1971 is its ability to mute the input

signal to an attenuation level of 102 dB. This is accom-

plished internally by physically disconnecting the output from

the input while also grounding the output pin through ap-

proximately 2 kΩ.

The mute function is obtained during power-up of the device

or by sending any binary data of 0011 1111 and above

serially to the device. The device may be placed into mute at

any time during operation, allowing the designer to make the

mute command accessible to the end-user.

DC INPUTS

Although the µPot was designed to be used as an attenuator

for signals within the audio spectrum, it is also capable of

tracking and attenuating an input DC voltage. The device will

track voltages to either supply rail.

One point to remember about DC tracking is that with a

buffer at the output of the µPot, the resolution of DC tracking

will depend upon the gain configuration of that output buffer

and its supply voltage. Also, the output buffer’s supply volt-

age does not have to be the same as the µPot’s supply

voltage. Giving the buffer some gain can provide more reso-

lution when tracking small DC voltages.

01235307

FIGURE 6. Higher Performance

Active Half-Supply Buffering

01235308

FIGURE 7. Active Reference with Active Gain Buffering

01235309

FIGURE 8. Logarithmic Gain Amplifier Circuit

LM1971

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Physical Dimensions inches (millimeters)

unless otherwise noted

Order Number LM1971M

8-Lead (0.150" Wide) Molded Small Outline Package, JEDEC

NS Package Number M08A

LM1971

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Order Number LM1971N

8-Lead (0.300" Wide) Molded Dual-In-Line Package

NS Package Number N08E

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can be reasonably expected to cause the failure of

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LM1971 Overture Audio Attenuator Series Digitally Controlled 62 dB Audio Attenuator with Mute

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.