TJA1022TK,118 - NXP Semiconductors

1. General description

The TJA1022 is a dual LIN transceiver that provides the interface between a Local

Interconnect Network (LIN) master/slave protocol controller and the physical bus in a LIN

network. It is primarily intended for in-vehicle subnetworks using baud rates up to 20 kBd

and is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602. The TJA1022 is

pin compatible with th e TJA1020, TJA10 21 and TJA102 7 ( see Section 18). The TJA1022

and TJA1027 are also software compatible.

The transmit data streams generated by the protocol controller are converted by the

TJA1022 into optimized bus signals shaped to minimize ElectroMagnetic Emissions

(EME). The LIN bus output pins are pulled HIGH via internal termination resistors. For a

master application, an external resistor in series with a diode should be connected

between pin VBAT and each of the LIN pin s. The re ceivers dete ct receive da ta streams on

the LIN bus input pins and transfer them via pins RXD1 and RXD2 to the microcontroller.

Power consumption is very low when both transceivers are in Sleep mode. However, the

TJA1022 can still be woken up via pins LIN1/LIN2 and SLP1_N/SLP2_N.

2. Features and benefits

2.1 General

Two LIN transceivers in a single package

LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602 compliant

Baud rate up to 20 kBd

Very low ElectroMagnetic Emissions (EME)

Very low current consumption in Sleep mode with remote LIN wake-up

Input levels compatible with 3.3 V and 5 V devices

Integrated termination resistors for LIN slave applications

Passive behavior in unpowered state

Operational during cranking pulse: full operation from 5 V upwards

Undervoltage detectio n

K-line compatible

Available in SO14 and HVSON14 packages

Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical

Inspection (AOI) capability

Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)

compliant)

Pin-compatible with the TJA1020, TJA1021 and TJA1027 (see Section 18)

Software-compatible with the TJA1027

TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

Rev. 2 — 24 April 2013 Product data sheet

Product data sheet Rev. 2 — 24 April 2013 2 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

2.2 Protection

Very high ElectroMagnetic Immunity (EMI)

Very high ESD robustness: 8 kV according to IEC 61000-4-2 for pin s LIN1 , LIN2 a nd

VBAT

Bus terminal and battery pin protected against transients in the automotive

environmen t (IS O 7637)

Bus terminal short-circuit proof to battery and ground

Thermally protected

Initial TXD dominant check when switching to Normal mode

TXD dominant time-out function

3. Quick reference data

4. Ordering information

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VBAT battery supply voltage limiting values 0.3 - +42 V

operating range 5 - 18 V

IBAT battery supply current Sleep mode (both channels); bus recessive (both

channels); VLINx =V

BAT; VSLPx_N =0V 2.5 7 10 A

Standby mode (both channel s); bus recessive

(both channels); VLINx =V

BAT; VSLPx_N =0V 2.5 7 10 A

Normal mode (both channels); bus recessive

(both channels); VTXDx =5 V; V

LINx = VBAT;

VSLPx_N = 5 V

300 1600 3200 A

VLIN voltage on pin LIN pins LIN1 and LIN2; limiting value; with respect

to GND and VBAT

42 - +42 V

VESD electrostatic discharge voltage on pins LIN1, LIN2 and VBAT; according to IEC

61000-4-2 8- +8kV

Tvj virtual junction temperature 40 - +150 C

Table 2. Ordering informatio n

Type number Package

Name Description Version

TJA1022T SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

TJA1022TK HVSON14 plastic, thermal enhanced very thin small outline package; no leads;

14 terminals; body 3  4. 5  0.85 mm SOT1086-2

Product data sheet Rev. 2 — 24 April 2013 3 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

5. Block diagram

Fig 1. Block diagram

POWER-ON RESET AND

UNDERVOLTAGE DETECTION

TJA1022

GND

015aaa288

TEMPERATURE

PROTECTION

CONTROL

BUS

TIMER

VBAT

LIN1

SLP1_N

TXD1

RXD1

DOM

TIMER

BUS

TIMER

LIN2

SLP2_N

TXD2

RXD2

DOM

TIMER

VBAT

Product data sheet Rev. 2 — 24 April 2013 4 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

6. Pinning information

6.1 Pinning

6.2 Pin description

[1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON14 package

should be soldered to board ground (and not to any other voltage level).

a. TJA1022T: SO14 package b. TJA1022TK: HVSON14 package

Fig 2. Pin configuratio n diagrams

TJA1022T

RXD1 n.c.

SLP1_N LIN1

TXD1 n.c.

RXD2 n.c.

SLP2_N V

BAT

n.c. LIN2

TXD2 GND

015aaa286

7 8

terminal 1

index area TJA1122TK

015aaa287

RXD1 1

SLP1_N 2

RXD2 4

SLP2_N 5

n.c. 6

TXD2 7

n.c.14

LIN113

n.c.12

n.c.11

BAT

LIN29

GND8

TXD1

Table 3. Pin description

Symbol Pin Description

RXD1 1 receive data output 1 (open-drain); active LOW after a wake-up event

SLP1_N 2 sleep control input 1 (active LOW); resets wake-up request on RXD1

TXD1 3 transmit data input 1

RXD2 4 receive data output 2 (open-drain); active LOW after a wake-up event

SLP2_N 5 sleep control input 2 (active LOW); resets wake-up request on RXD2

n.c. 6 not connected

TXD2 7 transmit data input 2

GND 8[1] ground

LIN2 9 LIN bus line 2 input/output

VBAT 10 battery supply

n.c. 11 not connected

n.c. 12 not connected

LIN1 13 LIN bus line 1 input/output

n.c. 14 not connected

Product data sheet Rev. 2 — 24 April 2013 5 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

7. Functional description

The TJA1022 is the int er fa ce be tw ee n th e LI N mas te r/s lave protocol con trolle r an d the

physical bus in a LIN net wor k. Accor din g to the Open System Interconnect (OSI) model,

this is the LIN physical layer.

The LIN transceivers are optimized for, but not limited to, automotive applications with

excellent ElectroMagnetic Compatibility (EMC) performance.

7.1 LIN 2.x/SAE J2602 compliant

The TJA1022 is fully LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602 compliant. The

LIN physical layer is independent of higher OSI model layers (e.g. the LIN protocol).

Consequently, nodes containing a LIN 2.2A-compliant physical layer can be combined,

without restriction, with LIN physical layer nodes that comply with earlier revisions

(LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0, LIN 2.1 and LIN 2.2).

7.2 Operati ng modes

The transceivers are fully operational in Normal mode. A low-power Sleep mode is also

supported, as well as a Reset mode. Standby mode facilitates the transition between

Sleep and Normal modes.

The transceivers operate independently (except in Reset mode), so one transceiver can

be in Normal mode while the other is Sleep or Standby etc. Power consumption is at a

minimum when both transceivers are in Sleep mode.

7.2.1 Normal mode

In Normal mode, the TJA1022 can transmit and receive data via the LIN bus lines. The

transceivers operate independently, so one can be active while the other is off.

A transceiver will switch from Sleep or Standby mode to Normal mode if SLPx_N is held

HIGH for tgotonorm. If SLPx_N is held LOW for tgotosleep, the transceiver will switch from

Normal to Sleep mode.

The receivers detect data streams on the LIN bus lines (via pins LIN1 and LIN2) and

transfer the input via pins RXD1 and RXD2 to the microcontroller (see Figure 6): HIGH for

a recessive level and LOW for a dominant level on the bus. The receivers have

supply-voltage related thresholds with hysteresis and integrated filters to suppress bus

line noise.

T ransmit data streams from the protocol controller are detected on the TXDx pins and are

converted by the transmitters into optimized bus signals shaped to minimize EME. The

LIN bus output pins are pulled HIGH via internal slave termination resistors. For a master

application, an external resistor in series with a diode should be connected between pin

VBAT and the appropriate LINx pin (see Figure 6).

Product data sheet Rev. 2 — 24 April 2013 6 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

7.2.2 Sleep mode

A transceiver will switch to Sleep mode from Normal mode if SLPx_N is held LOW for

tgotosleep. The relevant LIN transmit path is disabled as soon as SLPx_N goes LOW.

Power consumption is very low when both transceivers are in Sleep mode.

The volt age levels on LINx and TXDx have no ef fect on a transition to Sleep mode. So the

transceiver will still switch to Sleep mode even if TXDx is held LOW or there is a

continuous dominant level on LINx (e.g. due to a short circuit to ground).

Although current consumption is extremely low when both transceivers are in Sleep

mode, the TJA1022 can still be woken up remotely via the LIN bus pins or by the

microcontroller via pins SLPx_N. Filters on the receiver inputs (LIN1 and LIN 2) and on

pins SLPx_N prevent unwanted wake-up events occurring due to automotive transients or

radio frequency interference. To be valid, all wake-up events must be maintained for a

specific length of time (twake(dom)LIN for a remote wake-up and tgotonorm for a wake-up via

SLPx_N). Pin RXDx is floating when a transceiver is in Sleep mode.

(1) A positive edge on SLPx_N triggers a transition to Normal mode in the corresponding LIN transceiver; the LIN transmitter is

enabled once TXDx goes HIGH; in the event of thermal shutdown, both LIN transceivers are disabled.

(2) Power dissipation is at a minimum when both transceivers are in Sleep mode.

(3) When a transceiver switches to Standby mode in response to a LIN bus wake-up event, the associated RXDx pin (RXD1 or

RXD2) will be LOW to indicate which LIN channel was the source of the wake-up request.

Fig 3. State diagram

015aaa290

(SLPx_N = 1)

> t

gotonorm

(SLPx_N = 1)

> t

gotonorm

(SLPx_N = 0)

> t

gotosleep

(LINx = 0 → 1; after LINx = 0)

> t

wake(dom)LIN

falling V

BAT

< V

th(POR)L

Normal x

RXDx: data output

Transmitter: on

(1)

Standby x

RXDx: LOW

(3)

Transmitter: off

Sleep x

(2)

RXDx: floating

Transmitter: off

Reset

RXDx: floating

Transmitter: off

rising V

BAT

> V

th(POR)H

Product data sheet Rev. 2 — 24 April 2013 7 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

If a remote wake-up event (see Figure 4) is detected on either of the LIN bus lines, the

associated transceiver will switch to Standby mode. A wake-up initiated by the

microcontroller (SLPx_N HIGH for t gotonorm) will cause the relevant transceiver to switch to

Normal mode while the other transceiver remains in its current state.

7.2.3 Standby mode

Standby mode is a n interme diate mode be twee n Slee p and Nor ma l mod es. A transceiver

will switch from Sleep mode to Standby mode in response to a LIN bus wake-up event.

Pin RXDx will go low to indicate to the microcontroller the source of the remote wake-up

(LIN1 or LIN2). A transceiver will switch from Standby to Normal mode if the

microcontroller holds SLPx_N HIGH for tgotonorm.

7.2.4 Reset mode

When the TJA1022 is in Reset mode, all input signals are ignored and all output drivers

are off. The TJA1022 switches to Reset mode when the voltage on VBAT drops below the

LOW-leve l power-on reset threshold, V th(POR)L. When the vo ltag e on VBAT rises above the

HIGH-level power-on reset threshold, Vth(POR)H, the transceivers switch to Sleep mode.

[1] Both transceivers enter Sleep mode after a power-on reset (e.g. after switching on VBAT).

[2] The appropriate transceiver will switch automatically to Standby x mode if a remote LINx wake-up event is

detected in Sleep x mode.

[3] RXDx will be LOW to indicate the source of the remote wake-up request; RXDx will go HIGH in response to

a positive edge on pin SLPx_N.

[4] A positive edge on SLPx_N will trigger a transition to Normal mode; the transmitter will be off if TXDx is

LOW and will be enabled as soon as TXDx goes HIGH.

Table 4. Operating mo des

Mode SLPx_N RXDx Transmitter x Description

Reset x floating off all inputs ignored; all output

drivers off

Sleep x[1] 0 floating off no wake-up request detected

Standby x[2] 0LOW

[3] off remote wake-up request

detected

Normal x 1 HIGH: recessive

LOW: dominant on/off[4] bus signal shaping enabled

Product data sheet Rev. 2 — 24 April 2013 8 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

7.3 Transceiver wake-up

7.3.1 Remote wake-up via the LIN bus

A falling edge on pin LINx followed by a LOW level main tained for twake(dom)LIN followed by

a rising edge on pin LINx triggers a remote wake-up (see Figure 4). It should be noted that

the time period twake(dom)LIN is measured either in Nor mal mode while TXDx is HIGH, or in

Sleep mode irrespective of the status of pin TXDx.

7.3.2 Wake-up via SLPx_N

If SLPx_N is held HIGH for tgotonorm, the transceiver will switch from Sleep mode to

Normal mode.

7.4 Operation during automotive cranking pulses

TJA1022 remains fully operational during automotive cranking pulses because the LIN

transceivers are fully specified down to VBAT = 5 V.

7.5 Operation when supply voltage is outside specified operating range

If VBAT > 18 V or VBAT < 5 V, the TJA1022 may remain operational, but parameter values

cannot be guaranteed to remain within the operating ranges specified in Table 7 and

Table 8.

In Normal mode:

•If the input level on pin TXDx is HIGH, the LIN transmitter output on pin LINx will be

recessive.

•If the input level on pin LINx is recessive, the receiver output on pin RXDx will be

HIGH.

•If the voltage on pin VBAT rises to 27 V (e.g. during an automotive jump-start), the total

LIN network pull-up resist ance should be gre ater than 680  and the total LIN network

capacitance should be less than 6.8 nF to ensure reliable LIN data transfer.

•If the voltage on pin V BAT drops below the LOW -level VBAT LOW threshold, Vth(VBATL)L,

the active LIN transmit path(s) is interrupted and both LIN outputs will be recessive.

The previously active LIN transmit path(s) is switched on again when VBAT rises

above Vth(VBATL)H and the associated TXDx pin is HIGH.

Fig 4. Remote wake-up behavior

015aaa297

LIN recessive

LIN dominant

sleep mode standby mode

VBUSdom

VBUSrec

ground

VLINx twake(dom)LIN

Product data sheet Rev. 2 — 24 April 2013 9 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

If the voltage on pin VBAT drops below the LOW-level power-on reset threshold, Vth(POR)L,

the TJA1022 switches to Reset mode (i.e. all output drivers are disabled an d all inputs are

ignored). The TJA1022 switches to Sleep mode if VBAT > Vth(POR)H.

7.6 Fail-safe features

Pin TXDx is pulled down to ground in order to force a predefined level on the transmit dat a

input if the pin is disconnected.

Pin SLPx_N is pulled down to ground to ensure the tran scei ver is fo rced to Sleep x mode

if SLPx_N is disconnected.

Pins RXD1 and RXD2 are set floating if VBAT is disconnected.

The current in the transmitter output stage is limited in order to protect the transmitter

against short circuits to pins VBAT or GND.

A loss of power (pins VBAT and GND) has no impact on the bus lines or on the

microcontroller. No reverse current will flow from the bus lines into the LINx pins. The

current path from VBAT to LINx via the integrated LIN slave termination resistors remains.

The TJA1022 can be disconnected from the power supply without influencing the LIN

busses.

The output drivers on pins LIN1 and LIN2 are protected against ove rtemperature

conditions. If the junction temperature exceeds the shutdown junction temperature, Tj(sd),

the thermal prote ct i on circu it disa b les th e ou tp ut drive rs . Th e dr ive rs ar e ena ble d ag a in

when the junction temperature falls below Tj(sd) and pin TXDx is HIGH.

The initial TXD dominant check prevents the bus being driven to a permanent dominant

state (blocking all network communications) if pin TXDx is forced permanently LOW by a

hardware and/or software application failure. The input level on TXDx is checked after a

transition to Normal mode. If TXDx is LOW, the transmit path will remain disabled and will

only be enabled when TXDx goes HIGH.

Once the transmitter has been enabled, a TXD dominant time-out timer is started every

time pin TXDx goes LOW. If the LOW state on pin TXDx pe rsists for longer than the

TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, releasing the bus

line to recessive state. The TXD dominant time-out timer is reset when pin TXDx goes

HIGH.

Product data sheet Rev. 2 — 24 April 2013 10 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

8. Limiting values

[1] Equivalent to discharging a 150 pF capacitor through a 330  resistor.

[2] Equivalent to discharging a 100 pF capacitor through a 1.5 k  resistor.

[3] Equivalent to discharging a 200 pF capacitor through a 10  resistor and a 0.75 H coil.

[4] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tj=T

amb +PRth(j-a), where Rth(j-a) is a fixed value.

The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).

9. Thermal characteristics

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND, unless

otherwise specified. Positive currents flow into the IC.

Symbol Parameter Conditions Min Max Unit

VBAT battery supply voltage 0.3 +42 V

VTXD voltage on pin TXD pins TXD1 and TXD2 0.3 +7 V

VRXD voltage on pin RXD pins RXD1 and RXD2 0.3 +7 V

VSLP_N voltage on pin SLP_N pins SLP1_N and SLP2_N 0.3 +7 V

VLIN voltage on pin LIN pins LIN1 and LIN2; with respect to

GND and VBAT

42 +42 V

V(LIN1-LIN2)voltage difference between pin

LIN1 and pin LIN2 (absolute

value)

-42 V

VESD electrostatic discharge voltage

according to IEC 61000-4-2 on pins LIN1, LIN2 and VBAT [1] 8+8 kV

human body model on pins LIN1, LIN2 and VBAT [2] 8+8 kV

on pins TXD1, TXD2, RXD1, RXD2,

SLP1_N and SLP2_N [2] 2+2 kV

charge device model all pins 750 +750 V

machine model all pins [3] 200 +200 V

Tvj virtual junction temperature [4] 40 +150 C

Tstg storage temperature 55 +150 C

Table 6. Thermal characteristics

According to IEC 60747-1.

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient SO14 package; in free air 145 K/W

HVSON14 package; in free air 50 K/W

Product data sheet Rev. 2 — 24 April 2013 11 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

10. Static characteristics

Table 7. Static ch aracteristics

VBAT = 5 V to 18 V; Tvj =





C to +150



C; RL(LIN-VBAT) = 500



; all voltages are referenced to pin GND; positive currents

flow into the IC; typical values are given at VBAT = 12 V ; unl e ss ot herwise spec if ie d . [1]

Symbol Parameter Conditions Min Typ Max Unit

Supply

VBAT battery supply voltage 5 - 18 V

IBAT batte ry supply current Sleep mode (both channels);

bus recessive (both channels);

VLINx =V

BAT; VSLPx_N =0V

2.5 7 10 A

Sleep mode (both channels);

bus dominant (both channels);

VLINx =0V; V

SLPx_N =0V;

VBAT =12V

300 800 3200 A

Standby mode (both chan nels);

bus recessive (both channels);

VLINx =V

BAT; VSLPx_N =0V

2.5 7 10 A

Standby mode (both chan nels);

bus dominant (both channels);

VLINx =0V; V

SLPx_N =0V;

VBAT =12V

200 600 2000 A

Normal mode (both channels);

bus recessive (both channels);

VTXDx =5 V; V

LINx =V

BAT;

VSLPx_N =5V

300 1600 3200 A

Normal mode (both channels);

bus dominant (both channels);

VTXDx =0 V; V

SLPx_N =5V;

VBAT = 12 V

1410mA

Undervoltage reset

Vth(POR)L LOW -level power-on reset

threshold vo ltage power-on reset 1.6 3.1 3.9 V

Vth(POR)H HIGH-level power-on reset

threshold vo ltage 2.3 3.4 4.3 V

Vhys(POR) power-on reset hysteresis

voltage [2] 0.05 0.3 1 V

Vth(VBATL)L LOW-level VBAT LOW

threshold vo ltage 3.9 4.4 4.7 V

Vth(VBATL)H HIGH-level VBAT LOW

threshold vo ltage 4.2 4.7 4.9 V

Vhys(VBATL) VBAT LOW hyster e s is

voltage [2] 0.15 0.3 0.6 V

Pins TXDx and SLPx_N

VIH HIGH-level input voltage 2 - 7 V

VIL LOW-level input voltage 0.3 - +0.8 V

Vhys hysteresis vol tage [2] 50 200 400 mV

Rpd pull-down resistance on TXDx 50 125 325 k

on SLPx_N 100 250 6 50 k

Product data sheet Rev. 2 — 24 April 2013 12 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to

cover the specified temperature and power supply voltage range.

[2] Not tested in production; guaranteed by design.

IIL LOW-level input current VTXDx = 0 V or VSLPx_N =0 V 5- +5A

Pin RXDx (open-drain)

IOL LOW-level output current VRXDx =0.4V 2 - - mA

ILH HIGH-level leakage

current [2] 5- +5A

Pin LINx

IBUS_LIM current limitation for driver

dominant state VBAT =18V; V

LINx =18V;

VTXDx =0V 40 - 100 mA

IBUS_PAS_dom receiver dominant input

leakage current including

pull-up resistor

VBAT = 12 V; VLINx = 0 V ;

VTXDx = 5 V [2] 600 - - A

IBUS_PAS_rec receiver recessive input

leakage current VBAT = 5 V; VLINx = 18 V;

VTXDx = 5 V [2] -01A

IBUS_NO_GND loss-of-ground bus current VBAT =18V; V

LINx =0V [2] 750 - +10 A

IBUS_NO_BAT loss-of-battery bus current VBAT =0V; V

LINx =18V [2] --1A

VBUSdom receiver dominant state - - 0.4VBAT V

VBUSrec receiver recessive state 0.6VBAT -- V

VBUS_CNT receiver center voltage VBUS_CNT =

(VBUSdom + VBUSrec)/2 0.475VBAT 0.5VBAT 0.525VBAT V

VHYS receiver hysteresis voltage VHYS = VBUSrec VBUSdom - - 0.175VBAT V

VSerDiode voltage drop at the serial

diode in pull-up path with Rslave;

ISerDiode =0.9mA [2] 0.4 - 1.0 V

VO(dom) dominant output voltage Normal mode; VTXDx = 0 V ;

VBAT = 7.0 V [2] --1.4V

Normal mode; VTXDx = 0 V;

VBAT = 18 V [2] --2.0V

Rslave slave resistance 20 30 6 0 k

CLIN capacitance on pin LIN pins LIN1 and LIN2; with

respect to GND [2] --20pF

Thermal shutdown

Tj(sd) shutdown junction

temperature [2] 150 - 200 C

Table 7. Static ch aracteristics …continued

VBAT = 5 V to 18 V; Tvj =





C to +150



C; RL(LIN-VBAT) = 500



; all voltages are referenced to pin GND; positive currents

flow into the IC; typical values are given at VBAT = 12 V ; unl e ss ot herwise spec if ie d . [1]

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 24 April 2013 13 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

11. Dynamic characteristics

[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to

cover the specified temperature and power supply voltage ranges.

Table 8. Dynamic characteristics

VBAT = 5 V to 18 V; Tvj =





C to +150



C; RL(LIN-VBAT) = 500



; all voltages are referenced to pin GND; positive currents

flow into the IC; typical values are given at VBAT = 12 V, unless otherwise specified.[1]

Symbol Parameter Conditions Min Typ Max Unit

Duty cycles

1 duty cycle 1 Vth(rec)(max) = 0.744 VBAT;

Vth(dom)(max) = 0.581 VBAT;

tbit = 50 s; VBAT =7Vto18V

[2][4][5] 0.396 - -

Vth(rec)(max) =0.768 VBAT;

Vth(dom)(max) = 0.6 VBAT;

tbit = 50 s; VBAT =5Vto7V

[2][4][5] 0.396 - -

2 duty cycle 2 Vth(rec)(min) = 0.422  VBAT;

Vth(dom)(min) = 0.284 VBAT;

tbit =50s; VBAT =7.6Vto18V

[3][4][5] --0.581

Vth(rec)(min) = 0.405  VBAT;

Vth(dom)(min) = 0.271 VBAT;

tbit =50s; VBAT = 5.6 V to 7.6 V

[3][4][5] --0.581

3 duty cycle 3 Vth(rec)(max) = 0.778  VBAT;

Vth(dom)(max) = 0.616 VBAT;

tbit =96s; VBAT =7Vto18V

[2][4][5] 0.417 - -

Vth(rec)(max) = 0.805  VBAT;

Vth(dom)(max) = 0.637 VBAT;

tbit =96s; VBAT =5Vto7V

[2][4][5] 0.417 - -

4 duty cycle 4 Vth(rec)(min) = 0.389  VBAT;

Vth(dom)(min) = 0.251 VBAT;

tbit =96s; VBAT =7.6Vto18V

[3][4][5] --0.590

Vth(rec)(min) = 0.372  VBAT

Vth(dom)(min) = 0.238 VBAT

tbit =96s; VBAT = 5.6 V to 7.6 V

[3][4][5] --0.590

Tim in g ch ar acteristics

trx_pd receiver propagation

delay rising and falling;

CRXDx = 20 pF; RRXDx = 2.4 k

[5] --6s

trx_sym receiver propagation

delay symmetry CRXDx = 20 pF; RRXDx = 2.4 k;

rising edge with respect to falling edge [5] 2- +2s

twake(dom)LIN LIN dominant wake-up

time Sleep mode 30 80 150 s

tgotonorm go to normal time time period for mode change from

Sleep or Standby mode to Normal

mode

2610s

tinit(norm) normal mode

initialization time 7- 20s

tgotosleep go to sleep time time period for mode change from

Normal to Sleep mode 2610s

tto(dom)TXD TXD dominant time-out

time timer started at falling edge on TXDx 6 12 50 ms

Product data sheet Rev. 2 — 24 April 2013 14 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

[2] . Variable tbus(rec)(min) is illustrated in the LIN timing diagram in Figure 5.

[3] . Variable tbus(rec)(max) is illustrated in the LIN timing diagram in Figure 5.

[4] Bus load conditions: CBUS = 1 nF and RBUS =1k; CBUS = 6.8 nF and RBUS = 660 ; CBUS = 10 nF and RBUS = 500 .

[5] See timing diagram in Figure 5.

13tbus recmin

bit



-------------------------------

24tbus recmax

bit



--------------------------------

Fig 5. Timi ng diag ram of LIN tra n sc e iver duty cycle

VTXDx

tbit tbit

Vth(rec)(max)

Vth(dom)(max)

Vth(rec)(min)

Vth(dom)(min)

thresholds of

receiving node 1

thresholds of

receiving node 2

LINx BUS

signal

VBAT

receiving

node 1

receiving

node 2

VRXDx

trx_pdf

015aaa296

trx_pdf

trx_pdr trx_pdf

trx_pdf

trx_pdr

tbus(rec)(min)

tbus(dom)(max)

tbus(rec)(max)

tbus(dom)(min)

Product data sheet Rev. 2 — 24 April 2013 15 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

12. Application information

12.1 Application diagram

12.2 ESD robustness according to LIN EMC test specification

ESD robustness (IEC 61000-4-2) has been tested by an external test house according to

the LIN EMC test specification (part of Conformance Test Specification Package for

LIN 2.1, October 10th, 2008). The test report is available on request.

12.3 Hardware requirements for LIN interfaces in automotive applications

The TJA1022 satisfies the "Hardware Requ irement s for L IN, CAN and FlexRay Interfaces

in Automotive Applications", Version 1.2, March 2011.

(1) Master: C = 1 nF; slave: C = 220 pF

Fig 6. Application diagram

015aaa291

1 kΩ

VBAT

LIN BUS

LINE 1

only for

master node

TJA1022

VDD

GND

TX0

RX1

RX0

TXD1

RXD1

MICRO-

CONTROLLER

BATTERY

+3 V/

+5 V

LIN1

(1)

VECU

TXD2

RXD2

SLP1_N

SLP2_N

Px.x

Px.y

TX1

LIN2

(1)

1 kΩ

LIN BUS

LINE 2

Table 9. ESD robustness (IEC 61000-4-2) according to LIN EMC tes t specification

Pin Test configuration Value Unit

LIN no capacitor connected to LIN pin 12 kV

220 pF capacitor connected to LIN pin 12 kV

VBAT 100 nF capacitor connected to VBAT pin > 14kV

Product data sheet Rev. 2 — 24 April 2013 16 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

13. Test information

13.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for

integrated circuits, and is suitable for use in automotive applicat ion s.

Product data sheet Rev. 2 — 24 April 2013 17 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

14. Package outline

Fig 7. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 2 — 24 April 2013 18 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

Fig 8. Package outline SOT1086-2 (HVSON14)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1086-2 - - -

MO-229

- - -

sot1086-2

10-07-14

10-07-15

Unit

mm max

nom

min

1.00

0.85

0.80

0.05

0.03

0.00 0.2 4.6

4.5

4.4

4.25

4.20

4.15

3.1

3.0

2.9 0.65 3.9 0.45

0.40

0.35 0.1

Dimensions

HVSON14: plastic, thermal enhanced very thin small outline package; no leads;

14 terminals; body 3 x 4.5 x 0.85 mm SOT1086-2

A1b

0.35

0.32

0.29

cDD

hEE

1.65

1.60

1.55

0.35

0.30

0.25

0.1

0.05

0 2.5 5 mm

scale

terminal 1

index area

detail X

AC B

vCw

terminal 1

index area

Product data sheet Rev. 2 — 24 April 2013 19 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate prec a ut io ns ar e taken as

described in JESD625-A or equivalent standards.

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 2 — 24 April 2013 20 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 9) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in acco rdance with

Table 10 and 11

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach hig her temperatures duri ng reflow

soldering, see Figure 9.

Table 10. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 11. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 2 — 24 April 2013 21 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17. Soldering of HVSON packages

Section 16 contains a brief introduction to the techniques most co mmonly used to solder

Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON

leadless package ICs can be found in the following application notes:

•AN10365 “Surface mount reflow soldering description”

•AN10366 “HVQFN application information”

MSL: Moisture Sensitivity Level

Fig 9. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 2 — 24 April 2013 22 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

18. Mounting

The TJA1022 pin layou t has been de signed to be comp a tible with the TJA102 0, TJA1021

and TJA1027. This makes it possible to design a board with a single socket that can

accommodate all four IC’s. The appropriate device would be inserted into the socket,

depending on the application, as illustrated in Figure 10.

Fig 10. The TJA1022 is pin compatible with the TJA1027, TJA1020 and TJA1021

TJA1020

RXD INH

NSLP BAT

NWAKE LIN

TXD GND

TJA1027

RXD n.c.

SLP_N VBAT

n.c. LIN

TXD GND

TJA1021

RXD INH

SLP_N VBAT

WAKE_N LIN

TXD GND

TJA1022

RXD1 n.c.

SLP1_N LIN1

TXD1 n.c.

RXD2 n.c.

SLP2_N VBAT

n.c. LIN2

TXD2 GND

7 8

015aaa308

Product data sheet Rev. 2 — 24 April 2013 23 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

19. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TJA1022 v.2 20130424 Product data sheet - TJA1022 v.1

Modifications: •text in Title, Section 1, Section 2.1, Section 7.1 revised to include LIN 2.2A compliance

•text in Section 1 (first p aragraph) revised to be consistent with TJa1027/TJa1029

•Figure 2: revised/resized

•text in Section 7.1 revised to be consistent with TJA1029

•Section 13.1: text revised

TJA1022 v.1 20120330 Product data sheet - -

Product data sheet Rev. 2 — 24 April 2013 24 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

20.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless ot herwise agreed in writing, t he product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the appl ication or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the obj ective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 24 April 2013 25 of 26

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

No offer to sell or license — Nothing in this document may be interpret ed or

construed as an of fer to sell product s that is op en for accept ance or the grant ,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characte ristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Translations — A non-English (translated) versio n of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

20.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors TJA1022

Dual LIN 2.2A/SAE J2602 transceiver

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 24 April 2013

Document identifier: TJA1022

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

22. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

7.1 LIN 2.x/SAE J2602 compliant. . . . . . . . . . . . . . 5

7.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5

7.2.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.2.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2.4 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.3 Transceiver wake-up . . . . . . . . . . . . . . . . . . . . 8

7.3.1 Remote wake-up via the LIN bus . . . . . . . . . . . 8

7.3.2 Wake-up via SLPx_N . . . . . . . . . . . . . . . . . . . . 8

7.4 Operation during automotive cranking pulses . 8

7.5 Operation when supply voltage is outside

specified operating range . . . . . . . . . . . . . . . . . 8

7.6 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 9

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10

9 Thermal characteristics . . . . . . . . . . . . . . . . . 10

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 11

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13

12 Application information. . . . . . . . . . . . . . . . . . 15

12.1 Application diagram . . . . . . . . . . . . . . . . . . . . 15

12.2 ESD robustness according to LIN EMC

test specification. . . . . . . . . . . . . . . . . . . . . . . 15

12.3 Hardware requirements for LIN interfaces

in automotive applications . . . . . . . . . . . . . . . 15

13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 16

13.1 Quality information . . . . . . . . . . . . . . . . . . . . . 16

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17

15 Handling information. . . . . . . . . . . . . . . . . . . . 19

16 Soldering of SMD packages . . . . . . . . . . . . . . 19

16.1 Introduction to soldering. . . . . . . . . . . . . . . . . 19

16.2 Wave and reflow soldering . . . . . . . . . . . . . . . 19

16.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 19

16.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 20

17 Soldering of HVSON packages. . . . . . . . . . . . 21

18 Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 23

20 Legal information . . . . . . . . . . . . . . . . . . . . . . 24

20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 24

20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 24

20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 25

21 Contact information . . . . . . . . . . . . . . . . . . . . 25

22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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TJA1022T,118 TJA1022TK,118