LMP7731 www.ti.com SNOSAT6E - JULY 2007 - REVISED MARCH 2013 2.9 nV/sqrt(Hz) Low Noise, Precision, RRIO Amplifier Check for Samples: LMP7731 FEATURES DESCRIPTION 1 (Typical Values, TA = 25C, VS = 5V) 23 * * * * * * * * * * * Input Voltage Noise - f = 3 Hz 3.3 nV/Hz - f = 1 kHz 2.9 nV/Hz CMRR 130 dB Open Loop Gain 130 dB GBW 22 MHz Slew Rate 2.4 V/s THD @ f = 10 kHz, AV = +1, RL = 2 k 0.001% Supply Current per Channel 2.2 mA Supply Voltage Range 1.8V to 5.5V Operating Temperature Range -40C to 125C Input Bias Current 1.5 nA RRIO This operational amplifier offers low voltage noise of 2.9 nV/Hz with a 1/f corner of only 3 Hz. The LMP7731 has bipolar input stages with a bias current of only 1.5 nA. This low input bias current, complemented by the very low level of voltage noise, makes the LMP7731 an excellent choice for photometry applications. The LMP7731 provides a wide GBW of 22 MHz while consuming only 2 mA of current. This high gain bandwidth along with the high open loop gain of 130 dB enables accurate signal conditioning in applications with high closed loop gain requirements. The LMP7731 has a supply voltage range of 1.8V to 5.5V, making it an ideal choice for battery operated portable applications. APPLICATIONS * * * The LMP7731 is a single, low noise, rail-to-rail input and output, low voltage amplifier. The LMP7731 is part of the LMPTM precision amplifier family and is ideal for precision and low noise applications with low voltage requirements. Gas Analysis Instruments Photometric Instrumentation Medical Instrumentation The LMP7731 is offered in the space saving 5-Pin SOT-23 and 8-Pin SOIC packages. Typical Performance Characteristics Input Voltage Noise vs. Frequency Input Current Noise vs. Frequency 100 100 10 VS = 2.5V, 3.3V, 5V CURRENT NOISE (pA/ Hz) VOLTAGE NOISE (nV/ Hz) VS = 2.5V, 3.3V, 5V VCM = 0.5V VCM = 2.5V VCM = 0.5V 10 VCM = 2.5V 1 0.1 1 10 100 1k 10k 1 0.1 1 10 100 FREQUENCY (Hz) FREQUENCY (Hz) Figure 1. Figure 2. 1k 10k 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LMP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2013, Texas Instruments Incorporated LMP7731 SNOSAT6E - JULY 2007 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (3) (1) (2) Human Body Model Inputs pins only 2000V All other pins 2000V Machine Model 200V Charge Device Model 1000V VIN Differential 2V Supply Voltage (VS = V+ - V-) 6.0V -65C to 150C Storage Temperature Range Junction Temperature (4) +150C max Soldering Information (1) (2) (3) (4) Infrared or Convection (20 sec) 235C Wave Soldering Lead Temp. (10 sec) 260C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC Board. Operating Ratings (1) -40C to 125C Temperature Range + - Supply Voltage (VS = V - V ) Package Thermal Resistance (JA) (1) 1.8V to 5.5V 5-Pin SOT-23 265C/W 8-Pin SOIC 190C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. 2.5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 2.5V, V- = 0V, VCM = V+/2, RL >10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter Input Offset Voltage VOS (1) (2) (3) (4) 2 Min (2) Typ (3) Input Offset Voltage Temperature Drift Max (2) VCM = 2.0V 9 500 600 VCM = 0.5V 9 500 600 VCM = 2.0V 0.5 5.5 VCM = 0.5V 0.2 5.5 VCM = 2.0V 1 30 45 VCM = 0.5V 12 50 75 (4) TCVOS IB Test Conditions Input Bias Current Units V V/C nA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum Ratings indicate junction temperature limits beyond which the device maybe permanently degraded, either mechanically or electrically. All limits are specified by testing, statistical analysis or design. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Ambient production test is performed at 25C with a variance of 3C. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 LMP7731 www.ti.com SNOSAT6E - JULY 2007 - REVISED MARCH 2013 2.5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 2.5V, V- = 0V, VCM = V+/2, RL >10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter IOS TCIOS CMRR PSRR Test Conditions Min (2) AVOL (3) Common Mode Rejection Ratio Power Supply Rejection Ratio Common Mode Voltage Range Open Loop Voltage Gain 1 VCM = 0.5V 11 60 80 VCM = 0.5V and VCM = 2.0V 0.0474 0.15V VCM 0.7V 0.23V VCM 0.7V 101 89 120 1.5V VCM 2.35V 1.5V VCM 2.27V 105 99 129 2.5V V+ 5V 111 105 129 Large Signal CMRR 80 dB 0 112 104 130 RL = 2 k to V+/2 VOUT = 0.5V to 2.0V 109 90 119 dB V dB RL = 10 k to V+/2 4 50 75 RL = 2 k to V+/2 13 50 75 RL = 10 k to V /2 6 50 75 RL = 2 k to V+/2 9 50 75 Output Voltage Swing Low IS nA/C 2.5 RL = 10 k to V+/2 VOUT = 0.5V to 2.0V + Supply Current (Per Channel) nA 117 VOUT Output Current Units dB Output Voltage Swing High IOUT (2) VCM = 2.0V Input Offset Current Input Offset Current Drift Max 50 75 1.8V V+ 5.5V CMVR Typ Sourcing, VOUT = V+/2 VIN (diff) = 100 mV 22 12 31 Sinking, VOUT = V+/2 VIN (diff) = -100 mV 15 10 44 mV from either rail mA VCM = 2.0V 2.0 2.7 3.4 VCM = 0.5V 2.3 3.1 3.9 mA SR Slew Rate AV = +1, CL = 10 pF, RL = 10 k to V+/2, VO = 2 VPP 2.4 V/s GBW Gain Bandwidth CL = 20 pF, RL = 10 k to V+/2 21 MHz + GM Gain Margin CL = 20 pF, RL = 10 k to V /2 14 dB M Phase Margin CL = 20 pF, RL = 10 k to V+/2 60 deg RIN Input Resistance THD+N Total Harmonic Distortion + Noise AV = 1, f = 1 kHz, Amplitude = 1V Input Referred Voltage Noise Density f = 1 kHz, VCM = 2.0V 3 f = 1 kHz, VCM = 0.5V 3 Input Voltage Noise 0.1 Hz to 10 Hz 75 Input Referred Current Noise Density f = 1 kHz, VCM = 2.0V 1.1 f = 1 kHz, VCM = 0.5V 2.3 en in Differential Mode 38 k Common Mode 151 M 0.002 % nV/Hz nVPP pA/Hz Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 3 LMP7731 SNOSAT6E - JULY 2007 - REVISED MARCH 2013 3.3V Electrical Characteristics www.ti.com (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 3.3V, V- = 0V, VCM = V+/2, RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter Input Offset Voltage VOS Test Conditions Min (2) Typ (3) IB Input Offset Voltage Temperature Drift VCM = 2.5V 6 VCM = 0.5V 6 500 600 VCM = 2.5V 0.5 5.5 VCM = 0.5V 0.2 5.5 VCM = 2.5V 1.5 30 45 VCM = 0.5V 13 50 77 VCM = 2.5V 1 50 70 VCM = 0.5V 11 60 80 Input Bias Current IOS Input Offset Current TCIOS CMRR PSRR Input Offset Current Drift Common Mode Rejection Ratio Power Supply Rejection Ratio VCM = 0.5V and VCM = 2.5V 0.048 0.15V VCM 0.7V 0.23V VCM 0.7V 101 89 120 1.5V VCM 3.15V 1.5V VCM 3.07V 105 99 130 2.5V V+ 5.0V 111 105 129 + 1.8V V 5.5V CMVR Common Mode Voltage Range Large Signal CMRR 80 dB + AVOL Open Loop Voltage Gain RL = 10 k to V /2 VOUT = 0.5V to 2.8V + RL = 2 k to V /2 VOUT = 0.5V to 2.8V 0 130 110 92 119 SR (1) (2) (3) (4) 4 Slew Rate nA nA dB V dB RL = 10 k to V+/2 5 50 75 RL = 2 k to V+/2 14 50 75 RL = 10 k to V /2 9 50 75 RL = 2 k to V+/2 13 50 75 Output Voltage Swing Low IS V/C nA/C 3.3 112 104 + Supply Current (Per Channel) V 117 VOUT Output Current Units dB Output Voltage Swing High IOUT (2) 500 600 (4) TCVOS Max Sourcing, VOUT = V+/2 VIN (diff) = 100 mV 28 22 45 Sinking, VOUT = V+/2 VIN (diff) = -100 mV 25 20 48 mV from either rail mA VCM = 2.5V 2.1 2.8 3.5 VCM = 0.5V 2.4 3.2 4.0 AV = +1, CL = 10 pF, RL = 10 k to V+/2, VOUT = 2 VPP 2.4 mA V/s Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum Ratings indicate junction temperature limits beyond which the device maybe permanently degraded, either mechanically or electrically. All limits are specified by testing, statistical analysis or design. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Ambient production test is performed at 25C with a variance of 3C. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 LMP7731 www.ti.com SNOSAT6E - JULY 2007 - REVISED MARCH 2013 3.3V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 3.3V, V- = 0V, VCM = V+/2, RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter GBW Test Conditions Gain Bandwidth Min (2) Typ + 22 + CL = 20 pF, RL = 10 k to V /2 (3) Max (2) Units MHz GM Gain Margin CL = 20 pF, RL = 10 k to V /2 14 dB M Phase Margin CL = 20 pF, RL = 10 k to V+/2 62 deg RIN Input Resistance THD+N Total Harmonic Distortion + Noise AV = 1, f = 1 kHz, Amplitude = 1V, Input Referred Voltage Noise Density f = 1 kHz, VCM = 2.5V 2.9 f = 1 kHz, VCM = 0.5V 2.9 Input Voltage Noise 0.1 Hz to 10 Hz 65 Input Referred Current Noise Density f = 1 kHz, VCM = 2.5V 1.1 f = 1 kHz, VCM = 0.5V 2.1 en in 5V Electrical Characteristics Differential Mode 38 k Common Mode 151 M 0.002 % nV/Hz nVPP pA/Hz (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5V, V- = 0V, VCM = V+/2, RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter Input Offset Voltage VOS Test Conditions Min (2) IB Input Offset Voltage Temperature Drift CMRR PSRR Input Offset Current Drift Common Mode Rejection Ratio Power Supply Rejection Ratio 6 VCM = 0.5V 6 500 600 VCM = 4.5V 0.5 5.5 VCM = 0.5V 0.2 5.5 VCM = 4.5V 1.5 30 50 VCM = 0.5V 14 50 85 VCM = 4.5V 1 50 70 VCM = 0.5V 11 65 80 VCM = 0.5V and VCM = 4.5V 0.0482 0.15V VCM 0.7V 0.23V VCM 0.7V 101 89 120 1.5V VCM 4.85V 1.5V VCM 4.77V 105 99 130 2.5V V+ 5V 111 105 129 1.8V V+ 5.5V CMVR AVOL (4) Common Mode Voltage Range Open Loop Voltage Gain (2) VCM = 4.5V Input Offset Current TCIOS Max 500 600 Input Bias Current IOS (2) (3) (3) (4) TCVOS (1) Typ Large Signal CMRR 80 dB Units V V/C nA nA nA/C dB dB 117 0 5 RL = 10 k to V+/2 VOUT = 0.5V to 4.5V 112 104 130 RL = 2 k to V+/2 VOUT = 0.5V to 4.5V 110 94 119 V dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum Ratings indicate junction temperature limits beyond which the device maybe permanently degraded, either mechanically or electrically. All limits are specified by testing, statistical analysis or design. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Ambient production test is performed at 25C with a variance of 3C. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 5 LMP7731 SNOSAT6E - JULY 2007 - REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5V, V- = 0V, VCM = V+/2, RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter Test Conditions (2) Min Typ (3) Max RL = 10 k to V+/2 8 50 75 RL = 2 k to V+/2 24 50 75 RL = 10 k to V+/2 9 50 75 RL = 2 k to V+/2 23 50 75 Output Voltage Swing High VOUT Output Voltage Swing Low IOUT IS Output Current Supply Current (Per Channel) Sourcing, VOUT = V+/2 VIN (diff) = 100 mV 33 27 47 Sinking, VOUT = V+/2 VIN (diff) = -100 mV 30 25 49 (2) Units mV from either rail mA VCM = 4.5V 2.2 3.0 3.7 VCM = 0.5V 2.5 3.4 4.2 mA SR Slew Rate AV = +1, CL = 10 pF, RL = 10 k to V+/2, VOUT = 2 VPP 2.4 V/s GBW Gain Bandwidth CL = 20 pF, RL = 10 k to V+/2 22 MHz + GM Gain Margin CL = 20 pF, RL = 10 k to V /2 12 dB M Phase Margin CL = 20 pF, RL = 10 k to V+/2 65 deg RIN Input Resistance Differential Mode 38 k 151 M THD+N Total Harmonic Distortion + Noise AV = 1, f = 1 kHz, Amplitude = 1V 0.001 % Input Referred Voltage Noise Density f = 1 kHz, VCM = 4.5V 2.9 f = 1 kHz, VCM = 0.5V 2.9 Input Voltage Noise 0.1 Hz to 10 Hz 78 Input Referred Current Noise Density f = 1 kHz, VCM = 4.5V 1.1 f = 1 kHz, VCM = 0.5V 2.2 en in Common Mode nV/Hz nVPP pA/Hz Connection Diagrams OUT - V 5 1 N/C -IN 2 + +IN + V - 3 4 +IN 2 3 8 + 7 6 N/C + V OUT -IN V - Figure 3. 5-Pin SOT-23 Top View 6 1 4 5 N/C Figure 4. 8-Pin SOIC Top View Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 LMP7731 www.ti.com SNOSAT6E - JULY 2007 - REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Offset Voltage Distribution TCVOS Distribution 10 16 VS = 2.5V VS = 2.5V VCM = 2V 14 VCM = 2V 12 -40C d TA d 25C PERCENTAGE (%) PERCENTAGE (%) 8 6 4 10 8 6 4 2 2 0 -50 -40 -30 -20 -10 0 0 -0.5 10 20 30 40 50 0 VOS (PV) 0.5 Figure 5. 1.5 Figure 6. Offset Voltage Distribution TCVOS Distribution 10 16 VS = 3.3V, 5V VS = 3.3V, 5V VCM = VS -0.5V 14 VCM = VS -0.5V 12 -40C d TA d 25C PERCENTAGE (%) 8 PERCENTAGE (%) 1 TCVOS (PV/C) 6 4 10 8 6 4 2 2 0 -50 -40 -30 -20 -10 0 0 -0.5 10 20 30 40 50 0 VOS (PV) Figure 7. 1 1.5 Figure 8. Offset Voltage Distribution TCVOS Distribution 10 25 VS = 2.5V, 3.3V VS = 2.5V VCM = 0.5V VCM = 0.5V 8 20 PERCENTAGE (%) PERCENTAGE (%) 0.5 TCVOS (PV/C) 6 4 2 -40C d TA d 25C 15 10 5 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 VOS (PV) 0 -1.5 -1 -0.5 0 0.5 TCVOS (PV/C) Figure 9. Figure 10. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 7 LMP7731 SNOSAT6E - JULY 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Offset Voltage Distribution TCVOS Distribution 14 25 VS = 5V VS = 3.3V, 5V 12 VCM = 0.5V 20 PERCENTAGE (%) PERCENTAGE (%) 10 8 6 4 VCM = 0.5V -40C d TA d 125C 15 10 5 2 0 -40 -30 -20 -10 0 10 20 30 0 -1.5 40 -1 -0.5 TCVOS (PV/C) Figure 11. Figure 12. Offset Voltage vs. Temperature 0.5 Offset Voltage vs. Temperature 60 20 VS = 2.5V, 3.3V, 5V VS = 2.5V, 3.3V, 5V VCM = 0.5V VCM = VS - 0.5V 40 5 TYPICAL PARTS 15 20 10 VOS (PV) VOS (PV) 0 VOS (PV) 0 -20 5 TYPICAL PARTS 5 0 -40 -40 -20 0 20 40 60 -5 -40 -20 80 100 120 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) Figure 13. Figure 14. PSRR vs. Frequency CMRR vs. Frequency 160 0 VS = 2.5V, 3.3V, 5V 140 -20 -PSRR 120 -60 CMRR (dB) PSRR (dB) -40 VS = 5V -80 V = 2.5V S +PSRR -100 60 20 VS = 5V 100 1k 10k 100k 1M 10M 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. 8 80 40 VS = 3.3V -120 -140 10 100 Figure 16. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 LMP7731 www.ti.com SNOSAT6E - JULY 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Offset Voltage vs. Supply Voltage Offset Voltage vs. VCM 5 100 VS = 2.5V 50 -5 VOS (PV) OFFSET VOLTAGE (PV) 75 25C 0 -40C -10 125C 25 85C 25C 0 -15 -40C -25 85C -20 -50 -25 1.5 125C 2 2.5 3 3.5 4 4.5 5 -75 5.5 0 0.5 1 SUPPLY VOLTAGE (V) Figure 18. Offset Voltage vs. VCM Offset Voltage vs. VCM 2.5 100 VS = 5V VS = 3.3V 75 75 50 50 VOS (PV) 125C VOS (PV) 2 Figure 17. 100 85C 25 25C 0 -40C -25 125C 25 85C 25C 0 -40C -25 -50 -50 -75 -75 0 0.5 1 1.5 2 2.5 3 3.3 0 1 2 3 4 5 VCM (V) VCM (V) Figure 19. Figure 20. Input Offset Voltage Time Drift Slew Rate vs. Supply Voltage 1 3.4 RISING EDGE 3.2 VS = 5V 0.8 RL = 2 k: SLEW RATE (V/Ps) OFFSET VOLTAGE DRIFT (PV) 1.5 VCM (V) 0.6 0.4 3 2.8 FALLING EDGE 2.6 AV = +1 2.4 VIN = 1 VPP 0.2 2.2 0 0 50 100 150 200 250 300 2 1.5 RL = 10 k: CL = 10 pF 2 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) TIME (s) Figure 21. Figure 22. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 9 LMP7731 SNOSAT6E - JULY 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Time Domain Voltage Noise Time Domain Voltage Noise Figure 23. Figure 24. Time Domain Voltage Noise Output Voltage vs. Output Current 1000 VS = 2.5V, 3.3V, 5V VOUT FROM RAIL (mV) 800 VS = 2.5V 600 400 SINK 200 0 -200 -400 SOURCE -600 -800 0 5 10 15 20 25 30 OUTPUT CURRENT (mA) Figure 25. Figure 26. Input Bias Current vs. VCM Input Bias Current vs. VCM 100 100 VS = 2.5V 125C 60 85C 40 25C 20 0 -20 -40 -40C -60 0 -20 1.5 2 2.5 -40C -40 -60 -80 1 25C 20 -100 0.5 85C 40 -80 0 0.5 1 1.5 2 2.5 3 3.5 VCM (V) VCM (V) Figure 27. 10 60 -100 0 VS = 3.3V 125C 80 INPUT BIAS CURRENT (nA) INPUT BIAS CURRENT (nA) 80 Figure 28. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 LMP7731 www.ti.com SNOSAT6E - JULY 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Input Bias Current vs. VCM Open Loop Frequency Response Over Temperature 100 100 INPUT BIAS CURRENT (nA) 225 VS = 5V 125C 80 GAIN 80 180 60 40 60 20 GAIN (dB) 25C 0 -20 -40 PHASE 20 45 VS = 2.5V, TA = 25C -40C 0 0 VS = 2.5V, 3.3V, 5V -20 RL = 10 k: TA = -40C, 25C, 85C, 125C -40 1M 10M 100k 1k 10k -80 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VCM (V) Open Loop Frequency Response Open Loop Frequency Response 100 225 VS = 5V GAIN GAIN 180 80 135 60 RL = 10 k: 180 CL = 20 pF 135 -40C 90 25C 90 40 PHASE 20 V = 2.5V, C = 100 pF, S L 45 RL = 10 k: GAIN (dB) GAIN (dB) RL = 2 k: PHASE () VS = 5V, CL = 20 pF, 40 PHASE 20 45 85C 0 0 VS = 2.5V, 3.3V, 5V -20 -40 RL = 2 k:, 10 k: 1k 10k 100k 1M 10M -90 100M -40 1k 10k 10M Figure 32. THD+N vs. Frequency THD+N vs. Output Voltage -90 100M 1 RL = 100 k: RL = 100 k: CL = 10 pF CL = 10 pF f = 1 kHz VO = VS -1V 0.1 VS = 2.5V THD+N (%) THD+N (%) 1M Figure 31. 1 0.01 100k -45 FREQUENCY (Hz) FREQUENCY (Hz) 0.1 0 125C -20 -45 CL = 20 pF, 50 pF, 100 pF PHASE () 225 60 -90 100M Figure 30. 100 80 -45 FREQUENCY (Hz) Figure 29. 0 135 90 40 -60 -100 VS = 5V, TA = -40C PHASE () 85C VS = 3.3V 0.01 0.001 VS = 2.5V 0.001 VS = 3.3V VS = 5V VS = 5V 0.0001 10 100 1k 10k 100k 0.0001 FREQUENCY (Hz) 0.1 1 10 VOUT (VPP) Figure 33. Figure 34. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 11 LMP7731 SNOSAT6E - JULY 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Small Signal Step Response 20 mV/DIV 500 mV/DIV Large Signal Step Response VS = 5V VIN = 2 VPP f = 10 kHz VS = 5V VIN = 100 mVPP f = 10 kHz AV = +1 AV = +1 RL = 10 k: RL = 10 k: CL = 10 pF CL = 10 pF Figure 35. Figure 36. Large Signal Step Response Small Signal Step Response 200 mV/DIV 10 Ps/DIV 1 V/DIV 10 Ps/DIV VS = 5V VIN = 400 mVPP f = 10 kHz VS = 5V VIN = 100 mVPP f = 10 kHz AV = +10 AV = +10 RL = 10 k: RL = 10 k: CL = 10 pF CL = 10 pF 10 Ps/DIV 10 Ps/DIV Figure 37. Figure 38. Supply Current vs. Supply Voltage Output Swing High vs. Supply Voltage 3.5 40 RL = 2 k: 3 125C VOUT FROM RAIL (mV) SUPPLY CURRENT (mA) 35 85C 2.5 25C -40C 2 30 125C 25 85C 20 -40C 15 25C 10 5 1.5 1.5 12 2 2.5 3 3.5 4 4.5 5 5.5 0 1.5 2 2.5 3 3.5 4 4.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 39. Figure 40. Submit Documentation Feedback 5 5.5 Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 LMP7731 www.ti.com SNOSAT6E - JULY 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Output Swing Low vs. Supply Voltage Sinking Current vs, Supply Voltage 60 40 -40C RL = 2 k: 25C 50 125C 30 25 ISINK (mA) VOUT FROM RAIL (mV) 35 85C 20 15 85C 40 125C 30 -40C 25C 10 20 5 0 1.5 2 2.5 3 3.5 4 4.5 5 10 1.5 5.5 2 2.5 3 3.5 4 4.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 41. Figure 42. 5 5.5 Sourcing Current vs. Supply Voltage 60 -40C ISOURCE (mA) 50 25C 40 125C 30 85C 20 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 43. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 13 LMP7731 SNOSAT6E - JULY 2007 - REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION LMP7731 The LMP7731 is a single, low noise, rail-to-rail input and output, and low voltage amplifier. The low input voltage noise of only 2.9 nV/Hz with a 1/f corner at 3 Hz makes the LMP7731 ideal for sensor applications where DC accuracy is of importance. The LMP7731 has a high gain bandwidth of 22 MHz. This wide bandwidth enables use of the amplifier at higher gain settings while retaining usable bandwidth for the application. This is particularly beneficial when system designers need to use sensors with very limited output voltage range as it allows larger gains in one stage which in turn increases the signal to noise ratio. The LMP7731 has proprietary input bias cancellation circuitry on the input stages. This allows the LMP7731 to have only about 1.5 nA bias current with a bipolar input stage. This low input bias current, paired with the inherent lower input voltage noise of bipolar input stages makes the LMP7731 an excellent choice for precision applications. The combination of low input bias current, and low input voltage noise enables the user to achieve unprecedented accuracy and higher signal integrity. Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical support and extensive characterization data are available for sensitive applications or applications with a constrained error budget. The LMP7731 is offered in the space saving 5-Pin SOT-23 and 8-Pin SOIC packages. These small packages are ideal solutions for area constrained PC boards and portable electronics. INPUT BIAS CURRENT CANCELLATION The LMP7731 has proprietary input bias current cancellation circuitry on their input stages. The LMP7731 has rail-to-rail input. This is achieved by having two input stages in parallel. Figure 44 shows only one of the input stages as the circuitry is symmetrical for both stages. Figure 44 shows that as the common mode voltage gets closer to one of the extreme ends, current I1 significantly increases. This increased current shows as an increase in voltage drop across resistor R1 equal to I1*R1 on IN+ of the amplifier. This voltage contributes to the offset voltage of the amplifier. When common mode voltage is in the mid-range, the transistors are operating in the linear region and I1 is significantly small. The voltage drop due to I1 across R1 can be ignored as it is orders of magnitude smaller than the amplifier's input offset voltage. As the common mode voltage gets closer to one of the rails, the offset voltage generated due to I1 increases and becomes comparable to the amplifiers offset voltage. IBIAS CANCELLATION CIRCUIT V + INPUT STAGE + V R R C1 C2 R1 IN + I1 Q1 Q2 R2 IN - Figure 44. Input Bias Current Cancellation 14 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 LMP7731 www.ti.com SNOSAT6E - JULY 2007 - REVISED MARCH 2013 INPUT VOLTAGE NOISE MEASUREMENT The LMP7731 has very low input voltage noise. The peak-to-peak input voltage noise of the LMP7731 can be measured using the test circuit shown in Figure 45 0.1 PF 100 k: 10: 2 k: LMP7731 + + LMP7731 VOLTAGE GAIN = 50,000 4.7 PF - 4.3 k: 22 PF 2.2 PF 110 k: 100 k: SCOPE x1 RIN = 1M 24.3 k: 0.1 PF Figure 45. 0.1 Hz to 10 Hz Noise Test Circuit The frequency response of this noise test circuit at the 0.1 Hz corner is defined by only one zero. The test time for the 0.1 Hz to 10 Hz noise measurement using this configuration should not exceed 10 seconds, as this time limit acts as an additional zero to reduce or eliminate the noise contributions of noise from frequencies below 0.1 Hz. Figure 46 shows typical peak-to-peak noise for the LMP7731 measured with the circuit in Figure 45 for the LMP7731. Figure 46. 0.1 Hz to 10 Hz Input Voltage Noise Measuring the very low peak-to-peak noise performance of the LMP7731, requires special testing attention. In order to achieve accurate results, the device should be warmed up for at least five minutes. This is so that the input offset voltage of the op amp settles to a value. During this warm up period, the offset can typically change by a few V because the chip temperature increases by about 30C. If the 10 seconds of the measurement is selected to include this warm up time, some of this temperature change might show up as the measured noise. Figure 47 shows the start-up drift of five typical LMP7731 units. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 15 LMP7731 SNOSAT6E - JULY 2007 - REVISED MARCH 2013 www.ti.com OFFSET VOLTAGE DRIFT (PV) 1 VS = 5V 0.8 RL = 2 k: 0.6 0.4 0.2 0 50 0 100 150 200 250 300 TIME (s) Figure 47. Start-Up Input Offset Voltage Drift During the peak-to-peak noise measurement, the LMP7731 must be shielded. This prevents offset variations due to airflow. Offset can vary by a few nV due to this airflow and that can invalidate measurements of input voltage noise with a magnitude which is in the same range. For similar reasons, sudden motions must also be restricted in the vicinity of the test area. The feed-through which results from this motion could increase the observed noise value which in turn would invalidate the measurement. DIODES BETWEEN THE INPUTS The LMP7731 has a set of anti-parallel diodes between the input pins as shown in Figure 48. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the amount of differential input voltage that is allowed on the input pins. A differential signal larger than the voltage needed to turn on the diodes might cause damage to the diodes. The differential voltage between the input pins should be limited to 3 diode drops or the input current needs to be limited to 20 mA. V ESD IN + + V R1 ESD R2 + IN - ESD ESD - - V V Figure 48. Anti-Parallel Diodes between Inputs DRIVING AN ADC Analog to Digital Converters, ADCs, usually have a sampling capacitor on their input. When the ADC's input is directly connected to the output of the amplifier a charging current flows from the amplifier to the ADC. This charging current causes a momentary glitch that can take some time to settle. There are different ways to minimize this effect. One way is to slow down the sampling rate. This method gives the amplifier sufficient time to stabilize its output. Another way to minimize the glitch caused by the switch capacitor is to have an external capacitor connected to the input of the ADC. This capacitor is chosen so that its value is much larger than the internal switching capacitor and it will hence provide the voltage needed to quickly and smoothly charge the 16 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 LMP7731 www.ti.com SNOSAT6E - JULY 2007 - REVISED MARCH 2013 ADC's sampling capacitor. Since this large capacitor will be loading the output of the amplifier as well, an isolation resistor is needed between the output of the amplifier and this capacitor. The isolation resistor, RISO, separates the additional load capacitance from the output of the amplifier and will also form a low-pass filter and can be designed to provide noise reduction as well as anti-aliasing. The drawback to having RISO is that it reduces signal swing since there is some voltage drop across it. Figure 49 (a) shows the ADC directly connected to the amplifier. To minimize the glitch in this setting, a slower sample rate needs to be used. Figure 49 (b) shows RISO and an external capacitor used to minimize the glitch. FEEDBACK NETWORK (a) ADC V+ SENSOR INPUT NETWORK V- (b) FEEDBACK NETWORK V+ ADC RISO SENSOR INPUT NETWORK V- C Figure 49. Driving an ADC Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 17 LMP7731 SNOSAT6E - JULY 2007 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E * 18 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 17 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7731 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LMP7731MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LMP77 31MA LMP7731MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LMP77 31MA LMP7731MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AY3A LMP7731MFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AY3A LMP7731MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AY3A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMP7731MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP7731MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP7731MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP7731MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP7731MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP7731MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP7731MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0 LMP7731MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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