6-56
Features
• Industry Standard Pinout
• Very Low Operating Current. . . . . . . . . . . . . . . . . . 8mA
at VDD = 5V and Cycle Time = 1µs
• Two Chip Select Inputs Simple Memory Expansion
• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
Battery Voltage
• Output Disable for Common I/O Systems
• Three-State Data Output for Bus Oriented Systems
• Separate Data Inputs and Outputs
• TTL Compatible (MWS5101A)
Pinout
MWS5101, MWS5101A
(PDIP, SBDIP)
TOP VIEW
Description
The MWS5101 and MWS5101A are 256 word by 4-bit static
random access memories designed for use in memory
systems where high speed, very low operating current, and
simplicity in use are desirable. They have separate data
inputs and outputs and utilize a single power supply of 4V to
6.5V. The MWS5101 and MWS5101A differ in input voltage
characteristics (MWS5101A is TTL compatible).
Two Chip Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high impedance state
during a write operation independent of the Chip Select input
condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
For applications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
static RAM, CDP1822 may be used.
The MWS5101 and MWS5101A types are supplied in 22
lead hermetic dual-in-line, sidebrazed ceramic packages (D
suffix), in 22 lead dual-in-line plastic packages (E suffix), and
in chip form (H suffix).
Ordering Information
1
11
10
9
8
7
6
5
3
2
4
22
12
13
14
15
16
17
18
19
21
20
A2
A1
A0
A5
A6
A7
DI1
VSS
DO1
DI2
A4
CSI
O.D.
CS2
R/W
DO4
DI4
DO3
DI3
DO2
A3 VDD
PACKAGE TEMP. RANGE
MWS5101
350ns
MWS5101A
350ns PKG. NO.250ns 250ns
PDIP
Burn-In 0oC to +70oC MWS5101EL2 MWS5101ELS MWS5101AEL2 MWS5101AEL3 E22.4
MWS5101AEL3X E22.4
SBDIP
Burn-In 0oC to +70oC - MWS5101DL3X - MWS5101ADL3 D22.4A
D22.4A
March 1997
MWS5101,
MWS5101A
256-Word x 4-Bit
LSI Static RAM
File Number 1106.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
6-57
Functional Block Diagram
OPERATIONAL MODES
MODE
INPUTS
OUTPUT
CHIP SELECT 1
(CS1)CHIP SELECT 2
(CS2)OUTPUT
DISABLE (OD) READ/WRITE
(R/W)
Read 0101Read
Write 0100Data In
Write 0110High Impedance
Standby 1 X X X High Impedance
Standby X 0 X X High Impedance
Output Disable X X 1 X High Impedance
NOTE: Logic 1 = High, Logic 0 = Low, X = Don’t Care.
(8 x 32)
STORAGE
ARRAY
(5)
INPUT
BUFFERS
AND
ALL ROWS
DESELECT
FUNCTION
A0
A1
A2
A3
A4 21
1
2
3
4
(4)
GATES
DI1
DI2
DI3
DI4 15
13
11
9
(3)
INPUT
BUFFERS
AND
ALL COLUMNS
DESELECT
FUNCTION
A5
A6
A7 7
6
5
CSI
CS2
INPUT PROTECTION
18
17
19 CONTROL
ACONTROL
C
CONTROL
B
(32)
ROW
DECODERS
BIT (1)
(8 x 32)
STORAGE
ARRAY
BIT (2)
(8 x 32)
STORAGE
ARRAY
BIT (3)
(8 x 32)
STORAGE
ARRAY
BIT (4)
BUFFER
DRIVERS
(4)
D01
D02
D03
D04
16
14
12
10
BITS
(1-4)
(8)
COLUMN
DECODERS
(8)
COLUMN
DECODERS
(8)
COLUMN
DECODERS
(8)
COLUMN
DECODERS
22 VDD
†
†
†
†
†
†
†
†
†
†
†
†
†
R/W 20
†
†
†
†††
††
††
††
††
8VSS
†††
† †† †††
OUTPUT
NETWORK PROTECTION
CIRCUIT
OVER VOLTAGE
PROTECTION
CIRCUIT
VSS VSS VSS
OD
VDD VDD VDD
MWS5101, MWS5101A
6-58
Absolute Maximum Ratings Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal). . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A
SBDIP Package. . . . . . . . . . . . . . . . . . 80 21
Operating Temperature Range (TA)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC
Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150oC
Maximum Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ±0.79mm)
from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Recommended Operating Conditions At TA = Full P ac kage Temperature Range. F or maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
PARAMETER
LIMITS
UNITSMIN MAX
DC Operating Voltage Range 4 6.5 V
Input Voltage Range VSS VDD V
Static Electrical Specifications At TA = 0oC to +70oC, VDD = 5V ±5%
PARAMETER SYMBOL
CONDITIONS LIMITS
UNITS
VO
(V) VIN
(V)
MWS5101 MWS5101A
MIN (NO TE 1)
TYP MAX MIN (NO TE 1)
TYP MAX
Quiescent Device
Current L2 Types IDD - 0, 5 - 25 50 - 25 50 µA
L3 Types - 0, 10 - 100 200 - 100 200 µA
Output Low (Sink) Current IOL 0.4 0, 5 2 4 - 2 4 - mA
Output High (Source) Current IOH 4.6 0, 5 -1 -2 - -1 -2 - mA
Output Voltage Low-Level VOL - 0, 5 - 0 0.1 - 0 0.1 V
Output Voltage High-Level VOH - 0, 5 4.9 5 - 4.9 5 - V
Input Low Voltage VIL - - - - 1.5 - - 0.65 V
Input High Voltage VIH - - 3.5 - - 2.2 - - V
Input Leakage Current IIN - 0, 5 - - ±5- -±5µA
Operating Current (Note 2) IDD1 - 0, 5 - 4 8 - 4 8 mA
Three-State Output
Leakage Current L2 Types IOUT 0, 5 0, 5 - - ±5- -±5µA
L3 Types 0, 5 0, 5 - - ±5- -±5µA
Input Capacitance CIN - - - 5 7.5 - 5 7.5 pF
Output Capacitance COUT - - - 10 15 - 10 15 pF
NOTES:
1. Typical values are for TA = +25oC and nominal VDD.
2. Outputs open circuited; Cycle time = 1µs.
MWS5101, MWS5101A
6-59
Dynamic Electrical Specifications at TA = 0oC to +70oC, VDD = 5V ±5%
PARAMETER SYMBOL
LIMITS (NOTE 1)
UNITS
L2 TYPES L3 TYPES
(NOTE 2)
MIN (NOTE 3)
TYP MAX (NOTE 2)
MIN (NOTE 3)
TYP MAX
READ CYCLE TIMES (FIGURE 1)
Read Cycle tRC 250 - - 350 - - ns
Access from Address tAA - 150 250 - 200 350 ns
Output Valid from Chip Select 1 tDOA1 - 150 250 - 200 350 ns
Output Valid from Chip Select 2 tDOA2 - 150 250 - 200 350 ns
Output Valid from Output Disable tDOA3 - - 110 - - 150 ns
Output Hold from Chip Select 1 tDOH1 20 - - 20 - - ns
Output Hold from Chip Select 2 tDOH2 20 - - 20 - - ns
Output Hold from Output Disable tDOH3 20 - - 20 - - ns
WRITE CYCLE TIMES (FIGURE 2)
Write Cycle tWC 300 - - 400 - - ns
Address Setup tAS 110 - - 150 - - ns
Write Recovery tWR 40 - - 50 - - ns
Write Width tWRW 150 - - 200 - - ns
Input Data Setup Time tDS 150 - - 200 - - ns
Data in Hold tDH 40 - - 50 - - ns
Chip Select 1 Setup tCS1S 110 - - 150 - - ns
Chip Select 2 Setup tCS2S 110 - - 150 - - ns
Chip Select 1 Hold tCS1H 0--0--ns
Chip Select 2 Hold tCS2H 0--0--ns
Output Disable Setup tODS 110 - - 150 - - ns
NOTES:
1. MWS5101: tR, tF = 20ns , VIH = 0.7VDD, VIL = 0.3VDD; CL = 100pF and MWS5101A: tR, tF = 20ns , VIH = 2.2V, VIL = 0.65V; CL = 50pF
and 1 TTL Load.
2. Time required by a limit device to allow for the indicated function.
3. Typical values are for TA = 25oC and nominal VDD.
MWS5101, MWS5101A
6-60
tDOA1
tDOA2
tDOH1
tRC
tDOH3
tAA
DATA OUT
VALID HIGH
IMPEDANCE
HIGH
IMPEDANCE
CHIP SELECT 1
A0 - A7
CHIP SELECT 2
OUTPUT DISABLE
READ/WRITE
DATA OUT
tDOH2
tDOA3
FIGURE 1. READ CYCLE TIMING WAVEFORMS
A0-A7
tWC
tCS1S tCS1H
tCS2S tCS2H
tODS tDS tDH
tWRW
tAS
DON’T CARE
CHIP SELECT 1
CHIP SELECT 2
OUTPUT DISABLE
DI1-DI4
READ/WRITE
tWR
DATA IN STABLE
NOTE: tODS is required for common I/O operation only; for separate I/O operations, output disable is “don’t care”.
FIGURE 2. WRITE CYCLE TIME WAVEFORMS
(NOTE)
MWS5101, MWS5101A
6-61
Data Retention Specifications at TA = 0oC to +70oC; See Figure 3
PARAMETER SYMBOL
TEST
CONDITIONS LIMITS
UNITS
VDR
(V) VDD
(V)
ALL TYPES
MIN (NOTE 1)
TYP MAX
Minimum Data Retention Voltage VDR ---1.52V
Data Retention Quiescent Current L2 Types IDD 2-- 210µA
L3 Types 2 - - 5 50 µA
Chip Deselect to Data Retention Time tCDR - 5 600 - - ns
Recovery to Normal Operation Time tRC - 5 600 - - ns
VDD to VDR Rise and Fall Time tR, tF251 - -µs
NOTE:
1. Typical Values are for TA = 25oC and nominal VDD.
FIGURE 3. LOW VDD DATA RETENTION TIMING WAVEFORMS FIGURE 4. MEMORY CELL CONFIGURATION
0.95 VDD
VDD
tCDR
CS2
VIH
VIL
tRC
VIH
VIL
0.95 VDD
VDR
DATA RETENTION
MODE
tFtRWRITE
ADDRESS
DECODER
READ
ADDRESS
DECODER
VSS
DATA IN
VDD
DATA OUT
VDD
MWS5101, MWS5101A
6-62
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to ver ify that data sheets are current before placing orders. Information fur nished by Intersil is believed to be accurate
and reliable . However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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FIGURE 5. LOGIC DIAGRAM OF CONTROLS FOR MWS5101, MWS5101A
CHIP-SELECT
CONTROL
A
CHIP-SELECT AND
R/W CONTROL
B
OUTPUT
DISABLE
C
CONTROL
CONTROL B
CONTROL C
CONTROL A
CS1
CS2
R/W
OUTPUT
DISABLE
19
17
20
18
MWS5101, MWS5101A
