DRC-11522-883Z - Data Device Corporation

DRC-11522

TWO-CHANNEL DIGITAL-TO-RESOLVER

CONVERTER

DESCRIPTION

The DRC-11522 is a dual 16-bit digital-

to-resolver (D/R) converter. Each chan-

nel is independent from the other with

the exception of the 16 digital lines.

The DRC-11522 allows the user to pro-

gram the gain of the resolver output.

Packaged in a 36-pin double DIP, the

DRC-11522 is two digital-to-resolver

converters in one hybrid module.

Using an AC reference input, the DRC-

11522 is a digital-to-resolver convert-

er. When using a DC reference input,

the unit can be used as a hybrid digital-

to-sin/cos DC converter. With the refer-

ence input proportional to the radius

vector, the DRC-11522 converts polar

to rectangular coordinates.

The circuit design in the DRC-11522

allows for higher accuracy and

reduces the output scale factor varia-

tion so that the output can drive dis-

plays directly. The output line-to-line

voltage can be scaled by pin program-

ming. Other features include buffered

reference input, and a wide operating

temperature range.

APPLICATIONS

Because of its high reliability, small

size and low power consumption, the

DRC-11522 is ideal for the most strin-

gent and severe industrial and military

ground or avionics applications. All

units are available with MIL-PRF-

38534 processing.

Among the many possible applications

are computer-based systems in which

digital information is processed, such

as simulators, flight trainers, flight

instrumentation, fire control systems,

radar and navigation systems.

FEATURES

•

16-Bit Resolution

•

Pin Programmable Gain Control

•

Two Channels in One 36-Pin DDIP

•

Accuracy: to ±2 Min.

•

0.1% Scale Factor Variation with

Angle

•

DC-Coupled Reference

•

High Reliability CMOS D/R Chip

•

8-Bit/2-Byte Double-Buffered

Transparent Latches

OUTPUT

AMPLIFIERS

D/R CONVERTER

HIGH ACCURACY

LOW SCALE FACTOR

VARIATION

TRANSPARENT

LATCH

TRANSPARENT

LATCH

TRANSPARENT

LATCH

TRANSPARENT

LATCH

D/R CONVERTER

HIGH ACCURACY

LOW SCALE FACTOR

VARIATION

OUTPUT

AMPLIFIERS

REFERENCE CONDITIONER

REF

COS A

SIN A

GC1-A

GC2-A

LA-A LM-A

+C +S +C +S

COS B

SIN B

REFERENCE CONDITIONER

REF

GC1-B

GC2-B

LM-B LA-B

LL-A LL-B

DIGITAL INPUT

+15 V

-15 V

GND

FIGURE 1. DRC-11522 BLOCK DIAGRAM

TABLE 1. SPECIFICATIONS (for each channel)

Apply over temperature range, power supply ranges, reference voltage, and frequency range, and 10% harmonic distortion in the reference.

PARAMETER VALUE DESCRIPTION/REMARKS

RESOLUTION 16 bits (0.33 arc minutes) MSB = 180° LSB = 0.0055°

ACCURACY

Output Accuracy

Differential Linearity

Radius accuracy

±8 minutes to ±1 minute

(see ordering info)

±1 LSB max

±0.03%

Accuracy applies over operating temp. range

Simultaneous amplitude variation in both

outputs as a function of digital angle

DYNAMICS

Output Settling Time Less than 20 µsec for any digital step change. For any analog or digital step change

DIGITAL INPUT

Logic Type

Logic “0”

Logic “1”

Load Current

-0.3 V-dc to 1.25 V-dc

+2.0 V-dc to +5.5 V-dc

20 µA max to GND

20 µA to VL

Natural binary angle parallel positive logic CMOS

and TTL compatible.

Inputs are CMOS transient protected. Each input

has a 20 µA max pull down to GND.

External logic voltage not needed. TTL compatible.

Bits 1-16

LL, LM, LA (See timing Diagram, FIGURE 2)

REFERENCE INPUT

Type

Frequency Range

Voltage

Input Impedance

DC to 1000 Hz

3.5 V ±10%

10 M Ohm min

Programmable (See TABLE 2.)

DC to 10 kHz with reduced accuracy.

0 to ±10 peak AC or DC

Operational Amplifier Buffer

ANALOG OUTPUT

Type

Output Current

Max Output Voltage (Tracks

Reference Input Voltage)

Converter Gain (K)

Transformation Ratio Tol.

Scale Factor Variation

DC Offset

2 mA rms max

K * Vin * Sin θalso K * Vin * Cos θ

0.5, 1.0, or 2.0 ±1%

±0.2% max

±0.1% max

±10 mV typical, ±25 mV max

POWER SUPPLIES

Voltage

Max Voltage Without Damage

Current or Impedance

±15 VDC ±10%

±18 VDC

±40 mA max

For ±10 V peak output

TEMPERATURE RANGES (CASE)

Operating

-1 Option

-3 Option

Storage

-55°C to +125°C

0°C to +70°C

-60°C to +135°C

PHYSICAL CHARACTERISTICS

Type

Size

Weight

36-pin double DIP

0.78 x 1.9 x 0.21 inch

(2.0 x 4.8 x 0.53 cm)

0.6 oz (17g) max

Resolver

±10 V peak AC or DC

See TABLE 2.

Each Line to GND

TECHNICAL INFORMATION

DIGITAL INPUTS

For each channel, the 16-bit digital angle is double buffered with

transparent latches (See FIGURE 1). The latch controls have

internal pull-up current sources to +5 V, this puts the latches in

the transparent mode when they are not connected.

Angle is determined by adding the logic bits. The enable inputs

are LL (1st Latch LSBs), LM (1st Latch MSBs), and LA (2nd

Latch All); see FIGURE 2 for timing.

OUTPUT SCALING AND REFERENCE LEVEL

ADJUSTMENT

The DRC-11522 operates like a multiplying D/A converter in that

the voltage of each output line is directly proportional to the ref-

erence voltage. The maximum line-to-line levels are determined

by the output amplifiers and are programmable for a gain of 0.5,

1.0, or 2.0 (See TABLE 2.).

OUTPUT PHASING AND OUTPUT SCALE FACTOR

The analog output signals have the following phasing:

sin = (REF * K) Ao [1 + A(θ)] sin θ

cos = (REF * K) Ao [1 + A(θ)] cos θ

The output amplifiers simultaneously track reference voltage

fluctuations because they are proportional to (REF * K). The

transformation ratio Aois determined by the programmable gain

inputs (0.5, 1.0, or 2.0). The maximum variation in Aofrom all

causes is 0.1%. The term A(θ) represents the variation of the

amplitude with the digital signal input angle. A(θ), which is called

the scale factor variation, is a smooth function of (θ) without dis-

continuities and is less than ±0.1% for all values of (θ) The total

maximum variation in Ao[1 + A(θ)] is therefore ±0.2%.

Because the amplitude factor (REF * K) Ao [1 + A(θ)] varies

simultaneously on all output lines, it is not a source of error when

the DRC-11522 is driving a ratiometric system. However, if the

outputs are used independently, as in x-y plotters, the amplitude

variations must be taken into account.

TABLE 2. PROGRAMMABLE GAIN

GC1-A

(PIN 7)

GC2-A

(PIN 8)

GAIN

(K)

GND

OPEN

GND

OPEN

0.5

1.0

2.0

GC1-B

(PIN 4)

GC2-B

(PIN 5)

GAIN

(K)

TABLE 3. PINOUTS

PIN FUNCTION PIN FUNCTION

LL-B

COS A

SIN A

GC1-B

GC2-B

Ref B

GC1-A

GC2-A

Ref A

COS B

SIN B

+15 V

-15 V

LA-B

LA-A

LL-A

GND

Bit 16 (LSB)

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 (MSB)

LM-A

LM-B

NOTE: Functions LL, LM, LA both A and B may be left unconnected

when not used.

TABLE 4. PIN DEFINITIONS

PIN DEFINITION

GND

B1-B16

LM-A

LM-B

LL-A

LL-B

LA-A

LA-B

+15 V

-15 V

Ref-A

Ref-B

GC1-A

GC2-A

GC1-B

GC2-B

Sin A

Cos A

Sin B

Cos B

Power Supply Ground

Digital Ground

Analog Signal Ground

Digital Input bits B1, = MSB = 180 degrees

High Byte Enable (B1-B8) for MSB’s 8-bit Input register of

channel A. Logic high enables, low holds.

High Byte Enable (B1-B8) for MSB’s 8-bit Input register

channel B Logic high enables, low holds.

Low Byte Enable (B9-B16) for LSB’s 8-bit Input register of

channel A. Logic high enables, low holds

Low Byte Enable (B9-B16) for LSB’s 8-bit Input register of

channel B. Logic high enables, low holds.

Channel A Load Converter. Logic high transfers Channel A

input registers data into 16-bit holding register. When

low, Channel A is in hold mode.

Channel B Load Converter. Logic high transfers Channel B

input registers data into 16-bit holding register. When

low, Channel B is in hold mode.

Power Supply Voltage.

CAUTION:

REVERSAL OF POWER SUPPLIES

WILL DAMAGE THE CONVERTER.

Channel A reference voltage Input

Channel B reference voltage input

Channel A gain programming pin

Channel B gain programming pin

Analog output of Channel A

Analog output of Channel B

1.895 ±0.005

(48.1 ±0.13)

1.700 ±0.005

(43.2 ±0.13)

0.018 (0.46)

DIAM TYP

0.100 TYP(2.54)

TOL. NON-

CUMULATIVE

0.21 MAX

(5.3)

DOT

IDENTIFIES

PIN 1

0.775 ±0.005

(19.7 ±0.13) 0.600 ±0.005

(15.2 ±0.13)

0.09 ±0.01

(2.3 ±0.25)

0.10 ±0.01

(2.5 ±0.3)

SIDE VIEW

BOTTOM VIEW

0.25 MIN

(6.4)

0.015 MAX

(0.39)

SEATING

PLANE

0.055 (1.4)

RAD TYP

0.086 TYP

RADIUS

FIGURE 3. DRC-11522 MECHANICAL OUTLINE (36-PIN DOUBLE DIP)

Notes:

1. Dimensions shown are in inches (millimeters)

2. Lead identification numbers are for reference only.

3. Lead cluster shall be centered within ±0.010 (±2.54) of outline dimensions.

Lead spacing dimensions apply only at seating plane.

4. Pin material meets solderability requirements of MIL-STD-202E, Method 208C.

5. Package is Kovar with electroless nickel plating.

6. Case is electrically floating.

;;;;;

200 ns min.

LATCHED

DATA 1-16 BITS

100 ns min.

50 ns min.

;;;;

TRANSPARENT

FIGURE 2. LL, LM, AND LA TIMING DIAGRAM

ORDERING INFORMATION

DRC-11522-XXXX

Supplemental Process Requirements:

S = Pre-Cap Source Inspection

L = Pull Test

Q = Pull Test and Pre-Cap Inspection

K = One Lot Date Code

W = One Lot Date Code and PreCap Source

Y = One Lot Date Code and 100% Pull Test

Z = One Lot Date Code, PreCap Source and 100% Pull Test

Blank = None of the Above

Accuracy:

3 = ±4 minutes

4 = ±2 minutes

Process Requirements:

0 = Standard DDC Processing, no Burn-In (See table below.)

1 = MIL-PRF-38534 Compliant

2 = B*

3 = MIL-PRF-38534 Compliant with PIND Testing

4 = MIL-PRF-38534 Compliant with Solder Dip

5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip

6 = B* with PIND Testing

7 = B* with Solder Dip

8 = B* with PIND Testing and Solder Dip

9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.)

Temperature Grade/Data Requirements:

1 = -55°C to +125°C

2 = -40°C to +85°C

3 = 0°C to +70°C

4 = -55°C to +125°C with Variables Test Data

5 = -40°C to +85°C with Variables Test Data

8 = 0°C to +70°C with Variables Test Data

*Standard DDC Processing with burn-in and full temperature test —see table below.

—1015, Table 1BURN-IN

A2001CONSTANT ACCELERATION

C1010TEMPERATURE CYCLE

A and C1014SEAL

—2009, 2010, 2017, and 2032INSPECTION

CONDITION(S)METHOD(S)

TEST

MIL-STD-883

STANDARD DDC PROCESSING

The information in this data sheet is believed to be accurate; however, no responsibility is

assumed by Data Device Corporation for its use, and no license or rights are

granted by implication or otherwise in connection therewith.

Specifications are subject to change without notice.

PRINTED IN THE U.S.A.H-02/00-500

DATA DEVICE CORPORATION

REGISTERED TO ISO 9001

FILE NO. A5976

105 Wilbur Place, Bohemia, New York 11716-2482

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