74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state Rev. 4 -- 22 September 2020 Product data sheet 1. General description The 74LVC8T245; 74LVCH8T245 are 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a valid logic level. 2. Features and benefits * * * * * * * * * * * * Wide supply voltage range: * VCC(A): 1.2 V to 5.5 V * VCC(B): 1.2 V to 5.5 V High noise immunity Complies with JEDEC standards: * JESD8-7 (1.2 V to 1.95 V) * JESD8-5 (1.8 V to 2.7 V) * JESD8C (2.7 V to 3.6 V) * JESD36 (4.5 V to 5.5 V) ESD protection: * HBM JESD22-A114F Class 3A exceeds 4000 V * MM JESD22-A115-B exceeds 200 V * CDM JESD22-C101E exceeds 1000 V Maximum data rates: * 420 Mbps (3.3 V to 5.0 V translation) * 210 Mbps (translate to 3.3 V) * 140 Mbps (translate to 2.5 V) * 75 Mbps (translate to 1.8 V) * 60 Mbps (translate to 1.5 V) Suspend mode Latch-up performance exceeds 100 mA per JESD 78B Class II 24 mA output drive (VCC = 3.0 V) Inputs accept voltages up to 5.5 V Low power consumption: 30 A maximum ICC IOFF circuitry provides partial Power-down mode operation Specified from -40 C to +85 C and -40 C to +125 C 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74LVC8T245PW Temperature range Name Description Version -40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 -40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm 74LVCH8T245PW 74LVC8T245BQ 74LVCH8T245BQ SOT815-1 4. Functional diagram B1 B2 21 VCC(A) OE DIR Fig. 1. B3 20 B4 19 B5 18 B6 17 B7 16 B8 15 14 VCC(B) 22 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 10 A8 001aai472 Logic symbol DIR OE A1 B1 VCC(A) VCC(B) to other seven channels Fig. 2. 001aai473 Logic diagram (one channel) 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 2 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 5. Pinning information 5.1. Pinning 1 terminal 1 index area 24 VCC(B) VCC(A) 74LVC8T245 74LVCH8T245 74LVC8T245 74LVCH8T245 VCC(A) 1 DIR 2 24 VCC(B) 23 VCC(B) A1 3 22 OE A2 4 21 B1 A3 5 20 B2 A4 6 19 B3 A5 7 18 B4 A6 8 17 B5 A7 9 16 B6 A8 10 15 B7 GND 11 14 B8 GND 12 13 GND 2 23 VCC(B) A1 3 22 OE A2 4 21 B1 A3 5 20 B2 A4 6 19 B3 A5 7 18 B4 A6 8 17 B5 A7 9 16 B6 A8 10 15 B7 GND(1) GND 13 14 B8 GND 12 GND 11 001aak437 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. 001aak436 Fig. 3. DIR Pin configuration SOT355-1 (TSSOP24) Fig. 4. Pin configuration SOT815-1 (DHVQFN24) 5.2. Pin description Table 2. Pin description Symbol Pin Description VCC(A) 1 supply voltage A (An inputs/outputs, OE and DIR inputs are referenced to VCC(A)) DIR 2 direction control A1, A2, A3, A4, A5, A6, A7, A8 3, 4, 5, 6, 7, 8, 9, 10 data input or output GND [1] 11, 12, 13 ground (0 V) B1, B2, B3, B4, B5, B6, B7, B8 21, 20, 19, 18, 17, 16, 15, 14 data input or output OE 22 output enable input (active LOW) VCC(B) 23, 24 supply voltage B (Bn inputs/outputs are referenced to VCC(B)) [1] All GND pins must be connected to ground (0 V). 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 3 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. Supply voltage Input VCC(A), VCC(B) OE [2] DIR [2] An [2] Bn [2] 1.2 V to 5.5 V L L An = Bn input 1.2 V to 5.5 V L H input Bn = An 1.2 V to 5.5 V H X Z Z GND [1] X X Z Z [1] [2] Input/output [1] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. The An inputs/outputs, DIR and OE input circuit is referenced to VCC(A); The Bn inputs/outputs circuit is referenced to VCC(B). 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC(A) supply voltage A Conditions -0.5 +6.5 V VCC(B) supply voltage B -0.5 +6.5 V IIK input clamping current -50 - VI input voltage [1] -0.5 +6.5 IOK output clamping current VO < 0 V VO output voltage Active mode [1] [2] [3] -0.5 Suspend or 3-state mode [1] -0.5 +6.5 V [2] - 50 mA - 100 mA -100 - mA -65 +150 C - 500 mW VI < 0 V IO output current VO = 0 V to VCCO ICC supply current ICC(A) or ICC(B); per VCC pin IGND ground current per GND pin Tstg storage temperature Ptot total power dissipation [1] [2] [3] [4] Tamb = -40 C to +125 C -50 [4] - mA V mA VCCO + 0.5 V The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 6.5 V. For SOT355-1 (TSSOP24) package: Ptot derates linearly with 12.4 mW/K above 110 C. For SOT815-1 (DHVQFN24) package: Ptot derates linearly with 15.0 mW/K above 117 C. 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 4 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC(A) supply voltage A 1.2 5.5 V VCC(B) supply voltage B 1.2 5.5 V VI input voltage 0 5.5 V VO output voltage 0 VCCO V 0 5.5 V -40 +125 C - 20 ns/V VCCI = 1.4 V to 1.95 V - 20 ns/V VCCI = 2.3 V to 2.7 V - 20 ns/V VCCI = 3 V to 3.6 V - 10 ns/V VCCI = 4.5 V to 5.5 V - 5 ns/V Unit Active mode [1] Suspend or 3-state mode Tamb ambient temperature t/V input transition rise and fall rate [1] [2] VCCI = 1.2 V [2] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the input port. 9. Static characteristics Table 6. Typical static characteristics at Tamb = 25 C At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH Conditions HIGH-level output VI = VIH or VIL voltage IO = -3 mA; VCCO = 1.2 V Min Typ Max - 1.09 - V [1] VOL LOW-level output voltage VI = VIH or VIL IO = 3 mA; VCCO = 1.2 V [1] - 0.07 - V II input leakage current DIR, OE input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V [2] - - 1 A IBHL bus hold LOW current A or B port; VI = 0.42 V; VCCI = 1.2 V [2] - 19 - A IBHH bus hold HIGH current A or B port; VI = 0.78 V; VCCI = 1.2 V [2] - -19 - A IBHLO bus hold LOW overdrive current A or B port; VCCI = 1.2 V [2] [3] - 19 - A IBHHO bus hold HIGH overdrive current A or B port; VCCI = 1.2 V [2] [3] - -19 - A IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V [1] - - 1 A suspend mode A port; VO = 0 V or VCCO; VCC(A) = 5.5 V; VCC(B) = 0 V [1] - - 1 A suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 5.5 V [1] - - 1 A 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 5 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state Symbol Parameter IOFF Conditions Min Typ Max Unit power-off leakage A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V current - - 1 A B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V - - 1 A CI input capacitance DIR, OE input; VI = 0 V or 3.3 V; VCC(A) = 3.3 V - 3 - pF CI/O input/output capacitance A and B port; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V - 6.5 - pF [1] [2] [3] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the data input port. To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH. Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions -40 C to +85 C Min Max VCCI = 1.2 V 0.8VCCI VCCI = 1.4 V to 1.95 V 0.65VCCI VCCI = 2.3 V to 2.7 V -40 C to +125 C Unit Min Max - 0.8VCCI - V - 0.65VCCI - V 1.7 - 1.7 - V VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V VCCI = 4.5 V to 5.5 V 0.7VCCI - 0.7VCCI - V VCCI = 1.2 V 0.8VCC(A) - 0.8VCC(A) - V VCCI = 1.4 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V 0.7VCC(A) - 0.7VCC(A) - V VCCI = 1.2 V - 0.2VCCI - 0.2VCCI V VCCI = 1.4 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - VCCI = 3.0 V to 3.6 V - 0.8 VCCI = 4.5 V to 5.5 V - 0.3VCCI VCCI = 1.2 V - 0.2VCC(A) - 0.2VCC(A) V VCCI = 1.4 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V VCCI = 4.5 V to 5.5 V - 0.3VCC(A) - data input [1] DIR, OE input VCCI = 4.5 V to 5.5 V VIL LOW-level input voltage data input [1] 0.7 V - 0.8 V - 0.3VCCI V DIR, OE input 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 0.3VCC(A) V (c) Nexperia B.V. 2020. All rights reserved 6 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state Symbol Parameter Conditions -40 C to +85 C Min VOH VOL HIGH-level output voltage LOW-level output voltage -40 C to +125 C Unit Max Min Max - VCCO - 0.1 - V VI = VIH IO = -100 A; VCCO = 1.2 V to 4.5 V [2] VCCO - 0.1 IO = -6 mA; VCCO = 1.4 V 1.0 - 1.0 - V IO = -8 mA; VCCO = 1.65 V 1.2 - 1.2 - V IO = -12 mA; VCCO = 2.3 V 1.9 - 1.9 - V IO = -24 mA; VCCO = 3.0 V 2.4 - 2.4 - V IO = -32 mA; VCCO = 4.5 V 3.8 - 3.8 - V IO = 100 A; VCCO = 1.2 V to 4.5 V - 0.1 - 0.1 V IO = 6 mA; VCCO = 1.4 V - 0.3 - 0.3 V IO = 8 mA; VCCO = 1.65 V - 0.45 - 0.45 V IO = 12 mA; VCCO = 2.3 V - 0.3 - 0.3 V IO = 24 mA; VCCO = 3.0 V - 0.55 - 0.55 V VI = VIL [2] IO = 32 mA; VCCO = 4.5 V - 0.55 - 0.55 V II input leakage current DIR, OE input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V - 2 - 10 A IBHL bus hold LOW current A or B port VI = 0.49 V; VCCI = 1.4 V 15 - 10 - A VI = 0.58 V; VCCI = 1.65 V 25 - 20 - A VI = 0.70 V; VCCI = 2.3 V 45 - 45 - A VI = 0.80 V; VCCI = 3.0 V 100 - 80 - A VI = 1.35 V; VCCI = 4.5 V 100 - 100 - A IBHH IBHLO [1] bus hold HIGH A or B port current VI = 0.91 V; VCCI = 1.4 V bus hold LOW overdrive current [1] -15 - -10 - A VI = 1.07 V; VCCI = 1.65 V -25 - -20 - A VI = 1.70 V; VCCI = 2.3 V -45 - -45 - A VI = 2.00 V; VCCI = 3.0 V -100 - -80 - A VI = 3.15 V; VCCI = 4.5 V -100 - -100 - A VCCI = 1.6 V 125 - 125 - A VCCI = 1.95 V 200 - 200 - A VCCI = 2.7 V 300 - 300 - A VCCI = 3.6 V 500 - 500 - A 900 - 900 - A -125 - -125 - A -200 - -200 - A VCCI = 2.7 V -300 - -300 - A VCCI = 3.6 V -500 - -500 - A VCCI = 5.5 V -900 - -900 - A A or B port [1] [3] VCCI = 5.5 V IBHHO bus hold HIGH A or B port overdrive VCCI = 1.6 V current VCCI = 1.95 V 74LVC_LVCH8T245 Product data sheet [1] [3] All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 7 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state Symbol Parameter IOZ ICC -40 C to +85 C -40 C to +125 C Min Max Min Max Unit A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V [2] - 2 - 10 A suspend mode A port; VO = 0 V or VCCO; VCC(A) = 5.5 V; VCC(B) = 0 V [2] - 2 - 10 A suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 5.5 V [2] - 2 - 10 A A port; VI or VO = 0 V to 5.5 V; power-off leakage current VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V - 2 - 10 A B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V - 2 - 10 A VCC(A), VCC(B) = 1.2 V to 5.5 V - 15 - 20 A VCC(A) = 5.5 V; VCC(B) = 0 V - 15 - 20 A VCC(A) = 0 V; VCC(B) = 5.5 V -2 - -4 - A VCC(A), VCC(B) = 1.2 V to 5.5 V - 15 - 20 A VCC(B) = 0 V; VCC(A) = 5.5 V -2 - -4 - A VCC(B) = 5.5 V; VCC(A) = 0 V - 15 - 20 A - 25 - 30 A - 50 - 75 A OFF-state output current IOFF Conditions supply current A port; VI = 0 V or VCCI; IO = 0 A [1] B port; VI = 0 V or VCCI; IO = 0 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI VCC(A), VCC(B) = 1.2 V to 5.5 V ICC additional supply current per input; VCC(A), VCC(B) = 3.0 V to 5.5 V DIR and OE input; DIR or OE input at VCC(A) - 0.6 V; A port at VCC(A) or GND; B port = open [1] [2] [3] [4] A port; A port at VCC(A) - 0.6 V; DIR at VCC(A); B port = open [4] - 50 - 75 A B port; B port at VCC(B) - 0.6 V; DIR at GND; A port = open [4] - 50 - 75 A VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH. For non bus hold parts only (74LVC8T245). 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 8 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 10. Dynamic characteristics Table 8. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for wave forms see Fig. 5 and Fig. 6. [1] Symbol Parameter tpd propagation delay tdis disable time ten [1] enable time Conditions VCC(B) Unit 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V An to Bn 11.0 8.5 7.4 6.2 5.7 5.4 ns Bn to An 11.0 10.0 9.5 9.1 8.9 8.9 ns OE to An 9.5 9.5 9.5 9.5 9.5 9.5 ns OE to Bn 10.2 8.2 7.8 6.7 7.3 6.4 ns OE to An 13.5 13.5 13.5 13.5 13.5 13.5 ns OE to Bn 13.6 10.3 8.9 7.5 7.1 7.0 ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 9. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for wave forms see Fig. 5 and Fig. 6. [1] Symbol Parameter Conditions 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V tpd An to Bn 11.0 10.0 9.5 9.1 8.9 8.8 ns Bn to An 11.0 8.5 7.3 6.2 5.7 5.4 ns OE to An 9.5 6.8 5.4 3.8 4.1 3.1 ns OE to Bn 10.2 9.1 8.6 8.1 7.8 7.8 ns OE to An 13.5 9.0 6.9 4.8 3.8 3.2 ns OE to Bn 13.6 12.5 12.0 11.5 11.4 11.4 ns tdis ten [1] propagation delay disable time enable time VCC(A) Unit tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C Voltages are referenced to GND (ground = 0 V). [1] [2] Symbol Parameter CPD [1] [2] power dissipation capacitance Conditions VCC(A) and VCC(B) Unit 1.8 V 2.5 V 3.3 V 5.0 V A port: (direction A to B); B port: (direction B to A) 1 1 1 2 pF A port: (direction B to A); B port: (direction A to B) 13 13 13 13 pF CPD is used to determine the dynamic power dissipation (PD in W). 2 2 PD = CPD x VCC x fi x N + (CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 (CL x VCC x fo) = sum of the outputs. fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = . 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 9 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state Table 11. Dynamic characteristics for temperature range -40 C to +85 C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6. [1] Symbol Parameter Conditions VCC(B) Unit 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.5 V 0.1 V propagation delay An to Bn 1.7 27 1.7 23 1.3 18 1.0 15 0.8 13 ns Bn to An 0.9 27 0.9 25 0.8 23 0.7 23 0.7 22 ns disable time OE to An 1.5 30 1.5 30 1.5 30 1.5 30 1.4 30 ns OE to Bn 2.4 34 2.4 33 1.9 15 1.7 14 1.3 12 ns OE to An 0.4 34 0.4 34 0.4 34 0.4 34 0.4 34 ns OE to Bn 1.8 36 1.8 34 1.5 18 1.2 15 0.9 13 ns propagation delay An to Bn 1.7 25 1.7 21.9 1.3 9.2 1.0 7.4 0.8 7.1 ns Bn to An 0.9 23 0.9 23.8 0.8 23.6 0.7 23.4 0.7 23.4 ns disable time OE to An 1.5 30 1.5 29.6 1.5 29.4 1.5 29.3 1.4 29.2 ns OE to Bn 2.4 33 2.4 32.2 1.9 13.1 1.7 12.0 1.3 10.3 ns OE to An 0.4 24 0.4 24.0 0.4 23.8 0.4 23.7 0.4 23.7 ns OE to Bn 1.8 34 1.8 32.0 1.5 16.0 1.2 12.6 0.9 10.8 ns propagation delay An to Bn 1.5 23 1.5 21.4 1.2 9.0 0.8 6.2 0.6 4.8 ns Bn to An 1.2 18 1.2 9.3 1.0 9.1 1.0 8.9 0.9 8.8 ns tdis disable time OE to An 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 ns OE to Bn 2.3 31 2.3 29.6 1.8 11.0 1.7 9.3 0.9 6.9 ns ten enable time OE to An 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 ns OE to Bn 1.7 32 1.7 28.2 1.5 12.9 1.2 9.4 1.0 6.9 ns 23 1.5 21.2 1.1 8.8 0.8 6.3 0.5 4.4 ns tpd tdis ten enable time VCC(A) = 1.8 V 0.15 V tpd tdis ten enable time VCC(A) = 2.5 V 0.2 V tpd VCC(A) = 3.3 V 0.3 V tpd propagation delay An to Bn 1.5 Bn to An 0.8 15 0.8 7.2 0.8 6.2 0.7 6.1 0.6 6.0 ns tdis disable time OE to An 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 ns OE to Bn 2.1 30 2.1 29.0 1.7 10.3 1.5 8.6 0.8 6.3 ns OE to An 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 ns OE to Bn 1.8 31 1.8 27.7 1.4 12.4 1.1 8.5 0.9 6.4 ns propagation delay An to Bn 1.5 22 1.5 21.4 1.0 8.8 0.7 6.0 0.4 4.2 ns Bn to An 0.7 13 0.7 7.0 0.4 4.8 0.3 4.5 0.3 4.3 ns disable time OE to An 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 ns OE to Bn 2.0 30 2.0 28.7 1.6 9.7 1.4 8.0 0.7 5.7 ns OE to An 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 ns OE to Bn 1.5 31 1.5 27.6 1.3 11.4 1.0 8.1 0.9 6.0 ns ten enable time VCC(A) = 5.0 V 0.5 V tpd tdis ten [1] enable time tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 10 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range -40 C to +125 C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6. [1] Symbol Parameter Conditions VCC(B) Unit 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.5 V 0.1 V propagation delay An to Bn 1.7 32 1.7 27 1.3 21 1.0 18 0.8 16 ns Bn to An 0.9 32 0.9 30 0.8 28 0.7 28 0.7 26 ns disable time OE to An 1.5 34 1.5 34 1.5 34 1.5 34 1.4 34 ns OE to Bn 2.4 41 2.4 40 1.9 18 1.7 17 1.3 15 ns OE to An 0.4 40 0.4 40 0.4 40 0.4 40 0.4 40 ns OE to Bn 1.8 43 1.8 41 1.5 22 1.2 18 0.9 16 ns propagation delay An to Bn 1.7 30 1.7 25.9 1.3 13.2 1.0 11.4 0.8 11.1 ns Bn to An 0.9 27 0.9 28.8 0.8 27.6 0.7 27.4 0.7 27.4 ns disable time OE to An 1.5 34 1.5 33.6 1.5 33.4 1.5 33.3 1.4 33.2 ns OE to Bn 2.4 40 2.4 36.2 1.9 17.1 1.7 16.0 1.3 14.3 ns OE to An 0.4 28 0.4 28 0.4 27.8 0.4 27.7 0.4 27.7 ns OE to Bn 1.8 41 1.8 40 1.5 20 1.2 16.6 0.9 14.8 ns propagation delay An to Bn 1.5 28 1.5 25.4 1.2 13 0.8 10.2 0.6 8.8 ns Bn to An 1.2 23 1.2 13.3 1.0 13.1 1.0 12.9 0.9 12.8 ns tdis disable time OE to An 1.4 13 1.4 13 1.4 13 1.4 13 1.4 13 ns OE to Bn 2.3 37 2.3 33.6 1.8 15 1.7 14.3 0.9 10.9 ns ten enable time OE to An 1.0 17.2 1.0 17.2 1.0 17.3 1.0 17.2 1.0 17.3 ns OE to Bn 1.7 38 1.7 32.2 1.5 18.1 1.2 14.1 1.0 11.2 ns 28 1.5 25.2 1.1 12.8 0.8 10.3 0.5 10.4 ns tpd tdis ten enable time VCC(A) = 1.8 V 0.15 V tpd tdis ten enable time VCC(A) = 2.5 V 0.2 V tpd VCC(A) = 3.3 V 0.3 V tpd propagation delay An to Bn 1.5 Bn to An 0.8 18 0.8 11.2 0.8 10.2 0.7 10.1 0.6 10 ns tdis disable time OE to An 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 ns OE to Bn 2.1 36 2.1 33 1.7 14.3 1.5 12.6 0.8 10.3 ns OE to An 0.8 14.1 0.8 14.1 0.8 13.6 0.8 13.2 0.8 13.6 ns OE to Bn 1.8 37 1.8 31.7 1.4 18.4 1.1 12.9 0.9 10.9 ns propagation delay An to Bn 1.5 26 1.5 25.4 1.0 12.8 0.7 10 0.4 8.2 ns Bn to An 0.7 16 0.7 11 0.4 8.8 0.3 8.5 0.3 8.3 ns disable time OE to An 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 ns OE to Bn 2.0 36 2.0 32.7 1.6 13.7 1.4 12 0.7 9.7 ns OE to An 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 ns OE to Bn 1.5 37 1.5 31.6 1.3 18.4 1.0 13.7 0.9 10.7 ns ten enable time VCC(A) = 5.0 V 0.5 V tpd tdis ten [1] enable time tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 11 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 10.1. Waveforms and test circuit VI VM An, Bn input GND tPHL tPLH VOH VM Bn, An output VOL 001aai475 Measurement points are given in Table 13. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. The data input (An, Bn) to output (Bn, An) propagation delay times VI OE input VM GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCCO VM VX VOL tPZH tPHZ output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs enabled outputs disabled 001aai474 Measurement points are given in Table 13. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. Enable and disable times Table 13. Measurement points Supply voltage Input [1] Output [2] VCC(A), VCC(B) VM VM VX VY 1.2 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH - 0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH - 0.15 V 3.0 V to 5.5 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH - 0.3 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 12 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 14. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 14. Test data Supply voltage Input VCC(A), VCC(B) VI [1] t/V [2] CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ [3] 1.2 V to 5.5 V VCCI 1.0 ns/V 15 pF 2 k open GND 2VCCO [1] [2] [3] Load VEXT VCCI is the supply voltage associated with the data input port. dV/dt 1.0 V/ns. VCCO is the supply voltage associated with the output port. 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 13 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 11. Typical propagation delay characteristics 001aal268 14 tPHL (ns) 12 (1) 10 6 2 2 5 10 15 20 25 30 CL (pF) 35 a. HIGH to LOW propagation delay (A to B) 001aal270 14 tPHL (ns) 12 (1) (2) (3) (4) (5) (6) 10 0 (4) (5) (6) 0 8 6 6 4 4 2 2 10 15 20 25 30 CL (pF) 35 c. HIGH to LOW propagation delay (B to A) 10 15 20 25 30 CL (pF) 35 001aal271 14 tPLH (ns) 12 (1) (2) (3) (4) (5) (6) 10 5 5 b. LOW to HIGH propagation delay (A to B) 8 0 (3) 6 4 0 (2) 8 4 0 (1) 10 (2) (3) (4) (5) (6) 8 0 001aal269 14 tPLH (ns) 12 0 0 5 10 15 20 25 30 CL (pF) 35 d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 8. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.2 V 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 14 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 001aal272 14 tPHL (ns) 12 001aal273 14 tPLH (ns) 12 (1) (1) 10 10 (2) (2) 8 8 (3) (4) (5) (6) 6 6 4 4 2 2 0 0 5 10 15 20 25 30 CL (pF) 35 a. HIGH to LOW propagation delay (A to B) 001aal274 14 tPHL (ns) 12 10 6 0 10 15 20 25 30 CL (pF) 35 001aal275 14 tPLH (ns) 12 (1) (2) (3) (4) (5) (6) 8 6 4 2 2 0 5 b. LOW to HIGH propagation delay (A to B) 4 0 0 10 (1) (2) (3) (4) (5) (6) 8 (3) (4) (5) (6) 5 10 15 20 25 30 CL (pF) 35 c. HIGH to LOW propagation delay (B to A) 0 0 5 10 15 20 25 30 CL (pF) 35 d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 9. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.5 V 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 15 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 001aal276 14 tPHL (ns) 12 (1) (1) 10 8 10 (3) (3) 6 (4) (5) (6) 4 2 0 5 10 15 20 25 30 CL (pF) 35 a. HIGH to LOW propagation delay (A to B) 001aal278 14 tPHL (ns) 12 10 0 0 5 10 15 20 25 (1) (2) (3) (4) (5) (6) 6 (1) (2) (3) (4) (5) (6) 8 6 4 2 2 5 10 15 20 25 30 CL (pF) 35 c. HIGH to LOW propagation delay (B to A) 35 001aal279 14 tPLH (ns) 12 4 0 30 CL (pF) b. LOW to HIGH propagation delay (A to B) 10 8 0 (4) (5) (6) 4 2 0 (2) 8 (2) 6 001aal277 14 tPLH (ns) 12 0 0 5 10 15 20 25 30 CL (pF) 35 d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 10. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.8 V 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 16 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 001aal280 14 tPHL (ns) 12 (1) 10 8 8 (2) (3) 6 4 (4) (5) (6) 4 2 (2) (3) (4) (5) (6) 2 0 5 10 15 20 25 30 CL (pF) 35 a. HIGH to LOW propagation delay (A to B) 001aal282 14 tPHL (ns) 12 10 0 0 5 10 15 20 25 30 CL (pF) 35 b. LOW to HIGH propagation delay (A to B) 001aal283 14 tPLH (ns) 12 10 8 8 (1) (2) (3) (4) (5) (6) 6 4 (1) (2) (3) (4) (5) (6) 6 4 2 0 (1) 10 6 0 001aal281 14 tPLH (ns) 12 2 0 5 10 15 20 25 30 CL (pF) 35 c. HIGH to LOW propagation delay (B to A) 0 0 5 10 15 20 25 30 CL (pF) 35 d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 11. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 2.5 V 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 17 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 001aal284 14 tPHL (ns) 12 (1) 10 8 001aal285 14 tPLH (ns) 12 (1) 10 8 (2) (2) 6 (3) 6 (3) 4 (4) (5) (6) 4 (4) (5) (6) 2 0 2 0 5 10 15 20 25 30 CL (pF) 35 a. HIGH to LOW propagation delay (A to B) 001aal286 14 tPHL (ns) 12 10 0 5 10 15 20 25 30 CL (pF) 35 b. LOW to HIGH propagation delay (A to B) 001aal287 14 tPLH (ns) 12 10 8 8 (1) (2) (3) (4) (5) (6) 6 4 (1) (2) (3) (4) (5) (6) 6 4 2 0 0 2 0 5 10 15 20 25 30 CL (pF) 35 c. HIGH to LOW propagation delay (B to A) 0 0 5 10 15 20 25 30 CL (pF) 35 d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 12. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 3.3 V 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 18 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 001aal288 14 tPHL (ns) 12 (1) 10 8 8 (2) (3) 6 4 (4) (5) (6) 4 2 (2) (3) (4) (5) (6) 2 0 5 10 15 20 25 30 CL (pF) 35 a. HIGH to LOW propagation delay (A to B) 001aal290 14 tPHL (ns) 12 0 8 8 (1) (2) (3) (4) (5) (6) 4 5 10 15 20 25 35 (1) (2) (3) (4) (5) (6) 6 4 2 30 CL (pF) 001aal291 14 tPLH (ns) 12 10 6 0 b. LOW to HIGH propagation delay (A to B) 10 0 (1) 10 6 0 001aal289 14 tPLH (ns) 12 2 0 5 10 15 20 25 30 CL (pF) 35 c. HIGH to LOW propagation delay (B to A) 0 0 5 10 15 20 25 30 CL (pF) 35 d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 13. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 5 V 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 19 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 12. Application information 12.1. Unidirectional logic level-shifting application The circuit given in Fig. 14 is an example of the 74LVC8T245; 74LVCH8T245 being used in an unidirectional logic level-shifting application. VCC1 VCC1 VCC(A) VCC(B) 74LVC8T245 74LVCH8T245 GND An DIR VCC2 VCC2 Bn OE system-1 system-2 001aak438 Schematic given for one channel. Fig. 14. Unidirectional logic level-shifting application Table 15. Description unidirectional logic level-shifting application Name Function Description VCC(A) VCC1 supply voltage of system-1 (1.2 V to 5.5 V) GND GND device GND A OUT output level depends on VCC1 voltage B IN input threshold value depends on VCC2 voltage DIR DIR the GND (LOW level) determines B port to A port direction VCC(B) VCC2 supply voltage of system-2 (1.2 V to 5.5 V) OE OE The GND (LOW level) enables the output ports 12.2. Bidirectional logic level-shifting application Fig. 15 shows the 74LVC8T245; 74LVCH8T245 being used in a bidirectional logic level-shifting application. VCC1 VCC1 I/O-1 PULL-UP/DOWN VCC(A) GND A VCC(B) 74LVC8T245 74LVCH8T245 DIR VCC2 VCC2 I/O-2 PULL-UP/DOWN B OE OE DIR CTRL system-1 system-2 001aak439 Schematic given for one channel. Pull-up or pull-down only needed for 74LVC8T245. Fig. 15. Bidirectional logic level-shifting application 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 20 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state Table 16 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 16. Description bidirectional logic level-shifting application H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. State DIR CTRL OE I/O-1 I/O-2 Description 1 H L output input system-1 data to system-2 2 H H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on bus hold. 3 L H Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold. 4 L L input output system-2 data to system-1 12.3. Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 17. Typical total supply current (ICC(A) + ICC(B)) VCC(A) VCC(B) 74LVC_LVCH8T245 Product data sheet Unit 0V 1.8 V 2.5 V 3.3 V 5.0 V 0V 0 <1 <1 <1 <1 A 1.8 V <1 <2 <2 <2 2 A 2.5 V <1 <2 <2 <2 <2 A 3.3 V <1 <2 <2 <2 <2 A 5.0 V <1 2 <2 <2 <2 A All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 21 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 13. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 pin 1 index (A 3 ) A1 A Lp 1 L 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 16. Package outline SOT355-1 (TSSOP24) 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 22 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm D B SOT815-1 A A E A1 c detail X terminal 1 index area C e1 terminal 1 index area e 2 y1 C v M C A B w M C b 11 y L 12 1 e2 Eh 24 13 23 14 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 5.6 5.4 4.25 3.95 3.6 3.4 2.25 1.95 0.5 4.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT815-1 --- --- --- EUROPEAN PROJECTION ISSUE DATE 03-04-29 Fig. 17. Package outline SOT815-1 (DHVQFN24) 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 23 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 14. Abbreviations Table 18. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC_LVCH8T245 v.4 20200922 Product data sheet - Modifications: * * * The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Table 4: Derating values for Ptot total power dissipation updated. 74LVC_LVCH8T245 v.3 20111212 Modifications: * 74LVC_LVCH8T245 v.2 20110211 74LVC_LVCH8T245 v.1 20100111 74LVC_LVCH8T245 Product data sheet 74LVC_LVCH8T245 v.3 Product data sheet - 74LVC_LVCH8T245 v.2 Product data sheet - 74LVC_LVCH8T245 v.1 Product data sheet - - Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 24 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state 16. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Data sheet status Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes -- Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74LVC_LVCH8T245 Product data sheet Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the Nexperia product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). Nexperia does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 25 / 26 74LVC8T245; 74LVCH8T245 Nexperia 8-bit dual supply translating transceiver; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 9 10.1. Waveforms and test circuit...................................... 12 11. Typical propagation delay characteristics.............. 14 12. Application information........................................... 20 12.1. Unidirectional logic level-shifting application............20 12.2. Bidirectional logic level-shifting application.............. 20 12.3. Power-up considerations......................................... 21 13. Package outline........................................................ 22 14. Abbreviations............................................................ 24 15. Revision history........................................................24 16. Legal information......................................................25 (c) Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 22 September 2020 74LVC_LVCH8T245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 September 2020 (c) Nexperia B.V. 2020. All rights reserved 26 / 26