74LVC8T245PW,118 - NEXPERIA

74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

Rev. 4 — 22 September 2020 Product data sheet

1. General description

The 74LVC8T245; 74LVCH8T245 are 8-bit dual supply translating transceivers with 3-state outputs

that enable bidirectional level translation. They feature two data input-output ports (pins An and

Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and

VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making

the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V,

3.3 V and 5.0 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to

VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission

from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are

effectively isolated.

The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry

disables the output, preventing any damaging backflow current through the device when it is

powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and

B port are in the high-impedance OFF-state.

Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a valid logic

level.

2. Features and benefits

•Wide supply voltage range:

•VCC(A): 1.2 V to 5.5 V

•VCC(B): 1.2 V to 5.5 V

•High noise immunity

•Complies with JEDEC standards:

•JESD8-7 (1.2 V to 1.95 V)

•JESD8-5 (1.8 V to 2.7 V)

•JESD8C (2.7 V to 3.6 V)

•JESD36 (4.5 V to 5.5 V)

•ESD protection:

•HBM JESD22-A114F Class 3A exceeds 4000 V

•MM JESD22-A115-B exceeds 200 V

•CDM JESD22-C101E exceeds 1000 V

•Maximum data rates:

•420 Mbps (3.3 V to 5.0 V translation)

•210 Mbps (translate to 3.3 V)

•140 Mbps (translate to 2.5 V)

•75 Mbps (translate to 1.8 V)

•60 Mbps (translate to 1.5 V)

•Suspend mode

•Latch-up performance exceeds 100 mA per JESD 78B Class II

•±24 mA output drive (VCC = 3.0 V)

•Inputs accept voltages up to 5.5 V

•Low power consumption: 30 μA maximum ICC

•IOFF circuitry provides partial Power-down mode operation

•Specified from -40 °C to +85 °C and -40 °C to +125 °C

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

3. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

74LVC8T245PW

74LVCH8T245PW

-40 °C to +125 °C TSSOP24 plastic thin shrink small outline package; 24 leads;

body width 4.4 mm

SOT355-1

74LVC8T245BQ

74LVCH8T245BQ

-40 °C to +125 °C DHVQFN24 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 24 terminals;

body 3.5 × 5.5 × 0.85 mm

SOT815-1

4. Functional diagram

001aai472

DIR

VCC(A) VCC(B)

A1 A2 A3 A4 A5 A6 A7 A8

B1 B2 B3 B4 B5 B6 B7 B8

4 5 6 7 8 9 10

21 20 19 18 17 16 15 14

Fig. 1. Logic symbol

001aai473

to other seven channels

DIR

VCC(A) VCC(B)

Fig. 2. Logic diagram (one channel)

Product data sheet Rev. 4 — 22 September 2020 2 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

5. Pinning information

5.1. Pinning

74LVC8T245

74LVCH8T245

VCC(A) VCC(B)

DIR VCC(B)

A1 OE

A2 B1

A3 B2

A4 B3

A5 B4

A6 B5

A7 B6

A8 B7

GND B8

GND GND

001aak436

Fig. 3. Pin configuration SOT355-1 (TSSOP24)

001aak437

74LVC8T245

74LVCH8T245

Transparent top view

GND

A7 B6

A6 B5

A5 B4

A4 B3

A3 B2

A2 B1

A1 OE

DIR VCC(B)

GND

VCC(A)

VCC(B)

11 14

10 15

9 16

8 17

7 18

6 19

5 20

4 21

3 22

2 23

terminal 1

index area

GND(1)

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 4. Pin configuration SOT815-1 (DHVQFN24)

5.2. Pin description

Table 2. Pin description

Symbol Pin Description

VCC(A) 1 supply voltage A

(An inputs/outputs, OE and DIR inputs are referenced to VCC(A))

DIR 2 direction control

A1, A2, A3, A4,

A5, A6, A7, A8

3, 4, 5, 6,

7, 8, 9, 10

data input or output

GND [1] 11, 12, 13 ground (0 V)

B1, B2, B3, B4,

B5, B6, B7, B8

21, 20, 19, 18,

17, 16, 15, 14

data input or output

OE 22 output enable input (active LOW)

VCC(B) 23, 24 supply voltage B (Bn inputs/outputs are referenced to VCC(B))

[1] All GND pins must be connected to ground (0 V).

Product data sheet Rev. 4 — 22 September 2020 3 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

Supply voltage Input Input/output [1]

VCC(A), VCC(B) OE [2] DIR [2] An [2] Bn [2]

1.2 V to 5.5 V L L An = Bn input

1.2 V to 5.5 V L H input Bn = An

1.2 V to 5.5 V H X Z Z

GND [1] X X Z Z

[1] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.

[2] The An inputs/outputs, DIR and OE input circuit is referenced to VCC(A); The Bn inputs/outputs circuit is referenced to VCC(B).

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC(A) supply voltage A -0.5 +6.5 V

VCC(B) supply voltage B -0.5 +6.5 V

IIK input clamping current VI < 0 V -50 - mA

VIinput voltage [1] -0.5 +6.5 V

IOK output clamping current VO < 0 V -50 - mA

Active mode [1] [2] [3] -0.5 VCCO + 0.5 VVOoutput voltage

Suspend or 3-state mode [1] -0.5 +6.5 V

IOoutput current VO = 0 V to VCCO [2] - ±50 mA

ICC supply current ICC(A) or ICC(B); per VCC pin - 100 mA

IGND ground current per GND pin -100 - mA

Tstg storage temperature -65 +150 °C

Ptot total power dissipation Tamb = -40 °C to +125 °C [4] - 500 mW

[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] VCCO is the supply voltage associated with the output port.

[3] VCCO + 0.5 V should not exceed 6.5 V.

[4] For SOT355-1 (TSSOP24) package: Ptot derates linearly with 12.4 mW/K above 110 °C.

For SOT815-1 (DHVQFN24) package: Ptot derates linearly with 15.0 mW/K above 117 °C.

Product data sheet Rev. 4 — 22 September 2020 4 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Max Unit

VCC(A) supply voltage A 1.2 5.5 V

VCC(B) supply voltage B 1.2 5.5 V

VIinput voltage 0 5.5 V

Active mode [1] 0 VCCO VVOoutput voltage

Suspend or 3-state mode 0 5.5 V

Tamb ambient temperature -40 +125 °C

VCCI = 1.2 V [2] - 20 ns/V

VCCI = 1.4 V to 1.95 V - 20 ns/V

VCCI = 2.3 V to 2.7 V - 20 ns/V

VCCI = 3 V to 3.6 V - 10 ns/V

Δt/ΔV input transition rise and fall rate

VCCI = 4.5 V to 5.5 V - 5 ns/V

[1] VCCO is the supply voltage associated with the output port.

[2] VCCI is the supply voltage associated with the input port.

9. Static characteristics

Table 6. Typical static characteristics at Tamb = 25 °C

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

VI = VIH or VIL [1]VOH HIGH-level output

voltage IO = -3 mA; VCCO = 1.2 V - 1.09 - V

VI = VIH or VIL

VOL LOW-level output

voltage IO = 3 mA; VCCO = 1.2 V [1] - 0.07 - V

IIinput leakage

current

DIR, OE input; VI = 0 V to 5.5 V;

VCCI = 1.2 V to 5.5 V

[2] - - ±1 μA

IBHL bus hold LOW

current

A or B port; VI = 0.42 V; VCCI = 1.2 V [2] - 19 - μA

IBHH bus hold HIGH

current

A or B port; VI = 0.78 V; VCCI = 1.2 V [2] - -19 - μA

IBHLO bus hold LOW

overdrive current

A or B port; VCCI = 1.2 V [2] [3] - 19 - μA

IBHHO bus hold HIGH

overdrive current

A or B port; VCCI = 1.2 V [2] [3] - -19 - μA

A or B port; VO = 0 V or VCCO;

VCCO = 1.2 V to 5.5 V

[1] - - ±1 μA

suspend mode A port; VO = 0 V or VCCO;

VCC(A) = 5.5 V; VCC(B) = 0 V

[1] - - ±1 μA

IOZ OFF-state output

current

suspend mode B port; VO = 0 V or VCCO;

VCC(A) = 0 V; VCC(B) = 5.5 V

[1] - - ±1 μA

Product data sheet Rev. 4 — 22 September 2020 5 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

Symbol Parameter Conditions Min Typ Max Unit

A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V;

VCC(B) = 1.2 V to 5.5 V

- - ±1 μAIOFF power-off leakage

current

B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V;

VCC(A) = 1.2 V to 5.5 V

- - ±1 μA

CIinput capacitance DIR, OE input; VI = 0 V or 3.3 V; VCC(A) = 3.3 V - 3 - pF

CI/O input/output

capacitance

A and B port; VO = 3.3 V or 0 V;

VCC(A) = VCC(B) = 3.3 V

- 6.5 - pF

[1] VCCO is the supply voltage associated with the output port.

[2] VCCI is the supply voltage associated with the data input port.

[3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH.

Table 7. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Max Min Max

Unit

data input [1]

VCCI = 1.2 V 0.8VCCI - 0.8VCCI - V

VCCI = 1.4 V to 1.95 V 0.65VCCI - 0.65VCCI - V

VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V

VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V

VCCI = 4.5 V to 5.5 V 0.7VCCI - 0.7VCCI - V

DIR, OE input

VCCI = 1.2 V 0.8VCC(A) - 0.8VCC(A) - V

VCCI = 1.4 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V

VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V

VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V

VIH HIGH-level

input voltage

VCCI = 4.5 V to 5.5 V 0.7VCC(A) - 0.7VCC(A) - V

data input [1]

VCCI = 1.2 V - 0.2VCCI - 0.2VCCI V

VCCI = 1.4 V to 1.95 V - 0.35VCCI - 0.35VCCI V

VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V

VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V

VCCI = 4.5 V to 5.5 V - 0.3VCCI - 0.3VCCI V

DIR, OE input

VCCI = 1.2 V - 0.2VCC(A) - 0.2VCC(A) V

VCCI = 1.4 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V

VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V

VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V

VIL LOW-level

input voltage

VCCI = 4.5 V to 5.5 V - 0.3VCC(A) - 0.3VCC(A) V

Product data sheet Rev. 4 — 22 September 2020 6 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Max Min Max

Unit

VI = VIH

IO = -100 μA;

VCCO = 1.2 V to 4.5 V

[2] VCCO - 0.1 - VCCO - 0.1 - V

IO = -6 mA; VCCO = 1.4 V 1.0 - 1.0 - V

IO = -8 mA; VCCO = 1.65 V 1.2 - 1.2 - V

IO = -12 mA; VCCO = 2.3 V 1.9 - 1.9 - V

IO = -24 mA; VCCO = 3.0 V 2.4 - 2.4 - V

VOH HIGH-level

output voltage

IO = -32 mA; VCCO = 4.5 V 3.8 - 3.8 - V

VI = VIL [2]

IO = 100 μA;

VCCO = 1.2 V to 4.5 V

- 0.1 - 0.1 V

IO = 6 mA; VCCO = 1.4 V - 0.3 - 0.3 V

IO = 8 mA; VCCO = 1.65 V - 0.45 - 0.45 V

IO = 12 mA; VCCO = 2.3 V - 0.3 - 0.3 V

IO = 24 mA; VCCO = 3.0 V - 0.55 - 0.55 V

VOL LOW-level

output voltage

IO = 32 mA; VCCO = 4.5 V - 0.55 - 0.55 V

IIinput leakage

current

DIR, OE input; VI = 0 V to 5.5 V;

VCCI = 1.2 V to 5.5 V

- ±2 - ±10 μA

A or B port [1]

VI = 0.49 V; VCCI = 1.4 V 15 - 10 - μA

VI = 0.58 V; VCCI = 1.65 V 25 - 20 - μA

VI = 0.70 V; VCCI = 2.3 V 45 - 45 - μA

VI = 0.80 V; VCCI = 3.0 V 100 - 80 - μA

IBHL bus hold LOW

current

VI = 1.35 V; VCCI = 4.5 V 100 - 100 - μA

A or B port [1]

VI = 0.91 V; VCCI = 1.4 V -15 - -10 - μA

VI = 1.07 V; VCCI = 1.65 V -25 - -20 - μA

VI = 1.70 V; VCCI = 2.3 V -45 - -45 - μA

VI = 2.00 V; VCCI = 3.0 V -100 - -80 - μA

IBHH bus hold HIGH

current

VI = 3.15 V; VCCI = 4.5 V -100 - -100 - μA

A or B port [1] [3]

VCCI = 1.6 V 125 - 125 - μA

VCCI = 1.95 V 200 - 200 - μA

VCCI = 2.7 V 300 - 300 - μA

VCCI = 3.6 V 500 - 500 - μA

IBHLO bus hold LOW

overdrive

current

VCCI = 5.5 V 900 - 900 - μA

A or B port [1] [3]

VCCI = 1.6 V -125 - -125 - μA

VCCI = 1.95 V -200 - -200 - μA

VCCI = 2.7 V -300 - -300 - μA

VCCI = 3.6 V -500 - -500 - μA

IBHHO bus hold HIGH

overdrive

current

VCCI = 5.5 V -900 - -900 - μA

Product data sheet Rev. 4 — 22 September 2020 7 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Max Min Max

Unit

A or B port; VO = 0 V or VCCO;

VCCO = 1.2 V to 5.5 V

[2] - ±2 - ±10 μA

suspend mode A port;

VO = 0 V or VCCO; VCC(A) = 5.5 V;

VCC(B) = 0 V

[2] - ±2 - ±10 μA

IOZ OFF-state

output current

suspend mode B port;

VO = 0 V or VCCO; VCC(A) = 0 V;

VCC(B) = 5.5 V

[2] - ±2 - ±10 μA

A port; VI or VO = 0 V to 5.5 V;

VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V

- ±2 - ±10 μAIOFF power-off

leakage current

B port; VI or VO = 0 V to 5.5 V;

VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V

- ±2 - ±10 μA

A port; VI = 0 V or VCCI; IO = 0 A [1]

VCC(A), VCC(B) = 1.2 V to 5.5 V - 15 - 20 μA

VCC(A) = 5.5 V; VCC(B) = 0 V - 15 - 20 μA

VCC(A) = 0 V; VCC(B) = 5.5 V -2 - -4 - μA

B port; VI = 0 V or VCCI; IO = 0 A

VCC(A), VCC(B) = 1.2 V to 5.5 V - 15 - 20 μA

VCC(B) = 0 V; VCC(A) = 5.5 V -2 - -4 - μA

VCC(B) = 5.5 V; VCC(A) = 0 V - 15 - 20 μA

A plus B port (ICC(A) + ICC(B));

IO = 0 A; VI = 0 V or VCCI

ICC supply current

VCC(A), VCC(B) = 1.2 V to 5.5 V - 25 - 30 μA

per input;

VCC(A), VCC(B) = 3.0 V to 5.5 V

DIR and OE input;

DIR or OE input at VCC(A) - 0.6 V;

A port at VCC(A) or GND;

B port = open

- 50 - 75 μA

A port; A port at VCC(A) - 0.6 V;

DIR at VCC(A); B port = open

[4] - 50 - 75 μA

ΔICC additional

supply current

B port; B port at VCC(B) - 0.6 V;

DIR at GND; A port = open

[4] - 50 - 75 μA

[1] VCCI is the supply voltage associated with the data input port.

[2] VCCO is the supply voltage associated with the output port.

[3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH.

[4] For non bus hold parts only (74LVC8T245).

Product data sheet Rev. 4 — 22 September 2020 8 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

10. Dynamic characteristics

Table 8. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 °C

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for wave forms see Fig. 5 and Fig. 6. [1]

VCC(B)

Symbol Parameter Conditions

1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V

Unit

An to Bn 11.0 8.5 7.4 6.2 5.7 5.4 nstpd propagation delay

Bn to An 11.0 10.0 9.5 9.1 8.9 8.9 ns

OE to An 9.5 9.5 9.5 9.5 9.5 9.5 nstdis disable time

OE to Bn 10.2 8.2 7.8 6.7 7.3 6.4 ns

OE to An 13.5 13.5 13.5 13.5 13.5 13.5 nsten enable time

OE to Bn 13.6 10.3 8.9 7.5 7.1 7.0 ns

[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

Table 9. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 °C

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for wave forms see Fig. 5 and Fig. 6. [1]

VCC(A)

Symbol Parameter Conditions

1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V

Unit

An to Bn 11.0 10.0 9.5 9.1 8.9 8.8 nstpd propagation delay

Bn to An 11.0 8.5 7.3 6.2 5.7 5.4 ns

OE to An 9.5 6.8 5.4 3.8 4.1 3.1 nstdis disable time

OE to Bn 10.2 9.1 8.6 8.1 7.8 7.8 ns

OE to An 13.5 9.0 6.9 4.8 3.8 3.2 nsten enable time

OE to Bn 13.6 12.5 12.0 11.5 11.4 11.4 ns

[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C

Voltages are referenced to GND (ground = 0 V). [1] [2]

VCC(A) and VCC(B)

Symbol Parameter Conditions

1.8 V 2.5 V 3.3 V 5.0 V

Unit

A port: (direction A to B);

B port: (direction B to A)

1 1 1 2 pFCPD power dissipation

capacitance

A port: (direction B to A);

B port: (direction A to B)

13 13 13 13 pF

[1] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

Σ(CL × VCC 2 × fo) = sum of the outputs.

[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.

Product data sheet Rev. 4 — 22 September 2020 9 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

Table 11. Dynamic characteristics for temperature range -40 °C to +85 °C

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6. [1]

VCC(B)

1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V

Symbol Parameter Conditions

Min Max Min Max Min Max Min Max Min Max

Unit

VCC(A) = 1.5 V ± 0.1 V

An to Bn 1.7 27 1.7 23 1.3 18 1.0 15 0.8 13 nstpd propagation

delay Bn to An 0.9 27 0.9 25 0.8 23 0.7 23 0.7 22 ns

OE to An 1.5 30 1.5 30 1.5 30 1.5 30 1.4 30 nstdis disable time

OE to Bn 2.4 34 2.4 33 1.9 15 1.7 14 1.3 12 ns

OE to An 0.4 34 0.4 34 0.4 34 0.4 34 0.4 34 nsten enable time

OE to Bn 1.8 36 1.8 34 1.5 18 1.2 15 0.9 13 ns

VCC(A) = 1.8 V ± 0.15 V

An to Bn 1.7 25 1.7 21.9 1.3 9.2 1.0 7.4 0.8 7.1 nstpd propagation

delay Bn to An 0.9 23 0.9 23.8 0.8 23.6 0.7 23.4 0.7 23.4 ns

OE to An 1.5 30 1.5 29.6 1.5 29.4 1.5 29.3 1.4 29.2 nstdis disable time

OE to Bn 2.4 33 2.4 32.2 1.9 13.1 1.7 12.0 1.3 10.3 ns

OE to An 0.4 24 0.4 24.0 0.4 23.8 0.4 23.7 0.4 23.7 nsten enable time

OE to Bn 1.8 34 1.8 32.0 1.5 16.0 1.2 12.6 0.9 10.8 ns

VCC(A) = 2.5 V ± 0.2 V

An to Bn 1.5 23 1.5 21.4 1.2 9.0 0.8 6.2 0.6 4.8 nstpd propagation

delay Bn to An 1.2 18 1.2 9.3 1.0 9.1 1.0 8.9 0.9 8.8 ns

OE to An 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 nstdis disable time

OE to Bn 2.3 31 2.3 29.6 1.8 11.0 1.7 9.3 0.9 6.9 ns

OE to An 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 nsten enable time

OE to Bn 1.7 32 1.7 28.2 1.5 12.9 1.2 9.4 1.0 6.9 ns

VCC(A) = 3.3 V ± 0.3 V

An to Bn 1.5 23 1.5 21.2 1.1 8.8 0.8 6.3 0.5 4.4 nstpd propagation

delay Bn to An 0.8 15 0.8 7.2 0.8 6.2 0.7 6.1 0.6 6.0 ns

OE to An 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 nstdis disable time

OE to Bn 2.1 30 2.1 29.0 1.7 10.3 1.5 8.6 0.8 6.3 ns

OE to An 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 nsten enable time

OE to Bn 1.8 31 1.8 27.7 1.4 12.4 1.1 8.5 0.9 6.4 ns

VCC(A) = 5.0 V ± 0.5 V

An to Bn 1.5 22 1.5 21.4 1.0 8.8 0.7 6.0 0.4 4.2 nstpd propagation

delay Bn to An 0.7 13 0.7 7.0 0.4 4.8 0.3 4.5 0.3 4.3 ns

OE to An 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 nstdis disable time

OE to Bn 2.0 30 2.0 28.7 1.6 9.7 1.4 8.0 0.7 5.7 ns

OE to An 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 nsten enable time

OE to Bn 1.5 31 1.5 27.6 1.3 11.4 1.0 8.1 0.9 6.0 ns

[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

Product data sheet Rev. 4 — 22 September 2020 10 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

Table 12. Dynamic characteristics for temperature range -40 °C to +125 °C

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6. [1]

VCC(B)

1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V

Symbol Parameter Conditions

Min Max Min Max Min Max Min Max Min Max

Unit

VCC(A) = 1.5 V ± 0.1 V

An to Bn 1.7 32 1.7 27 1.3 21 1.0 18 0.8 16 nstpd propagation

delay Bn to An 0.9 32 0.9 30 0.8 28 0.7 28 0.7 26 ns

OE to An 1.5 34 1.5 34 1.5 34 1.5 34 1.4 34 nstdis disable time

OE to Bn 2.4 41 2.4 40 1.9 18 1.7 17 1.3 15 ns

OE to An 0.4 40 0.4 40 0.4 40 0.4 40 0.4 40 nsten enable time

OE to Bn 1.8 43 1.8 41 1.5 22 1.2 18 0.9 16 ns

VCC(A) = 1.8 V ± 0.15 V

An to Bn 1.7 30 1.7 25.9 1.3 13.2 1.0 11.4 0.8 11.1 nstpd propagation

delay Bn to An 0.9 27 0.9 28.8 0.8 27.6 0.7 27.4 0.7 27.4 ns

OE to An 1.5 34 1.5 33.6 1.5 33.4 1.5 33.3 1.4 33.2 nstdis disable time

OE to Bn 2.4 40 2.4 36.2 1.9 17.1 1.7 16.0 1.3 14.3 ns

OE to An 0.4 28 0.4 28 0.4 27.8 0.4 27.7 0.4 27.7 nsten enable time

OE to Bn 1.8 41 1.8 40 1.5 20 1.2 16.6 0.9 14.8 ns

VCC(A) = 2.5 V ± 0.2 V

An to Bn 1.5 28 1.5 25.4 1.2 13 0.8 10.2 0.6 8.8 nstpd propagation

delay Bn to An 1.2 23 1.2 13.3 1.0 13.1 1.0 12.9 0.9 12.8 ns

OE to An 1.4 13 1.4 13 1.4 13 1.4 13 1.4 13 nstdis disable time

OE to Bn 2.3 37 2.3 33.6 1.8 15 1.7 14.3 0.9 10.9 ns

OE to An 1.0 17.2 1.0 17.2 1.0 17.3 1.0 17.2 1.0 17.3 nsten enable time

OE to Bn 1.7 38 1.7 32.2 1.5 18.1 1.2 14.1 1.0 11.2 ns

VCC(A) = 3.3 V ± 0.3 V

An to Bn 1.5 28 1.5 25.2 1.1 12.8 0.8 10.3 0.5 10.4 nstpd propagation

delay Bn to An 0.8 18 0.8 11.2 0.8 10.2 0.7 10.1 0.6 10 ns

OE to An 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 nstdis disable time

OE to Bn 2.1 36 2.1 33 1.7 14.3 1.5 12.6 0.8 10.3 ns

OE to An 0.8 14.1 0.8 14.1 0.8 13.6 0.8 13.2 0.8 13.6 nsten enable time

OE to Bn 1.8 37 1.8 31.7 1.4 18.4 1.1 12.9 0.9 10.9 ns

VCC(A) = 5.0 V ± 0.5 V

An to Bn 1.5 26 1.5 25.4 1.0 12.8 0.7 10 0.4 8.2 nstpd propagation

delay Bn to An 0.7 16 0.7 11 0.4 8.8 0.3 8.5 0.3 8.3 ns

OE to An 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 nstdis disable time

OE to Bn 2.0 36 2.0 32.7 1.6 13.7 1.4 12 0.7 9.7 ns

OE to An 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 nsten enable time

OE to Bn 1.5 37 1.5 31.6 1.3 18.4 1.0 13.7 0.9 10.7 ns

[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

Product data sheet Rev. 4 — 22 September 2020 11 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

10.1. Waveforms and test circuit

001aai475

An, Bn input

GND

VOH

Bn, An output

VOL

tPHL tPLH

Measurement points are given in Table 13.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 5. The data input (An, Bn) to output (Bn, An) propagation delay times

001aai474

tPLZ

tPHZ

outputs

disabled

outputs

enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input

VOL

VOH

VCCO

GND

tPZL

tPZH

Measurement points are given in Table 13.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 6. Enable and disable times

Table 13. Measurement points

Supply voltage Input [1] Output [2]

VCC(A), VCC(B) VMVMVXVY

1.2 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH - 0.1 V

1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH - 0.15 V

3.0 V to 5.5 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH - 0.3 V

[1] VCCI is the supply voltage associated with the data input port.

[2] VCCO is the supply voltage associated with the output port.

Product data sheet Rev. 4 — 22 September 2020 12 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aae331

VEXT

VCC

VIVO

DUT

Test data is given in Table 14.

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance.

VEXT = External voltage for measuring switching times.

Fig. 7. Test circuit for measuring switching times

Table 14. Test data

Supply voltage Input Load VEXT

VCC(A), VCC(B) VI [1] Δt/ΔV [2] CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ [3]

1.2 V to 5.5 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO

[1] VCCI is the supply voltage associated with the data input port.

[2] dV/dt ≥ 1.0 V/ns.

[3] VCCO is the supply voltage associated with the output port.

Product data sheet Rev. 4 — 22 September 2020 13 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

11. Typical propagation delay characteristics

CL (pF)

35255 3020100 15

001aal268

tPHL

(ns)

(3)

(4)

(5)

(6)

(1)

(2)

a. HIGH to LOW propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal269

tPLH

(ns)

(4)

(5)

(6)

(1)

(3)

(2)

b. LOW to HIGH propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal270

tPHL

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

c. HIGH to LOW propagation delay (B to A)

CL (pF)

35255 3020100 15

001aal271

tPLH

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

d. LOW to HIGH propagation delay (B to A)

(1) VCC(B) = 1.2 V.

(2) VCC(B) = 1.5 V.

(3) VCC(B) = 1.8 V.

(4) VCC(B) = 2.5 V.

(5) VCC(B) = 3.3 V.

(6) VCC(B) = 5.0 V.

Fig. 8. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.2 V

Product data sheet Rev. 4 — 22 September 2020 14 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

CL (pF)

35255 3020100 15

001aal272

tPHL

(ns)

(3)

(4)

(5)

(6)

(1)

(2)

a. HIGH to LOW propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal273

tPLH

(ns)

(3)

(4)

(5)

(6)

(1)

(2)

b. LOW to HIGH propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal274

tPHL

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

c. HIGH to LOW propagation delay (B to A)

CL (pF)

35255 3020100 15

001aal275

tPLH

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

d. LOW to HIGH propagation delay (B to A)

(1) VCC(B) = 1.2 V.

(2) VCC(B) = 1.5 V.

(3) VCC(B) = 1.8 V.

(4) VCC(B) = 2.5 V.

(5) VCC(B) = 3.3 V.

(6) VCC(B) = 5.0 V.

Fig. 9. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.5 V

Product data sheet Rev. 4 — 22 September 2020 15 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

CL (pF)

35255 3020100 15

001aal276

tPHL

(ns)

(4)

(5)

(6)

(1)

(2)

(3)

a. HIGH to LOW propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal277

tPLH

(ns)

(4)

(5)

(6)

(1)

(2)

(3)

b. LOW to HIGH propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal278

tPHL

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

c. HIGH to LOW propagation delay (B to A)

CL (pF)

35255 3020100 15

001aal279

tPLH

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

d. LOW to HIGH propagation delay (B to A)

(1) VCC(B) = 1.2 V.

(2) VCC(B) = 1.5 V.

(3) VCC(B) = 1.8 V.

(4) VCC(B) = 2.5 V.

(5) VCC(B) = 3.3 V.

(6) VCC(B) = 5.0 V.

Fig. 10. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.8 V

Product data sheet Rev. 4 — 22 September 2020 16 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

CL (pF)

35255 3020100 15

001aal280

tPHL

(ns)

(4)

(5)

(6)

(1)

(3)

(2)

a. HIGH to LOW propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal281

tPLH

(ns)

(4)

(5)

(6)

(1)

(3)

(2)

b. LOW to HIGH propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal282

tPHL

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

c. HIGH to LOW propagation delay (B to A)

CL (pF)

35255 3020100 15

001aal283

tPLH

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

d. LOW to HIGH propagation delay (B to A)

(1) VCC(B) = 1.2 V.

(2) VCC(B) = 1.5 V.

(3) VCC(B) = 1.8 V.

(4) VCC(B) = 2.5 V.

(5) VCC(B) = 3.3 V.

(6) VCC(B) = 5.0 V.

Fig. 11. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 2.5 V

Product data sheet Rev. 4 — 22 September 2020 17 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

CL (pF)

35255 3020100 15

001aal284

tPHL

(ns)

(4)

(5)

(6)

(1)

(2)

(3)

a. HIGH to LOW propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal285

tPLH

(ns)

(4)

(5)

(6)

(1)

(2)

(3)

b. LOW to HIGH propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal286

tPHL

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

c. HIGH to LOW propagation delay (B to A)

CL (pF)

35255 3020100 15

001aal287

tPLH

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

d. LOW to HIGH propagation delay (B to A)

(1) VCC(B) = 1.2 V.

(2) VCC(B) = 1.5 V.

(3) VCC(B) = 1.8 V.

(4) VCC(B) = 2.5 V.

(5) VCC(B) = 3.3 V.

(6) VCC(B) = 5.0 V.

Fig. 12. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 3.3 V

Product data sheet Rev. 4 — 22 September 2020 18 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

CL (pF)

35255 3020100 15

001aal288

tPHL

(ns)

(4)

(5)

(6)

(1)

(2)

(3)

a. HIGH to LOW propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal289

tPLH

(ns)

(4)

(5)

(6)

(1)

(2)

(3)

b. LOW to HIGH propagation delay (A to B)

CL (pF)

35255 3020100 15

001aal290

tPHL

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

c. HIGH to LOW propagation delay (B to A)

CL (pF)

35255 3020100 15

001aal291

tPLH

(ns)

(1)

(2)

(3)

(4)

(5)

(6)

d. LOW to HIGH propagation delay (B to A)

(1) VCC(B) = 1.2 V.

(2) VCC(B) = 1.5 V.

(3) VCC(B) = 1.8 V.

(4) VCC(B) = 2.5 V.

(5) VCC(B) = 3.3 V.

(6) VCC(B) = 5.0 V.

Fig. 13. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 5 V

Product data sheet Rev. 4 — 22 September 2020 19 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

12. Application information

12.1. Unidirectional logic level-shifting application

The circuit given in Fig. 14 is an example of the 74LVC8T245; 74LVCH8T245 being used in an

unidirectional logic level-shifting application.

001aak438

74LVC8T245

74LVCH8T245

VCC1

system-1 system-2

VCC1

VCC2

VCC(A) VCC(B)

GND DIR

Schematic given for one channel.

Fig. 14. Unidirectional logic level-shifting application

Table 15. Description unidirectional logic level-shifting application

Name Function Description

VCC(A) VCC1 supply voltage of system-1 (1.2 V to 5.5 V)

GND GND device GND

A OUT output level depends on VCC1 voltage

B IN input threshold value depends on VCC2 voltage

DIR DIR the GND (LOW level) determines B port to A port direction

VCC(B) VCC2 supply voltage of system-2 (1.2 V to 5.5 V)

OE OE The GND (LOW level) enables the output ports

12.2. Bidirectional logic level-shifting application

Fig. 15 shows the 74LVC8T245; 74LVCH8T245 being used in a bidirectional logic level-shifting

application.

001aak439

PULL-UP/DOWN PULL-UP/DOWN

74LVC8T245

74LVCH8T245

VCC1

VCC1 VCC2 VCC2

I/O-2I/O-1

DIR CTRL

system-2system-1

VCC(A) VCC(B)

GND DIR

Schematic given for one channel.

Pull-up or pull-down only needed for 74LVC8T245.

Fig. 15. Bidirectional logic level-shifting application

Product data sheet Rev. 4 — 22 September 2020 20 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

Table 16 gives a sequence that will illustrate data transmission from system-1 to system-2 and then

from system-2 to system-1.

Table 16. Description bidirectional logic level-shifting application

H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.

State DIR CTRL OE I/O-1 I/O-2 Description

1 H L output input system-1 data to system-2

2 H H Z Z system-2 is getting ready to send data to

system-1. I/O-1 and I/O-2 are disabled. The

bus-line state depends on bus hold.

3 L H Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are

disabled. The bus-line state depends on bus

hold.

4 L L input output system-2 data to system-1

12.3. Power-up considerations

The device is designed such that no special power-up sequence is required other than GND being

applied first.

Table 17. Typical total supply current (ICC(A) + ICC(B))

VCC(B)

VCC(A)

0 V 1.8 V 2.5 V 3.3 V 5.0 V

Unit

0 V 0 < 1 < 1 < 1 < 1 μA

1.8 V < 1 < 2 < 2 < 2 2 μA

2.5 V < 1 < 2 < 2 < 2 < 2 μA

3.3 V < 1 < 2 < 2 < 2 < 2 μA

5.0 V < 1 2 < 2 < 2 < 2 μA

Product data sheet Rev. 4 — 22 September 2020 21 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

13. Package outline

UNIT A

1 A

2 A

3 b

p c D

(1) E

(2) (1)

e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

7.9

7.7

4.5

4.3 0.65 6.6

6.2

0.4

0.3

0.13 0.1 0.2 1

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT355-1 MO-153 99-12-27

03-02-19

0.25 0.5

0.2

w M

1 12

24 13

pin 1 index

detail X

(A )

v M A

A D

0 2.5 5 mm

scale

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

max.

1.1

Fig. 16. Package outline SOT355-1 (TSSOP24)

Product data sheet Rev. 4 — 22 September 2020 22 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

SOT815-1 - - - - - - - - - 03-04-29

SOT815-1

0 2.5 5 mm

scale

b y

y1 C

A C

v M

w M

terminal 1

index area

terminal 1

index area

UNIT A(1)

max. A1 b c e Eh L e1 y w v

mm 1 0.05

0.00

0.30

0.18 0.5 4.5

1.5 0.2 2.25

1.95

4.25

3.95 0.05 0.05

0.1 0.1

DIMENSIONS (mm are the original dimensions)

0.5

0.3

D(1)

5.6

5.4

E(1)

3.6

3.4

B A

DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;

no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm

A A1

detail X

Fig. 17. Package outline SOT815-1 (DHVQFN24)

Product data sheet Rev. 4 — 22 September 2020 23 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

14. Abbreviations

Table 18. Abbreviations

Acronym Description

CDM Charged Device Model

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

15. Revision history

Table 19. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC_LVCH8T245 v.4 20200922 Product data sheet - 74LVC_LVCH8T245 v.3

Modifications: •The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

•Table 4: Derating values for Ptot total power dissipation updated.

74LVC_LVCH8T245 v.3 20111212 Product data sheet - 74LVC_LVCH8T245 v.2

Modifications: •Legal pages updated.

74LVC_LVCH8T245 v.2 20110211 Product data sheet - 74LVC_LVCH8T245 v.1

74LVC_LVCH8T245 v.1 20100111 Product data sheet - -

Product data sheet Rev. 4 — 22 September 2020 24 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

16. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

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repeated exposure to limiting values will permanently and irreversibly affect

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In the event that customer uses the product for design-in and use in

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product for such automotive applications, use and specifications, and (b)

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Notice: All referenced brands, product names, service names and

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Product data sheet Rev. 4 — 22 September 2020 25 / 26

Nexperia 74LVC8T245; 74LVCH8T245

8-bit dual supply translating transceiver; 3-state

Contents

1. General description...................................................... 1

2. Features and benefits.................................................. 1

3. Ordering information....................................................2

4. Functional diagram.......................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description............................................................. 3

6. Functional description................................................. 4

7. Limiting values............................................................. 4

8. Recommended operating conditions..........................5

9. Static characteristics....................................................5

10. Dynamic characteristics............................................ 9

10.1. Waveforms and test circuit...................................... 12

11. Typical propagation delay characteristics.............. 14

12. Application information........................................... 20

12.1. Unidirectional logic level-shifting application............20

12.2. Bidirectional logic level-shifting application.............. 20

12.3. Power-up considerations......................................... 21

13. Package outline........................................................ 22

14. Abbreviations............................................................ 24

15. Revision history........................................................24

16. Legal information......................................................25

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 22 September 2020

Product data sheet Rev. 4 — 22 September 2020 26 / 26