Hybrid Systems HS 362 e-Channe Multiplexer With Precision Sample-And-Hold FEATURES SAMPLE/HOLS m 16SE or 8DIF Inputs Switchable Mode Control COMMANE: a High Speed: 7usec Acquisition Time to 0.01% ES q = Complete Front End for 12-Bit DAS " HOLD CAP a Protected Multiplexer Inputs grenesta o. ae DESCRIPTION The HS 362 is a complete 12-bit data acquisition system front end network. The HS 362 contains two 8-channel multiplexers and a precision sample and hold that can be user configured to accept either 8 differential inputs or 16 single-ended inputs. The sample and hold amplifier is designed to work in PRODUCT HIGHLIGHTS conjunction with most ADC's by connecting the status 1. The 16-input channels can be user configured for output of the ADC to the SAMPLE/HOLD contro! input either single-ended or differential operation. The of the HS 362. The convert command to the ADC will made select switching is LSTTL compatible for switch the HS 362 into hold mode during conversion. greater system flexibility. An output buffer is provided so that the user can 2. The HS 362 when used with a 12-bit ADC such as connect the HS 362 directly to the unbuffered analog the HS 574 forms a complete, high speed, uP input of most 12-bit successive approximation type compatible data acquisition system. ADC's. 3. Channel select addressing is combined with a When the HS 362 is used with a 12-bit, 25-microsecond latch controi to facilitate interface to wP busses. ADC such as the HS 574, system throughput rate is 4. Aprecision hold capacitor is provided with each 30kHz for full 12-bit precision. HS 362. FUNCTIONAL DIAGRAM orrseT HOLD ADJUST CMD HOLD SE/DIFF MODE SELECT CAPACITOR I: Fe fis fa fs cHOo O o CH10 CH20 ANALOG CH30 8 CHANNEL INPUTS CH40O MULTIPLEXER CH5 O |. cH 6 O , CH70 A | SINGLE ENDED/ SAMPLE & DIFFERENTIAL MOLD 16 Mone AMPLIFIER On ALOG O75 | - OUTPUT CH8 OS CH9 3 L CH 100 2 : ANALOG CH 110 8 CHANNEL INPUTS. CH 120-231 MULTIPLEXER CH 130 22 CH 140 Less HS 362 | ADDRESS SELECT ae LOGIC = 32 28 |29 {30 [31 P i b b 3 3 CHANNEL AE Ag Aq Ag +5V DIGITAL +15V ANALOG ~15V L GROUND GROU! INPUT CHANNEL SELECT 271PRELIMINARY TECHNICAL DATA SPECIFICATIONS (Typical @ + 25C and nominal power supplies unless otherwise specified) MODEL ANALOG INPUTS Number of Inputs Voltage Range> Bias Current, per Channel Impedance ON Channel OFF Channel Fault Current CMR Differential Mode @1kHz, 20V,,., MUX Crosstalk Any OFF Channel to any ON Channel @1kHz, 20V5.5 HS 362K 16 Single-Ended or 8 Differential +10V + 50nA max 1019 211 100pF 1018 Ay 1OpF 20mA, Internally limited 70dB min (80cB typ) - 80dB max (- 90aB typ) HS 362S/HS 362SB' Offset, Channel to Channel + 500 uw V max * ACCURACY Oftset Error, Tin tO Trax + 4m max . Gain Error, Tyin to Trax Linearity Error +0.02% FSR max @25C +0.01% max +0.005% max Twin tO Tax +0.015% max + 0.01% max Noise Error @25C 1mVp.p, 0.1 to MHz max * Tin tO TMax 2mVb 0.1 to MHz max * DRIFT (Tain to TMax) Gain + 4ppm/C max Offset, + 10V Range DIGITAL INPUT? INPUT CHANNEL SELECT CHANNEL LATCH SE/DIFF SAMPLE/HOLD + 4ppm/eS max 4-Bit Binary, CHANNEL ADDRESS 1LS TTL Load 4 = Latch Transparent 0 = Latched 8LS TTL Loads Q" = Single-ended Mode 4 = Differential Mode 2LS TTL Loads Q"' = Sample "4" = Hold High Impedance Input Vry= +1.4V SAMPLE AND HOLD DYNAMICS Acquisition Time, for 20V Step to +0.01% of Final Value? SAMPLE TO HOLD Step Settling Time, Hold Mode to + 1mV of Final Value Feedthrough @1kHz Droop Rate Aperture Delay Aperture Uncertainty 7usec, 10sec max 6mvV 600nsec ~70dB, - 60dB max 0.02mVi/ms, 1mV/ms max 225nsec 1Onsec POWER SUPPLY REQUIREMENTS+ Rated Voltage/Current Total Power TEMPERATURE RANGE Operation Storage NOTES: 1 Level B. nh VIH = 2.7V. w output impedance. b latch-up. a Specifications same as HS 362K. 272 + 15V, +5% @ 40mA max ~15V, +5% @ 20mA max +5V, + 5% @ 25mA max 775mW (typ) 1.0 Watt max 0 to 70C - 25C to +85C + 2ppm/C max soe 8 oe + ee # + + * * ~ 8 oe * 20mA max 20mA max 20mA max 500mWw (typ) 700mMW max ~55C to + 125C ~55C to + 160C The HS 362SB is processed and screened to the requirements of MIL-STD-883 Rev. C, . One LS TTL load is defined as: |, = 0.36mA max @ Vj_ = 0.4V. I}q = 20 Amax@ . For optimum acquisition time performance the analog input should be buffered with a low . The power supplies should be sequenced in this order: + 15V, - 15V, + 5V to avoid . Input voltage is limited to Vpp 4 volts maximum, or 11 volts for a 15 volt supply PACKAGE OUTLINE HS 362K (Plastic) 1,005 | (25.527) | MAX t 0.225 15.715) MAX 0.900 PIN 1 DOT _. 722.860) 1 " 032 op lef : sl] { 0.128 *|| (3.175) a ayy we : 3 t 0.100 a ol] (2.540) . : TYP 17 164 0.010 x 0.020 BOTTOM VIEW (0.254 x 0.508) HS 362S/B (Ceramic) l4 ~~ 9.035 1.00(25.4) 0.69(17.5)" [= MIN-*|+-MAX>| OIMENSIONS INCHES MM) *THIS DIMENSION IS FOR POLYSTYRENE CAPACITOR SUPPLIED 1.750 WITH HS 362K. (44.450) MAX HOLD ~ CAPACITOR 0.165 (4.19) MAX (0.89) MAX PIN 1 DOT 0.230 | ress *DIMENSION IS FOR TEFLON CAPACITOR SUPPLIED WITH 1.712 HS 362S/362SB. (43.48) MAX 17 HOLD 0,010 x 0.018 t BOTTOM VIEW (0.35 x 0.46) CAPACITOR otsa 1.625 0.562 MAX |+-MIN>|=-MAX-=/ af Oo PIN ASSIGNMENTS PIN | FUNCTION PIN | FUNCTION 1 | SE/DIFF MODE SELECT 32 |} CHANNEL LATCH 2 DIGITAL GROUND 31 INPUT CHANNEL ADDRESS. BIT Ap 3 +5V 30 INPUT CHANNEL ADDRESS. BIT A, 4 ANALOG INPUT, CHANNEL 7 29 INPUT CHANNEL ADDRESS. BIT Ag 5 ANALOG INPUT, CHANNEL 6 28 INPUT CHANNEL ADDRESS, BIT Ag 6 ANALOG INPUT, CHANNEL 5 27 ANALOG INPUT, CHANNEL 8 7 | ANALOG INPUT. CHANNEL 4 | 26 | ANALOG INPUT, CHANNEL 9 8 | ANALOG INPUT, CHANNEL 3 | 25 | ANALOG INPUT, CHANNEL 10 9 ANALOG INPUT, CHANNEL 2 24 ANALOG INPUT, CHANNEL 11 10 ANALOG INPUT, CHANNEL 1 23 ANALOG INPUT, CHANNEL 12 11 | ANALOG INPUT, CHANNEL 0 | 22 | ANALOG INPUT. CHANNEL 13 12 HOLD CAPACITOR 21 + 15V 43 SAMPLE/HOLD COMMAND 20 - 15V 14 | OFFSET ADJUST 19 | ANALOG INPUT, CHANNEL 14 tS OFFSET ADJUST 18 ANALOG INPUT, CHANNEL 15 16 ANALOG OUTPUT 17 ANALOG GROUND ABSOLUTE MAXIMUM RATING + V. Digital Supply +V. Analog Supply* -V. Analog Supply Vin. Signa! Vin. Digital AGnD!0DGND +5.5V + 16V - 16V +V, Analog Supply Oto +V. Digital Supply +1V *+V Analog Supply must remain 2 + V Digital SupplyAPPLICATIONS INFORMATION INPUTS The HS 362 has two 8-channel multiplexers as input elements. The output of these multiplexers are con- nected via analog switches to a differential amplifier. One unique feature of the HS 362 is that the internal analog switches can be controlled externally by a digital signal that configures the multiplexer output between single-ended and differential modes. This feature allows the user to select either of these input configuration modes without external hard-wire inter- connections. See Table 1. __ TTL LOGIC SE/DIFF INPUT MUX CONFIGURATION MODE SELECT 0 Single-ended, 16-channeis (PIN 1) 1 Differential, 8-channels Table 1. SE/DIFF Mode Select Truth Table MULTIPLEXER ADDRESSING Multiplexer channels are addressed by means of a level-triggered latch. A logic 1 applied to CHANNEL LATCH causes the address signals to feed directly to the multiplexer to select the desired input channel. The address information is held in the address select logic when a 0 is applied to the CHANNEL LATCH input. Input channel addressing is defined in Table 2. Although the fastest mode of operation involves chang- ing the channel address during the A/D conversion while the sample-and-hold amplifier is in the hold mode, this is not the recommended mode of operation. Latch control logic is shown in Table 3. ADDRESS ON CHANNEL (Pin Number) Differential AE A2 A1- AO Single Ended Hi Lo 0 0 0 0 OQ (11) None 0 0 0 1 1 (10) None 0 0 1 0 2 (9) None 0 0 1 1 3 (8) None 0 1 0 0 4 (7 None 0 1 0 1 5 (6) None 0 1 1 0 6 (5) None 0 1 1 1 7 (4) None 1 0 0 0 8 (27) 0(11) 0(27) 1 0 0 1 9 (26) 1(10) 1 (26) 1 0 1 0) 10 (25) 2 (9) 2 (25) 1 0 1 1 11 (24) 3 (8) 3 (24) 1 1 0 0 12 (23) 4 (7) 5 (23) 1 1 0 1 13 (22) 5 (6) 5 (22) 1 1 1 0 14 (19) 6 (5) 6 (19) 1 1 1 1 15 (18) 7 (4) 7: (18) Table 2. Input Channel Addressing Truth Table _ | TTL Logic | CHANNEL LATCH INPUT INPUT ADDRESS INPUTS 1 Address Passes To MUX (PIN 32) 0 Address Latched Table 3. CHANNEL LATCH Truth Table SAMPLE-AND-HOLD The sample-and-hold circuitry of the HS 362 is an improvement over other designs. Specifically, it offers a smaller hold step, faster acquisition and hold mode settling times, and lower noise in hold mode to improve system performance. A logic '1"' on the SAMPLE/ HOLD command input causes the sample-and-hold to freeze the analog signal while the ADC performs the conversion. Normally, the SAMPLE/HOLD command ts connected to the ADC status output which is at logic 1" during conversions and logic '0 between conver- sions. For slowly changing inputs. throughput speed may be increased by grounding the SAMPLE/HOLD command input and eliminating the hold capacitor. A 2000 pf polystyrene hold capacitor is provided with each HS 362K. A 2000 pf teflon hold capacitor is pro- vided with each HS 362S and HS 362SB. Use of this external hold capacitor ensures optimum performance with respect to sample-to-hoid step size and dielectric absorption effects. Smaller hold capacitors may be used for somewhat faster acquisition times with some penalty paid in a larger sample-to-hoid step (see Figs. 1 and 2). z 20 usec Q Ew QE 10 usec | a Ln G | < 0 1000 2000 4000 6000 8000 Cu (pf) Figure 1. Acquisition Time Vs. Hold Cap (20V Step to .01%) + 40mV a +20mV ar wi Ee n oD 0 = 5 = 20mV -40mV [ 2000 4000 6000 8000 Cu (pf) Figure 2. Typical Hold Step Vs. Hold Cap The hold capacitor is connected between pins 12 and 17. If an alternate capacitor is used. the designer must consider the errors that will be introduced. CAUTION: Polystyrene capacitors will be damaged if subjected to temperatures above + 85C. OFFSET ADJUSTMENT When the HS 362 1s used with an ADC, normally the system offset is adjusted at the ADC. However. an offset adjustment for the HS 362 's provided. Refer to Figure 3 for offset adjustment connections + 1SV t 50k&2 14 15 {3} HS 362 8_6 outPuT Figure 3. HS 362 Offset Voltage Adjustment ADC INTERFACE The HS 362 1s designed to be coupled with a orecision ADC forming a complete data acquisition system (DAS). This generalized connection 1s shown in Fig. 4 273APPLICATIONS INFORMATION (Continued) CONVERT [tho OR CAPACITOR _ START COMMAND ANALOG DIGITAL ANALOG MODE OUTAN OUTPUT {NPUTS SWITCH ANALOG TO DIGITAL S/H AMP CONVERTER ADDRESS [- Selec HS 362 CHANNEL _ INPUT SAMPLE/HOLD STATUS LATCH CHANNEL SELECT COMMAND Figure 4. Data Acquisition Timing of the DAS system (Fig. 4) is shown in Fig. 5. This configuration assumes the following important considerations: 1. Input channel is not changed during a conversion. 2. The MSB decision should not occur until after the S/H amplifier has settled in HOLD mode (tsp). 3. The LSB decision must be made prior to STATUS going low (tLgg20). The S/H amplifier transient during the sample-to- hold transition is shown in Figure 6. INPUT Ra CHANNEL KX oort X . X0oR1 SELECT 2 HANNEL caren \, (0 = LATCHED, 1 = TRANSPARENT) [_ \ i tO mux NEXT CHANNEL ADDRESS X ee X_ ADC ta fi CONVERT ' ~) ADC ne STATUS a . ANALOG qureur | A (ADC INPUT) | tsH | i ADC CLOCK == (INTERNAL) --- LE L___ i | p~tmse | j= tse 1 ' > MSB 7 LSB VALID ADC OUTPUT VALID C SYMBOL PARAMETER ta = Acquisition time, includes . 7us typ, 12 max MUX and sample/hold amplifier settling tgy = Sample to Hold settling 600ns typ tc = Conversion time depends on ADC tmsp = MSB delay trom STATUS 2 tgy tgp = Delay of STATUS from ADC CONV depends on ADC tLsg = Time from LSB decision to <0 STATUS low NOTES: 1. Input address shown is recommended to be latched during A/D conversion cycle. 2. The MSB decision should not occur until after the S/H amplifier has settled in HOLD mode (tg}). 3. LSB decision must be made prior to STATUS going low (tisg 2 0). Figure 5. Data Acquisition System Timing 274 Figure 6. Sample-to-Hold Step (Top), HOLD Command (Bottom) Scale: 20mV/div, vertical; 500 ns/div, horizontal POWER SUPPLY CONSIDERATIONS Analog and digital ground lines should be separated to prevent induced spurious signals being introduced into the system. Analog and digital grounds are not connected internally to the HS 362. These must be connected externally by the user. The choice of an optimum star point is an important consideration in the system layout. Grounds should be arranged to avaid loops and to minimize the coupling of voltage drop to sensitive analog sections. A suggested ground- ing approach is shown in Fig. 7. "ANALOG HS 362 ADC INPUTS DIGITAL ANALOG] "|_ ANALOG DIGITAL +5 +15 -15 GND GND GND GND 3) 2) 20) SOY -15V0 +15VO Ww +5VOQo 7 ANALOG 6 T | GND te DIGITALQ__> GND Figure 7. Power Supply and Grounding Connections In this example the system ground has been chosen to be located at the ADC for optimum performance. Should the grounds be connected at a different point in the system then back-to-back diodes (1N914 or equivalent) are recommended to prevent potential variations between the grounds from exceeding +1 volt. The HS 362 will function properly with as much as + 200mV between grounds. Power leads should be bypassed to ground as shown in Fig. 7. Either 1pf tantalum or 0.1pf ceramic capacitors are recommended. ORDERING INFORMATION TEMPERATURE MODEL RANGE DESCRIPTION HS 362K 0 to 70C Precision 16-channel HS 3628 55C to +125C = data acquisition system HS 362SB* -55Cto +125C analog input section. *Processed to MIL-STD-883 Rev. C, Level B. Specifications subject to change without notice.