Si9120
Vishay Siliconix
Document Number: 70006
S-42042—Rev. H, 15-Nov-04
www.vishay.com
1
Universal Input Switchmode Controller
FEATURES
D10- to 450-V Input Range
DCurrent-Mode Control
D125-mA Output Drive
DInternal Start-Up Circuit
DInternal Oscillator (1 MHz)
DSHUTDOWN and RESET
DESCRIPTION
The Si9120 is a BiC/DMOS integrated circuit designed for use
in low-power, high-efficiency off-line power supplies.
High-voltage DMOS inputs allow the controller to work over a
wide range of input voltages (10- to 450-VDC). Current-mode
PWM control circuitry is implemented in CMOS to reduce
quiescent current to less than 1.5 mA.
A CMOS output driver provides high-speed switching for
MOSFET devices with gate charge, Qg, up to 25 nC, enough
to supply 30 W of output power at 100 kHz. These devices,
when combined with an output MOSFET and transformer, can
be used to implement single-ended power converter
topologies (i.e., flyback and forward).
The Si9120 is available in both standard and lead (Pb)-free
16-pin plastic DIP and SOIC packages which are specified to
operate over the industrial temperature range of −40 _C to
85 _C.
FUNCTIONAL BLOCK DIAGRAM
+
−
−
+
+
−
+
−
+
−
FB COMP DISCHARGE
OSC
15 14 10 9 8
2 V
Ref
Gen
R
S
Q
R
S
Q
SENSE
4
12
13
Current-Mode
Comparator
C/L
1.2 V
Undervoltage Comparator
RESET
8.1 V
8.6 V
BIAS Current
Sources
To
Internal
Circuits
11
16
7
1
Comparator
Error
Amplifier
VREF
VCC
+VIN
VCC
SHUTDOWN
4 V (1%)
Clock (1/2 fOSC)
OSC
OUT
OSC
IN
Pre-Regulator/Start-Up
6
5
−VIN
OUTPUT
To
VCC
Applications information, see AN707 and AN708.
Si9120
Vishay Siliconix
www.vishay.com
2
Document Number: 70006
S-42042—Rev. H, 15-Nov-04
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to −VIN (Note: VCC < +VIN + 0.3 V)
VCC 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+VIN 450 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs (RESET
SHUTDOWN, OSC IN, OSC OUT) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . .
Linear Input
(FEEDBACK, SENSE, BIAS, VREF)−0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . .
HV Pre-Regulator Input Current (continuous) 5 mAa
. . . . . . . . . . . . . . . . . . . .
Continuous Output Current (Source or Sink) 125 mA. . . . . . . . . . . . . . . . . . .
Storage Temperature −65 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature −40 to 85_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction Temperature (TJ) 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation (Package)b
16-Pin Plastic DIP (J Suffix)c750 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin SOIC (Y Suffix)d900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Impedance (QJA)
16-Pin Plastic DIP 167_C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin SOIC 140_C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
a. Continuous current may be limited by the applications maximum input
voltage and the package power dissipation.
b. Device mounted with all leads soldered or welded to PC board.
c. Derate 6 mW/_C above 25_C.
d. Derate 7.2 mW/_C above 25_C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Voltages Referenced to −VIN
VCC 9.5 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+VIN 10 V to 450 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
fOSC 40 kHz to 1 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROSC 25 kW to 1 MW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linear Inputs 0 to VCC − 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputs 0 to VCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPECIFICATIONSa
Specific Test Conditions
DISCHARGE = −V
IN
= 0 V,
LIMITS
D Suffix −40 to 85_C
Parameter Symbol
DISCHARGE = −VIN = 0 V
,
VCC = 10 V +VIN = 300 V
RBIAS = 390 kW, ROSC = 330 kWTEMPBMINCTYPDMAXCUnit
Reference
Output Voltage VROSC IN = − VIN (OSC Disabled)
RL = 10 MW
Room
Full
3.88
3.82
4.0 4.12
4.14 V
Output ImpedanceeZOUT Room 15 30 45 kW
Short Circuit Current ISREF VREF = −VIN Room 70 100 130 mA
Temperature StabilityeTREF Full 0.5 1.0 mV/_C
Oscillator
Maximum FrequencyefMAX ROSC = 0 Room 1 3 MHz
Initial Accuracy
fOSC
CSTRAY Pin 9 5 pF
ROSC = 330 kWRoom 80 100 120
kHz
Initial Accuracy fOSC CSTRAY Pin 9 5 pF
ROSC = 150 kWRoom 160 200 240
kHz
Voltage Stability Df/f Df/f = f(13.5 V) − f(9.5 V) / f(9.5 V) Room 10 15 %
Temperature CoefficienteTOSC Full 200 500 ppm/_C
Error Amplifier
Feedback Input Voltage VFB FB Tied to COMP
OSC IN = − VIN (OSC Disabled) Room 3.92 4.08 V
Input BIAS Current IFB OSC IN = − VIN, VFB = 4 V Room 25 500 nA
Input OFFSET Voltage VOS OSC IN = − VIN Room 15 40 mV
Open Loop Voltage GaineAVOL OSC IN = − VIN Room 60 80 dB
Unity Gain BandwidtheBW OSC IN = − VIN Room 1.0 1.5 MHz
Si9120
Vishay Siliconix
Document Number: 70006
S-42042—Rev. H, 15-Nov-04
www.vishay.com
3
SPECIFICATIONSa
Specific Test Conditions
DISCHARGE = −V
IN
= 0 V,
LIMITS
D Suffix −40 to 85_C
Parameter Symbol
DISCHARGE = −VIN = 0 V
,
VCC = 10 V +VIN = 300 V
RBIAS = 390 kW, ROSC = 330 kWTEMPBMINCTYPDMAXCUnit
Error Amplifier (Cont’d)
Dynamic Output ImpedanceeZOUT Error Amp configured for 60 dB gain Room 1000 2000 W
Output Current
IOUT
Source VFB = 3.4 V Room −2.0 −1.4
mA
Output Current IOUT Sink VFB = 4.5 V Room 0.12 0.15 mA
Power Supply Rejection PSRR 9.5 V VCC 13.5 V Room 50 70 dB
Current Limit
Threshold Voltage VSOURCE VFB = 0 V Room 1.0 1.2 1.4 V
Delay to OutputetdVSENSE = 1.5 V, See Figure 1 Room 100 150 ns
Pre-Regulator/Start-Up
Input Voltage +VIN IIN = 10 mA Room 450 V
Input Leakage Current +IIN VCC 9.4 V Room 10 mA
VCC Pre-Regulator Turn-Off Threshold
Voltage VREG IPRE-REGULATOR = 10 mA Room 7.8 8.6 9.4
V
Undervoltage Lockout VUVLO Room 7.0 8.1 8.9 V
VREG −VUVLO VDELTA Room 0.3 0.6
Supply
Supply Current ICC CL = 500 pF at Pin 5 Room 0.85 1.5 mA
Bias Current IBIAS Room 10 15 20 mA
Logic
SHUTDOWN DelayetSD CL = 500 pF, VSENSE = −VIN
See Figure 2 Room 50 100
SHUTDOWN Pulse WidthetSW Room 50
ns
RESET Pulse WidthetRW See Fi
g
ure 3 Room 50 ns
Latching Pulse Width
SHUTDOWN and RESET LowetLW
See Figure 3
Room 25
Input Low Voltage VIL Room 2.0
V
Input High Voltage VIH Room 8.0 V
Input Current Input Voltage High IIH VIN = 10 V Room 1 5
mA
Input Current Input Voltage Low IIL VIN = 0 V Room −35 −25 mA
Output
Output High Voltage VOH IOUT = −10 mA Room
Full
9.7
9.5
V
Output Low Voltage VOL IOUT = 10 mA Room
Full
0.3
0.5
V
Output Resistance ROUT IOUT = 10 mA, Source or Sink Room
Full
20
25
30
50 W
Rise Timeetr
CL = 500 pF
Room 40 75
ns
Fall Timeetf
C
L
=
5
00
p
F
Room 40 75 ns
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25_C, Cold and Hot = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
a. 250 V +VIN 380 V place a 10-kW, 1/4-W resistor in series with a +VIN (Pin1).
380 V +VIN 450 V place a 15-kW, 1/4-W resistor in series with a +VIN (Pin1).
Connect a 0.01-mfd capacitor between +VIN (Pin 1) and −VIN (Pin 6).
Si9120
Vishay Siliconix
www.vishay.com
4
Document Number: 70006
S-42042—Rev. H, 15-Nov-04
TIMING WAVEFORMS
90%
OUTPUT
SENSE 1.5 V −
50%
0
90%
OUTPUT
0 −
0 −
50%
50% 50%
50% 50%
RESET
0 −
td
tr 10 ns
VCC
VCC
VCC
tSW
tLW
tRW
tf 10 ns
VCC
VCC
tSD
SHUTDOWN
SHUTDOWN tr, tf 10 ns
50%
0 −0 −
FIGURE 1. FIGURE 2.
FIGURE 3.
TYPICAL CHARACTERISTICS
Output Switching Frequency
vs. Oscillator Resistance
1 M
10 k
100 k
10 k
100 k 1 M
(Hz)f OUT
rOSC − Oscillator Resistance (W)
Si9120
Vishay Siliconix
Document Number: 70006
S-42042—Rev. H, 15-Nov-04
www.vishay.com
5
PIN CONFIGURATIONS AND ORDERING INFORMATION
+VIN BIAS
NC*
Dual-In-Line
FB
NC* COMP
SENSE RESET
OUTPUT SHUTDOWN
−VIN VREF
VCC DISCHARGE
OSC OUT OSC IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
+VIN BIAS
SOIC
FB
COMP
SENSE RESET
OUTPUT SHUTDOWN
−VIN VREF
VCC DISCHARGE
OSC OUT OSC IN
1
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
Note: Pins 2 and 3 are removed
ORDERING INFORMATION
Part Number Temperature Range Package
Si9120DY
Si9120DY-T1 SOIC-16
Si9120DY-T1—E3 −40 to 85_C
Si9120DJ
PDIP 16
Si9120DJ—E3 PDIP-16
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section
Due to the low quiescent current requirement of the Si9120
control circuitry, bias power can be supplied from the
unregulated input power source, from an external regulated
low-voltage supply, or from an auxiliary “bootstrap” winding on
the output inductor or transformer.
When power is first applied during start-up, +VIN (pin 1) will
draw a constant current. The magnitude of this current is
determined by a high-voltage depletion MOSFET which is
connected between +VIN and VCC (pin 7). This start-up
circuitry provides initial power to the IC by charging an external
bypass capacitance connected to the VCC pin. The constant
current is disabled when VCC exceeds 8.6 V. If VCC is not
forced to exceed the 8.6-V threshold, then VCC will be
regulated to a nominal value of 8.6 V by the pre-regulator
circuit.
As the supply voltage rises toward the normal operating
conditions, an internal undervoltage (UV) lockout circuit keeps
the output driver disabled until VCC exceeds the undervoltage
lockout threshold (typically 8.1 V). This guarantees that the
control logic will be functioning properly and that sufficient gate
drive voltage is available before the MOSFET turns on. The
design of the IC is such that the undervoltage lockout threshold
will be at least 300 mV less than the pre-regulator turn-off
voltage. Power dissipation can be minimized by providing an
external power source to VCC such that the constant current
source is always disabled.
Note: When driving large MOSFETs at high frequency without
a bootstrap VCC supply, power dissipation in the pre-regulator
may exceed the power rating of the IC package. For operation
of +VIN > 250 V, a 10-kW, 1/4-W resistor should be placed in
series with +VIN (Pin 1). For +VIN > 380 V, a 15-kW, 1/4-W
resistor is recommended.
BIAS
To properly set the bias for the Si9120, a 390-kW resistor
should be tied from BIAS (pin 16) to −VIN (pin 6). This
determines the magnitude of bias current in all of the analog
sections and the pull-up current for the SHUTDOWN and
RESET pins. The current flowing in the bias resistor is
nominally 15 mA.
Si9120
Vishay Siliconix
www.vishay.com
6
Document Number: 70006
S-42042—Rev. H, 15-Nov-04
DETAILED DESCRIPTION (CONT’D)
Reference Section
The reference section of the Si9120 consists of a temperature
compensated buried zener and trimmable divider network.
The output of the reference section is connected internally to
the non-inverting input of the error amplifier. Nominal reference
output voltage is 4 V. The trimming procedure that is used on
the Si9120 brings the output of the error amplifier (which is
configured for unity gain during trimming) to within 2% of 4 V.
This compensates for input offset voltage in the error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external voltage
source can be used to override the internal voltage source, if
desired, without otherwise altering the performance of the
device.
Error Amplifier
Closed-loop regulation is provided by the error amplifier, which
is intended for use with “around-the-amplifier” compensation.
A MOS differential input stage provides for high input
impedance. The noninverting input to the error amplifier
(VREF) is internally connected to the output of the reference
supply and should be bypassed with a small capacitor to
ground.
Oscillator Section
The oscillator consists of a ring of CMOS inverters, capacitors,
and a capacitor discharge switch. Frequency is set by an
external resistor between the OSC IN and OSC OUT pins.
(See Typical Characteristics for details of resistor value vs.
frequency.) The DISCHARGE pin should be tied to −VIN for
normal internal oscillator operation. A frequency divider in the
logic section limits switch duty cycle to 50% by locking the
switching frequency to one half of the oscillator frequency.
SHUTDOWN and RESET
SHUTDOWN (pin 12) and RESET (pin 13) are intended for
overriding the output MOSFET switch via external control
logic. The two inputs are fed through a latch preceding the
output switch. Depending on the logic state of RESET.
SHUTDOWN can be either a latched or unlatched input. The
output is off whenever SHUTDOWN is low. By simultaneously
having SHUTDOWN and RESET low, the latch is set and
SHUTDOWN has no effect until RESET goes high. See
Table TABLE 1.
Both pins have internal current source pull-ups and should be
left disconnected when not in use. An added feature of the
current sources is the ability to connect a capacitor and an
open-collector driver to the SHUTDOWN or RESET pins to
provide variable shutdown time.
TABLE 1.
TRUTH TABLE FOR SHUTDOWN AND
RESET PINS
SHUTDOWN RESET OUTPUT
H H Normal Operation
HNormal Operation (No Change)
L H Off (Not Latched)
L L Off (Latched)
LOff (Latched—No Change)
Output Driver
The push-pull driver output has a typical on-resistance of 20-W
maximum switching times are specified at 75 ns for a 500-pF
load. This is sufficient to directly drive MOSFETs such as the
IRF820, BUZ78 or BUZ80. Larger devices can be driven, but
switching times will be longer, resulting in higher switching
losses.
V ishay Siliconix maintains wor ldwide m anufacturing capability. Produc ts may be manufactur ed at one of several qualified locations . R eliabilit y data fo r Silicon Tec hnology a nd
Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see
http://www.vishay.com/ppg?70006.
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
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