FEATURES
DTrenchFETr Power MOSFET
DUltra-Low rSS(on)
DESD Protected: 4000 V
DNew MICRO FOOTr Chipscale Packaging Reduces
Footprint Area Profile (0.62 mm) and On-Resistance
Per Footprint Area
APPLICATIONS
DBattery Protection Circuit
- 1-2 Cell Li+/LiP Battery Pack for Portable Devices
Si8900EDB
Vishay Siliconix
Document Number: 71830
S-31916—Rev. E, 15-Sep-03
www.vishay.com
1
Bi-Directional N-Channel 20-V (D-S) MOSFET
PRODUCT SUMMARY
VS1S2 (V) rS1S2(on) (W) IS1S2 (A)
0.024 @ VGS = 4.5 V 7
20
0.026 @ VGS = 3.7 V 6.8
20
0.034 @ VGS = 2.5 V 5.0
0.040 @ VGS = 1.8 V 5.5
G2
S2
G1
S1
N-Channel
4 kW
4 kW
MICRO FOOT
Device Marking:
8900E = P/N Code
xxx = Date/Lot Traceability Code
S2
S2
S2
S2
67
Bump Side View
G2G1
5
4
8
9
S1S1
310
S1S1
21
Backside View
8900E
xxx
Pin 1 Identifier
ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED)
Parameter Symbol 5 secs Steady State Unit
Source1—Source2 Voltage VS1S2 20
V
Gate-Source Voltage VGS "12 V
Continuous Source1
—
Source2 Current (TJ
=
150
_
C)
aTA = 25_C
IS1S2
75.4
C
on
ti
nuous
S
ource
1
—
S
ource
2 C
urren
t (T
J
=
150_C)a
TA = 85_C
I
S1S2 5.1 3.9 A
Pulsed Source1—Source2 Current ISM 50
Maximum Power Dissipationa
TA = 25_C
PD
1.8 1
W
Maximum Power Dissipationa
TA = 85_CPD0.9 0.5 W
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150
Package Reflow Conditionsc
VPR 215 _C
Package Reflow Conditionsc
IR/Convection 220
C
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction to Ambienta
t v 5 sec
R
55 70
Maximum Junction-to-Ambienta
Steady State RthJA 95 120 _C/W
Maximum Junction-to-FootbSteady State RthJF 12 15
C/W
Notes
a. Surface Mounted on 1” x 1” FR4 Board.
b. The Foot is defined as the top surface of the package.
c. Refer to IPC/JEDEC (J-STD-020A), no manual or hand soldering.
Si8900EDB
Vishay Siliconix
www.vishay.com
2
Document Number: 71830
S-31916—Rev. E, 15-Sep-03
SPECIFICATIONS (TJ = 25_C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Condition Min Typ Max Unit
Static
Gate Threshold Voltage VGS(th) VSS = VGS, ID = 1.1 mA 0.45 1.0 V
Gate Body Leakage
IGSS
VSS = 0 V, VGS = "4.5 V "4mA
Gate-Body Leakage IGSS VSS = 0 V, VGS = "12 V "10 mA
Zero Gate Voltage Source Current
IS1S2
VSS = 16 V, VGS = 0 V 1
Zero Gate Voltage Source Current IS1S2 VSS = 16 V, VGS = 0 V, TJ = 85_C 5 mA
On-State Source CurrentaIS(on) VSS = 5 V, VGS = 4.5 V 5 A
VGS = 4.5 V, ISS = 1 A 0.020 0.024
Source1 Source2 On State Resistancea
r
VGS = 3.7 V, ISS = 1 A 0.022 0.026
Source1—Source2 On-State ResistancearS1S2(on) VGS = 2.5 V, ISS = 1 A 0.026 0.034 W
VGS = 1.8 V, ISS = 1 A0.032 0.040
Forward Transconductanceagfs VSS = 10 V, ISS = 1 A 31 S
Dynamicb
Turn-On Delay Time td(on) 3 5
Rise Time trV
SS
= 10 V, RL = 10 W4.5 7
Turn-Off Delay Time td(off)
VSS = 10 V
,
RL = 10 W
ISS ^ 1 A, VGEN = 4.5 V, RG = 6 W55 85 ms
Fall Time tf15 25
Notes
a. Pulse test; pulse width v 300 ms, duty cycle v 2%.
b. Guaranteed by design, not subject to production testing.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
0.01
100
10,000
Gate Current vs. Gate-Source Voltage
0
4
8
12
16
20
0 3 6 9 12 15
Gate-Current vs. Gate-Source Voltage
VGS - Gate-to-Source Voltage (V)
0.1
1
10
1,000
VGS - Gate-to-Source Voltage (V)
- Gate Current (IGSS mA)
0369 15
TJ = 25_C
TJ = 150_C
- Gate Current (mA)IGSS
IGSS @ 25_C (mA)
12
Si8900EDB
Vishay Siliconix
Document Number: 71830
S-31916—Rev. E, 15-Sep-03
www.vishay.com
3
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
0
2
4
6
8
10
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.00
0.01
0.02
0.03
0.04
0.05
0246810
0
2
4
6
8
10
01234
0.6
0.8
1.0
1.2
1.4
1.6
-50 -25 0 25 50 75 100 125 150
VGS = 5 thru 1.5 V
25_C
TC = 125_C
-55_C
Output Characteristics Transfer Characteristics
On-Resistance vs. Drain Current
VDS - Drain-to-Source Voltage (V)
- Drain Current (A)ID
VGS - Gate-to-Source Voltage (V)
- Drain Current (A)ID
- On-Resistance (rDS(on) W)
ID - Drain Current (A)
On-Resistance vs. Junction Temperature
TJ - Junction Temperature (_C)
(Normalized)
- On-Resistance (rDS(on) W)
1 V
0.00
0.02
0.04
0.06
0.08
0.10
012345
On-Resistance vs. Gate-to-Source Voltage
- On-Resistance (rDS(on) W)
VGS - Gate-to-Source Voltage (V)
-0.4
-0.3
-0.2
-0.1
-0.0
0.1
0.2
-50 -25 0 25 50 75 100 125 150
Threshold Voltage
Variance (V)VGS(th)
TJ - Temperature (_C)
VGS = 4.5 V
VGS = 2.5 V
VGS = 1.8 V
VGS = 3.7 V
VGS = 4.5 V
IS1S2 = 1 A
IS1S2 = 1 A
IS1S2 = 5 A
IS1S2 = 1.1 mA
Si8900EDB
Vishay Siliconix
www.vishay.com
4
Document Number: 71830
S-31916—Rev. E, 15-Sep-03
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
0
5
30
Power (W)
Single Pulse Power, Junction-to-Ambient
Time (sec)
20
25
10-3 10-2 1 10 60010-1
10-4 100
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Normalized Thermal Transient Impedance, Junction-to-Ambient
Square Wave Pulse Duration (sec)
Normalized Effective Transient
Thermal Impedance
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 95_C/W
3. TJM - T
A = PDMZthJA(t)
t1
t2
t1
t2
Notes:
4. Surface Mounted
PDM
1 1000100.10.01
15
10-3 10-2 110-1
10-4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Normalized Thermal Transient Impedance, Junction-to-Foot
Square Wave Pulse Duration (sec)
Normalized Effective Transient
Thermal Impedance
100
10
Si8900EDB
Vishay Siliconix
Document Number: 71830
S-31916—Rev. E, 15-Sep-03
www.vishay.com
5
PACKAGE OUTLINE
MICRO FOOT: 10−BUMP (2 X 5, 0.8−mm PITCH)
Recommended Land
Mark on Backside of Die
e
e
10 O 0.30 X 0.31
Note 3
Solder Mask O X 0.40
8900E
xxx
b Diamerter
E
D
S1e
e
S2
Bump Note 2
Silicon
A
A2
A1
NOTES (Unless Otherwise Specified):
1. Laser mark on the silicon die back, coated with a thin metal.
2. Bumps are Eutectic solder 63/57 Sn/Pb.
3. Non-solder mask defined copper landing pad.
MILLIMETERS* INCHES
Dim Min Max Min Max
A0.600 0.650 0.0236 0.0256
A10.260 0.290 0.102 0.0114
A20.340 0.360 0.0134 0.0142
b0.370 0.410 0.0146 0.0161
D4.050 4.060 0.1594 0.1598
E1.980 2.000 0.0780 0.0787
e0.750 0.850 0.0295 0.0335
S10.430 0.450 0.0169 0.0177
S20.580 0.600 0.0228 0.0236
* Use millimeters as the primary measurement.