For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX5866 ultra-low-power, highly integrated analog
front end is ideal for portable communication equipment
such as handsets, PDAs, WLAN, and 3G wireless termi-
nals. The MAX5866 integrates dual, 8-bit receive ADCs
and dual, 10-bit transmit DACs while providing the high-
est dynamic performance at ultra-low power. The ADCs’
analog I-Q input amplifiers are fully differential and
accept 1VP-P full-scale signals. Typical I-Q channel
phase matching is ±0.2° and amplitude matching is
±0.05dB. The ADCs feature 48dB SINAD and 70.1dBc
spurious-free dynamic range (SFDR) at fIN = 25MHz and
fCLK = 60MHz. The DACs’ analog I-Q outputs are fully
differential with ±400mV full-scale output, and 1.4V com-
mon-mode level. Typical I-Q channel phase matching is
±0.4° and gain matching is ±0.1dB. The DACs also fea-
ture dual, 10-bit resolution with 64.2dBc SFDR, at fOUT =
6MHz and fCLK = 60MHz.
The ADCs and DACs operate simultaneously or indepen-
dently for frequency-division duplex (FDD) and time-divi-
sion duplex (TDD) modes. A 3-wire serial interface
controls power-down and transceiver modes of opera-
tion. The typical operating power is 96mW at fCLK =
60MHz with the ADCs and DACs operating simultane-
ously in transceiver mode. The MAX5866 features an
internal 1.024V voltage reference that is stable over the
entire operating power-supply range and temperature
range. The MAX5866 operates on a +2.7V to +3.3V ana-
log power supply and a +2.7V to +3.3V digital I/O power
supply for logic compatibility. The quiescent current is
12mA in idle mode and 1µA in shutdown mode. The
MAX5866 is specified for the extended (-40°C to +85°C)
temperature range and is available in a 48-pin thin QFN
package.
Applications
Narrowband/Wideband CDMA Handsets
and PDAs
Fixed/Mobile Broadband Wireless Modems
3G Wireless Terminals
VSAT Modems
Features
♦Integrated Dual, 8-Bit ADCs and Dual, 10-Bit DACs
♦Ultra-Low Power
80mW at fCLK = 60MHz (RxMode)
52.5mW at fCLK = 60MHz (TxMode)
Low-Current Idle and Shutdown Modes
♦Excellent Dynamic Performance
48dB SINAD at fIN = 25MHz (ADC)
64.2dBc SFDR at fOUT = 6MHz (DAC)
♦Excellent Gain/Phase Match
±0.2°Phase, ±0.05dB Gain at fIN = 25MHz (ADC)
♦Internal/External Reference Option
♦+2.7V to +3.3V Digital Output Level (TTL/CMOS
Compatible)
♦Multiplexed Parallel Digital Input/Output for
ADCs/DACs
♦Miniature 48-Pin Thin QFN Package (7mm ✕7mm)
♦Evaluation Kit Available (Order MAX5865EVKIT)
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
________________________________________________________________ Maxim Integrated Products 1
ADC
IA+
IA-
QA+
QA-
ID+
ID-
QD+
QD-
REFP
COM
REFN
DIN
SCLK
CS
REFIN
DAC
DAC
ADC
OUTPUT
MUX
DAC
INPUT
MUX
CLK
DA0–DA7
DD0–DD9
MAX5866
REF
AND
BIAS
SERIAL
INTERFACE
AND SYSTEM
CONTROL
ADC
Functional Diagram
19-3223; Rev 0; 2/04
EVALUATION KIT
AVAILABLE
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX5866ETM
-40°C to +85°C48 Thin QFN-EP*
(7mm x 7mm)
*EP = Exposed paddle.
Pin Configuration appears at end of data sheet.
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND, OVDD to OGND................................-0.3V to +3.4V
GND to OGND.......................................................-0.3V to +0.3V
IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN,
REFIN, COM to GND..............................-0.3V to (VDD + 0.3V)
DD0–DD9, SCLK, DIN, CS, CLK,
DA0–DA7 to OGND .............................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN (derate 26.3mW/°C above
+70°C)..............................................................................2.1W
Thermal Resistance θJA.................................................+38°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input ampli-
tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF,
Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
UNITS
POWER REQUIREMENTS
Analog Supply Voltage VDD 2.7 3.0 3.3 V
Output Supply Voltage OVDD 2.7
VDD
V
AD C op er ati ng m od e, fIN
= 25M H z, fC LK =
60M H z, D AC op er ati ng m od e, fOU T
= 6M H z32 38
ADC operating mode (Rx), fIN = 25MHz,
fCLK = 60M H z, DAC digital inputs at zero or
OVD D
26.6
DAC operating mode (Tx), fOUT = 6MHz,
fCLK = 60M H z, ADC off
17.5
Standby mode, DAC digital inputs and CLK
at zero or OVDD 2.0
Idle mode, DAC digital inputs at zero or
OVDD, fCLK = 60M H z
14.5
mA
VDD Supply Current
Shutdown mode, digital inputs and CLK at
zero or OVDD, CS = OVDD 1µA
ADC operating mode, fIN = 25MHz, fCLK =
60MHz, DAC operating mode, fOUT = 6MHz
9.9 mA
Idle mode, DAC digital inputs at zero or
OVDD, fCLK = 60M H z
108.4
OVDD Supply Current
Shutdown mode, DAC digital inputs and
CLK at zero or OVDD, CS = OVDD 1
µA
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input ampli-
tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF,
Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
ADC DC ACCURACY
Resolution 8Bits
Integral Nonlinearity INL
±0.36
LSB
Differential Nonlinearity DNL No missing codes over temperature
±0.2
LSB
Offset Error Residual DC offset error
±0.86
±6
%FS
Gain Error Includes reference error
±0.67
±5
%FS
DC Gain Matching
±0.03 ±0.25
dB
Offset Matching ±3LSB
Gain Temperature Coefficient
±42
ppm/°C
Offset error (VDD ±5%)
±0.48
Power-Supply Rejection PSRR Gain error (VDD ±5%)
±0.07
LSB
ADC ANALOG INPUT
Input Differential Range VID Differential or single-ended inputs
±0.512
V
Input Common-Mode Voltage
Range
VDD / 2
V
RIN Switched capacitor load 90 kΩ
Input Impedance CIN 5pF
ADC CONVERSION RATE
Maximum Clock Frequency fCLK (Note 2) 60
MHz
Channel I 5
Data Latency Channel Q 5.5
Clock
cycles
ADC DYNAMIC CHARACTERISTICS (Note 3)
fIN = 10MHz
48.4
Signal-to-Noise Ratio SNR fIN = 25MHz 47
48.1
dB
fIN = 10MHz
48.3
Signal-to-Noise and Distortion
Ratio SINAD fIN = 25MHz
46.5
48 dB
fIN = 10MHz
71.7
Spurious-Free Dynamic Range SFDR fIN = 25MHz
55.5 70.6
dBc
fIN = 10MHz
-73.7
Third-Harmonic Distortion HD3 fIN = 25MHz
-69.9
dBc
Intermodulation Distortion IMD f1 = 5.1MHz, -7dBFS; f2 = 5.2MHz, -7dBFS
-68.5
dBc
Third-Order Intermodulation
Distortion IM3 f1 = 5.1MHz, -7dBFS; f2 = 5.2MHz, -7dBFS
-72.4
dBc
fIN = 10MHz
-71.2
Total Harmonic Distortion THD fIN = 25MHz
-68.6
-55 dBc
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input ampli-
tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF,
Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Full-Power Bandwidth FBW AIN = -0.5dBFS
150
MHz
Aperture Delay 3.3 ns
Aperture Jitter 3.3
psRMS
Overdrive Recovery Time 1.5 x full-scale input 2 ns
ADC INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection fINX = 5.5MHz at -0.5dBFS, fINY = 0.9MHz at
-0.5dBFS (Note 5)
-73
dB
Amplitude Matching fIN = 5.5MHz at -0.5dBFS (Note 6)
±0.05
dB
Phase Matching fIN = 5.5MHz at -0.5dBFS (Note 6)
±0.2
D eg r ees
DAC DC ACCURACY
Resolution N 10 Bits
Integral Nonlinearity INL
±0.3
LSB
Differential Nonlinearity DNL Guaranteed monotonic
±0.2
LSB
Zero-Scale Error Residual DC offset ±3LSB
Full-Scale Error Include reference error -35
+35
LSB
DAC DYNAMIC PERFORMANCE
DAC Conversion Rate (Note 2) 60
Msps
Noise over Nyquist NDfOUT = 6MHz, fCLK = 60MHz
-130.8
dBc/Hz
Glitch Impulse 10 pVs
fCLK = 45MHz, fOUT = 2.2MHz
69.5
Spurious-Free Dynamic Range SFDR fCLK = 60MHz, fOUT = 6MHz
58.5 64.2
dBc
Total Harmonic Distortion
(to Nyquist) THD fCLK = 60MHz, fOUT = 6MHz
-60.6
-56 dB
Signal-to-Noise Ratio
(to Nyquist) SNR fCLK = 60MHz, fOUT = 6MHz 56 dB
DAC INTERCHANNEL CHARACTERISTICS
DAC-to-DAC Output Isolation fOUTX, Y = 6.0MHz, fOUTX, Y = 6.2MHz 70 dB
Gain Mismatch Between DAC
Outputs fOUT = 2.2MHz, fCLK = 60MHz
±0.1
dB
Phase Mismatch Between DAC
Outputs fOUT = 2.2MHz, fCLK = 60MHz
±0.4
D eg r ees
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input ampli-
tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF,
Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC ANALOG OUTPUT
Full-Scale Output Voltage VFS
±400
mV
Output Common-Mode Range
1.29 1. 5
V
ADC-DAC INTERCHANNEL CHARACTERISTICS
ADC-DAC Isolation ADC fINI = fINQ = 25MHz, DAC fOUTI =
fOUTQ = 6MHz, fCLK = 60MHz 70 dB
ADC-DAC TIMING CHARACTERISTICS
CLK Rise to I-ADC Channel-I
Output Data Valid tDOI Figure 3 (Note 4) 3 4.9 8.5 ns
CLK Fall to Q-ADC Channel-Q
Output Data Valid tDOQ Figure 3 (Note 4) 3 6.2 8.5 ns
I-DAC Data to CLK Fall Setup
Time tDSI Figure 4 (Note 4) 9 ns
Q-DAC Data to CLK Rise Setup
Time tDSQ Figure 4 (Note 4) 9 ns
CLK Fall to I-DAC Data Hold Time
tDHI Figure 4 (Note 4) -3 ns
C LK Ri se to Q- D AC D ata H ol d Ti m e
tDHQ Figure 4 (Note 4) -3 ns
Clock Duty Cycle 50 %
CLK Duty-Cycle Variation
±10
%
Digital Output Rise/Fall Time 20% to 80% 2.0 ns
SERIAL INTERFACE TIMING CHARACTERISTICS
Falling Edge of CS to Rising Edge
of First SCLK Time tCSS Figure 5 (Note 4) 10 ns
DIN to SCLK Setup Time tDS Figure 5 (Note 4) 10 ns
DIN to SCLK Hold Time tDH Figure 5 (Note 4) 0 ns
SCLK Pulse-Width High tCH Figure 5 (Note 4) 25 ns
SCLK Pulse-Width Low tCL Figure 5 (Note 4) 25 ns
SCLK Period tCP Figure 5 (Note 4) 50 ns
SCLK to CS Setup Time tCS Figure 5 (Note 4) 0 ns
CS High Pulse Width tCSW Figure 5 (Note 4) 80 ns
MODE RECOVERY TIMING CHARACTERISTICS
From shutdown to Rx mode, Figure 6, ADC
settles to within 1dB 10
Shutdown Wake-Up Time
tWAKE
,
SD
From shutdown to Tx mode, Figure 6, DAC
settles to within 10 LSB error 40
µs
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
6_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input ampli-
tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF,
Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
From idle to Rx mode with CLK present
during idle, Figure 6, ADC settles to within
1dB SINAD
10
Idle Wake-Up Time (with CLK)
tWAKE
,
ST0
From idle to Tx mode with CLK present
during idle, Figure 6, DAC settles to 10 LSB
error
10
µs
From standby to Rx mode, Figure 6, ADC
settles to within 1dB SINAD 10
Standby Wake-Up Time
tWAKE
,
ST1
From standby to Tx mode, Figure 6, DAC
settles to 10 LSB error 40
µs
Enable Time from Xcvr or Tx to Rx tENABLE
,
Rx
ADC settles to within 1dB SINAD 10 µs
Enable Time from Xcvr or Rx to Tx tENABLE
,
Tx
DAC settles to 10 LSB error 10 µs
INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, and VCOM are generated internally.)
Positive Reference VREFP - VCOM
0.256
V
Negative Reference VREFN - VCOM
-0.256
V
Common-Mode Output Voltage VCOM VDD / 2
- 0.15 VDD / 2
VDD / 2
+ 0.15
V
Differential Reference Output VREF VREFP - VREFN
+0.49 +0.512 +0.534
V
Differential Reference
Temperature Coefficient REFTC
±16
ppm/°C
Maximum REFP/REFN/COM
Source Current
ISOURCE
2mA
Maximum REFP/REFN/COM
Sink Current ISINK 2mA
BUFFERED EXTERNAL REFERENCE (REFIN = 1.024V; VREFP, VREFN, and VCOM are generated internally.)
Reference Input VREFIN
1.024
V
Differential Reference Output VDIFF VREFP - VREFN
0.512
V
Common-Mode Output Voltage VCOM
VDD / 2
V
Maximum REFP/REFN/COM
Source Current ISOURCE 2mA
Maximum REFP/REFN/COM
Sink Current ISINK 2mA
REFIN Input Resistance
>500
kΩ
REFIN Input Current
-0.7
µA
DIGITAL INPUTS (CLK, SCLK, DIN, CS, DD0–DD9)
Input High Threshold VINH DD0–DD9, CLK, SCLK, DIN, CS 0.7 x
OVDD
V
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz, 50% duty cycle, ADC input ampli-
tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF,
Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input Low Threshold VINL DD0–DD9, CLK, SCLK, DIN, CS 0.3 x
OVDD
V
Input Leakage DIIN DD0–DD9, CLK, SCLK, DIN, CS = OGND or
OVDD ±5µA
Input Capacitance DCIN 5pF
DIGITAL OUTPUTS (DA0–DA7)
Output Voltage Low VOL ISINK = 200µA 0.2 x
OVDD
V
Output Voltage High VOH ISOURCE = 200µA 0.8 x
OVDD
V
Tri-State Leakage Current ILEAK ±5µA
Tri-State Output Capacitance COUT 5pF
Note 1: Specifications from TA= +25°C to +85°C are guaranteed by production tests. Specifications from TA= +25°C to -40°C are
guaranteed by design and characterization.
Note 2: The minimum clock frequency for the MAX5866 is 40MHz.
Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 4: Guaranteed by design and characterization.
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-
ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tone bins.
Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
Typical Operating Characteristics
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM =
0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
-110
-70
-90
-30
-50
-10
-80
-100
-40
-60
-20
0
051015 20 25 30
ADC CHANNEL-IA FFT PLOT
MAX5866 toc01
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 60MHz
fIA = 12.499MHz
fQA = 19.99MHz
IA
QA HD3 HD2
-110
-70
-90
-30
-50
-10
-80
-100
-40
-60
-20
0
ADC CHANNEL-QA FFT PLOT
MAX5866 toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)
051015 20 25 30
fCLK = 60MHz
fIA = 12.499MHz
fQA = 19.99MHz
HD3 HD2
IA
QA
-110
-70
-90
-30
-50
-10
-80
-100
-40
-60
-20
0
ADC CHANNEL-IA TWO-TONE FFT PLOT
MAX5866 toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)
051015 20 25 30
fCLK = 60MHz
f1 = 11.813MHz
f2 = 12.795MHz
AIA = -7dBFS PER TONE
f1f2
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
8_______________________________________________________________________________________
-80
-75
-70
-65
-60
-55
-50
-45
-40
0255075100 125
ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX5866 toc07
ANALOG INPUT FREQUENCY (MHz)
THD (dB)
50
55
60
65
70
75
80
0255075100125
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX5866 toc08
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
40
45
50
55
65
60
75
70
80
0255075100 125
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX5866 toc09
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
SINGLE ENDED
0
10
20
30
50
40
60
-24 -20 -16 -12 -8 -4 0
ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
MAX5866 toc10
ANALOG INPUT POWER (dBFS)
SNR (dB)
fIN = 10.0732MHz
0
10
20
30
50
40
60
-24 -20 -16 -12 -8 -4 0
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO
vs. ANALOG INPUT POWER
MAX5866 toc11
ANALOG INPUT POWER (dBFS)
SINAD (dB)
fIN = 10.0732MHz
-80
-75
-70
-65
-35
-40
-45
-55
-60
-50
-30
-24 -20 -16 -12 -8 -4 0
ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
MAX5866 toc12
ANALOG INPUT POWER (dBFS)
THD (dB)
fIN = 10.0732MHz
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM =
0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
-110
-70
-90
-30
-50
-10
-80
-100
-40
-60
-20
0
ADC CHANNEL-QA TWO-TONE FFT PLOT
MAX5866 toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
05101520 25 30
fCLK = 60MHz
f1 = 11.813MHz
f2 = 12.795MHz
AQA = -7dBFS PER TONE
f2
f1
46.0
46.5
47.0
47.5
48.0
48.5
49.0
49.5
50.0
0255075100125
ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
MAX5866 toc05
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
46.0
46.5
47.0
47.5
48.0
48.5
49.0
49.5
50.0
0255075100 125
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO
vs. ANALOG INPUT FREQUENCY
MAX5866 toc06
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
_______________________________________________________________________________________ 9
-80
-75
-70
-55
-60
-65
-50
ADC TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
MAX5866 toc16
SAMPLING RATE (MHz)
THD (dB)
fIN = 10.7MHz
40 42 46 5044 48 52 54 56 58 60
50
55
60
75
70
65
80
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
MAX5866 toc17
SAMPLING RATE (MHz)
SFDR (dBc)
fIN = 10.7MHz
40 42 46 5044 48 52 54 56 58 60
ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
MAX5866 toc18
CLOCK DUTY CYCLE (%)
SNR (dB)
55 60
45 5040
46
47
48
49
50
45
fIN = 25MHz
ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLE
MAX5866 toc19
CLOCK DUTY CYCLE (%)
SINAD (dB)
55 6050
45
40
46
47
48
49
50
45
fIN = 25MHz
-55
-65
-70
-60
-75
-50
40 45 50 55 60
ADC TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
MAX5866 toc20
CLOCK DUTY CYCLE (%)
THD (dB)
fIN = 25MHz
50
55
65
75
60
70
80
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
MAX5866 toc21
CLOCK DUTY CYCLE (%)
SFDR (dBc)
40 45 50 55 60
fIN = 25MHz
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM =
0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
30
35
40
45
75
70
65
55
50
60
80
-24 -20 -16 -12 -8 -4 0
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
MAX5866 toc13
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
fIN = 10.0732MHz
44
45
46
49
48
47
50
40 42 46 5044 48 52 54 56 58 60
ADC SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
MAX5866 toc14
SAMPLING RATE (MHz)
SNR (dB)
fIN = 10.7MHz
45
46
47
49
48
50
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO
vs. SAMPLING RATE
MAX5866 toc15
SAMPLING RATE (MHz)
SINAD (dB)
fIN = 10.7MHz
40 42 46 5044 48 52 54 56 58 60
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
10 ______________________________________________________________________________________
DAC SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
MAX5866 toc25
SAMPLING RATE (MHz)
SFDR (dBc)
565450 5244 46 4842
61
62
63
64
65
66
67
68
69
70
60
40 6058
fOUT = fCLK/10
DAC SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
MAX5866 toc26
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
6842
55
60
65
70
75
80
50
010
DAC SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT POWER
MAX5866 toc27
OUTPUT POWER (dBFS)
SFDR (dBc)
-5-10-15-20-25
40
50
60
70
80
90
30
-30 0
fOUT = 6MHz
DAC CHANNEL-ID SPECTRAL PLOT
MAX5866 toc28
FREQUENCY (MHz)
AMPLITUDE (dB)
15 20 3025105
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0
fID = 6MHz
DAC CHANNEL-QD SPECTRAL PLOT
MAX5866 toc29
FREQUENCY (MHz)
AMPLITUDE (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
15 20 30251050
fQD = 6MHz
DAC CHANNEL-ID TWO-TONE
SPECTRAL PLOT
MAX5866 toc30
FREQUENCY (MHz)
AMPLITUDE (dB)
27.523.018.514.09.55.0
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0.5
f1 = 4MHz, f2 = 4.5MHz, -7dBFS
f1f2
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM =
0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
-3.0
-2.5
-0.5
1.5
-1.5
0.5
-1.0
1.0
-2.0
0
2.0
-40 -15 3510 60 85
ADC OFFSET ERROR
vs. TEMPERATURE
MAX5866 toc22
TEMPERATURE (°C)
OFFSET ERROR (%FS)
-1.0
-0.8
0
0.8
-0.4
0.4
-0.2
0.6
-0.6
0.2
1.0
-40 -15 3510 60 85
ADC GAIN ERROR
vs. TEMPERATURE
MAX5866 toc23
TEMPERATURE (°C)
GAIN ERROR (%FS)
0
10
20
IDD
IOVDD
5
15
25
30
40 44 5248 56 60
SUPPLY CURRENT
vs. SAMPLING RATE
MAX5866 toc24
SAMPLING RATE (MHz)
SUPPLY CURRENT (mA)
Rx MODE ONLY
fIN = 10MHz
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
______________________________________________________________________________________ 11
ADC INTEGRAL NONLINEARITY
MAX5866 toc34
DIGITAL OUTPUT CODE
INL (LSB)
224192128 16064 9632
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0256
ADC DIFFERENTIAL NONLINEARITY
MAX5866 toc35
DIGITAL OUTPUT CODE
DNL (LSB)
224192128 16064 9632
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0256
DAC INTEGRAL NONLINEARITY
MAX5866 toc36
DIGITAL INPUT CODE
INL (LSB)
896768512 640256 384128
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
01024
DAC DIFFERENTIAL NONLINEARITY
MAX5866 toc37
DIGITAL INPUT CODE
DNL (LSB)
896768512 640256 384128
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
01024
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX5866 toc38
TEMPERATURE (°C)
VREFP - VREFN (V)
603510-15
0.505
0.510
0.515
0.520
0.500
-40 85
VREFP - VREFN
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 3.0V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK = 60MHz 50% duty cycle, ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM =
0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
DAC CHANNEL-QD TWO-TONE
SPECTRAL PLOT
MAX5866 toc31
FREQUENCY (MHz)
AMPLITUDE (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
27.523.018.514.09.55.00.5
f1 = 4MHz, f2 = 4.5MHz, -7dBFS
f1f2
SUPPLY CURRENT
vs. SAMPLING RATE
MAX5866 toc33
SAMPLING RATE (MHz)
SUPPLY CURRENT (mA)
5654525048464442
5
10
15
20
25
30
0
40 58 60
Xcvr MODE
IOVDD
IDD
fIN = 10MHz
fOUT = 6MHz
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
12 ______________________________________________________________________________________
PIN NAME FUNCTION
1REFP Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible.
2, 8, 11,
33, 39, 43 VDD Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a
0.1µF capacitor.
3IA+ Channel IA Positive Analog Input. For single-ended operation, connect signal source to IA+.
4IA- Channel IA Negative Analog Input. For single-ended operation, connect IA- to COM.
5, 7, 12, 37,
42 GND Analog Ground. Connect all pins to GND ground plane.
6CLK Conversion Clock Input. Clock signal for both ADCs and DACs.
9QA- Channel QA Negative Analog Input. For single-ended operation, connect QA- to COM.
10 QA+ Channel QA Positive Analog Input. For single-ended operation, connect signal source to QA+.
13–16, 19–22
DA0–DA7
ADC Tri-State Digital Output Bits. DA7 is the most significant bit (MSB), and DA0 is the least
significant bit (LSB).
17 OGND Output Driver Ground
18 OVDD Output Driver Power Supply. Supply range from +2.7V to VDD to accommodate most logic levels.
Bypass OVDD to OGND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
23–32
DD0–DD9
DAC Digital Input Bits. DD9 is the MSB, and DD0 is the LSB.
34 DIN 3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK.
35 SCLK 3-Wire Serial-Interface Clock Input
36 CS 3-Wire Serial-Interface Chip-Select Input. Apply logic low to enable the serial interface.
38 N.C. No Connection
40, 41
QD+, QD-
DAC Channel-QD Differential Voltage Output
44, 45 ID-, ID+ DAC Channel-ID Differential Voltage Output
46 REFIN Reference Input. Connect to VDD for internal reference.
47 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
48 REFN Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF
capacitor.
—EPExposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
Pin Description
Detailed Description
The MAX5866 integrates dual 8-bit receive ADCs and
dual 10-bit transmit DACs while providing ultra-low
power and highest dynamic performance at a conver-
sion rate of 60Msps. The ADCs’ analog input amplifiers
are fully differential and accept 1VP-P full-scale signals.
The DACs’ analog outputs are fully differential with
±400mV full-scale output range at 1.4V common mode.
The MAX5866 includes a 3-wire serial interface to con-
trol operating modes and power management. The ser-
ial interface is SPI™ and MICROWIRE™ compatible.
The MAX5866 serial interface selects shutdown, idle,
standby, transmit, receive, and transceiver modes.
The MAX5866 can operate in FDD or TDD applications
by configuring the device for transmit, receive, or trans-
ceiver modes through a 3-wire serial interface. In TDD
mode, the digital bus for receive ADC and transmit
DAC can be shared to reduce the digital I/O to a single
10-bit parallel multiplexed bus. In FDD mode, the
MAX5866 digital I/O can be configured for an 18-bit,
parallel multiplexed bus to match the dual 8-bit ADC
and dual 10-bit DAC.
The MAX5866 features an internal precision 1.024V
bandgap reference that is stable over the entire power-
supply and temperature ranges.
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
______________________________________________________________________________________ 13
SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
Figure 1. MAX5866 ADC Internal T/H Circuits
S3b
S3a
COM
S5b
S5a
QA+
QA-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLD HOLD CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACK TRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
IA+
IA-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX5866
MAX5866
Dual 8-Bit ADC
The ADC uses a seven-stage, fully differential,
pipelined architecture that allows for high-speed con-
version while minimizing power consumption. Samples
taken at the inputs move progressively through the
pipeline stages every half clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is 5 clock cycles for channel IA and 5.5 clock
cycles for channel QA. The ADC’s full-scale analog
input range is ±VREF with a common-mode input range
of VDD / 2 ±0.2V. VREF is the difference between VREFP
and VREFN. See the Reference Configurations section
for details.
Input Track-and-Hold (T/H) Circuits
Figure 1 displays a simplified functional diagram of the
ADC’s input T/H circuitry. In track mode, switches S1,
S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully
differential circuits sample the input signals onto the
two capacitors (C2a and C2b) through switches S4a
and S4b. S2a and S2b set the common mode for the
amplifier input, and open simultaneously with S1, sam-
pling the input waveform. Switches S4a, S4b, S5a, and
S5b are then opened before switches S3a and S3b
connect capacitors C1a and C1b to the output of the
amplifier and switch S4c is closed. The resulting differ-
ential voltages are held on capacitors C2a and C2b.
The amplifiers charge capacitors C1a and C1b to the
same values originally held on C2a and C2b. These val-
ues are then presented to the first-stage quantizers and
isolate the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the ADC to
track and sample/hold analog inputs of high frequen-
cies (> Nyquist). Both ADC inputs (IA+, QA+, IA-, and
QA-) can be driven either differentially or single ended.
Match the impedance of IA+ and IA-, as well as QA+
and QA-, and set the common-mode voltage to mid-
supply (VDD / 2) for optimum performance.
ADC Digital Output Data (DA0–DA7)
DA0–DA7 are the ADCs’ digital logic outputs. The logic
level is set by OVDD from +2.7V to VDD. The digital out-
put coding is offset binary (Table 1, Figure 2). The
capacitive load on digital outputs DA0–DA7 should be
kept as low as possible (<15pF) to avoid large digital
currents feeding back into the analog portion of the
MAX5866 and degrading its dynamic performance.
Buffers on the digital outputs isolate them from heavy
capacitive loads. Adding 100Ωresistors in series with
the digital outputs close to the MAX5866 helps improve
ADC performance. Refer to the MAX5865 EV kit
schematic for an example of the digital outputs driving
a digital buffer through 100Ωseries resistors.
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
14 ______________________________________________________________________________________
Table 1. Output Codes vs. Input Voltage
DIFFERENTIAL
INPUT VOLTAGE DIFFERENTIAL INPUT
(LSB) OFFSET BINARY
(DA7–DA0) OUTPUT DECIMAL
CODE
127
(+full scale - 1LSB) 1111 1111 255
126
(+full scale - 2LSB) 1111 1110 254
+1 1000 0001 129
0
(bipolar zero) 1000 0000 128
-1 0111 1111 127
-127
(-full scale + 1LSB) 0000 0001 1
-128
(-full scale) 0000 0000 0
VREF 127
128
×
VREF 126
128
×
VREF 1
128
×
VREF 0
128
×
VREF 1
128
×
−
VREF 127
128
×
−
VREF 128
128
×
−
ADC System Timing Requirements
Figure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel IA
(CHI) and channel QA (CHQ) are simultaneously sam-
pled on the rising edge of the clock signal (CLK) and
the resulting data is multiplexed at the DA0–DA7 out-
puts. CHI data is updated on the rising edge and CHQ
data is updated on the falling edge of the CLK.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for CHI and 5.5
clock cycles for CHQ.
Dual 10-Bit DAC
The 10-bit DACs are capable of operating with clock
speeds up to 60MHz. The DAC’s digital inputs, DD0–DD9,
are multiplexed on a single 10-bit bus. The voltage refer-
ence determines the data converters’ full-scale output
voltages. See the Reference Configurations section for
setting reference voltage. The DACs utilize a current-array
technique with a 1mA (with 1.024V reference) full-scale
output current driving a 400Ωinternal resistor resulting in
a ±400mV full-scale differential output voltage. The
MAX5866 is designed for differential output only and is
not intended for single-ended application. The analog
outputs are biased at 1.4V common mode and designed
to drive a differential input stage with input impedance
≥70kΩ. This simplifies the analog interface between RF
quadrature upconverters and the MAX5866. RF upcon-
verters require a 1.3V to 1.5V common-mode bias. The
internal DC common-mode bias eliminates discrete level-
setting resistors and code-generated level-shifting while
preserving the full dynamic range of each transmit DAC.
Table 2 shows the output voltage vs. input code.
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
______________________________________________________________________________________ 15
Figure 2. ADC Transfer Function
INPUT VOLTAGE (LSB)
-1-126 -125
256
2 x VREF
1 LSB = VREF = VREFP - VREFN
VREF VREF
VREF
VREF
0+1-127 +126 +128+127-128 +125
(COM)
(COM)
OFFSET BINARY OUTPUT CODE (LSB)
0000 0000
0000 0001
0000 0010
0000 0011
1111 1111
1111 1110
1111 1101
0111 1111
1000 0000
1000 0001
Figure 3. ADC System Timing Diagram
tDOQ tDOI
5 CLOCK-CYCLE LATENCY (CHI), 5.5 CLOCK-CYCLE LATENCY (CHQ)
DA0–DA7 D0Q D1I D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q
CHI
CHQ
CLK
MAX5866
DAC Timing
Figure 4 shows the relationship between the clock, input
data, and analog outputs. Data for the I channel is
latched on the falling edge of the clock signal, and Q-
channel data is latched on the rising edge of the clock
signal. Both I and Q outputs are simultaneously updated
on the next rising edge of the clock signal.
3-Wire Serial Interface and
Operation Modes
The 3-wire serial interface controls the MAX5866 opera-
tion modes. Upon power-up, the MAX5866 must be pro-
grammed to operate in the desired mode. Use the 3-wire
serial interface to program the device for the shutdown,
idle, standby, Rx, Tx, or Xcvr mode. An 8-bit data register
sets the operation modes as shown in Table 3. The serial
interface remains active in all six modes.
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
16 ______________________________________________________________________________________
Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC =
1.024V, External Reference Mode VREFDAC = VREFIN)
DIFFERENTIAL OUTPUT VOLTAGE OFFSET BINARY
(DD0–DD9) INPUT DECIMAL CODE
11 1111 1111 1023
11 1111 1110 1022
10 0000 0001 513
10 0000 0000 512
01 1111 1111 511
00 0000 0001 1
00 0000 0000 0
VREFDAC
2.56
1023
1023
×
VREFDAC
2.56
1021
1023
×
VREFDAC
2.56
3
1023
×
VREFDAC
2.56
1
1023
×
VREFDAC
2.56
1
1023
×
−
VREFDAC
2.56
1021
1023
×
−
VREFDAC
2.56
1023
1023
×
−
Figure 4. DAC System Timing Diagram
tDSQ
tDSI
Q: N - 2 I: N - 1
DD0–DD9
CLK
ID
QD
Q: N - 1 I: N Q: N I: N + 1
N - 2 N - 1 N
N - 2 N - 1 N
tDHQ
tDHI
Shutdown mode offers the most dramatic power sav-
ings by shutting down all the analog sections of the
MAX5866 and placing the ADCs’ digital outputs in tri-
state mode. When the ADCs’ outputs transition from tri-
state to on, the last converted word is placed on the
digital outputs. The DACs’ digital bus inputs must be
zero or OVDD because the bus is not internally pulled
up. The DACs’ previously stored data is lost when com-
ing out of shutdown mode. The wake-up time from shut-
down mode is dominated by the time required to
charge the capacitors at REFP, REFN, and COM. In
internal reference mode and buffered external refer-
ence mode, the wake-up time is typically 40µs to enter
Xcvr mode, 10µs to enter Rx mode, and 40µs to enter
Tx MODE.
In idle mode, the reference and clock distribution cir-
cuits are powered, but all other functions are off. The
ADCs’ outputs are forced to tri-state. The DACs’ digital
bus inputs must be zero or OVDD, because the bus is
not internally pulled up. The wake-up time required for
the device to become fully operational from idle mode
is 10µs. When the ADCs’ outputs transition from tri-state
to on, the last converted word is placed on the digital
outputs. In the idle mode, the supply current is lowered
if the clock input is set to zero or OVDD; however, the
wake-up time extends to 40µs.
In standby mode, only the ADCs’ reference is powered;
the rest of the device’s functions are off. The pipeline
ADCs are off and DA0 to DA7 are in tri-state mode. The
DACs’ digital bus inputs must be zero or OVDD
because the bus is not internally pulled up. The wake-
up time from standby mode to the Xcvr mode is domi-
nated by the 40µs required to activate the pipeline
ADCs and DACs. When the ADC outputs transition from
tri-state to active, the last converted word is placed on
the digital outputs.
The serial digital interface is a standard 3-wire connec-
tion compatible with SPI/QSPI™/MICROWIRE/DSP
interfaces. Set CS low to enable the serial data loading
at DIN. Following the CS high-to-low transition, data is
shifted synchronously, MSB first, on the rising edge of
the serial clock (SCLK). After 8 bits are loaded into the
serial input register, data is transferred to the latch. CS
must transition high for a minimum of 80ns before the
next write sequence. The SCLK can idle either high or
low between transitions. Figure 5 shows the detailed
timing diagram of the 3-wire serial interface.
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
______________________________________________________________________________________ 17
QSPI is a trademark of Motorola, Inc.
Table 3. MAX5866 Operation Modes
FUNCTION DESCRIPTION D7
(
MSB
)
D6 D5 D4 D3 D2 D1 D0
Shutdown
D evi ce shutd ow n. RE F i s off, AD C s ar e
off, and the AD C b us i s tr i - stated ; D AC s
ar e off and the D AC i np ut b us m ust b e
set to zer o or OV
D D
.
XXXXX000
Idle
REF and CLK are on, ADCs are off,
and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
set to zero or OVDD.
XXXXX001
Rx
REF is on, ADCs are on; DACs are off,
and the DAC input bus must be set to
zero or OVDD.
XXXXX010
Tx REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are on. XXXXX011
Xcvr REF is on, ADCs and DACs are on. X X X X X 1 0 0
Standby
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are off and the
DAC input bus must be set to zero or
OVDD.
XXXXX101
X= Don’t care.
MAX5866
Mode Recovery Timing
Figure 6 shows the mode recovery timing diagram.
tWAKE is the wake-up time when exiting shutdown, idle,
or standby mode and entering into Rx, Tx, or Xcvr
mode. tENABLE is the recovery time when switching
between any Rx, Tx, or Xcvr mode. tWAKE or tENABLE is
the time for the ADC to settle within 1dB of specified
SINAD performance and DAC settling to 10 LSB error.
tWAKE or tENABLE times are measured after the 8-bit
serial command is latched into the MAX5866 by CS
transitioning high. tENABLE for Xcvr mode is dominated
by the DAC wake-up time. The recovery time is 10µs to
switch between Xcvr, Tx, or Rx modes. The recovery
time is 40µs to switch from shutdown or standby mode
to Xcvr mode.
System Clock Input (CLK)
CLK input is shared by both the ADCs and DACs. It
accepts a CMOS-compatible signal level set by OVDD
from +2.7V to VDD. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (<2ns). Specifically,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide the lowest possible jitter.
Any significant clock jitter limits the SNR performance
of the on-chip ADCs as follows:
where fIN represents the analog input frequency and
tAJ is the time of the clock jitter.
SNR tt
IN AJ
=× ×× ×
20 1
2
log π
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
18 ______________________________________________________________________________________
Figure 5. 3-Wire Serial Interface Timing Diagram
MSB
CS
SCLK
DIN LSB
tCSW
tCS
tCP
tCSS tCL
tCH
tDS
tDH
Figure 6. MAX5866 Mode Recovery Timing Diagram
CS
SCLK
DIN
ID/QD
DAO–DA7
8-BIT DATA
ADC DIGITAL OUTPUT.
SINAD SETTLES WITHIN 1dB
DAC ANALOG OUTPUT. OUTPUT
SETTLES TO 10 LSB ERROR
tWAKE, SD, ST_ (Rx) OR tENABLE, Rx
tWAKE, SD, ST_ (Tx) OR tENABLE TX
Clock jitter is especially critical for undersampling
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX5866 clock input operates
with an OVDD / 2 voltage threshold and accepts a 50%
±10% duty cycle.
Reference Configurations
The MAX5866 features an internal precision 1.024V
bandgap reference that is stable over the entire power-
supply and temperature range. The REFIN input pro-
vides two modes of reference operation. The voltage at
REFIN (VREFIN) sets reference operation mode (Table 4).
In internal reference mode, connect REFIN to VDD. VREF
is an internally generated 0.512V. COM, REFP, and REFN
are low-impedance outputs with VCOM = VDD / 2, VREFP
= VDD / 2 + VREF / 2, and VREFN = VDD / 2 - VREF / 2.
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
In buffered external reference mode, apply 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with VCOM = VDD / 2,
VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 -
VREFIN / 4. Bypass REFP, REFN, and COM each with a
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF
capacitor. In this mode, the DAC’s full-scale output volt-
age and common-mode voltage are proportional to the
external reference. For example, if the VREFIN is
increased by 10% (max), the DACs’ full-scale output
voltage is also increased by 10% or to ±440mV, and
the common-mode voltage increases by 10%.
Applications Information
Using Balun Transformer AC-Coupling
An RF transformer (Figure 7) provides an excellent
solution to convert a single-ended signal source to a
fully differential signal for optimum ADC performance.
Connecting the center tap of the transformer to COM
provides a VDD / 2 DC level shift to the input. A 1:1
transformer can be used, or a step-up transformer can
be selected to reduce the drive requirements. In gener-
al, the MAX5866 provides better SFDR and THD with
fully differential input signals than single-ended signals,
especially for high input frequencies. In differential
mode, even-order harmonics are lower as both inputs
(IA+, IA-, QA+, QA-) are balanced, and each of the
ADC inputs only requires half the signal swing com-
pared to single-ended mode. Figure 8 shows an RF
transformer converting the MAX5866 DACs’ differential
analog outputs to single ended.
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
______________________________________________________________________________________ 19
Table 4. Reference Modes
VREFIN REFERENCE MODE
>0. 8 x VDD
Internal reference mode. VREF is internally
generated to be 0.512V. Bypass REFP,
REFN, and COM each with a 0.33µF
capacitor.
1.024V ±10%
Buffered external reference mode. An
external 1.024V ±10% reference voltage
is applied to REFIN. VREF is internally
generated to be VREFIN / 2. Bypass REFP,
REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a
0.1µF capacitor.
Figure 7. Balun-Transformer-Coupled Single-Ended-to-
Differential Input Drive for ADCs
COM
IA+
IA-
25Ω
0.1µF
0.33µF
25Ω
0.1µF
VIN
MAX5866
22pF
22pF
QA+
QA-
25Ω
0.1µF
0.33µF
25Ω
0.1µF
VIN
22pF
22pF
MAX5866
Using Op-Amp Coupling
Drive the MAX5866 ADCs with op amps when a balun
transformer is not available. Figures 9 and 10 show the
ADCs being driven by op amps for AC-coupled single-
ended, and DC-coupled differential applications.
Amplifiers such as the MAX4354/MAX4454 provide
high speed, high bandwidth, low noise, and low distor-
tion to maintain the input-signal integrity. Figure 10 can
also be used to interface with the DAC differential ana-
log outputs to provide gain or buffering. The DAC dif-
ferential analog outputs cannot be used in single-
ended mode because of the internally generated
1.4VDC common-mode level. Also, the DAC analog
outputs are designed to drive a differential input stage
with input impedance ≥70kΩ. If single-ended outputs
are desired, use an amplifier to provide differential-to-
single-ended conversion and select an amplifier with
proper input common-mode voltage range.
FDD and TDD Modes
The MAX5866 can be used in diverse applications oper-
ating FDD or TDD modes. The MAX5866 operates in Xcvr
mode for FDD applications such as WCDMA3GPP (FDD)
and 4G technologies. Also, the MAX5866 can switch
between Tx and Rx modes for TDD applications like
TD-SCDMA, WCDMA-3GPP (TDD), IEEE 802.11a/b/g,
and IEEE 802.16.
In FDD mode, the ADC and DAC operate simultaneously.
The ADC bus and DAC bus are dedicated and must be
connected in 18-bit parallel (8-bit ADC and 10-bit DAC)
to the digital baseband processor. Select Xcvr mode
through the 3-wire serial interface and use the conversion
clock to latch data. In FDD mode, the MAX5866 uses
96mW power at fCLK = 60MHz. This is the total power of
the ADC and DAC operating simultaneously.
In TDD mode, the ADC and DAC operate independent-
ly. The ADC and DAC bus are shared and can be con-
nected together, forming a single 10-bit parallel bus to
the digital baseband processor. Using the 3-wire serial
interface, select between Rx mode to enable the ADC
and Tx mode to enable the DAC. When operating in Rx
mode, the DAC does not transmit because the core is
disabled and in Tx mode, the ADC bus is tri-state. This
eliminates any unwanted spurious emissions and pre-
vents bus contention. In TDD mode, the MAX5866 uses
80mW power in Rx mode at fCLK = 60MHz, and the
DAC uses 52.5mW in Tx mode.
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
20 ______________________________________________________________________________________
Figure 9. Single-Ended Drive for ADCs
MAX5866
0.1µF
1kΩ
1kΩ
100Ω
100Ω
CIN
22pF
CIN
22pF
INB+
INB-
COM
INA+
INA-
0.1µFRISO
50Ω
RISO
50Ω
REFP
REFN
VIN
0.1µF
1kΩ
1kΩ
100Ω
100Ω
CIN
22pF
CIN
22pF
0.1µFRISO
50Ω
RISO
50Ω
REFP
REFN
VIN
Figure 8. Balun-Transformer-Coupled Differential-to-Single-
Ended Output Drive for DACs
MAX5866
ID+
ID-
VOUT
QD+
QD-
VOUT
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
______________________________________________________________________________________________________ 21
Figure 10. ADC DC-Coupled Differential Drive
MAX5866
INA+
COM
INA-
RISO
22Ω
RISO
22Ω
R11
600Ω
R9
600Ω
R3
600Ω
R2
600Ω
R1
600Ω
R10
600Ω
R8
600Ω
R5
600Ω
R4
600Ω
R7
600Ω
R6
600Ω
CIN
5pF
CIN
5pF
Figure 11. Typical Application Circuit for TDD
ADC
ADC
DAC
DAC
ADC
OUTPUT
MUX
DAC
INPUT
MUX
CLK
10-BIT
DIGITAL BASEBAND
PROCESSOR
SERIAL BUS
MAX5866
MAX2820
T/R
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
22 ___________________________________________________________________________________________________
0
2
1
4
3
7
6
5
000 010001 011 100 101 110
AT STEP
011 (1/2 LSB )
AT STEP
001 (1/4 LSB )
111
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
Figure 12a. Integral Nonlinearity
0
2
1
4
3
6
5
000 010001 011 100 101
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
1 LSB
1 LSB
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
Figure 12b. Differential Nonlinearity
Figure 11 illustrates the MAX5866 working with the
MAX2820 in TDD mode to provide a complete 802.11b
radio front-end solution. Because the MAX5866 DAC has
full differential analog outputs with a common-mode level
of 1.4V, and the ADC has wide-input common-mode
range, it can interface directly with RF transceivers while
eliminating discrete components and amplifiers used for
level-shifting circuits. Also, the DAC’s full dynamic range
is preserved because the internally generated common-
mode level eliminates code-generated level shifting or
attenuation due to resistor level shifting. The MAX5866
ADC has 1VP-P full-scale range and accepts input com-
mon-mode levels of VDD / 2 (±200mV). These features
simplify the analog interface between RF quadrature
demodulator and ADC while eliminating discrete gain
amplifiers and level-shifting components.
Grounding, Bypassing, and
Board Layout
The MAX5866 requires high-speed board layout design
techniques. Refer to the MAX5865 EV kit data sheet for
a board layout reference. Locate all bypass capacitors
as close to the device as possible, preferably on the
same side of the board as the device, using surface-
mount devices for minimum inductance. Bypass VDD to
GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF capacitor. Bypass OVDD to OGND with a 0.1µF
ceramic capacitor in parallel with a 2.2µF capacitor.
Bypass REFP, REFN, and COM each to GND with a
0.33µF ceramic capacitor. Bypass REFIN to GND with
a 0.1µF capacitor.
Multilayer boards with separated ground and power
planes yield the highest level of signal integrity. Use a
split ground plane arranged to match the physical loca-
tion of the analog ground (GND) and the digital output
driver ground (OGND) on the device package. Connect
the MAX5866 exposed backside paddle to the GND
plane. Join the two ground planes at a single point so
the noisy digital ground currents do not interfere with
the analog ground plane. The ideal location for this
connection can be determined experimentally at a
point along the gap between the two ground planes.
Make this connection with a low-value, surface-mount
resistor (1Ωto 5Ω), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy digital system’s ground plane (e.g.,
downstream output buffer or DSP ground plane).
Route high-speed digital signal traces away from sensi-
tive analog traces. Make sure to isolate the analog
input lines to each respective converter to minimize
channel-to-channel crosstalk. Keep all signal lines short
and free of 90°turns.
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the device are measured using
the end-point method. (DAC Figure 12a).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes (ADC) and a monotonic transfer function
(ADC and DAC) (DAC Figure 12b).
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
ADC Offset Error
Ideally, the midscale transition occurs at 0.5 LSB above
midscale. The offset error is the amount of deviation
between the measured transition point and the ideal
transition point.
DAC Offset Error
Offset error (Figure 12a) is the difference between the
ideal and actual offset point. The offset point is the out-
put value when the digital input is midscale. This error
affects all codes by the same amount and usually can
be compensated by trimming.
ADC Gain Error
Ideally, the ADC full-scale transition occurs at 1.5 LSB
below full scale. The gain error is the amount of devia-
tion between the measured transition point and the
ideal transition point with the offset error removed.
ADC Dynamic Parameter Definitions
Aperture Jitter
Figure 13 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 13).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error) and results directly
from the ADC’s resolution (N bits):
SNR(max) = 6.02dB x N + 1.76dB (in dB)
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
ENOB = (SINAD - 1. 76) / 6.02
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1 is the fundamental amplitude and V2–V6are
the amplitudes of the 2nd- through 6th-order harmonics.
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 ±f2), (2 ✕f1), (2 ✕f2), (2 ✕f1 ±f2), (2 ✕f2
±f1). The individual input tone levels are at -7dBFS.
3rd-Order Intermodulation (IM3)
IM3 is the power of the worst third-order intermodula-
tion product relative to the input power of either input
tone when two tones, f1and f2, are present at the
inputs. The 3rd-order intermodulation products are (2 x
f1 ±f2), (2 ✕f2 ±f1). The individual input tone levels are
at -7dBFS.
THD (V +V +V +V +V )
V
2
23
24
25
26
2
1
=
20log
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
tAD
tAJ
TRACK TRACK
CLK
Figure 13. T/H Aperture Timing
______________________________________________________________________________________ 23
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
24 ______________________________________________________________________________________
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supply is changed ±5%.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by 3dB. Note
that the T/H performance is usually the limiting factor
for the small-signal input bandwidth.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as the full-
power bandwidth frequency.
DAC Dynamic Parameter Definitions
Total Harmonic Distortion
THD is the ratio of the RMS sum of the output harmonics
up to the Nyquist frequency divided by the fundamental:
where V1is the fundamental amplitude and V2through
Vn are the amplitudes of the 2nd through nth harmonic
up to the Nyquist frequency.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component up to the Nyquist frequency excluding DC.
THD (V +V + ...+ V )
V
2
23
2n
2
1
=
20log
Chip Information
TRANSISTOR COUNT: 16,765
PROCESS: CMOS
CS
SCLK
VDD
DD9
DD6
DD5
DD4
DD2
DD3
DD8
DD7
DIN
IA+
IA-
GND
CLK
GND
VDD
QA-
GND
QA+
VDD
VDD
REFP 1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
OGND
OVDD
DA4
DA6
DD1
DD0
DA7
DA3
DA2
DA1
DA0
COM
REFIN
ID+
ID-
VDD
GND
QD-
QD+
VDD
GND
N.C.
REFN
QFN
MAX5866
DA5
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
Pin Configuration
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
______________________________________________________________________________________ 25
32, 44, 48L QFN.EPS
PROPRIETARY INFORMATION
APPROVAL
TITLE:
DOCUMENT CONTROL NO.
21-0144
PACKAGE OUTLINE
32, 44, 48L THIN QFN, 7x7x0.8 mm
1
C
REV.
2
e
L
e
L
A1 A
A2
E/2
E
D/2
D
DETAIL A
D2/2
D2
b
L
k
E2/2
E2
(NE-1) X e
(ND-1) X e
e
C
L
C
L
C
L
C
L
k
DALLAS
SEMICONDUCTOR
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PROPRIETARY INFORMATION
DOCUMENT CONTROL NO.APPROVAL
TITLE:
C
REV.
2
2
21-0144
PACKAGE OUTLINE
32, 44, 48L THIN QFN, 7x7x0.8 mm
DALLAS
SEMICONDUCTOR