SG3524
REGU LATING PUL SE WID T H MOD UL AT O RS
COMPLETE PWM POWER CONTROL CIR-
CUITRY
UNCOMMITTED OUTPUTS FOR SINGLE-
ENDED OR PUSH PULL APPLICATI ONS
LOW STA NDB Y CURRENT 8mA TYPICAL
OPERATION UP TO 300KHz
1% MAXIMUM TEMPERATURE VARIATION
OF REFERENCE VOLT AGE
DESCRIPTION
The SG3524 incorporates on a single monolithic
chip all the function required for the construction
of regulat ing power suppies inverters or switching
regulators. They can also be used as the control
element for high power-output applications. The
SG3524 family was designed for switching regu-
lators of either polarity, transformer-coupled dc-
to-dc converters, transformerless voltage dou-
blers and polarity converter applications
employing fixed-frequency, pulse-width modula-
tion techniques. The dual alternating outputs al-
lows either single-ended or push-pull applications.
Each device includes an on-ship reference, error
amplifier, programmable oscillator, pulse-steering
flip flop, two uncommitted output transistors, a
high-gain comparator, and current-limiting and
shut-down circuitry.
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
July 2000
®
BLOCK DIAGRAM
DIP16 SO16
ORDERING NUMBERS: SG3524N (DIP16)
SG3524P (SO16)
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ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VIN Supply Voltage 40 V
ICCollector Output Current 100 mA
IRReference Output Current 50 mA
ITCurrent Through CT Terminal – 5 mA
Ptot Total Power Dissipation at Tamb = 70°C1000mW
T
stg Storage Temperature Range – 65 to 150 °C
Top Operating Ambient Temperature Range: 0 to 70 °C
THERMAL DATA
Symbol Parameter DIP16 SO16 Unit
Rth j-amb
Rth j- alum i na Thermal Resistance Junction-ambient Max.
Thermal Resistance Junction-alumina (*) Max. 80
––
50 °C/W
°C/W
(*) Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 x 20mm;
0.65mm thickness with infinite heatsink.
PIN C ONNECTION (Top view )
SG3524
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ELECTRICAL CHARACTERISTICS (unless otherwise stated, these specifications apply for Tj = 0 to
70°C, VIN = 20V, and f = 20KHz).
Symbol Parameter Test Condition Min. Typ. Max. Unit
REFERENCE SECTION
VREF Output Voltage 4.6 5 5.4 V
∆VREF Line Regulation VIN = 8 to 40V 10 30 mV
∆VREF Load Regulation IL = 0 to 20mA 20 50 mV
Ripple Rejection f = 120Hz, Tj = 25°C66dB
Short Circuit Current Limit VREF = 0, Tj = 25°C 100 mA
∆VREF/∆T Temperature Stability Over Operating Temperature range 0.3 1 %
∆VREF Long Term Stability Tj = 125°C, t = 1000Hrs 20 mV
OSCILLATOR SECTION
fMAX Maximum Frequency CT = 0.001µF, RT = 2KΩ300 KHz
Initial Accuracy RT and CT Constant 5 %
Voltage Stability VIN = 8 to 40V, Tj = 25°C1%
∆f/∆T Temperature Stability Over Operating Temperature Range 2 %
Output Amplitude Pin 3, Tj = 25°C 3.5 V
Output Pulse Width CT = 0.01µF, Tj = 25°C0.5µs
ERROR AMPLIFIER SECTION
VOS Input Offset Voltage VCM = 2.5V 2 10 mV
IbInput Bias Current 2 10 µA
GVOpen Loop Voltage Gain 60 80 dB
CMV Common Mode Voltage Tj = 25°C1.83.4V
CMR Common Mode Rejection Tj = 25°C70dB
B Small Signal Bandwidth AV = 0dB, Tj = 25°C 3 MHz
VOOutput Voltage Tj = 25°C0.53.8V
COMPARATOR SECTION
Duty-cycle % Each Output On 0 45 %
VIT Input Threshold Zero Duty-cycle 1 V
Maximum Duty-cycle 3.5 V
IbInput Bias Current 1 µA
CURRENT LIMITING SECTION
Sense Voltage Pin 9 = 2V with Error Amp. Set for
Max. Out.
Tj = 25°C
180 200 220 mV
Sense Voltage T.C. 0.2 mV/°C
CMV Common Mode Voltage –1 1
OUTPUT SECTION(each output)
Collector-emitter Voltage 40 V
Collector Leackage Curr. VCE = 40V 0.1 50 µA
Saturation Voltage IC = 50mA 1 2 V
Emitter Output Voltage VIN = 20V 17 18 V
trRise Time RC = 2KΩ, Tj = 25°C0.2µs
t
f
Fall Time RC = 2KΩ, Tj = 25°C0.1µs
I
q
(*) Total Standby Current VIN = 40V 8 10 mA
(*) Excluding oscillator charging current, error and current limit dividers, and with outputs open.
SG3524
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Figure 1: Open-loop Voltage Amplification of
Error Amplifier vs. Frequency Figure 2: Oscillator Frequency vs. Tim ing
Components.
Figure 3: Output Dead Time vs. Timing
Capacitance Value. Figure 4: Output Saturation Voltage vs. load
Current.
Figure 5: Open Loop Test Circuit.
SG3524
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PRINCIPLES OF OPERATION
The SG3524 is a fixed frequency pulse-with-
modulation voltage regulator control circuit. The
regulator operates at a frequency that is pro-
grammed by one t iming res istor (RT) and one t im-
ing capacitor (CT). RT established a constant
charging current for CT. This results in a linear
voltage ramp at CT, which is fed to the compara-
tor providing linear control of the output pulse
width by the error amplifier. the SG3524 contains,
an on-board 5V regulator that serves as a refer-
ence as well as powering the SG3524’s internal
control circ uitry and is also useful in supplying ex-
ternal support functions. This reference voltage is
lowered externally by a resistor divider to provide
a reference within the common mode range the
error amplifier or an external reference may be
used. The power supply output is sensed by a
second resistor divider network to generale a
feedback signal to error amplifier. The amplifier
output voltage is t hen compared to the linear volt-
age ramp at CT. The resulting modulated pulse
out of the high-gain comparator is then steered to
the appropr iate output pas s trans istors (QA or QB)
by the pulse-steering flip-flop, which is synchro-
nously toggled by the oscillator output. The oscil-
lator out put pulse also serves as a blanking pulse
to assure both output are never on simultane-
ously during the transition times. The wi dth of the
blanking pulse is controlled by the value of CT.
The outputs may be applied in a push-pull con-
figuration in which their frequency is half that of
the base oscillator, or paralleled for single-ended
applications in which the frequency is equal to
that of the oscillator. The output of the error am-
plifier shares a common input to the comparator
with the current limiting at shutdown circuitry and
can be overr idden by signals from either of these
inputs. T his common point is also available ex ter-
nally and may be employed to control t he gain of,
or to compensate, the error amplifier, or to pro-
vide additional control to the r egulator.
RECOMMENDE D O PERAT ING CONDIT IONS
Supply voltage VIN 8 to 40V
Reference Output Current 0 to 20mA
Current trough CT Terminal - 0.03 to -2mA
Timing Resistor, RT1.8 to 100KΩ
Timing Capacitor, CT0.001 to 0.1µF
TYPICAL APPLIC ATIONS DATA
OSCILLATOR
The oscillator controls the frequency of the
SG3524 and is programmed by RT and CT ac-
cording to the approxim ate formula:
f = 1.18
RT CT
where:
RT is in KΩ
CT is in µF
f is in KHz
Pratical values of CT fall between 0.001 and
0.1µF. Pratical values of RT fall between 1.8 and
100KΩ. This results in a f requency r ange typically
from 120Hz to to 500KH z.
BLANKING
The output pulse of oscillator is used as a blank-
ing pulse at the output. This pulse width is con-
trolled by the value of CT.I f small values of CT are
required for frequency control, the oscillator out-
put pulse width may still be incr eased by applying
a shunt capacitance of up to 100pF from pin 3 to
ground. If still greater dead-time is required, it
should be accomplished by limiting the maximum
duty cycle by clamping the out put of the error am-
plifier. This can eas ily be done with the circuit be-
low:
SYNCRONOUS OPE RATION
When an external clock is desired, a clock pulse
of approximately 3V can be applied directly to the
oscillator output terminal. The impedance to
ground at this point is approximately 2KΩ. In this
configuration RT CT must be selected for a clock
period slightly greater than that the external clock.
If two more SG2524 r egulators are to be operated
synchronously, all oscillator output terminals
should be tied together, all CT terminals con-
nected to a single timing capacitor, and timing re-
sistor connected to a single RT terminal. The
other RT t erminals can b e left open or shorted to
VREF. Minimum lead lengths should be used be-
tween the CT terminals.
Figure 6.
SG3524
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Figure 7: Flyback Converter Circuit.
Figure 8: PUSH-PU LL Transformer-coupled circuit.
SG3524
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DIP16
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
OUTLINE AND
MECHANICAL DATA
SG3524
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SO16 Narrow
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45˚ (typ.)
D (1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F (1) 3.8 4 0.150 0.157
G 4.6 5.3 0.181 0.209
L 0.4 1.27 0.016 0.050
M 0.62 0.024
S
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
OUTLINE AND
MECHANICAL DATA
8˚(max.)
SG3524
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Infor mation furni shed is bel ieved to be ac curate and reliabl e. Howev er, STMicroel ectr onics assum es no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
grante d by implication or otherwis e under any patent or patent righ ts of STMicroelectronics. Specifica tion mentione d in this publication are
subj ect to change without notic e. This public ation supers edes and rep laces all informat ion p reviously supplied. STMic roelec tronic s products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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SG3524
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