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12/10/04
IRFR220NPbF
IRFU220NPbF
SMPS MOSFET HEXFET® Power MOSFET
lHigh frequency DC-DC converters
Benefits
Applications
lLow Gate to Drain Charge to Reduce
Switching Losses
lFully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
lFully Characterized Avalanche Voltage
and Current
VDSS RDS(on) max (mΩ) ID
200V 600 5.0A
Typical SMPS Topologies
l Telecom 48V input Forward Converters
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 5.0
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 3.5 A
IDM Pulsed Drain Current 20
PD @TC = 25°C Power Dissipation 43 W
Linear Derating Factor 0.71 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery dv/dt 7.5 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Absolute Maximum Ratings
PD- 95063A
Notes through are on page 10
D-Pak
IRFR22ON I-Pak
IRFU220N
lLead-Free
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Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 2.6 ––– ––– S VDS = 50V, ID = 2.9A
QgTotal Gate Charge –– – 15 23 I D = 2.9A
Qgs Gate-to-Source Charge ––– 2.4 3.6 nC VDS = 160V
Qgd Gate-to-Drain ("Miller") Charge ––– 6.1 9.2 VGS = 10V,
td(on) Turn-On Delay Time ––– 6.4 ––– VDD = 100V
trRise Time ––– 11 ––– ID = 2.9A
td(off) Turn-Off Delay Time ––– 20 –– – RG = 24Ω
tfFall Time ––– 12 ––– VGS = 10V
Ciss Input Capacitance ––– 300 ––– VGS = 0V
Coss Output Capacitance ––– 53 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 15 ––– pF ƒ = 1.0MHz
Coss Output Capacitance ––– 300 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 23 ––– VGS = 0V, VDS = 160V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 46 ––– VGS = 0V, VDS = 0V to 160V
Dynamic @ TJ = 25°C (unless otherwise specified)
ns
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy––– 46 mJ
IAR Avalanche Current––– 2.9 A
EAR Repetitive Avalanche Energy––– 4.3 mJ
Avalanche Characteristics
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, I S = 2.9A, VGS = 0V
trr Reverse Recovery Time ––– 90 1 40 ns T J = 25°C, IF = 2.9A
Qrr Reverse RecoveryCharge ––– 320 480 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Diode Characteristics
5.0
20
A
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 200 – –– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.23 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 600 mΩVGS = 10V, ID = 2.9A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
––– ––– 25 µA VDS = 200V, VGS = 0V
––– ––– 250 VDS = 160V, VGS = 0V, T J = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V
IGSS
IDSS Drain-to-Source Leakage Current
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 3.5
RθJA Junction-to-Ambient (PCB mount)* –– – 50 °C/W
RθJA Junction-to-Ambient ––– 110
Thermal Resistance
IRFR/U220NPbF
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.01
0.1
1
10
100
0.1 1 10 100
20µs PU LSE WIDT H
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.1
1
10
100
0.1 1 10 100
20µs PU LSE WIDTH
T = 175 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.1
1
10
100
4.0 5.0 6.0 7.0 8.0 9.0 10.0
V = 5 0 V
20µs PULSE WIDTH
DS
V , Gate-to-Sou rce Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 175 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
4.8A
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0 5 10 15 20 25
0
4
8
12
16
20
Q , To ta l Ga te Cha rg e (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
2.9A
V = 40V
DS
V = 100V
DS
V = 160V
DS
0.1
1
10
100
0.4 0.6 0.8 1.0 1.2
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 175 C
J°
0.1
1
10
100
1 10 100 100
0
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 175 C
= 25 C
°°
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
110 100 1000
VDS, Drain-to-Source V oltage (V)
1
10
100
1000
10000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = C
gs + Cgd, C
ds SHORTED
Crss
= C
gd
Coss
= C
ds + Cgd
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Fig 10a. Switching Time Test Circuit
V
DS
9
0%
1
0%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
VGS
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
0.01
0.1
1
10
0.000001 0.00001 0.0001 0.001 0.01 0.1
Notes:
1. D u ty fa c to r D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Durati on ( s ec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
25 50 75 100 125 150 175
0.0
1.0
2.0
3.0
4.0
5.0
T , Case Temperature ( C )
I , Drain Current (A)
°
C
D
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25 50 75 100 125 150 175
0
20
40
60
80
Starting T , Junction Tempera t ur e ( C)
E , Single Puls e Avalanche Energy (m J)
J
AS
°
ID
TOP
BOTTOM
1.2A
2.1A
2.9A
Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13b. Gate Charge Test CircuitFig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
IRFR/U220NPbF
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
e-Applied
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFET® Power MOSFETs
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
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D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
12
I N THE ASSEMBLY LINE "A"
ASSEMBLED ON WW 16, 1999
EXAMPLE: WITH ASSEMBLY
THIS IS AN IRFR120
LOT CODE 1234 YEAR 9 = 199
9
DATE CODE
WEE K 16
PART NUM BER
LOGO
INTERNATIONAL
RECTIFIER
AS S EMBLY
LOT CODE
916A
IRFU120
34
YEAR 9 = 1999
DATE CODE
OR
P = DESIGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
Note: "P" in assembly line position
indic a tes "Lead-F ree "
12 34
WEEK 16
A = ASSEMBLY SITE CODE
PART NUMBER
IRFU120
LINE A
LOGO
LOT CODE
ASSEMBLY
INTERNATIONAL
RECTIFIER
IRFR/U220NPbF
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I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
ASSEMBLY
EXAMPLE: WITH AS SEMBLY
THIS IS A N IRFU120
YEA R 9 = 199
9
DATE CODE
LINE A
WEEK 19
IN THE ASS EMB LY LINE "A"
ASSEMB LED ON WW 19, 1999
LOT CODE 5678
PART NUMBER
56
IRFU120
INTERNATIONAL
LOGO
RECTIFIER
LOT CO DE
919A
78
Note: "P" in assembly line
position indic a tes "Lea d-Free"
OR
56 78
AS S EMBLY
LOT CODE
RECTIFIER
LOGO
INTERNATIONAL IRFU120
PART NU MBE R
WEEK 19
DATE CODE
YEAR 9 = 1999
A = AS SE MB LY SIT E CODE
P = DE SIGNATES LEAD-FREE
PRO DUCT (OPTIO NA L)
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Repetitive rating; pulse width limited by
max. junction temperature.
ISD ≤ 2.9A, di/dt ≤ 320A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Notes:
Starting TJ = 25°C, L = 11mH
RG = 25Ω, IAS = 2.9A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
* When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to application note #AN-994.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 12/04
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FE E D DIRECTIO N FE E D DIRECTIO N
16.3 ( .641
)
15.7 ( .619
)
TRR TRL
N
OTES :
1
. CONTROLLING DIMENS IO N : MILLIM ETER.
2
. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3
. OUTLINE CON F O RMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONF OR M S TO E IA - 481.
16 mm
13 INC H
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/